Automatic hardware interface detection

Abstract

A device (19) for processing near field communication type applications, the device (19) comprising: a host processor (21) configured to process a device application using a near field communication type application, and comprising a host wired data interface stage (22) having an encoder (23), the encoder is configured to encode data based on a first interface protocol and to transmit the encoded data via N information lines (5); an NFC controller (25) configured to handle a contactless interface (4) of the near field communication type and comprising an NFC controller wired data interface stage (26) having a first decoder (7) configured to communicate with the host wired data interface stage (22) via N information lines (5) based on a first interface protocol and a second decoder (8) configured to communicate with the host wired data interface stage (22) via N information lines (5) based on a second interface protocol, the second decoder (8) is configured to communicate with the other host wired data interface stage of the other host processor via the N information lines (5) based on a second interface protocol; a protocol selection stage (28) of the NFC controller wired data interface stage (26) configured to select either the first decoder (7) or the second decoder (8) to decode data received via the N information lines (5) according to a selected first interface protocol or a selected second interface protocol, the protocol selection stage (28) is configured to analyze a signal on at least one of the N information lines (5) based on a fixed information line connection scheme of each of the first interface protocol and the second interface protocol during a boot process after energization of the NFC controller (25) to select the first decoder (7) or the second decoder (8), and decoding means for decoding data received via the N information lines (5) according to the selected first interface protocol or second interface protocol.

Description

Technical Field

[0001] The present invention relates to a device for processing near field communication type applications, the device comprising:

[0002] a host processor structured to process device applications using near field communication type applications and including a host wired data interface stage having an encoder structured to encode data based on a first interface protocol and communicate the encoded data via the N information lines;

[0003] an NFC controller constructed to handle a near field communication type contactless interface and comprising an NFC controller wired data interface stage having a first decoder constructed to communicate with a host wired data interface stage via the N information lines based on a first interface protocol and a second decoder constructed to communicate with another host wired data interface stage of another host processor via the N information lines based on a second interface protocol;

[0004] The protocol selection stage of the wired data interface stage of the NFC controller is constructed to select the first decoder or the second decoder to decode the data received via the N information lines according to the selected first interface protocol or the selected second interface protocol. Background Art

[0005] The applicant sells an integrated circuit PTX 100R, which is used as an NFC controller in devices such as RFID readers with near field communication (NFC) functionality. NFC technology was developed by an industry consortium called NFC Forum (http: / / www.nfc-forum.ofg) and is derived from RFID technology. NFC components can operate in "reader" mode, "card emulation" mode and "device" mode standardized by ISO 18.092. The NFC component transmits a magnetic field via its near field communication contactless interface, sends data by modulating the amplitude of the magnetic field, and receives data by load modulation and inductive coupling. In emulation mode, such as described in EP 1 327 222, the NFC component operates passively like a transponder to dialogue with another reader and is seen as an RFID chip by the other reader.

[0006] The known reader with the integrated circuit PTX 100R comprises an integrated circuit host processor or reader processor which handles all types of applications related to the normal reader functions of the device, such as payment applications. Figure 11 shows a block diagram of such a reader 1 with a host processor 2 according to the prior art. In order to add a near field communication function and a contactless interface to the reader 1, an integrated circuit PTX 100R is added to the reader 1 as an NFC controller 3, which enables NFC communication via a contactless interface 4. The NFC Forum specification "NFC Controller Interface (NCI)" defines a software interface protocol for implementing communication between the host processor 2 and the NFC controller 3. The host processor 2 implements the NCI interface using a software stack called a host driver, which communicates with a software stack called a controller driver processed in the NFC controller 3 based on the NCI interface.

[0007] The device disclosed in EP 3 160 165 B 1 comprises such a host processor 2, which implements the NCI interface only in the host processor. This concept is called a "split-stack" NFC architecture of the host processor 2 and the NFC controller 3, which enables the NFC controller 3 to only require a relatively small software stack to be processed, requiring less computing power and storage area. This has the advantage that all non-time-critical and / or memory-consuming tasks of the reader's near field communication application are processed by the host processor 2, while time-critical tasks are processed by the NFC controller 3.

[0008] Regardless of how the NCI interface is implemented and how these processes are divided between the host processor 2 and the NFC controller 3, the two integrated circuits must be connected via a hardware contact interface to exchange data / information between the host processor 2 and the NFC controller 3. In one direction, data from the host processor 2 must be transmitted to the smart card or other NFC device via the contactless interface 4, and in the other direction, data from the other NFC device received via the contactless interface 4 must be transmitted to the host processor 2 via the hardware interface. There are several known different hardware interfaces used by the host processor, such as the serial peripheral interface SPI or the inter-integrated circuit data bus I2C or the universal asynchronous receiver transmitter UART, to name just three different interface protocols. Each of these hardware interfaces is defined by a publicly available specification that defines the connection scheme of the integrated circuits. In this connection scheme, it is defined how many information lines 5 must be used to physically connect the host processor 2 and the NFC controller 3, and which information line 5 transmits which information, such as a clock signal or a data signal, and whether the data must be encoded / decoded. In addition, in these specifications, the interface protocol is defined, which determines when which signal must be provided on the different information lines to, for example, start communication.

[0009] The goal of the manufacturer of an NFC controller, such as the known NFC controller 3, is that the NFC controller 3 should be able to communicate with as many different host processors 2 as possible from different manufacturers on the market. Therefore, the NFC controller 3 comprises an NFC controller wired data interface level 6, which is able to communicate based not only on one but on several of these different hardware interfaces and interface protocols. Figure 2 Show according to Figure 1 The NFC controller wired data interface level 6 therefore includes decoders / encoders 7, 8 and 9 for each of these different interface protocols. This means that the first decoder / encoder 7 is capable of encoding and decoding data for the first interface protocol of the serial peripheral interface SPI, the second decoder / encoder 8 is capable of encoding and decoding data for the second interface protocol of the integrated circuit data bus I2C, and the third decoder / encoder 9 is capable of encoding and decoding data for the third interface protocol of the universal asynchronous receiver transmitter UART. In addition, the NFC controller wired data interface level 6 includes an interface protocol level 10, which is constructed to communicate according to all these different interface protocols. In order to be able to select the selected decoder 7, 8 or 9 used by the host processor 2 and the selected interface protocol, the NFC controller 3 includes a protocol selection level 11 and two additional pins 12 and 13 for connecting two information lines. These information lines SIF and information line 5 are connected to the host wired data interface level 16, which includes an encoder / decoder 17 and a host interface protocol level 18. The technical specification of the NFC controller 3 defines which voltage must be provided on which pins 12 and 13 to enable the protocol selection stage 11 to select which of these interface protocols is used by the host processor 2 and should also be used by the NFC controller 3. As an example only, the SIF pin 12 needs to be set to logic "0" (e.g. ground potential) and the SIF pin 13 needs to be set to logic "1" (e.g. 5V) to select the first interface protocol, the decoder / encoder 7 selected by the protocol selection stage 11 being implemented as the SPI first interface protocol. Other logic combinations at pins 12 and 13 are used to select other interface protocols for the hardware interface communication between the host processor 2 and the NFC controller 3. The SIF pins 12 and 13 can be connected to two output pins 14 and 15 of the host processor 2, such as Figure 2 In another embodiment, a fixed wired solution may be used, in which a fixed connection to ground potential or a 5 V power supply is implemented for SIF pins 12 and 13, since an interface protocol has to be selected only during the implementation of the integrated circuit on a printed circuit board and the decoder / encoder used by the host processor 2 has to be done once.

[0010] The disadvantage of this solution is that at least the NFC controller 3 and, depending on the different possible implementations described above, the host processor 2 also typically needs to provide these two additional SIF pins in order to select the hardware interface protocol to be used. This increases the chip area and cost of the integrated circuit and the complexity of the reader's printed circuit board. Summary of the invention

[0011] The object of the present invention is to provide a device and a chipset and a method of processing near field communication type applications, which improves the use of the limited chip area of ​​the NFC controller and reduces the effort of implementing the chipset into the device.

[0012] This object is achieved by a device according to claim 1 and a chipset according to claim 9 and a method according to claim 10. The NFC controller of the claimed device comprises a protocol selection stage, which is constructed to analyze signals on at least one of two, three or more information lines of the hardware interface between the host processor and the NFC controller. A prerequisite for the protocol selection stage is that the device manufacturer has implemented the fixed information line connection scheme of the NFC controller technical specification to connect the host processor with the NFC controller for the interface protocol used by the host processor. During the boot process after the NFC controller is powered on, the protocol selection stage analyzes the signals on these information lines to select a first decoder stage or a second decoder stage to decode the data received via the N information lines according to the selected first interface protocol or the selected second interface protocol. This is possible because the fixed connection scheme in the NFC controller specification has been used, which hardware information line (pin of the integrated circuit) between the host processor and the NFC controller must be used for which line of the interface protocol used by the host processor. The protocol selection stage is constructed to detect all changes in potentials or signals received from the host processor on the N information lines of the hardware interface, and since all these different interface protocols transmit defined potentials, signals or commands on defined information lines during power-on and during communication initialization, the comparison with the signals expected by the different interface protocols can determine which interface protocol the host processor uses to select the appropriate decoder / encoder stage. This selection at the protocol selection stage also includes selecting the interface protocol at the interface protocol level of the NFC controller wired data interface level, starting from this selection, the interface protocol communicates with the host wired data interface level based on the selected interface protocol. Since the NFC controller of the device to be protected can automatically detect the interface protocol used by the host processor, SIF information lines and pins on the NFC controller and the host processor are not required to select the interface protocol, which reduces the chip area of ​​the NFC controller and the work of implementing the chipset into the device.

[0013] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.It will be appreciated by those skilled in the art that the various embodiments may be combined. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A block diagram of a reader device with an NFC controller according to the prior art is shown.

[0015] Figure 2 Show Figure 1 Relevant details of the reader shown.

[0016] Figure 3 A device according to an embodiment of the invention is shown.

[0017] Figure 4 The signals of the I2C specification are shown having a start state and a stop state. DETAILED DESCRIPTION

[0018] Figure 3 A device 19 is shown implementing the functionality of a payment terminal or reader to enable an NFC device 20 (such as a mobile phone or a smart card) to make payments via the NFC wireless interface 4. Figure 3 For those blocks or stages having the same functions as those described for the device 1 of the prior art, the same Figure 2 The same reference numerals are used in the drawings.

[0019] The device 19 includes a host processor 21, which is configured to process payment applications, and includes a host wired data interface stage 22 having an encoder / decoder 23, which is configured to encode data based on a first interface protocol. In a first embodiment of the present invention, the first interface protocol is a serial peripheral interface SPI protocol known to those skilled in the art. The host wired data interface stage 22 also includes a host interface protocol stage 24 for transmitting data encoded based on SPI encoded data via N=4 information lines 5.

[0020] In order to connect the host processor 21 with the NFC controller 25 of the device 19, the two integrated circuits must be connected via a hardware contact interface to exchange data / information via the information line 5. In one direction, data from the host processor 21 must be transmitted to the NFC device 20 via the contactless interface 4, and in the other direction, data from the NFC device 20 received via the contactless interface 4 must be transmitted to the host processor 21 via the hardware interface. There are several known different hardware interfaces used by the host processor, such as the serial peripheral interface SPI or the inter-integrated circuit data bus I2C or the universal asynchronous receiver transmitter UART, to name just three different interface protocols. Each of these hardware interfaces is specified by a publicly available specification that specifies the connection scheme of the integrated circuit. In the connection scheme, it is specified how many information lines 5 must be used to physically connect the host processor 21 and the NFC controller 25, and which information line 5 transmits which information, such as a clock signal or a data signal, and whether the data must be encoded / decoded. In these specifications, the interface protocol is also specified, which determines when which signal must be provided on the different information lines to, for example, start communication.

[0021] The goal of the manufacturer of NFC controllers, such as NFC controller 25, is that the NFC controller 25 should be able to communicate with as many different host processors 21 as possible from different manufacturers on the market. Therefore, the NFC controller 25 includes an NFC controller wired data interface level 26, which can communicate based not only on one, but on several of these different hardware interfaces and interface protocols. The NFC controller wired data interface level 26 therefore includes decoders / encoders 7, 8 and 9 for each of these different interface protocols. This means that the first decoder / encoder 7 is capable of encoding and decoding data for a first interface protocol of a serial peripheral interface SPI, the second decoder / encoder 8 is capable of encoding and decoding data for a second interface protocol of an inter-integrated circuit data bus I2C, and the third decoder / encoder 9 is capable of encoding and decoding data for a third interface protocol of a universal asynchronous receiver transmitter UART. In addition, the NFC controller wired data interface level 26 includes an NFC interface protocol level 27, which is constructed to communicate according to all these different interface protocols. In order to be able to select the selected decoder 7, 8 or 9 and the selected interface protocol used by the host processor 21, the NFC controller 25 includes a protocol selection stage 28, which is constructed to analyze the signal on at least one of the four information lines 5 during the boot process after the NFC controller 25 is powered on, based on the fixed information line connection scheme of each of the first interface protocol, the second interface protocol and the third interface protocol, to select the first decoder stage 7 or the second decoder stage 8 or the third decoder stage 9 for decoding the data received via the four information lines 5 according to the selected first interface protocol, the second interface protocol or the third interface protocol.

[0022] The connection scheme of the NFC controller 25 in its data sheet or technical specifications stipulates that the pin of the host processor 21 providing the clock signal for the hardware interface must be connected via the first information line 29 to the pin of the NFC controller 25 that should receive the clock signal for the hardware interface, regardless of which of the three possible interface protocols the host processor 21 uses. This is possible because all these interface protocols use a clock signal. The other three information lines 5 must be connected to other input / output pins of the host interface protocol level 24 and the NFC interface protocol level 27. The specification of the serial peripheral interface SPI used by the host processor 21 stipulates that the following three information lines are provided at three pins of the host controller 21:

[0023] 1.POCI (Peripheral Output / Controller Input) or MISO (Master Input / Slave Output)

[0024] 2. PICO (Peripheral Input / Controller Output) or MOSI (Master Output / Slave Input)

[0025] 3.SS (from selection)

[0026] And the connection scheme of the NFC controller 25 stipulates that if the host processor 21 uses the serial peripheral interface SPI, the POCI or MISO pin of the host processor 21 must be connected to the pin of the NFC controller 25 specified in the specification of the NFC controller 25 via the second information line 30. In addition, the PICO or MOSI pin of the host processor 21 must be connected to the pin of the NFC controller 25 specified in the specification of the NFC controller 25 via the third information line 31, and the SS pin of the host processor 21 must be connected to the pin specified in the specification of the NFC controller 25 via the fourth information line 32. The protocol selection level 28 stores information for all three possible and supported interface protocols on how these interface protocols start communicating after the host processor 21 (master) and the NFC controller 25 (slave) are powered on and what signals must be expected. After power-on, the NFC interface protocol level 27 is constructed to switch all pins of the hardware interface, which means all pins connected to the information line 5 as input pins to detect all types of received signals or potential changes or commands or address information. Based on these signals detected at the pins of the NFC interface protocol level 27 connected to the information line 5, the protocol selection level 28 is able to detect which interface protocol is used by the host processor 21 and select the appropriate decoder 7, 8 or 9, as well as the appropriate interface protocol for further communication between the NFC interface protocol level 27 and the host interface protocol level 24.

[0027] In the above embodiment, when the host processor uses the serial peripheral interface SPI, the protocol selection stage 28 is constructed to detect a change from logic "1" (typically 5V) to logic "0" (typically ground potential) on the second information line 30 for transmitting the chip select signal SS, and then detect the start of the clock signal on the first information line 29. Based on these detections, the protocol selection stage 28 is constructed to determine that the host wired data interface stage 22 uses the serial peripheral interface SPI, and selects the SPI decoder as the first decoder stage 7 to decode the data received via the information line 5. The NFC controller 25 continues to use this first interface protocol until the next power-off and later power-on occur. This provides the advantage that the interface protocol used by the host processor 21 can be quickly detected and saved by analyzing only the signal at the pin without analyzing the data at the data decoder level.

[0028] The NFC controller wired data interface 26 is also constructed to observe the frame detection or error detection output of the selected decoder 7 to decide whether the detection and selection process must be restarted. Based on the detection of the decoder 7, in the event of an increase in errors detected in the data or frames received from the host processor 21, the protocol selection level 28 is constructed to analyze the signals received at the pins of the NFC controller 25 connected to the information line 5 not only after power-on but also during normal communication to reconfirm the selection or change the selection of the interface protocol and decoder. This makes it possible to correct an erroneous initial selection due to the absence of a signal detected after power-on. Recheck of the selected interface protocol for data processing at the data decoder level.

[0029] Now, the method of how to handle this automatic selection of the interface protocol is explained in more detail. The method comprises the following steps:

[0030] In a first step, the power-on process in these integrated circuits is handled after the host processor 21 and the NFC controller 25 are powered on. These power-on processes are known to those skilled in the art and may include filling some memory areas with initial values ​​and switching some pins to input or output pins.

[0031] In a second step, the NFC controller 25 waits for a waiting period of a few milliseconds or seconds or a similar period of time to ensure that the host processor 21 completes its power-on process. Afterwards, the NFC controller 25 analyzes the signal received on at least one of the four information lines 5 of the hardware wired data interface between the host processor 21 and the NFC controller 25 based on the fixed information line connection scheme of each of the first interface protocol, the second interface protocol and the third interface protocol of the hardware wired data interface that the host processor 21 can use. Based on the analysis, the first decoder stage 7 and the first interface protocol or the second decoder stage 8 and the second interface protocol or the third decoder stage 9 and the third interface protocol of the NFC controller 25 are selected for decoding the data received via the four information lines 5 according to the selected first interface protocol or the selected second interface protocol or the third interface protocol. In this way, automatic detection of the interface protocol used by the host processor 21 is achieved.

[0032] In a second embodiment of the invention, another host processor uses the inter-integrated circuit data bus I2C second interface protocol and encodes the data to be transmitted to the NFC controller 25 according to the second interface protocol. The specification of this I2C bus stipulates that the master device (host processor 21) starts to communicate in bytes via the address / data signal ADS (data line = fourth information line 32), where the first seven bits are address bits for addressing the slave device (NFC controller 25) and the eighth bit indicates whether the slave device is to receive data from the master device or send data to the master device. In addition, the other two address pins of the slave device can also be used to change two bits of the fixed I2C address implemented in the integrated circuit of the slave device, so that up to four identical integrated circuits with changed address bits can be used and addressed on the same I2C bus. The protocol selection stage 28 is constructed to observe, within a detection period of a few milliseconds or seconds or a similar period of time, whether the clock signal CLK is detected on the first information line 29, while no change of the signal is detected on the second information line 30 and the third information line 31 (address change line) connected to the other two address pins of the NFC controller 25 and used to change two of the seven address bits sent by the host processor 21 on the fourth information line 32 (address / data signal ADS) to start communication. This is possible because the fixed information line connection scheme of the NFC controller 25 stipulates that the second information line 30 and the third information line 31 must be set to a fixed potential (ground or VDD) in the case where the host processor 21 uses the second interface protocol with the I2C bus. Therefore, when the host processor 21 starts communication, no change of the signal or potential is detected on the address line / second and third information lines 30 and 31. As a result, if the protocol selection stage 28 detects the clock signal CLK and there is no change on the second information line 30 and the third information line 31, it is determined that the inter-IC I2C data bus is used as the second interface protocol by the host wired data interface stage of the other host processor and the I2C decoder is selected as the second decoder stage 8 to decode the data received on the fourth information line 32 after the communication between the host processor 21 and the NFC controller 25 is initialized. In another embodiment, the other two address pins of the NFC controller can be hardwired to the ground potential or VDD to provide them with a fixed potential and address within the I2C bus. The advantage of this embodiment is that the host processor does not need these other two pins to be connected to the second information line 30 and the third information line 31. The detection period is usually a few clock cycles of the clock signal to ensure that the checked or detected state is actually achieved.

[0033] In a third embodiment of the present invention, another host processor is connected to the NFC controller 25, which uses a universal asynchronous receiver transmitter UART third interface protocol and encodes data to be transmitted to the NFC controller 25 according to the third interface protocol. The protocol selection stage 28 is constructed to determine that the universal asynchronous receiver transmitter UART is used as the third interface protocol by the host wired data interface stage of the other host processor if neither the first interface protocol nor the second interface protocol is selected during the selection period, and to process the selection of the above-mentioned first or second interface protocol during the selection period, and is constructed to select the UART decoder as the third decoder stage 9 to decode the data received via the information line 5.

[0034] The principle of automatically detecting which interface protocol and / or which encoding has been used by one integrated circuit for a hardware interface with a second integrated circuit and automatically selecting the appropriate interface protocol and / or decoder at the second integrated circuit has been explained based on a device processing an NFC type application. This principle can be used for any other RFID type application and even further for any other type of integrated circuit, without involving any wireless interface.

[0035] The number of information lines connecting the pins of the host processor and the NFC controller depends on the different interface protocols used by the two integrated circuits. If only two wired hardware interface protocols are used, then N=2, but if only one of the interface protocols that can be selected within the NFC controller is used, then N=3 or N=4, or more information lines can be used. For practical reasons, it depends on how many information lines are required for the interface protocol used by the host processor and how many information lines are used to connect the two integrated circuits.

[0036] Those skilled in the art will appreciate that, based on the different interface protocols selectable within the protocol selection stage 28 of the NFC controller 25, all types of different signal changes can be identified to distinguish supported interface protocols in a fast and cost-effective manner.

[0037] In another embodiment of the present invention, the signal on the information line 5 is analyzed by the protocol selection stage 28 to identify the inter-IC I2C, without the need for two additional address pins as described in the second embodiment. Figure 3 and Figure 4As shown, the I2C specification stipulates that in the signal 33, the clock signal CLK received by the NFC controller 25 on the first information line 29 and the start state 34 and stop state 35 of the address / data signal ADS received by the NFC controller 25 on the fourth information line 32. In the start state 34, the clock signal CLK and the address / data signal ADS both have a high potential, then the address / data signal ADS becomes a low potential, and the clock signal CLK remains at a high potential, and then the clock signal CLK also becomes a low potential. If the protocol selection stage 28 detects the start state 34 after power-on, the protocol selection stage 8 determines that the inter-integrated circuit I2C data bus is used as the second interface protocol by the host wired data interface stage 22, and selects the I2C decoder as the second decoder 8 to decode the data received on the fourth information line 32.

[0038] In another embodiment of the present invention, the serial peripheral interface SPI is identified by the following analysis of the signal on the information line 5 by the protocol selection stage 28. The SS pin of the host processor 21 connected to the NFC controller 25 via the fourth information line 32 is high and then becomes low, which means that the NFC controller 25 is selected by the host processor 21. If after that, the polarity of the clock signal CLK received from the host processor 21 on the first information line 29 changes at least 16 times, which means that at least 8 bits have been received, and if after that, the NFC controller 25 is still selected by the low potential on the fourth information line 32, the protocol selection stage 28 is constructed to determine that the host wired data interface stage 22 uses the serial peripheral interface SPI, and selects the SPI decoder as the first decoder stage 7 to decode the data received via the information line 5.

[0039] In another embodiment of the present invention, if the other two interface protocols are not selected, not only is the universal asynchronous receiver transmitter UART selected, but it is also actively identified by the following analysis of the signal on the information line 5 by the protocol selection stage 28. The specification of UART only stipulates two information lines, one in each direction. How to achieve the fixed information line connection scheme between the NFC controller 25 and the host processor stipulates that the RDX pin of the host processor 21 must be connected to the TDX pin of the NFC controller 25 via the first information line 29, and the TDX pin of the host processor 21 must be connected to the RDX pin of the NFC controller 25 via the second information line 30. If the protocol selection stage 28 first detects a high potential on the second information line 30, then detects a low potential, and then detects a high potential again, while the potential of the first information line 30 does not change, the protocol selection stage 28 is constructed to determine that the universal asynchronous receiver transmitter UART is used as the third interface protocol by the host wired data interface stage 22 of the host processor 21.

[0040] Furthermore, it is advantageous to use not only one but more of the above analysis results of the protocol selection stage 28 to decide or reconfirm which interface protocol has to be selected after power-up or during normal processing.

Claims

1. A device (19) for processing near field communication type applications, the device (19) comprising: a host processor (21) configured to process device applications using near field communication type applications and comprising a host wired data interface stage (22) having an encoder (23) configured to encode data based on a first interface protocol and transmit the encoded data via N information lines (5); An NFC controller (25) configured to process a contactless interface (4) of the near field communication type and comprising an NFC controller wired data interface stage (26) having a first decoder (7) configured to communicate with the host wired data interface stage (22) via the N information lines (5) based on the first interface protocol and a second decoder (8) configured to communicate with another host wired data interface stage of another host processor via the N information lines (5) based on the second interface protocol; a protocol selection stage (28) of the NFC controller wired data interface stage (26) configured to select the first decoder (7) or the second decoder (8) to decode data received via the N information lines (5) according to the selected first interface protocol or the selected second interface protocol, Features The protocol selection stage (28) is configured to analyze a signal on at least one of the N information lines (5) based on a fixed information line connection scheme of each of the first interface protocol and the second interface protocol during a boot process after the NFC controller (25) is powered on, so as to select the first decoder (7) or the second decoder (8) for decoding data received via the N information lines (5) according to the selected first interface protocol or second interface protocol.

2. The device (19) according to claim 1, wherein: If the host wired data interface level (22) uses the first interface protocol or the second interface protocol, the protocol selection level (28) is constructed to analyze N=3 or N=4 information lines (5), wherein the first information line (29) is used to transmit a clock signal, and the second information line (30) and the third information line (31) and / or the fourth information line (32) are used to transmit and / or receive data and / or address information and / or other signals according to the expected received signal.

3. The device (19) according to claim 2, wherein: The protocol selection stage (28) is constructed to detect a change from logic "1" to logic "0" of ground potential on a second information line (30) for transmitting a chip selection signal, and only thereafter to detect the start of a clock signal on a first information line (29), and wherein the protocol selection stage (28) is constructed to, when both are detected, determine that the host wired data interface stage (22) uses a serial peripheral interface SPI and select an SPI decoder as the first decoder (8) to decode data received via the information line (5).

4. The device (19) according to claim 2 or 3, wherein: The protocol selection stage (28) is constructed to observe during a detection period, and if a clock signal is detected on the first information line (29) and no signal change is detected on the second information line (30) and the third information line (31) connected to the other address pins of the NFC controller (25) and used as address change lines, it is determined that the inter-integrated circuit I2C data bus is used as the second interface protocol by the host wired data interface stage (22), and an I2C decoder is selected as the second decoder (8) to decode the data received on the fourth information line (32).

5. The device (19) according to claim 4, wherein: The protocol selection stage (28) is constructed to determine that the host wired data interface stage (22) uses a universal asynchronous receiver / transmitter (UART) as a third interface protocol if neither the first interface protocol nor the second interface protocol is selected during a selection period, and select a UART decoder as a third decoder (9) to decode data received via the information line.

6. The device (19) according to any one of claims 2 to 5, wherein: The NFC controller wired data interface (26) includes an encoder to encode data to be transmitted to the host processor (21) based on a selected interface protocol.

7. The device (19) according to any one of the preceding claims, wherein: The NFC controller wired data interface (26) observes the frame detection or error detection output of the selected decoder (7, 8, 9) to determine whether the detection and selection process must be restarted.

8. The device (19) according to any one of the preceding claims, wherein: The protocol selection stage (28) configures all information line pins of the NFC controller (25) integrated circuit as input pins after power-on to detect potential errors in the implementation of the information line connection scheme.

9. A chipset for a device (19) for processing near field communication type applications, characterized in that The chipset comprises a host controller (21) and an NFC controller (25) of a device (19) as claimed in claims 1 to 8.

10. A method for processing a near field communication type application using a device (19) according to any one of claims 1 to 8, the device (19) comprising a host processor (21) for processing a device application using the near field communication type application and an NFC controller (25) for processing a contactless interface (4) of the near field communication type, wherein the following steps are processed in the NFC controller (25): After the power of the host processor (21) and the NFC controller (25) is turned on, processing the power-on process in these integrated circuits; ·in, The NFC controller (25) analyzes a signal received on at least one of the N information lines of the hardware wired data interface, based on a fixed information line (5) connection scheme of each of a first interface protocol and a second interface protocol of the hardware wired data interface between the host processor (21) and the NFC controller (25) that can be used by the host processor (21), after waiting for a period of time to ensure that the host processor (21) completes its power-on process, to select a first decoder (7) and a first interface protocol or a second decoder (8) and a second interface protocol of the NFC controller (25) for decoding data received via the N information lines (5) according to the selected first interface protocol or the selected second interface protocol.

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