Serial data receiver with even / odd mismatch compensation

Abstract

A serial data receiver circuit included in a computer system may include: a front-end circuit; a sampling circuit including a plurality of analog-to-digital converter circuits; and a recovery circuit. The sampling circuit can sample a serial data stream at different times corresponding to even number symbols and odd number symbols in the serial data stream. The recovery circuitry may process respective samples of the even number symbols and the odd number symbols using different coefficients in order to recover data symbols encoded in the serial data stream.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 376,208, filed on September 19, 2022, entitled “Serial Data Receiver with Even / Odd Mismatch Compensation,” which is incorporated herein by reference in its entirety. Background Art Technical Field

[0003] The present disclosure relates to the field of high speed communication interface design, and in particular to minimizing symbol error rates.

[0004] Related technical description

[0005] Computing systems often include multiple interconnected integrated circuits. In some cases, the integrated circuits can communicate using communication channels or links to send and receive data bits. Such communication channels can support parallel communication, where multiple data bits are sent in parallel, or serial communication, where data bits are sent one bit at a time in a serial manner.

[0006] Data sent between integrated circuits can be encoded to facilitate transmission. For example, in the case of serial communication, the data can be encoded to provide transitions between logic states sufficient to allow clock and data recovery circuits to operate. Alternatively, in the case of parallel communication, the data can be encoded to reduce switching noise or improve signal integrity.

[0007] During data transmission, the physical characteristics of the communication channel may attenuate the transmitted signal associated with a particular data bit. For example, the impedance of the wiring included in the communication channel or link may attenuate certain frequency ranges of the transmitted signal. Additionally, impedance mismatches between the wiring included in the communication channel and a device coupled to the communication channel may cause reflections of the transmitted signal, which may degrade subsequent transmitted signals corresponding to other data bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an implementation of an ADC-based receiver circuit for a computer system.

[0009] Figure 2 is a block diagram of another embodiment of a receiver circuit for a computer system.

[0010] Figure 3 is a block diagram of an implementation of an analog front end circuit.

[0011] Figure 4 is a block diagram of an implementation of a sampling circuit employing multiple analog-to-digital converter circuits.

[0012] Figure 5 is a block diagram of an implementation of a recovery circuit for an ADC-based receiver circuit.

[0013] Figure 6 is a block diagram of a computer system including a transmitter circuit and a receiver circuit.

[0014] Figure 7 is a flow chart of an embodiment of a method for operating a receiver circuit using different sampling thresholds for odd data symbols and even data symbols.

[0015] Figure 8 is a flow chart of an embodiment of a method for operating a receiver circuit using different coefficients to process samples corresponding to odd data samples and even data samples.

[0016] Fig. 9 is a block diagram of one embodiment of a system on a chip including a receiver circuit.

[0017] Fig.10 is a block diagram of various embodiments of a computer system that may include a receiver circuit.

[0018] Fig.11 An example of a non-transitory computer-readable storage medium storing circuit design information is illustrated. DETAILED DESCRIPTION

[0019] A computing system may include one or more integrated circuits, such as, for example, a central processing unit (CPU) and a memory. Various integrated circuits included in a computing system may communicate via a serial or parallel interface. In a parallel interface, multiple data bits are transmitted simultaneously, while in a serial interface, data is transmitted as a series of sequential single data bits. When a serial interface is used to transmit data between two devices included in a computing system, data may be sent according to different protocols. For example, data may be sent using a return-to-zero (RZ) protocol, a non-return-to-zero (NRZ) protocol, a pulse amplitude modulation (PAM), or any suitable combination thereof.

[0020] Serial data streams are often sent without an accompanying clock signal. In this case, the clock signal is recovered from the serial data stream (in a process known as "clock recovery") and is used to sample the serial data stream to determine the values ​​of the included data symbols. Various techniques can be used to recover the clock signal. For example, a receiver circuit can generate a clock signal with a frequency that is approximately the same as the frequency of the clock signal used to create the serial data stream. A phase-locked loop circuit can then be used to phase-align the clock signal with the transitions in the serial data stream. Alternatively, the serial data stream can be oversampled, i.e., sampled at a frequency higher than the frequency of the clock signal used to generate the serial data stream.

[0021] The process of recovering a clock signal from a serial data stream is always imperfect, causing the edges of the clock signal to deviate from their ideal positions. This deviation of the clock edges is called "jitter" and can be the result of various effects in the circuit, such as power supply noise, thermal noise, ground bounce, etc.

[0022] Receiver circuits for serial data streams may be analog based, or they may employ analog-to-digital converter (ADC) circuits. ADC-based receiver circuits convert an equalized version of the input data signal into bits in the digital domain, allowing additional processing (e.g., feed-forward equalization) to be performed as digital signal processing operations.

[0023] In addition to jitter introduced into the transmitted signal by the physical characteristics of the channel, duty cycle distortion (DCD) in the transmitter circuitry can cause different impulse responses for even-numbered and odd-numbered symbols in the serial data stream. The effect of different impulse responses for even-numbered and odd-numbered symbols in the serial data stream can be demonstrated by the level separation mismatch between different symbol values ​​for even-numbered and odd-numbered symbols (referred to as the “level separation mismatch ratio” or “R LM ”) and further increased.

[0024] The difference in impulse response and the mismatch in level separation between even and odd symbols can result in a higher error rate for one or both of the even or odd symbols when recovering the transmitted symbols. For example, compensating for even symbols can result in a higher error rate for odd symbols and vice versa. Attempting to sample and process both even and odd samples in the same manner can result in higher error rates for both.

[0025] The embodiments illustrated in the accompanying drawings and described below provide techniques for compensating for different impulse responses and level separation mismatches for even-numbered symbols and odd-numbered symbols in serial data recovery. By using different sampling thresholds for even-numbered symbols and odd-numbered symbols or post-processing even-numbered symbols and odd-numbered symbols using different coefficients, the error rates associated with different impulse responses and level separation mismatches can be reduced.

[0026] Figure 1 A block diagram depicting an embodiment of a receiver circuit is illustrated in As illustrated, the receiver circuit 100 includes a front end circuit 101, a sampling circuit 102, and a recovery circuit 104. In various embodiments, the sampling circuit 102 includes an optional retimer circuit 103.

[0027] Front end circuit 101 is configured to generate equalized signal 108 using signal 106. In some embodiments, signal 106 encodes a serial data stream including data symbols 107. In various embodiments, signal 106 may encode data symbols 107 according to one of a variety of symbol encodings. For example, signal 106 may be transmitted according to RZ, NRZ, PAM3, or any other suitable symbol encoding.

[0028] The sampling circuit 102 includes an analog-to-digital converter circuit 105. A first subset of the analog-to-digital converter circuits 105 is configured to sample the equalized signal 108 at a time corresponding to an odd-numbered data symbol of the data symbol 107 using the recovered clock signal 112 to generate odd-numbered samples 113A. A second subset of the analog-to-digital converter circuits 105 is configured to sample the equalized signal 108 at a time corresponding to an even-numbered data symbol of the data symbol 107 using the recovered clock signal 112 to generate even-numbered samples 113B. By using different sampling thresholds, the sampling circuit 102 can compensate for the difference between the odd-numbered data symbols and the even-numbered data symbols in the data symbol 107 caused by duty cycle distortion or level mismatch.

[0029] Using multiple analog-to-digital converter circuits operating in rapid succession, odd samples 113A and even samples 113B can be generated in sequence at the arrival frequency of data symbols 107. Such arrival frequencies may be too high for recovery circuit 104 to handle. In such cases, a retimer circuit (such as retimer circuit 103) can adjust the timing of odd samples 113A and even samples 113B. In various embodiments, retimer circuit 103 is configured to retime odd samples 113A and even samples 113B. In some cases, the retimed odd samples 113A and even samples 113B can be timed to a single clock phase. In some cases, the frequency of the retimed odd samples 113A and even samples 113B is less than the frequency of data symbols 107.

[0030] The recovery circuit 104 is configured to use the odd samples 113A and the even samples 113B to generate the recovered data symbols 111 and the recovered clock signal 112. As described below, in order to generate the recovered data symbols 111 and the recovered clock signal 112, the recovery circuit 104 may also be configured to use the odd samples 113A and the even samples 113B to perform additional equalization operations (e.g., feed-forward equalization). Since a given one of the odd samples 113A and the even samples 113B includes a plurality of bits whose values ​​collectively correspond to the voltage level of the signal 106 at a given point in time, the recovery circuit 104 may perform its functions in the digital domain. In various embodiments, portions of the recovery circuit 104 may be implemented using digital signal processing (DSP) techniques.

[0031] exist Figure 1 In the embodiment of the present invention, different sampling thresholds are used to adjust the variation between even-numbered data symbols and odd-numbered data symbols. In other embodiments, different techniques can be used to adjust the variation. Figure 2 Another embodiment of a receiver circuit is depicted in . As illustrated, the receiver circuit 200 includes a front-end circuit 101, a sampling circuit 201, and a recovery circuit 202. In various embodiments, the sampling circuit 201 includes an optional retimer circuit 103.

[0032] Sampling circuit 201 includes analog-to-digital converter circuit 105. A first subset of analog-to-digital converter circuits 105 is configured to sample equalized signal 108 at times corresponding to odd-numbered data symbols of data symbols 107 using recovered clock signal 112 to generate odd samples 203A. A second subset of analog-to-digital converter circuits 105 is configured to sample equalized signal 108 at times corresponding to even-numbered data symbols of data symbols 107 using recovered clock signal 112 to generate even samples 203B.

[0033] The recovery circuit 202 is configured to use the odd samples 203A and the even samples 203B to generate the recovered data symbols 111 and the recovered clock signal 112. As described below, in order to generate the recovered data symbols 111 and the recovered clock signal 112, the recovery circuit 202 may also be configured to perform additional equalization operations (e.g., feed-forward equalization) using the odd samples 203A and the even samples 203B using the odd coefficients 204A and the even coefficients 204B, respectively. Since a given one of the odd samples 203A and the even samples 203B includes a plurality of bits whose values ​​collectively correspond to the voltage level of the signal 106 at a given point in time, the recovery circuit 204 may perform its functions in the digital domain. In various embodiments, portions of the recovery circuit 204 may be implemented using digital signal processing (DSP) techniques.

[0034] Note that in some implementations, a combination of techniques may be employed to compensate for variations between odd-numbered data symbols and even-numbered data symbols. For example, in some implementations, the equalized signal 108 may be sampled using different sampling thresholds for odd-numbered data symbols and even-numbered data symbols, and the resulting samples may be processed using corresponding sets of coefficients.

[0035] As described above, the front end circuit 101 is configured to generate the equalized signal 108 . Figure 3, a block diagram of an embodiment of the front-end circuit 101 is depicted. As illustrated, the front-end circuit 101 includes a filter circuit 301 and an automatic gain control circuit 302. It should be noted that although the front-end circuit 101 is depicted as being implemented using a continuous-time linear equalization technique, in other embodiments, other equalization techniques may be employed.

[0036] Filter circuit 301 is configured to generate filtered signal 303 using signal 106. In various implementations, to generate filtered signal 303, filter circuit 301 may also be configured to attenuate high frequency noise in signal 106. In some cases, filter circuit 301 may also be configured to attenuate low frequency components in signal 106 at or near a DC level.

[0037] In various embodiments, filter circuit 301 can be implemented using a series of filter circuits, each filter circuit having a different transfer function. For example, filter circuit 301 can include three filter circuits. The first filter circuit can be a high-pass filter circuit, while the second filter circuit and the third filter circuit can be band-pass filter circuits. In some embodiments, filter circuit 301 can additionally include a variable gain amplifier circuit coupled to the output of the last filter circuit in the three filter circuits.

[0038] The automatic gain control circuit 302 is configured to generate the equalized signal 108 using the filtered signal 303. In various embodiments, the automatic gain control circuit 302 can be implemented as a closed-loop control circuit that maintains the amplitude of the data symbols at an optimal level for sampling using feedback derived from the equalized signal 108. In various embodiments, the automatic gain control circuit 302 can include any suitable combination of attenuators and amplifier circuits that can be dynamically activated or deactivated to maintain the amplitude of the data symbols.

[0039] It is noted that although the front end circuit 101 is depicted as including the filter circuit 301 and the automatic gain control circuit 302 , different and / or additional circuit blocks may be included when different equalization techniques are employed.

[0040] Go to Figure 4 , depicting an embodiment of the sampling circuit 102. As illustrated, the sampling circuit 102 includes sampling buffers 401A-401D, sub-analog-to-digital converter circuits (denoted as "sub-ADCs 402A-402D"), switches 403A-403D, and a clock generation circuit 404. Note that although Figure 4 In the embodiment of FIG. 4 , four sampling buffers, four switches, and four sub-ADCs are depicted, but different numbers of sampling buffers, switches, and sub-ADCs may be used in other embodiments.

[0041] Switches 403A-403D are configured to couple equalized signal 108 to corresponding ones of sampling buffers 401A-401D using buffer clock 405. In various embodiments, each of buffer clocks 405 may be phase-shifted relative to one another so that only one of switches 403A-403D is closed at any given time. In various embodiments, the respective frequencies of buffer clocks 405 may be based on the frequency of recovered clock signal 112 and the number of sampling buffers and sub-ADCs included in sampling circuit 102.

[0042] In various embodiments, switches 403A-403D may be implemented using one or more switching metal oxide semiconductor field effect transistors (MOSFETs), fin field effect transistors (FinFETs), gate all around field effect transistors (GAAFETs), or any other suitable switching devices.

[0043] Each of the sampling buffers 401A-401D is configured to buffer the equalized signal 108 and the analog-to-digital converter circuit included in the corresponding driver sub-ADC in the driver sub-ADCs 402A-402D. In various embodiments, the sampling buffers 401A-401D may be implemented as unity gain amplifier circuits, or any other suitable circuit configured to buffer analog signals and provide additional drive to allow driving multiple analog-to-digital converter circuits.

[0044] Each of the sub-ADCs 402A-402D includes a plurality of analog-to-digital circuits coupled to a corresponding one of the sampling buffers 401A-401D and configured to generate sampled signals 407A-407D based on a voltage level of an output of the corresponding one of the sampling buffers 401A-401D. In various implementations, each of the sampled signals 407A-407D may carry a corresponding symbol stream generated by a corresponding sub-ADC in the sub-ADCs 402A-402D. The analog-to-digital circuits included in a given one of the sub-ADCs 402A-402D are sequentially activated by the ADC clocks 406A and 406B.

[0045] When a given analog-to-digital converter circuit is activated, it samples the output of its corresponding sampling buffer. Once the output has been sampled, there may be a period of time (referred to as a "resolution period" or "resolving period") for the analog-to-digital converter circuit to generate a number of bits whose values ​​correspond to the voltage level of the sampled output. The duration of the resolution period and the number of bits generated vary with the type of analog-to-digital circuit employed. In various embodiments, the sum of the sampling period and the resolution period for the analog-to-digital converter circuit included in a given sub-ADC may be less than or equal to the active time of a corresponding one of the buffer clocks 405.

[0046] The individual analog-to-digital converter circuits included in sub-ADCs 402A-402D may be implemented as flash ADCs, successive approximation ADCs, or any other suitable type of analog-to-digital converter circuits. Although only four ADCs are depicted as included in sub-ADCs 402A-402D, any suitable number of analog-to-digital converter circuits may be employed in other embodiments. In such cases, clock generation circuit 404 would be configured to generate the necessary number of ADC clock signals.

[0047] Clock generation circuit 404 is configured to generate buffer clock 405 and ADC clocks 406A and 406B. In various embodiments, clock generation circuit 404 may be implemented using a phase-locked loop circuit, a delay-locked loop circuit, a delay circuit, or any other type of circuit suitable for generating multiple clock signals with different phases.

[0048] Go to Figure 5 , depicts a block diagram of a recovery circuit 500. As illustrated, the recovery circuit 500 includes an offset circuit 501, a feed-forward equalization circuit (denoted as "FFE circuit 502"), a data recovery circuit 503, a clock recovery circuit 505, and a logic circuit 506. Note that in various implementations, the recovery circuit 500 may correspond to either the recovery circuit 104 or the recovery circuit 202.

[0049] The offset circuit 501 is configured to generate adjusted samples 507 using the offset coefficient 511 and the sample 504. Note that in various embodiments, the sample 504 may correspond to the odd sample 113A and the even sample 113B (or alternatively, the odd sample 203A and the even sample 203B). In various embodiments, the sample 504 may include a mismatch due to manufacturing variability across different ones of the sub-ADCs 402A-402D. In order to correct the mismatch, the offset circuit 501 may be configured to add an offset to each sample based on the offset coefficient 511 and multiply each sample by a gain factor specified by the offset coefficient 511. Note that in the presence of a serializer circuit, an operation to correct the mismatch may be performed before serialization so that the sample is corrected before being serialized. In some embodiments, the offset circuit 501 may also perform a saturation function to prevent any of the adjusted samples 507 from going out of range during the adjustment process.

[0050] The FFE circuit 502 is configured to perform a feed-forward equalization operation on the adjusted sample 507 using the FFE coefficient 512 to generate the equalized sample 508. The FFE circuit 502 may be configured to generate a delayed version of the adjusted sample 507. The FFE circuit 502 may also be configured to combine the delayed version of the adjusted sample 507 according to the offset coefficient 511 to generate the equalized sample 508. It should be noted that there are numerous techniques that can be used to perform feed-forward equalization, and in various embodiments, the FFE circuit 502 may be configured to employ any suitable technique. In various embodiments, the FFE circuit 502 may be implemented as a digital finite impulse response (FIR) filter.

[0051] Data recovery circuit 503 is configured to generate recovered data symbols 111 using equalized samples 508 and odd DFE coefficients 513A and even DFE coefficients 513B. In various embodiments, data recovery circuit 503 may be configured to perform decision feedback equalization operations as part of generating recovered data symbols 111. Note that there are numerous techniques that may be used to recover data symbols from equalized samples 508, and in various embodiments, data recovery circuit 503 may be configured to employ any suitable technique for data recovery. Note also that in some embodiments, only a single set of DFE coefficients may be employed.

[0052] The clock recovery circuit 505 includes an oscillator circuit 513 and is configured to generate a recovered clock signal 112 using the equalized samples 508 and the recovered data symbols 111. In various embodiments, the oscillator circuit 513 is a voltage-controlled oscillator circuit having two control ports. The signal for one of the control ports is adjusted in response to a change in the phase error indication derived from the equalized samples 508 and the recovered data symbols 111. This control path is referred to as a "proportional" path. In other embodiments, the oscillator circuit 513 may include a single control port, and information corresponding to both the proportional path and the integral path may be combined for use with the single control port. Note that, depending on the frequency of the signal generated by the oscillator circuit 513, a frequency divider circuit may be employed.

[0053] Logic circuit 506 is configured to generate offset coefficients 511, FFE coefficients 512, odd DFE coefficients 513A, and even DFE coefficients 513B using recovered data symbols 111 and equalized samples 508. For example, in some embodiments, logic circuit 506 may be configured to adapt the FFE, DFE, and offset coefficients using a least mean square (LMS) algorithm or any suitable adaptation algorithm.

[0054] Please note that Figure 5The embodiments of the recovery circuit 104 depicted in FIG. 1 are merely examples. In other embodiments, different circuit blocks and different configurations of these circuit blocks are possible and contemplated. For example, in some cases, feed-forward equalization may be omitted, or differently adjusted samples may be used for the data recovery circuit and the clock recovery circuit.

[0055] As described above, receiver circuits, such as receiver circuits 100 and 200 , may be employed in a computer system. Figure 6 A block diagram of an embodiment of such a computer system is depicted in As illustrated, computer system 600 includes devices 601 and 602 coupled via a communication bus 607 .

[0056] Device 601 includes circuit block 603 and transmitter circuit 604. In various embodiments, device 601 may be a processor circuit, a processor core, a memory circuit, or any other suitable circuit block on an integrated circuit that may be included in a computer system. Note that while device 601 depicts only a single circuit block and a single transmitter circuit, in other embodiments, additional circuit blocks and additional transmitter circuits may be employed.

[0057] Transmitter circuit 604 is configured to serially transmit a signal corresponding to data received from circuit block 603 via communication bus 607. Such a signal may differentially encode one or more bits such that at a particular point in time, the difference between the respective voltage levels of lines 608A and 608B corresponds to a particular bit value. In some cases, generation of the signal may include encoding the bits prior to transmission. Note that while communication bus 607 is depicted as including two lines, any suitable number of lines may be employed in other embodiments.

[0058] Device 602 includes receiver circuit 605 and circuit block 606. Similar to device 601, device 602 may be a processor circuit, a processor core, a memory circuit, or any other suitable circuit block configured to receive data from transmitter circuit 604. In various embodiments, receiver circuit 605 may correspond to Figure 1 The receiver circuit 100 depicted in Figure 2 Receiver circuit 200 depicted in .

[0059] In some embodiments, devices 601 and 602 may be fabricated on a common integrated circuit. In other embodiments, devices 601 and 602 may be located on different integrated circuits mounted on a common substrate or circuit board. In such cases, communication bus 607 may include metal or other conductive traces on the substrate or circuit board. Although only two devices are depicted in computer system 600, any suitable number of devices may be employed in other embodiments.

[0060] In summary, various embodiments of a receiver circuit for a computer system are disclosed. Broadly speaking, a device is envisioned in which a front-end circuit is configured to generate an equalized signal using a plurality of signals encoding a serial data stream including a plurality of data symbols. The sampling circuit includes a first plurality of analog-to-digital converter circuits and a second plurality of analog-to-digital converter circuits. The first plurality of analog-to-digital converter circuits are configured to sample the equalized signal using a recovered clock signal and a first threshold at a time corresponding to an odd-numbered data symbol in a plurality of data symbols to generate a first plurality of samples. The second plurality of analog-to-digital converter circuits are configured to sample the equalized signal using the recovered clock signal and a second threshold at a time corresponding to an even-numbered data symbol in the plurality of data symbols to generate a second plurality of samples. The recovery circuit is configured to process the first plurality of samples and the second plurality of samples to generate a plurality of recovered data symbols.

[0061] In other embodiments, the first plurality of analog-to-digital converter circuits are configured to sample the equalized signal using the recovered clock signal at times corresponding to odd-numbered data symbols in the plurality of data symbols to generate a first plurality of samples. The second plurality of analog-to-digital converter circuits are configured to sample the equalized signal using the recovered clock signal at times corresponding to even-numbered data symbols in the plurality of data symbols to generate a second plurality of samples. The recovery circuit is configured to process the first plurality of samples using a first set of coefficients and process the second plurality of samples using a second set of coefficients to generate a plurality of recovered data symbols.

[0062] Go to Figure 7 , depicts a flow chart depicting an embodiment for operating a receiver circuit for a serial data stream. The method, which may be applied to various receiver circuits, such as receiver circuit 100 , begins at block 701 .

[0063] The method includes generating an equalized signal using at least one signal encoding a serial data stream including a plurality of data symbols (block 702). In some embodiments, generating the equalized signal includes filtering the at least one signal to generate a filtered signal, and adjusting a magnitude of the filtered signal to generate the equalized signal.

[0064] The method also includes sampling, by a first plurality of analog-to-digital converter circuits, the equalized signal at times corresponding to odd-numbered data symbols to generate a first plurality of samples (block 703). In various embodiments, sampling, by the first plurality of analog-to-digital converter circuits, the equalized signal includes sampling, by the first plurality of analog-to-digital converter circuits, the equalized signal using corresponding sampling clock signals in a plurality of sampling clock signals to generate corresponding sets of first samples. In some embodiments, the plurality of sampling clock signals are based on the recovered clock signal, wherein a given sample included in a particular set of the corresponding sets of first samples is aligned with a corresponding one of the plurality of sampling clock signals.

[0065] The method also includes sampling, by a second plurality of analog-to-digital converter circuits, the equalized signal at times corresponding to even-numbered data symbols to generate a second plurality of samples (block 704). In various embodiments, sampling, by the second plurality of analog-to-digital converter circuits, the equalized signal includes sampling, by the second plurality of analog-to-digital converter circuits, the equalized signal using corresponding sampling clock signals of the plurality of sampling clock signals to generate corresponding sets of second samples.

[0066] In some embodiments, sampling the equalized signal includes: sampling the equalized signal by a plurality of buffer circuits using corresponding buffer clock signals among a plurality of buffer clock signals to generate a corresponding plurality of buffer samples; and quantizing corresponding buffer samples among the corresponding plurality of buffer samples by a first plurality of analog-to-digital converter circuits to generate the corresponding set of samples.

[0067] In some embodiments, the method may include generating a plurality of retimed samples using the corresponding set of first samples and a different clock signal having a frequency different from respective frequencies of the plurality of sampling clock signals.

[0068] The method also includes generating a plurality of recovered data symbols using the first plurality of samples and the second plurality of samples (block 705). In some embodiments, the method also includes generating a recovered clock signal using the first plurality of samples and the second plurality of samples. In various embodiments, the method also includes generating the plurality of sampling clock signals using the recovered clock signal.

[0069] Please note that Figure 8 One or more operations depicted in the flowchart may be included in Figure 7 The method ends in block 706.

[0070] Go to Figure 8, depicts a flow chart depicting embodiments of different methods for operating a receiver circuit for a serial data stream. The method, which may be applied to various receiver circuits (such as receiver circuit 200 ), begins at block 801 .

[0071] The method includes generating an equalized signal using at least one signal encoding a serial data stream including a plurality of data symbols (block 802).

[0072] The method also includes sampling, by a first plurality of analog-to-digital converter circuits, the equalized signal at times corresponding to odd-numbered data symbols to generate a first plurality of samples (block 803).

[0073] The method also includes sampling, by a second plurality of analog-to-digital converter circuits, the equalized signal at times corresponding to even-numbered data symbols to generate a second plurality of samples (block 804).

[0074] The method also includes generating a plurality of recovered data symbols by processing the first plurality of samples using a first set of coefficients and processing the second plurality of samples using a second set of coefficients (block 805). In various embodiments, generating the plurality of recovered data symbols includes performing a first decision feedback equalization operation on the first plurality of samples using the first set of coefficients and performing a second decision feedback equalization operation on the second plurality of samples using the second set of coefficients. In various embodiments, the first set of coefficients and the second set of coefficients are based on which sub-ADCs generated the first plurality of symbols and the second plurality of symbols. In some cases, the first set of coefficients and the second set of coefficients may also be based on sampling thresholds used by the sub-ADCs to generate the first plurality of symbols and the second plurality of symbols.

[0075] Please note that from Figure 7 One or more steps of the method described in the flowchart may include Figure 8 The method ends in block 806.

[0076] exist Fig. 9 A block diagram of a system on a chip (SoC) is illustrated in . In the illustrated embodiment, SoC 900 includes processor circuitry 901, memory circuitry 902, analog / mixed signal circuitry 903, and input / output circuitry 904, each of which is coupled to a communication bus 905. In various embodiments, SoC 900 may be configured for use in a desktop computer, a server, or in a mobile computing application such as, for example, a tablet computer, a laptop computer, or a wearable computing device.

[0077] In various embodiments, processor circuit 901 may represent a general purpose processor that performs computing operations. For example, processor circuit 901 may be a central processing unit (CPU) such as a microprocessor, a microcontroller, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA).

[0078] In various embodiments, memory circuit 902 may include any suitable type of memory, such as, for example, dynamic random access memory (DRAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or non-volatile memory. Fig. 9 A single memory circuit is illustrated in FIG. 1 , but in other embodiments, any suitable number of memory circuits may be employed.

[0079] The analog / mixed signal circuit 903 may include a crystal oscillator circuit, a phase-locked loop (PLL) circuit, an analog-to-digital converter (ADC) circuit, and a digital-to-analog converter (DAC) circuit (all not shown). In other embodiments, the analog / mixed signal circuit 903 may be configured to perform power management tasks by including an on-chip power supply and voltage regulator.

[0080] Input / output circuitry 904 may be configured to coordinate data transfers between SoC 900 and one or more peripheral devices. Such peripheral devices may include, but are not limited to, storage devices (e.g., magnetic or optical media based storage devices, including hard drives, tape drives, CD drives, DVD drives, etc.), audio processing subsystems, or any other suitable type of peripheral device. In some embodiments, input / output circuitry 904 may be configured to implement a Universal Serial Bus (USB) protocol or an IEEE 1394 The version of the agreement, and include Figure 1 The receiver circuit 100 depicted in Figure 2 Receiver circuit 200 depicted in .

[0081] The input / output circuitry 904 may also be configured to coordinate data transfers between the SoC 900 and one or more devices (e.g., other computing systems or integrated circuits) coupled to the SoC 900 via a network. In one embodiment, the input / output circuitry 904 may be configured to perform data processing required to implement an Ethernet (IEEE 802.3) networking standard such as, for example, Gigabit Ethernet or 10 Gigabit Ethernet, but it is contemplated that any suitable networking standard may be implemented. In some embodiments, the input / output circuitry 904 may be configured to implement a plurality of discrete network interface ports. In various embodiments, the input / output circuitry 904 includes a receiver circuit 906, which may correspond to, for example, a plurality of discrete network interface ports. Figure 1 and Figure 2The receiver circuit 100 or the receiver circuit 200 depicted in FIG.

[0082] Now go to Fig.10 , illustrates various types of systems that may include any of the circuits, devices, or systems described above. The system or device 1000, which may combine or otherwise utilize one or more of the techniques described herein, may be used in a wide range of fields. For example, the system or device 1000 may be used as part of the hardware of a system such as a desktop computer 1010, a laptop computer 1020, a tablet computer 1030, a cellular or mobile phone 1040, or a television 1050 (or a set-top box coupled to a television).

[0083] Similarly, the disclosed elements can be used in a wearable device 1060, such as a smart watch or a health monitoring device. In many embodiments, a smart watch can implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. A wearable device can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also contemplated, including devices worn around the neck, devices implantable in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0084] The system or device 1000 may also be used in various other environments. For example, the system or device 1000 may be used in the environment of a server computer system (such as a dedicated server) or on shared hardware that implements a cloud-based service 1070. Further, the system or device 1000 may be implemented in a wide range of dedicated everyday devices, including common devices 1080 in the home, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is often referred to as the "Internet of Things" (IoT). Elements may also be implemented in various modes of transportation. For example, the system or device 1000 may be used for control systems, guidance systems, entertainment systems, etc. of various types of vehicles 1090.

[0085] Fig.10 The applications illustrated in the examples are merely exemplary and are not intended to limit the potential future applications of the disclosed system or device. Other example applications include, but are not limited to: portable game devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0086] Fig.111 is a block diagram illustrating an example of a non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 1120 is configured to process design information 1115 stored on a non-transitory computer-readable storage medium 1110 and manufacture an integrated circuit 1130 based on the design information 1115.

[0087] The non-transitory computer-readable storage medium 1110 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1110 may be an installation medium, such as a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory, such as flash memory, a magnetic medium, for example, a hard drive or an optical storage device; a register, or other similar type of memory element, etc. The non-transitory computer-readable storage medium 1110 may include other types of non-transitory memory or a combination thereof. The non-transitory computer-readable storage medium 1110 may include two or more memory media that may reside in different locations, such as different computer systems connected by a network.

[0088] The design information 1115 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, and the like. The design information 1115 may be used by the semiconductor manufacturing system 1120 to manufacture at least a portion of the integrated circuit 1130. The format of the design information 1115 may be recognizable by at least one semiconductor manufacturing system, such as, for example, the semiconductor manufacturing system 1120. In some embodiments, the design information 1115 may include a netlist specifying elements of a cell library and their connectivity. One or more cell libraries used during logic synthesis of circuits included in the integrated circuit 1130 may also be included in the design information 1115. Such cell libraries may include information indicating a device or transistor level netlist, mask design data, characterization data, and the like of the cells included in the cell library.

[0089] In various embodiments, integrated circuit 1130 may include one or more custom macrocells, such as memory and analog or mixed signal circuits, etc. In this case, design information 1115 may include information related to the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to a graphic data system (GDSII) or any other suitable format.

[0090] Semiconductor manufacturing system 1120 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 1120 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0091] In various embodiments, the integrated circuit 1130 is configured to operate according to the circuit design specified by the design information 1115, which may include performing any of the functionality described herein. For example, the integrated circuit 1130 may include any of the various elements shown or described herein. In addition, the integrated circuit 1130 may be configured to perform various functions described herein in conjunction with other components. In addition, the functionality described herein may be performed by multiple connected integrated circuits.

[0092] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0093] ***

[0094] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," etc. are not necessarily to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the present disclosure.

[0095] The present disclosure may discuss potential advantages that may be generated by the disclosed embodiments. Not all of these implementations will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why an implementation that falls within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuits outside the scope of the present disclosure that, in combination with one of the disclosed embodiments, negate or reduce one or more of the disclosed advantages. In addition, suboptimal design execution of a particular implementation (e.g., a specific implementation technique or tool) may also negate or reduce the disclosed advantages. Even assuming a specific implementation of the technology, the realization of the advantages may still depend on other factors, such as the environmental conditions in which the specific implementation is deployed. For example, the input provided to a particular implementation may prevent one or more problems solved in the present disclosure from occurring in a particular occasion, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors external to the present disclosure, it is hereby clarified that any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from the present disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantage often depends on technical realities of additional factors.

[0096] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on the present disclosure, even if only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any contrary statement in the present disclosure. Therefore, the present application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications and equivalents, which will be apparent to those skilled in the art who are aware of the beneficial effects of the present disclosure.

[0097] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined, where appropriate, with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may be combined, where appropriate.

[0098] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent upon a single other claim, additional dependencies are also contemplated. Any combination of dependent claims consistent with the present disclosure is contemplated and may be claimed in this or another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0099] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0100] ***

[0101] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0102] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim does not exclude additional instances of that item without the accompanying context. A "plurality" of an item refers to a collection of two or more of the items.

[0103] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0104] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0105] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0106] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0107] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "a first circuit," "a second circuit," "a particular circuit," "a given circuit," etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0108] The phrase "based on" is used to describe one or more factors that influence a determination. The term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based only on specified factors or on specified factors and other unspecified factors. Consider the phrase "A is determined based on B." The phrase specifies that B is a factor used to determine A or that B influences the determination of A. The phrase does not exclude that the determination of A may also be based on some other factor such as C. The phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0109] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, the effect may be responsive to these factors alone, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "A is performed in response to B." The phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. The phrase does not exclude that the execution of A may also be responsive to certain other factors, such as C. The phrase also does not exclude that the execution of A may be performed jointly in response to B and C. The phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0110] ***

[0111] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. The expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be "configured to" perform a task even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, and a memory storing executable program instructions, etc. The phrase is not used herein to refer to an intangible thing.

[0112] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0113] The term "configured to" is not intended to mean "capable of being configured to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function. After being appropriately programmed, the FPGA may then be considered "configured to" perform a particular function.

[0114] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing the function]” construct to phrase the claim element.

[0115] Different "circuits" may be described in the present disclosure. These circuits or "circuits" constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or taken from a standard library. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuits.

[0116] Thus, the disclosed circuits / units / components and other elements illustrated in the drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode for an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For one skilled in the computer arts, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0117] In various embodiments, as described in the preceding paragraphs, circuits, units, and other elements may be defined by the functions or operations they are configured to implement. The arrangement relative to each other and such circuits / units / components and the way they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall into the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can implement the structure by coding a description of a circuit / unit / component in a hardware description language (HDL) such as Verilog or VHDL without excessive experimentation and using the application of ordinary technicians. HDL descriptions are often expressed in a way that can be displayed as functional. However, for those skilled in the art, the HDL description is a way to transform the structure of a circuit, unit, or component into the next level of specific implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized for a library of cells designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design along with the synthesized circuits. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to a situation where a circuit or logic designer never specifies a particular set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0118] The fact that many different low-level combinations of circuit elements can be used to achieve the same specification of a circuit results in a large number of identical structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries provided for a particular project, etc. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0119] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

[0120] Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to include all such variations and modifications.

Claims

1. A device, comprising: a front end circuit configured to generate an equalized signal using a plurality of signals encoding a serial data stream including a plurality of data symbols; a sampling circuit comprising a first plurality of analog-to-digital converter circuits and a second plurality of analog-to-digital converter circuits, wherein the first plurality of analog-to-digital converter circuits are configured to sample the equalized signal at times corresponding to odd-numbered data symbols of the plurality of data symbols using a recovered clock signal to generate a first plurality of samples, and wherein the second plurality of analog-to-digital converter circuits are configured to sample the equalized signal at times corresponding to even-numbered data symbols of the plurality of data symbols using the recovered clock signal to generate a second plurality of samples; and A recovery circuit is configured to process the first plurality of samples and the second plurality of samples to generate a plurality of recovered data symbols.

2. The apparatus of claim 1 , wherein the first plurality of analog-to-digital converter circuits are further configured to sample the equalized signal using corresponding sampling clock signals in a first plurality of sampling clock signals to generate corresponding sets of a first plurality of samples, wherein the first plurality of sampling clock signals are based on the recovered clock signal, and wherein a given sample included in a particular set of the first plurality of samples is aligned with a corresponding one of the first plurality of sampling clock signals. 3 . The apparatus of claim 2 , wherein the sampling circuit is further configured to generate the plurality of sampling clock signals using the recovered clock signal.

4. The apparatus of claim 2 , further comprising a retimer circuit configured to generate a first plurality of retimed samples using the first plurality of samples and a different clock signal, wherein a frequency of the different clock signal is different from a corresponding frequency of the first plurality of sampling clock signals.

5. The apparatus of claim 2 , wherein the sampling circuit further comprises a plurality of buffer circuits configured to sample the equalized signal based on corresponding buffer clock signals in a plurality of buffer clock signals to generate a corresponding plurality of buffered samples, and wherein the first plurality of analog-to-digital converter circuits are configured to quantize corresponding buffered samples in the corresponding plurality of buffered samples to generate the corresponding sets of first plurality of samples.

6. The apparatus of claim 1 , wherein to generate the equalized signal, the front-end circuit is further configured to: filtering the plurality of signals to generate a filtered signal; and The magnitude of the filtered signal is adjusted to generate the equalized signal.

7. A method comprising: generating an equalized signal using at least one signal encoding a serial data stream including a plurality of data symbols; sampling, by a first plurality of analog-to-digital converter circuits, the equalized signal at times corresponding to odd-numbered data symbols using a first threshold to generate a first plurality of samples; sampling, by a second plurality of analog-to-digital converter circuits, the equalized signal at times corresponding to even-numbered data symbols using a second threshold to generate a second plurality of samples; as well as A plurality of recovered data symbols are generated using the first plurality of samples and the second plurality of samples.

8. The method of claim 7, further comprising generating a recovered clock signal using the first plurality of samples and the second plurality of samples, and wherein generating the equalized signal comprises: filtering the at least one signal to generate a filtered signal; as well as The magnitude of the filtered signal is adjusted to generate the equalized signal.

9. The method of claim 8, wherein sampling, by the first plurality of analog-to-digital converter circuits, the equalized signal using the first threshold comprises: The equalized signal is sampled by the first plurality of analog-to-digital converter circuits using corresponding sampling clock signals of a plurality of sampling clock signals to generate the corresponding sets of samples, wherein the plurality of sampling clock signals are based on the recovered clock signal, and wherein a given sample included in a particular set of the corresponding sets of samples is aligned with a corresponding one of the plurality of sampling clock signals.

10. The method of claim 9, further comprising generating the plurality of sampling clock signals using a recovered clock signal.

11. The method of claim 10, further comprising generating a plurality of retimed samples using the corresponding sets of samples and a different clock signal, wherein the different clock signal has a frequency different from respective frequencies of the plurality of sampling clock signals.

12. The method of claim 11, wherein sampling the equalized signal comprises: sampling, by a plurality of buffer circuits, the equalized signal using corresponding buffer clock signals of a plurality of buffer clock signals to generate a corresponding plurality of buffered samples; as well as Respective buffered samples of the corresponding plurality of buffered samples are quantized by a subset of the first plurality of analog-to-digital converter circuits and the second plurality of analog-to-digital converter circuits to generate the corresponding set of samples.

13. The method of claim 11, wherein generating the plurality of recovered data symbols comprises performing a feed-forward equalization operation using the corresponding set of samples.

14. A device, comprising: a front end circuit configured to generate an equalized signal using a plurality of signals encoding a serial data stream including a plurality of data symbols; a sampling circuit comprising a first plurality of analog-to-digital converter circuits and a second plurality of analog-to-digital converter circuits, wherein the first plurality of analog-to-digital converter circuits are configured to sample the equalized signal at times corresponding to odd-numbered data symbols of the plurality of data symbols using a recovered clock signal to generate a first plurality of samples, and wherein the second plurality of analog-to-digital converter circuits are configured to sample the equalized signal at times corresponding to even-numbered data symbols of the plurality of data symbols using the recovered clock signal to generate a second plurality of samples; and A recovery circuit is configured to process the first plurality of samples using a first set of coefficients and to process the second plurality of samples using a second set of coefficients to generate a plurality of recovered data symbols.

15. The apparatus of claim 14, wherein the first plurality of analog-to-digital converter circuits are further configured to sample the equalized signal using corresponding sampling clock signals in a first plurality of sampling clock signals to generate corresponding sets of a first plurality of samples, wherein the first plurality of sampling clock signals are based on the recovered clock signal, and wherein a given sample included in a particular set of the first plurality of samples is aligned with a corresponding one of the first plurality of sampling clock signals. 16 . The apparatus of claim 15 , wherein the sampling circuit is further configured to generate the first plurality of sampling clock signals using the recovered clock signal.

17. The apparatus of claim 15, further comprising a retimer circuit configured to generate a first plurality of retimed samples using the first plurality of samples and a different clock signal, wherein a frequency of the different clock signal is different from a corresponding frequency of the first plurality of sampling clock signals.

18. The apparatus of claim 15 , wherein the sampling circuit further comprises a plurality of buffer circuits configured to sample the equalized signal based on corresponding buffer clock signals in a plurality of buffer clock signals to generate a corresponding plurality of buffered samples, and wherein the first plurality of analog-to-digital converter circuits are configured to quantize corresponding buffered samples in the corresponding plurality of buffered samples to generate the corresponding set of first samples.

19. The apparatus of claim 14, wherein to process the first plurality of samples, the recovery circuit is further configured to perform a decision feedback equalization operation on the first plurality of samples using the first set of coefficients, and to perform a second decision feedback equalization operation on the second plurality of samples using the second set of coefficients.

20. The apparatus of claim 14, wherein to generate the equalized signal, the front-end circuit is further configured to: filtering the plurality of signals to generate a filtered signal; and The magnitude of the filtered signal is adjusted to generate the equalized signal.

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