Current measurement system

Abstract

The present disclosure relates to a current measurement system for a digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage, the output voltage of the digital LDO being dependent on a first DAC code signal, the current measurement system comprising a current determination unit configured to receive the first DAC code signal, and generate an output current signal using the first DAC code signal.

Description

[0001] The present disclosure relates to a current measurement system. In particular, the present disclosure relates to a current measurement system for a digital low dropout regulator (LDO).

[0002] background

[0003] Figure 1A A digital LDO 100 known in the prior art (Jun Liu et al., A Fully-Synthesizable 0.6V Digital LDOwith Dual-Loop Control using Digital Standard Cells, 2016 14th IEEE International Conference on New Circuits and Systems (NEWCAS), Vancouver, BC, Canada, 2016, pp. 1-4) is shown.

[0004] LDO 100 includes a main comparator 102; shift registers 104, 106; a counter 108; a buffer 110; transistors 112, 114, 116, 118; a panic circuit 120 including comparators 122, 124 and a logic block 126; a clock circuit 128 including a multiplexer 130 and a frequency scaler 132; and a capacitor Co having an equivalent series resistance (ESR) Ro.

[0005] The LDO 100 uses a coarse digital-to-analog converter (DAC) 134 and a fine DAC 136 , each driven by an up-down counter 104 , 106 and a clocking scheme 128 that times the response to a “panic” detected by a window comparator provided by the panic circuit 120 .

[0006] The main control loop is a single comparator 102 (or 1-bit ADC) that compares the feedback voltage VFB derived from the output voltage VLDO with the target voltage VREF.

[0007] The operation of the up-down counters 104, 106 acts as an integrating function of the error signal CMP, so that the stability of the loop depends on the zeroing of the external decoupling capacitor Co, which has an ESR denoted by Ro.

[0008] When a “panic” is detected, i.e., the output voltage VLDO has exceeded the range defined by the window comparator 120, the coarse up-down counter 104 and the fine up-down counter 106 are clocked at the full clock speed CLK, and the output current is ramped towards a new target value (up or down) under the control of the main comparator output CMP.

[0009] Since the output of the DAC 134, 136 is essentially a current source provided by the transistors 112, 114, 116, 118, the output voltage VLDO is the integral of this current, so the control is 90° phase shifted relative to the output voltage VLDO. Typically, the result is a limit cycle of the DAC code. Since the capacitor Co has a certain ESR (denoted by Ro), the amplitude of the limit cycling period is reduced to a stable state. However, the "panic" mode fast timing is one timing cycle, which is 32 clock cycles in this example. When the "panic" fast timing times out, the fine loop 136 operates at 1 / 32 of the clock speed.

[0010] The coarse DAC output and fine DAC output are controlled using a current mirror scheme. This has two benefits:

[0011] 1. It aligns the switching operation and the dynamics of the LDO and makes the performance as expected.

[0012] 2. It reduces the PSRR sensitivity of the output stage.

[0013] Figure 1B It is a schematic diagram of a current mirror scheme 138 for controlling coarse and fine DAC outputs as known in the prior art (Xiangyu Mao et al., A 1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization and Auxiliary Constant Current Control Achieving High Accuracy and Fast DVS, IEEE Transactions on Circuits and Systems-I: General Papers, Vol. 69, No. 11, November 2022).

[0014] The current mirror scheme 138 includes a transistor 140 , a current source 142 , a capacitor 144 , an amplifier 146 , and an absorption buffer 148 .

[0015] Overview

[0016] It is desired to measure the output current of a digital LDO.

[0017] According to a first aspect of the present disclosure, a current measurement system for a digital low dropout regulator (LDO) is provided, wherein the digital LDO is used to receive a reference voltage and generate an output voltage, wherein the output voltage of the digital LDO depends on a first DAC code signal, and the current measurement system includes a current determination unit, which is configured to receive the first DAC code signal and generate an output current signal using the first DAC code signal.

[0018] Optionally, the LDO includes a comparison circuit and a first digital-to-analog converter, the comparison circuit being configured to receive a reference voltage, receive a feedback voltage, the feedback voltage depending on the output voltage, compare the reference voltage and the feedback voltage, and generate an error signal depending on the comparison between the reference voltage and the feedback voltage, the first digital-to-analog converter being configured to receive the error signal and generate a first DAC code signal based on the error signal.

[0019] Optionally, the comparison circuit includes a main comparator or a 1-bit analog-to-digital converter.

[0020] Optionally, the first digital-to-analog converter comprises a first shift register configured to generate a first DAC code signal.

[0021] Optionally, the first shift register comprises an up-down counter.

[0022] Optionally, the first digital-to-analog converter includes a plurality of first current sources, and each of the first current sources is used as 1 bit of the first DAC code signal.

[0023] Optionally, each first current source comprises a first transistor.

[0024] Optionally, the first shift register comprises a plurality of outputs, each output being associated with a single bit of the first DAC code signal and coupled to a gate of one of the plurality of first transistors.

[0025] Optionally, the first digital-to-analog converter comprises a plurality of first buffer circuits, and each output is coupled to a gate of one of the plurality of first transistors via the buffer circuit.

[0026] Optionally, each first buffer circuit includes a first inverter.

[0027] Optionally, the digital LDO includes an output capacitor having an equivalent series resistance, and the first DAC signal is provided to the output capacitor to generate the output voltage.

[0028] Optionally, the current determination unit is configured to generate the output current signal by calculating the output current using the first DAC code signal and providing the output current signal using the calculated output current.

[0029] Optionally, the current determination unit is configured to calculate the output current by multiplying the first DAC code signal by a first variable.

[0030] Optionally, the current measurement system comprises an average current determination unit configured to receive the output current signal and to provide an average output current signal.

[0031] Optionally, the average current determination unit comprises a low pass filter.

[0032] Optionally, the low pass filter comprises an infinite impulse response (IIR) filter.

[0033] Optionally, the current measurement system comprises a warning circuit for indicating when the output current exceeds a first threshold current value or falls below a second threshold current value.

[0034] Optionally, the digital LDO includes: a panic circuit configured to detect when a feedback voltage exceeds a first threshold voltage value or drops below a second threshold voltage value, and when the feedback voltage exceeds the first threshold voltage value or drops below the second threshold voltage value, control the first digital-to-analog converter to operate in a panic mode; and a clock circuit configured to provide a clock signal to the comparison circuit, operate in a fast mode by providing the clock signal at a first frequency during the panic mode, and operate in a slow mode by providing the clock signal at a second frequency when not in the panic mode, the second frequency being less than the first frequency, wherein when the clock circuit operates in the slow mode, the warning circuit is configured to indicate when the output current exceeds the first threshold current value or drops below the second threshold current value.

[0035] Optionally, the panic circuit is configured to output a panic signal in response to detecting that the feedback voltage exceeds a first threshold voltage value or drops below a second threshold voltage value, the panic signal being used to switch the first digital-to-analog converter to a panic mode.

[0036] Optionally, the panic circuit comprises a first comparator configured to compare the feedback voltage with a first threshold voltage value and a second comparator configured to compare the feedback voltage with a second threshold voltage value.

[0037] Optionally, the panic circuit comprises a logic circuit configured to receive the outputs of the first comparator and the second comparator and to provide a panic signal in response to the first comparator output and the second comparator output indicating that the feedback voltage has exceeded a first threshold voltage value or has fallen below a second threshold voltage value.

[0038] Optionally, the digital LDO includes a counter circuit configured to receive the panic signal and the error signal, wherein the first digital-to-analog converter includes a first shift register configured to generate the first DAC code signal, and the counter circuit is further configured to increment the first shift register when the first digital-to-analog converter operates in the panic mode.

[0039] Optionally, the clock circuit includes a multiplexer and a frequency scaling unit for receiving an input clock signal, the clock circuit is configured to provide the input clock signal as the clock signal during a fast mode, and the frequency scaling unit is configured to reduce the frequency of the input clock signal when generating the clock signal during a slow mode.

[0040] Optionally, the current measurement system includes a current mirror configured to control the coarse and fine DAC outputs.

[0041] Optionally, the digital LDO comprises a second digital-to-analog converter configured to receive the error signal and generate a second DAC code signal based on the error signal, the output voltage depending on the second DAC code signal.

[0042] Optionally, the first digital-to-analog converter provides coarse control of the output voltage and the second digital-to-analog converter provides fine control of the output voltage.

[0043] Optionally, the current determination unit is configured to generate the output current signal using the second DAC code signal.

[0044] Optionally, the second digital-to-analog converter comprises a second shift register configured to generate a second DAC code signal.

[0045] Optionally, the second shift register comprises an up-down counter.

[0046] Optionally, the second digital-to-analog converter includes a plurality of second current sources, wherein each second current source is used as 1 bit of the second DAC code signal.

[0047] Optionally, each second current source comprises a second transistor.

[0048] Optionally, the second shift register comprises a plurality of outputs, each output being associated with a single bit of the second DAC code signal and coupled to a gate of one of the plurality of second current sources.

[0049] Optionally, the second digital-to-analog converter comprises a plurality of second buffer circuits, and each output is coupled to a gate of one of the plurality of second current sources via the buffer circuit.

[0050] Optionally, each second buffer circuit includes a second inverter.

[0051] Optionally, the digital LDO includes an output capacitor having an equivalent series resistance, and the first DAC signal and the second DAC signal are provided to the output capacitor to generate an output voltage.

[0052] Optionally, the current determination unit is configured to generate the output current signal by calculating the output current using the first DAC code signal and the second DAC code signal and providing the output current signal using the calculated output current.

[0053] Optionally, the current determination unit is configured to calculate the output current by adding: a multiplication of the first DAC code signal and the first variable and a multiplication of the second DAC code signal and the second variable.

[0054] According to a second aspect of the present disclosure, a voltage regulator system is provided, which includes a digital low dropout regulator (LDO) and a current measurement system, the digital LDO is used to receive a reference voltage and generate an output voltage, and the current measurement system includes a current determination unit, which is configured to receive a first DAC code signal, the output voltage of the digital LDO depends on the first DAC code signal, and use the first DAC code signal to generate an output current signal.

[0055] It will be appreciated that the voltage regulator of the second aspect may include the features set out in the first aspect, and may be combined with other features described herein.

[0056] According to a third aspect of the present disclosure, a method for measuring current from a digital low dropout regulator (LDO) is provided, wherein the digital LDO is used to receive a reference voltage and generate an output voltage, the output voltage of the digital LDO depends on a first DAC code signal, the method comprising receiving the first DAC code signal at a current determination unit, and using the current determination unit to generate an output current signal using the first DAC code signal.

[0057] It will be appreciated that the method of the third aspect may include features set out in the first aspect and / or the second aspect, and may be combined with other features described herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The present disclosure is described in more detail below by way of example and with reference to the accompanying drawings, in which:

[0060] Figure 1A A digital LDO known in the prior art is shown. Figure 1B is a schematic diagram of a current mirror scheme known in the prior art for controlling coarse and fine DAC outputs;

[0061] Figure 2A is a schematic diagram of a current measurement system for a digital LDO according to a first embodiment of the present disclosure, Figure 2B is a schematic diagram of a current measurement system together with a specific example of an LDO, Figure 2C Yes Figure 2B A schematic diagram of a specific embodiment of an LDO shown;

[0062] Figure 3A is a schematic diagram of a current measurement system according to a second embodiment of the present disclosure, Figure 3B is a schematic diagram of a current measurement system showing a specific embodiment of an average current determination unit, Figure 3C is a schematic diagram of a current measurement system according to a third embodiment of the present disclosure, Figure 3Dis a timing diagram showing an example operation of the warning circuit, wherein the output current signal varies with time, Figure 3E is a schematic diagram of a current measurement system according to a fourth embodiment of the present disclosure;

[0063] Figure 4A According to the fifth embodiment of the present disclosure Figure 3C A schematic diagram of a specific embodiment of a current measurement system used together with an LDO, Figure 4B According to the sixth embodiment of the present disclosure, the current measuring system (eg Figure 3C A schematic diagram of a specific embodiment of an LDO used in conjunction with a current measurement system of FIG. Figure 4C is a clock circuit according to the present disclosure;

[0064] Figure 5 According to the seventh embodiment of the present disclosure Figure 2A A schematic diagram of a specific embodiment of an LDO used in conjunction with a current measurement system;

[0065] Figure 6 is a schematic diagram of a digital LDO and a current measurement system according to an eighth embodiment of the present disclosure;

[0066] Fig. 7A is a block diagram of an IIR filter that can be implemented in a current measurement system to provide an average output current signal, Figure 7B is a schematic diagram of an IIR filter including a comparator; and

[0067] Figure 8 is a diagram showing simulation results of an actual implementation of an IIR filter.

[0068] Detailed Description

[0069] Figure 2A 2 is a schematic diagram of a current measurement system 200 for a digital LDO 202 according to a first embodiment of the present disclosure. During operation, the digital LDO 202 receives a reference voltage Vref and generates an output voltage Vout. The output voltage Vout of the digital LDO 202 depends on a DAC code signal 204.

[0070] The current measurement system 200 includes a current determination unit 206 configured to receive the DAC code signal 204 and generate an output current signal 207 using the DAC code signal 204 .

[0071] The current measurement system 200 may calculate the output current by performing a calculation using the DAC code signal 204 to generate an output current signal 207 , wherein the output current signal 207 is generated using the calculated output current.

[0072] The output current may also be referred to as a load current, where the load current is the current provided to the circuit components during operation of the LDO 202 .

[0073] For example, the output current may be calculated by multiplying the DAC code signal 204 by a variable, which may be represented by the following equation:

[0074] Iout=qq×v1 (1)

[0075] Where Iout is the output current, qq is the DAC code signal 204, and v1 is a variable.

[0076] For example, if it is known that each bit of the DAC code signal 216 indicates a 10 mA current, then making v1 = 10 mA will provide an output current Iout.

[0077] Figure 2B is a schematic diagram of a current measurement system 200 along with a specific example of an LDO 202 that includes a comparison circuit 208 configured to receive a reference voltage Vref and a feedback voltage Vfb. The feedback voltage Vfb depends on the output voltage Vout of the LDO 202. For example, in a specific embodiment, the feedback voltage Vfb may be equal to the output voltage Vout, and in another specific embodiment, the feedback voltage Vfb may be a scaled-down version of the output voltage Vout.

[0078] In operation, the comparison circuit 208 compares the reference voltage Vref and the feedback voltage Vfb, and then generates an error signal 210, which depends on the comparison between the voltages Vref and Vfb. The comparison circuit 208 can, for example, include a main comparator or a 1-bit analog-to-digital converter. The error signal 210 can indicate the difference between the voltages Vref and Vfb.

[0079] LDO 202 also includes a digital-to-analog converter (DAC) 212 that receives the error signal 210 and generates a DAC code signal 204 based on the error signal 210 .

[0080] Figure 2C Yes Figure 2B A schematic diagram of a specific embodiment of the LDO 202 is shown, and as will be appreciated by skilled artisans, the LDO 202 may be used with any of the current measurement systems described herein.

[0081] The DAC 212 includes a shift register 214 configured to generate the DAC code signal 204. The shift register 214 may include an up-down counter.

[0082] DAC 212 may include multiple current sources 216, 218, wherein each current source 216, 218 is used for 1 bit of DAC code signal 204. It should be understood that in the present embodiment, two current sources 216, 218 are shown, and other embodiments may include additional current sources according to the understanding of the skilled person. Current source 216 includes transistor 220, and current source 218 includes transistor 222.

[0083] The shift register 214 provides a plurality of outputs 219. Each output 219 is associated with a single bit of the DAC code signal 204 and is coupled to the gate of one of the transistors 220,222.

[0084] The DAC 212 accepts a binary "word" (a number of bits with scaled weights). The DAC 212 can perform a binary to thermometer decode, for example:

[0085]

[0086] Thus, there is one output current source for each bit of the DAC code signal 204. A thermometer is easier to drive and match than a binary weighted current source, but mathematically they are identical. The shift register 214 can generate a thermometer count, which is often referred to as a "walking one".

[0087] The DAC code signal 204 may be provided by the output 219 of the shift register 214. For example, if one output is 0 and the other output is 1, the value of the DAC code signal 204 may be 01. In this example, the DAC code signal 204 may be a single signal indicating the value 01, or it may be formed by two different signals, one having a value of 0 and the other having a value of 1, and the two signals together forming the DAC code signal 204. Bit values ​​may also be extracted from the current sources 216, 218 to provide the DAC code signal 204.

[0088] DAC 212 includes buffer circuits 224, 226, wherein each output 219 is coupled to a gate via one of the buffer circuits 224, 226. Buffer circuits 224, 226 may each include an inverter. In this embodiment, buffer circuit 224 includes inverter 228, and buffer circuit 226 includes inverter 230.

[0089] LDO 202 may include an output capacitor Co having an equivalent series resistance (ESR) Ro, wherein DAC signal 204 is provided to output capacitor Co to generate output voltage Vout. It should be noted that the resistor symbol represented by Ro is the ESR of capacitor Co and is therefore not a separate physical component implemented within the circuit.

[0090] Figure 3A is a schematic diagram of a current measurement system 300 according to a second embodiment of the present disclosure. The current measurement system 300 includes a current determination unit 206. The current measurement system 300 of this embodiment also includes an average current determination unit 302, which is configured to receive the output current signal 207 and provide an average output current signal 304. The average output current signal 304 represents the average output current of the LDO 202.

[0091] Figure 3B is a schematic diagram of a current measurement system 300 showing a specific embodiment of an average current determination unit 302. In this embodiment, the average current determination unit 302 includes a low pass filter 306, and the output current signal 207 is filtered by the low pass filter 306 to provide an average output current signal 304. The low pass filter 306 may include an infinite impulse response (IIR) filter 308.

[0092] Figure 3C 3 is a schematic diagram of a current measurement system 310 according to a third embodiment of the present disclosure. The current measurement system 310 includes a current determination unit 206. The current measurement system 310 also includes a warning circuit 312.

[0093] Figure 3D 3 is a timing diagram showing an example operation of the warning circuit 312, wherein the output current signal (shown by trace 314) varies with time. Two threshold current values ​​Th1, Th2 are shown on the diagram.

[0094] During operation, if the output current Iout exceeds the threshold Th1 (as indicated by the output current signal rising above the threshold Th1 at time t1), the warning circuit 312 indicates that the output current Iout has exceeded the threshold Th1. Similarly, if the output current drops below the threshold Th2, the warning circuit 312 indicates that the output current Iout has dropped below the threshold Th2, for example, as indicated at time t2.

[0095] Warning circuit 312 may indicate that a threshold has been passed by providing an indicator signal 313 that may be provided to LDO 202 , current measurement system 310 , or any other suitable circuit or system, with the receiving circuit or system responding accordingly to the indication that the threshold current has been passed.

[0096] Figure 3E 3 is a schematic diagram of a current measurement system 316 according to a fourth embodiment of the present disclosure. The current measurement system 316 includes a current determination unit 206 , an average current determination unit 302 , and a warning circuit 312 .

[0097] Figure 4A is a fifth embodiment according to the present disclosure Figure 3C It should be understood that in another embodiment, according to the understanding of technicians, the current measurement system 310 can be composed of a LDO 202 of a specific embodiment of the current measurement system 310. Figure 3E A current measurement system 316 or any other current measurement system is provided.

[0098] In this embodiment, LDO 202 includes a panic circuit 400, which can be used as a Figure 1A A panic circuit 120 is described.

[0099] In operation, the panic circuit 400 detects when the feedback voltage Vfb exceeds a first threshold voltage value Vref1 or drops below a second threshold voltage value Vref2, and triggers a panic condition in response to the feedback voltage being outside a normal operating range. In a panic condition, the panic circuit 400 controls the DAC 212 to operate in a panic mode. This functionality may be provided by a panic signal 401 generated by the panic circuit 400, which is then provided to the DAC 212 and switches the DAC 212 to a panic mode.

[0100] LDO 202 also includes a clock circuit 402 that can be used to Figure 1A 1. The clock circuit 128 is described. During operation, the clock circuit 402 provides a clock signal 404 to the comparison circuit 208. The clock circuit 402 operates in a fast mode during the panic mode and operates in a slow mode otherwise. During the fast mode, the clock circuit 402 provides the clock signal 404 at a higher frequency than the frequency provided during the slow mode.

[0101] In a specific embodiment, the warning circuit 312 is used to indicate that the output current has passed outside of an operating window surrounded by a threshold value during the slow mode of the clock circuit 402 .

[0102] In a particular embodiment, the warning circuit 312 may be used to indicate that the output current has passed outside of the operating window only during the slow mode, but not during the fast mode.

[0103] Alert circuit 312 may receive signal 403 from clock circuit 402 indicating the current operating mode.

[0104] Figure 4B 2 is a schematic diagram of a specific embodiment of an LDO 202 according to a sixth embodiment of the present disclosure. The LDO 202 can be used with a current measurement system (eg, Figure 3C Used together with the current measurement system 310).

[0105] The panic circuit 400 includes a comparator 406 configured to compare the feedback voltage Vfb with a threshold voltage value Vref1 and a comparator 408 configured to compare the feedback voltage Vfb with a threshold voltage value Vref2 .

[0106] Panic circuit 400 may include logic circuit 410 configured to receive the outputs of comparators 406 , 408 and provide panic signal 401 in response to the comparator output indicating that feedback voltage Vfb has exceeded threshold voltage value Vref1 or has fallen below threshold voltage value Vref2 .

[0107] LDO 202 may include a counter circuit 412 configured to receive panic signal 401 and error signal 210. Counter circuit 412 is also configured to increment shift register 214 when DAC 212 operates in panic mode.

[0108] Figure 4C The clock circuit 402 may include a multiplexer 414 for receiving an input clock signal 416 and a frequency scaling unit 418. The clock circuit 402 is configured to provide the input clock signal 416 as the clock signal 404 during the fast mode, and the frequency scaling unit 418 is configured to reduce the frequency of the input clock signal 416 when generating the clock signal 404 during the slow mode.

[0109] Figure 5 According to the seventh embodiment of the present disclosure Figure 2A FIG. 2 is a schematic diagram of a specific embodiment of an LDO 202 used in conjunction with the current measurement system 200 of FIG. 2. It should be understood that in another embodiment, according to the understanding of a skilled person, the current measurement system 200 can be provided by any other current measurement system as described herein.

[0110] In this embodiment, LDO 202 includes a DAC 500 that generates a DAC code signal 502. Based on the description of DAC 212, the operation of DAC 500 will be clear to the skilled person. In addition, in other embodiments, according to the understanding of the skilled person, DAC 500 can include any features described with respect to the specific embodiment of DAC 212. DAC 212 can provide a coarse control of the output voltage Vout, and DAC 500 can provide a fine control of the output voltage Vout.

[0111] The current determination unit 206 may be configured to generate an output current signal 207 using the two DAC code signals 204, 502. The current determination unit 206 may calculate the output current by performing calculations using the DAC code signals 204, 502, thereby generating the output current signal 207, the output current signal 207 being generated using the calculated output current.

[0112] For example, the output current may be calculated by multiplying each of the DAC code signals 204, 502 by a variable, which may be represented by the following equation:

[0113] Iout=qq×v1+qqf×v2 (2)

[0114] Where Iout is the output current, qq is the DAC code signal 204, qqf is the DAC code signal 502, v1 is the first variable, and v2 is the second variable.

[0115] Figure 6 is a schematic diagram of a digital LDO 600 and a current measurement system 602 according to an eighth embodiment of the present disclosure. The digital LDO 600 includes the following components:

[0116] The clocked comparator (as previously described, associated with the comparator circuit 208). During operation, the clocked comparator 208 compares the target "vref" voltage (previously labeled Vref) to the output "vout" voltage (previously labeled Vout) and generates a "comp" signal (previously referred to as the error signal 210) that is used by the coarse up-down counter (associated with the specific embodiment of the shift register 214) and the fine up-down counter (associated with the specific embodiment of the DAC 500 including the shift register 604).

[0117] Panic comparators (depending on the specific implementation of the panic circuit 400). These panic comparators form window comparators and provide outputs indicating whether the output voltage vout is too high "toohi" or too low "toolo". These outputs are used to form a "panic".

[0118] Shift_counter_coarse (described previously with respect to shift register 214). In the present embodiment, this is a 4-bit up-down counter that controls the large coarse step DAC 212. In the current embodiment, each bit 216, 218 of the DAC 212 is a 10mA current source, ie, 0 to 150mA output.

[0119] Shift_counter_fine (previously described with respect to shift register 604). In this embodiment, this is a 5-bit up-down counter that controls the small fine step DAC 500. Each bit of the DAC 500 is a 750 μA current source, i.e., a 0 to 23.23 mA output. The fine DAC 500 is scaled to approximately 2.2 times the coarse step size. When the up-down counter 604 reaches a limit (31 or 0), it indicates an increment ("inc") or decrement ("dec") of the coarse counter 212,

[0120] For example, when the upper limit 31 is reached, the coarse DAC 212 increments by 10 mA.

[0121] This causes the fine DAC 500 to subtract the nearest 9.25 mA, or 12 codes, causing the next output current to increase by 1 fine DAC 500 step size of 0.75 mA. This allows the control loop to adapt to slowly changing loads without triggering a "panic".

[0122] Clock_control (previously described with respect to clock circuit 402). In this embodiment, clock circuit 402 controls the duration of the panic mode signal ("fast" and "fine") by gating the clock ("gate") every 16 cycles, allowing the "fine" mode to run at 1 / 16 the clock speed, and divides the system clock for the slower fine control mode.

[0123] Detection, because the current measurement system 602, according to the understanding of the skilled person, can be provided by any current measurement system described herein. In this embodiment, the current measurement system 602 is a telemetry block that uses coarse and fine DAC codes ("qq" and "qqfine") to warn and indicate the output current (labeled as "Iload")

[0124] When it reaches its maximum value ("warn" and "limit"). The output current can also be measured using an IIR filter and a DAC code. In this example, two different indicator signals (labeled 606, 608) are provided, an indicator signal 606 is provided when the output current Iload exceeds 125mA, and an indicator signal 608 is provided when the output current Iload exceeds 152mA.

[0125] Overshoot detection. This is a RS latch-triggered pull-down resistor used when VOUT is above the "tooHi" threshold. This is an active mechanism to discharge the output capacitor Co if the load current drops (e.g. to zero). In another embodiment, it can also be used to discharge the output when the LDO is off.

[0126] The current measurement system 602 of the present embodiment provides the function of the average current determination unit 302 by providing the average output current signal 304 , and provides the function of the warning circuit 312 by providing the current warning flag 606 and the limit flag 608 .

[0127] The output current measurement is a good indicator of the state or health of the load. It can give an indication of a system fault or (obstruction) failure.

[0128] If the load exceeds the capability of the LDO, the output voltage is not at the desired level, and “Warning” and “Limit” flags allow the system to determine its operating status.

[0129] One advantage of the digital LDO 600 is that the metering of the operation is easily measured by digital means. Since the coarse DAC output and the fine DAC output 204, 502 are scaled currents, this means that the digital control value is a reasonable representation of the output current. Regardless of the actual output current, the coarse and fine DAC codes 204, 502 have numerical limits that define the maximum output current.

[0130] The "Warning" flag and the "Limit" flag are simple digital thresholds with hysteresis to warn the system as needed. The average output current is a scaled and low-pass filtered representation of the output DAC current.

[0131] For this embodiment, the output current can be generated using scaled representations from the coarse and fine DAC codes:

[0132] / / Calculate current in multiples of 10uA

[0133] Current = qq*1000+qqf*75;

[0134] This is easily accomplished using integer math:

[0135] / / Calculate current in multiples of 10uA

[0136] / / current = qq*1000+qqf*75;

[0137] Current = (qq<<10)-(qq<<4)-(qq<<3)+(qqf<<6)+(qqf<<3)+(qqf<<1)+qqf;

[0138] The warning flag and limit flag are hysteresis thresholds for this "current" value. This is only flagged when the circuit does not respond to transients (ie when operating at slow clock rates). Note that 5 = logical 1, 0 = logical 0.

[0139] / / Only mark when not reacting to transient state

[0140]

[0141] The current measurement system 602 may include a current mirror (not shown), for example, Figure 1B As shown and proposed in A1.2-A Calibration-Free Hybrid LDO With In-Loop Quantization andAuxiliary Constant Current Control Achieving High Accuracy and Fast DVS by Xiangyu Mao et al. (IEEE Transactions on Circuits and Systems-I: General Papers, Vol. 69, No. 11, November 2022). Since each "coarse" and "fine" DAC current step is known to be a fixed value (within the fine-tuning tolerance), the calculation of the average current is accurate. In addition, the use of a current source (rather than just an on / off switching MOS) improves the PSRR (as described in the cited paper).

[0142] Fig. 7A is a block diagram of an IIR filter 700, which can be implemented within the current measurement system 602 to provide the current measurement system 602 as previously described (e.g., with respect to Figure 3B The average current determining unit 302) may be used to determine the average output current signal as described above. IIR filtering of the fast and slow DAC current values ​​may be used to generate the average output current.

[0143] The IIR filter 700 includes multiplication units 702 , 704 , an addition unit 706 , and a unit delay block 708 . Figure 7B is a schematic diagram of an IIR filter including a comparator 710. The IIR filter 700 can be represented by the following transfer equation:

[0144]

[0145] In this example, a=32.

[0146] The average current is provided using an IIR filter 700. In a specific embodiment, the following code may be used (this makes integer math simple). The filter is calculated to have 2 "decimal places" of precision before outputting the integer value.

[0147] / / Current value IIR filtering, 2 DP

[0148] icalc=floor((32*icalc-icalc+4*current) / 32);

[0149] / / Output iavg (1LSB = 10uA), no DP

[0150] iavg = floor(icalc / 4);

[0151] Figure 8 800 is a graph showing simulation results of an actual implementation of the IIR filter 700, where the data is clocked at 6.25 MHz (100 MHz / 16). The frequency response is shown, where the IIR filter 700 is shown to have a low pass filter function with a gain of -3 dB at 31.5 kHz (-30 dB at 1 MHz). Gain (trace 800) and phase (trace 802) are shown.

[0152] Various improvements and modifications may be made to the above without departing from the scope of the present disclosure.

[0153] This disclosure provides the following:

[0154] Clause 1. A current measurement system for a digital low dropout regulator (LDO), the digital LDO being configured to receive a reference voltage and generate an output voltage, the output voltage of the digital LDO being dependent on a first DAC code signal, the current measurement system comprising:

[0155] A current determination unit, wherein the current measurement unit is configured to:

[0156] i) receiving the first DAC code signal; and

[0157] ii) generating an output current signal using the first DAC code signal.

[0158] Clause 2. The current measurement system of clause 1, wherein the LDO comprises:

[0159] A comparison circuit, the comparison circuit being configured to:

[0160] i) receiving the reference voltage;

[0161] ii) receiving a feedback voltage, wherein the feedback voltage depends on the output voltage;

[0162] iii) comparing the reference voltage and the feedback voltage; and

[0163] iv) generating an error signal, said error signal being dependent on a comparison between said reference voltage and said feedback voltage; and

[0164] A first digital-to-analog converter, wherein the first digital-to-analog converter is configured to:

[0165] i) receiving the error signal;

[0166] ii) generating the first DAC code signal based on the error signal.

[0167] Clause 3. The current measurement system of Clause 2, wherein the first digital-to-analog converter comprises a first shift register configured to generate the first DAC code signal.

[0168] Clause 4. The current measurement system of Clause 3, wherein the first digital-to-analog converter comprises a plurality of first current sources, and each of the first current sources is used as 1 bit of the first DAC code signal.

[0169] Clause 5. The current measurement system of Clause 4, wherein each of the first current sources comprises a first transistor.

[0170] Clause 6. The current measurement system of Clause 5, wherein the first shift register comprises a plurality of outputs, each output being associated with a single bit of the first DAC code signal and coupled to a gate of one of the plurality of first transistors.

[0171] Clause 7. The current measurement system of Clause 6, wherein the first digital-to-analog converter comprises a plurality of first buffer circuits, each output being coupled to a gate of one of the plurality of first transistors via one buffer circuit.

[0172] Clause 8. The current measurement system according to clause 1, wherein the current determination unit is configured to generate the output current signal by:

[0173] calculating an output current using the first DAC code signal; and

[0174] The output current signal is provided using the calculated output current.

[0175] Clause 9. The current measurement system of Clause 8, wherein the current determination unit is configured to calculate the output current by multiplying the first DAC code signal by a first variable.

[0176] Clause 10. The current measurement system of Clause 1, comprising an average current determination unit configured to receive the output current signal and provide an average output current signal.

[0177] Clause 11. The current measurement system of Clause 10, wherein the average current determination unit comprises a low pass filter.

[0178] Clause 12. The current measurement system of Clause 11, wherein the low pass filter comprises an infinite impulse response (IIR) filter.

[0179] Clause 13. The current measurement system of Clause 1, comprising a warning circuit for indicating when the output current exceeds a first threshold current value or falls below a second threshold current value.

[0180] Clause 14. The current measurement system of clause 13, wherein the digital LDO comprises:

[0181] A panic circuit, the panic circuit being configured to:

[0182] i) detecting when the feedback voltage exceeds a first threshold voltage value or drops below a second threshold voltage value; and ii) controlling the first digital-to-analog converter to operate in a panic mode when the feedback voltage exceeds the first threshold voltage value or drops below the second threshold voltage value; and

[0183] A clock circuit, the clock circuit being configured to:

[0184] i) providing a clock signal to the comparison circuit;

[0185] ii) operating in a fast mode during the panic mode by providing the clock signal at a first frequency; and iii) operating in a slow mode when not in the panic mode by providing the clock signal at a second frequency,

[0186] The second frequency is less than the first frequency; wherein:

[0187] The warning circuit is configured to:

[0188] i) when the clock circuit operates in the slow mode, indicating when the output current exceeds the first threshold current value or drops below the second threshold current value.

[0189] Clause 15. The current measurement system of clause 1, wherein the digital LDO comprises a second digital-to-analog converter configured to:

[0190] i) receiving the error signal; and

[0191] ii) generating a second DAC code signal based on the error signal, the output voltage depending on the second DAC code signal.

[0192] Clause 16. The current measurement system of Clause 15, wherein the current determination unit is configured to generate the output current signal using the second DAC code signal.

[0193] Clause 17. The current measurement system according to clause 16, wherein the current determination unit is configured to generate the output current signal by:

[0194] calculating an output current using the first DAC code signal and the second DAC code signal; and

[0195] The output current signal is provided using the calculated output current.

[0196] Clause 18. The current measurement system of Clause 17, wherein the current determination unit is configured to calculate the output current by adding: a multiplication of the first DAC code signal with a first variable and a multiplication of the second DAC code signal with a second variable.

[0197] Clause 19. A voltage regulator system comprising:

[0198] a digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage; and

[0199] A current measurement system comprising:

[0200] a current determination unit, the current determination unit being configured to:

[0201] i) receiving a first DAC code signal, wherein the output voltage of the digital LDO depends on the first DAC code signal; and

[0202] ii) generating an output current signal using the first DAC code signal.

[0203] Clause 20. A method of measuring current from a digital low dropout regulator (LDO), the digital LDO being configured to receive a reference voltage and generate an output voltage, the output voltage of the digital LDO being dependent on a first DAC code signal, the method comprising:

[0204] receiving the first DAC code signal at a current determination unit; and

[0205] Using the current determination unit, an output current signal is generated using the first DAC code signal.

Claims

1. A current measurement system for a digital low dropout regulator (LDO), the digital LDO being used to receive a reference voltage and generate an output voltage, the output voltage of the digital LDO depending on a first DAC code signal, the current measurement system comprising: a current determination unit, the current determination unit being configured to: i) receiving the first DAC code signal; as well as ii) generating an output current signal using the first DAC code signal.

2. The current measurement system according to claim 1, wherein: LDOs include: A comparison circuit, the comparison circuit being configured to: i) receiving the reference voltage; ii) receiving a feedback voltage, wherein the feedback voltage depends on the output voltage; iii) comparing the reference voltage and the feedback voltage; and iv) generating an error signal, said error signal being dependent on a comparison between said reference voltage and said feedback voltage; and A first digital-to-analog converter, wherein the first digital-to-analog converter is configured to: i) receiving the error signal; ii) generating the first DAC code signal based on the error signal.

3. The current measurement system according to claim 2, wherein: The first digital-to-analog converter includes a first shift register configured to generate the first DAC code signal.

4. The current measurement system according to claim 3, wherein: The first digital-to-analog converter includes a plurality of first current sources, and each of the first current sources is used as 1 bit of the first DAC code signal.

5. The current measurement system according to claim 4, wherein: Each of the first current sources includes a first transistor.

6. The current measurement system according to claim 5, wherein: The first shift register includes a plurality of outputs, each output being associated with a single bit of the first DAC code signal and coupled to a gate of one of the plurality of first transistors.

7. A current measurement system according to any preceding claim, wherein: The current determination unit is configured to generate the output current signal in the following manner: calculating an output current using the first DAC code signal; and The output current signal is provided using the calculated output current.

8. The current measurement system according to claim 7, wherein: The current determination unit is configured to calculate the output current by multiplying the first DAC code signal by a first variable.

9. The current measurement system according to any one of claims 1 to 6, comprising an average current determination unit configured to receive the output current signal and to provide an average output current signal.

10. A current measurement system according to any one of claims 1 to 6, comprising a warning circuit for indicating when the output current exceeds a first threshold current value or falls below a second threshold current value.

11. The current measurement system according to claim 10, wherein: The digital LDO includes: A panic circuit, the panic circuit being configured to: i) detecting when the feedback voltage exceeds a first threshold voltage value or drops below a second threshold voltage value; and ii) when the feedback voltage exceeds the first threshold voltage value or drops below the second threshold voltage value, controlling the first digital-to-analog converter to operate in a panic mode; and A clock circuit, the clock circuit being configured to: i) providing a clock signal to the comparison circuit; ii) operating in a fast mode during said panic mode by providing said clock signal at a first frequency; and iii) operating in a slow mode when not in the panic mode by providing the clock signal at a second frequency, The second frequency is less than the first frequency; wherein: The warning circuit is configured to: i) when the clock circuit operates in the slow mode, indicating when the output current exceeds the first threshold current value or drops below the second threshold current value.

12. The current measurement system according to any one of claims 1 to 6, wherein: The digital LDO includes a second digital-to-analog converter configured to: i) receiving the error signal; as well as ii) generating a second DAC code signal based on the error signal, the output voltage depending on the second DAC code signal.

13. A voltage regulator system comprising: a digital low dropout regulator (LDO) for receiving a reference voltage and generating an output voltage; as well as A current measurement system comprising: a current determination unit, the current determination unit being configured to: i) receiving a first DAC code signal, wherein the output voltage of the digital LDO depends on the first DAC code signal; as well as ii) generating an output current signal using the first DAC code signal.

14. A method for measuring current from a digital low dropout regulator (LDO), the digital LDO being configured to receive a reference voltage and generate an output voltage, the output voltage of the digital LDO being dependent on a first DAC code signal, the method comprising: receiving the first DAC code signal at a current determination unit; as well as Using the current determination unit, an output current signal is generated using the first DAC code signal.

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