A Timing Test Device, Method and Medium for a Launch Vehicle

Abstract

The present invention provides a timing test device for a launch vehicle, comprising: a communication module, configured to transmit timing signals acquired by at least one timing acquisition card to a timing synthesis card, so that the FPGA chip on the timing synthesis card periodically acquires the timing signals, and an upper computer software is used to issue instructions to the control module; a control module, configured to respond to the instructions to control a processor, an opto-isolator device and the timing synthesis card. During operation, the processor first performs self-check on each timing detection channel of the timer; a time synchronization module, which can upload to the network and store in a storage device after determining the data is valid; a test module, configured to determine whether the signal is valid and upload it, thereby efficiently realizing the determination of the validity of the timing signal. The present invention also exemplarily discloses a timing test method for a launch vehicle and an electronic device applying the method.

Description

Technical Field

[0001] The present invention relates to the technical field of launch vehicle control, and particularly to a timing test device, method and computer-readable storage medium for a launch vehicle. Background Art

[0002] The timing test of launch vehicles has been developed for many years. With the development and progress of launch vehicle technology, the carrying capacity of launch vehicles has been rapidly improved. As a result, the volume has become larger and the functions have become more numerous, leading to an increasing number of pyrotechnic devices on launch vehicles, and thus an increasing number of timings that need to be tested. Especially with the development of large launch vehicles, it is particularly necessary to use multiple timing test devices to conduct hierarchical tests. Therefore, it is particularly important for multiple timing test devices to have a unified time synchronization function. The time synchronization function is not only reflected among multiple timing test devices, but also reflected in synchronizing to accurate Beijing time. In the past, the functions of launch vehicles were limited, and the number of timing signals of launch vehicles was limited, so the number of timing signals that needed to be tested was relatively small. Most of the devices used in timing tests adopted single-device tests. Single devices had single functions and did not have networking capabilities. They could collect limited timing signals, and the accuracy of the signals tested by the test devices was relatively low, only meeting the previous test requirements, etc.

[0003] Currently, the timing test devices in use have a low degree of intelligence. Single devices have relatively single functions and cannot be used for networking. The number of timing signals that can be tested is very limited, making it difficult to conduct the timing test of large launch vehicles. Regarding the problem that it is necessary to accurately align to Beijing time during the launch of a launch vehicle, previous devices are even more powerless. The test devices do not have a time synchronization function, let alone the function of aligning with Beijing time at the launch site. This limits their application effects and leaves room for innovation and breakthrough in this disclosure. Summary of the Invention

[0004] The present invention provides a timing test device, method and computer-readable storage medium for a launch vehicle, which uses at least one timing signal for timing analysis and efficiently realizes the judgment of the effectiveness of the timing signal.

[0005] In a first aspect, a timing test device for a launch vehicle is provided, including: a communication module, a control module, a timing module, and a test module. Among them, the communication module is used to transmit the timing signals acquired by at least one timing acquisition card to a timing integration card, so that the FPGA chip on the timing integration card periodically acquires the timing signals, and uses a host computer software to send instructions to the control module; the control module is used to respond to the instructions to control a processor, an opto-isolator device, and a timing integration card, and the timing integration card is connected to the timing detection channels in the timer in the processor in a one-to-one correspondence; the opto-isolator device is connected to the timer in the processor in a one-to-one correspondence; during operation, the processor first performs self-check on each timing detection channel of the timer, including: adding a judgment logic to each timing detection channel of the timer; the timing module is used to power on each device of the system when the test module is working, then perform network connection and timing, and after completion, the test work can be started, and at the same time, data display, real-time data interpretation, and uploading the data to the network and storing it in a storage device are realized after judging the data to be valid; the test module is used to acquire at least one timing signal, and the at least one timing signal is transmitted to the timing integration card through resistor voltage division and opto-isolation, and the timing integration card performs timing analysis by judging the timing acquisition card number according to the slot position. If the at least one timing signal is in the same state at least 5 consecutive times on the same timing path and is inconsistent with the previous state, it is judged that the signal is valid and uploaded.

[0006] In some embodiments, it further includes: a power management module, which is used to manage the circuits and voltage conversion circuits in the timing test device of the launch vehicle and provide corresponding working voltages. The working voltages at least include: the working voltages of 1.8V, 3.5V, and 5V of the control module.

[0007] In some embodiments, for the control module, during operation, the processor first performs self-check on each timing detection channel of the timer, including: adding a judgment logic to each timing detection channel of the timer.

[0008] In some embodiments, the test module is used to acquire at least one timing signal, including: receiving the at least one timing signal through the at least one timing acquisition card according to a predetermined period; measuring and calculating the at least one timing signal, performing a preliminary interpretation according to predetermined parameters, and encoding the at least one timing signal according to the predetermined communication protocol of the launch vehicle.

[0009] In some embodiments, the judgment logic includes: for each timing detection channel of the timer, setting at least one target timing detection channel for timing detection, and acquiring the timing signals of the at least one timing acquisition card at a period of 0.2 ms.

[0010] In some embodiments, the control module includes: a core board, a data storage device, a WX1860 chip, and an input / output device, wherein the data storage device is a MASATA hard disk.

[0011] In a second aspect, a timing test method for a launch vehicle is provided, including: transmitting the timing signals acquired by at least one timing acquisition card to a timing integration card, such that the FPGA chip on the timing integration card periodically acquires the timing signals, and using a host computer software to send instructions to a control module; the control module responds to the instructions to control a processor, an opto-isolator device, and the timing integration card, and the timing integration card is connected to the timing detection channels in the timer of the processor in a one-to-one correspondence; the opto-isolator device is connected to the timers in the processor in a one-to-one correspondence; during operation, the processor first performs self-check on each timing detection channel of the timer, including: adding judgment logic to each timing detection channel of the timer; when the test module operates, power on each device of the system, then perform network connection and time synchronization, and after completion, the test work can be started, and at the same time, data display, real-time data interpretation, and uploading the data to the network and storing it in a storage device after judging the data to be valid are realized; the test module acquires at least one timing signal, and the at least one timing signal is transmitted to the timing integration card through resistor voltage division and opto-isolation, and the timing integration card performs timing analysis by judging the timing acquisition card number according to the slot position. If the same state appears at least 5 consecutive times in the same path of timing signals and is inconsistent with the previous state, the signal is judged to be valid and uploaded.

[0012] In a third aspect, the present invention provides an electronic device, which includes: a processor; a memory, on which computer-readable instructions are stored, and when the computer-readable instructions are executed by the processor, the above-mentioned timing test method for a launch vehicle is implemented.

[0013] In a fourth aspect, the present invention further provides a computer-readable storage medium, characterized in that program code is stored in the computer-readable storage medium, and the program code can be called by a processor to execute the above-mentioned timing test method for a launch vehicle.

[0014] Compared with the prior art, the present invention can at least achieve the following beneficial effects: at least one timing signal is used for timing analysis, and the effectiveness of the timing signal is efficiently judged.

[0015] The summary of the invention is provided to introduce a selection of concepts in a simplified form, which will be further described in the specific embodiments below. The summary of the invention is not intended to identify the key features or essential features of the present disclosure, nor is it intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other objects, features, and advantages of the present disclosure will become more apparent by describing the exemplary embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which, in the exemplary embodiments of the present disclosure, the same reference numerals generally represent the same components.

[0017] Figure 1 The schematic block diagram of the timing test device of the launch vehicle provided by the embodiment of the present application is shown;

[0018] Figure 2 The flowchart of the timing test method of the launch vehicle provided by the embodiment of the present application is shown;

[0019] Figure 3 The structural schematic diagram of an application of the timing test device of the launch vehicle provided by the embodiment of the present application is shown. Detailed implementation manners

[0020] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be more thorough and complete, and can fully convey the scope of the present disclosure to those skilled in the art.

[0021] As used herein, the term "including" and its variations mean open inclusion, that is, "including but not limited to". Unless otherwise stated, the term "or" means "and / or". The term "based on" means "at least partially based on". The terms "an exemplary embodiment" and "an embodiment" mean "at least one exemplary embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first", "second", etc. may refer to different or the same objects. There may also be other explicit and implicit definitions hereinafter.

[0022] The present application provides a timing test device for a launch vehicle. Please refer to Figure 1 This figure is a schematic diagram of the first embodiment of the present application. The following will be described in detail with reference to Figure 1 a timing test device for a launch vehicle provided in the first embodiment of the present application.

[0023] The present application provides a timing test device 100 for a launch vehicle. The processing flow of the timing test device 100 for the launch vehicle may include the following modules:

[0024] Communication module 102: The configuration module is used to transmit the timing signals acquired by at least one timing acquisition card to the timing integration card, so that the FPGA chip on the timing integration card periodically acquires the timing signals, and uses the host computer software to send instructions to the control module.

[0025] Control module 104: The control module is used to respond to instructions to control the processor, optocoupler isolation device, and timing synthesis card. The timing synthesis card is connected to the timing detection channels in the timer of the processor in a one-to-one correspondence; the optocoupler isolation device is connected to the timers in the processor in a one-to-one correspondence; during operation, the processor first performs self-checks using the timing detection channels of the timer.

[0026] Time synchronization module 106: When the test module is operating, it powers on all devices in the system, then performs network connection and time synchronization. After completion, it can start the test work, and at the same time, it realizes data display, real-time data interpretation, and uploads the data to the network and stores it in the storage device after determining the data is valid;

[0027] Test module 108: The test module is used to obtain at least one timing signal. The at least one timing signal is transmitted to the timing synthesis card through resistor voltage division and optocoupler. The timing synthesis card performs timing analysis by judging the timing acquisition card number according to the slot position. If the at least one timing signal is in the same state for at least 5 consecutive times on the same timing path and is inconsistent with the previous state, then the signal is judged to be valid and uploaded.

[0028] In some embodiments, it further includes: a power management module, which is used to manage the circuits and voltage conversion circuits in the timing test device of the launch vehicle, and provide corresponding working voltages. The working voltages at least include: the working voltages of 1.8V, 3.5V, and 5V for the control module.

[0029] In some embodiments, when the control module is operating, the processor first performs self-checks using the timing detection channels of the timer, including: adding judgment logic to the timing detection channels of the timer.

[0030] In some embodiments, the test module is used to obtain at least one timing signal, including: receiving the at least one timing signal through the at least one timing acquisition card according to a predetermined period; measuring and calculating the at least one timing signal, performing preliminary interpretation according to predetermined parameters, and encoding the at least one timing signal according to the predetermined communication protocol of the launch vehicle.

[0031] In some embodiments, when the test module judges that the signal is valid and uploads it, it includes: sending a message that the signal is valid to the host computer through the 1588 network port.

[0032] In some embodiments, the judgment logic includes: for each timing detection channel of the timer, setting at least one target timing detection channel for timing detection, and collecting timing signals of the at least one timing acquisition card at a period of every 0.2 ms.

[0033] In some embodiments, the control module includes: a core board, a data storage device, a WX1860 chip, and input / output devices, wherein the data storage device is a MASATA hard disk.

[0034] The embodiment of the present invention also provides a timing test method for a launch vehicle, including the following steps:

[0035] Transmit the timing signals acquired by at least one timing acquisition card to a timing synthesis card, so that the FPGA chip on the timing synthesis card periodically acquires the timing signals, and use the host computer software to send instructions to the control module;

[0036] The control module responds to the instructions to control the processor, opto-isolation devices, and the timing synthesis card. The timing synthesis card is connected to the timing detection channels in the timer of the processor in a one-to-one correspondence; the opto-isolation devices are connected to the timers in the processor in a one-to-one correspondence; during operation, the processor first performs self-checking using each timing detection channel of the timer;

[0037] When the test module is working, power on each device of the system, then perform network connection and time synchronization. After completion, the test work can be started, and at the same time, data display, real-time data interpretation are realized, and after judging the data to be valid, upload it to the network and store it in the storage device;

[0038] The test module acquires at least one timing signal. The at least one timing signal is transmitted to the timing synthesis card through resistor voltage division and opto-isolation. The timing synthesis card performs timing analysis by judging the timing acquisition card number according to the slot position. If the same state appears at least 5 consecutive times in the same path of timing signal and is inconsistent with the previous state, then judge the signal to be valid and upload it.

[0039] Figure 2 It is a schematic block diagram showing the timing test process of a launch vehicle according to an exemplary embodiment. The timing test process of the launch vehicle may include the following steps: After the test starts, configure and verify the network connection status of each device. On the premise of successful network connection, perform 1588 mode setting, and then perform 1588 synchronization test. If the 1588 synchronization test fails, perform 1588 mode setting again; if the 1588 synchronization test is successful, start the test. Acquire at least one timing signal from the test module, and perform data display and real-time interpretation; when the at least one timing signal is transmitted to the timing synthesis card through resistor voltage division and opto-isolation, the timing synthesis card performs timing analysis by judging the timing acquisition card number according to the slot position. If the same state appears at least 5 consecutive times in the same path of timing signal and is inconsistent with the previous state, then judge the signal to be valid and upload the corresponding data, and store the corresponding data in the storage device. Wherein, the data storage device is a MASATA hard disk.

[0040] An electronic device provided by an embodiment of the present invention may include a processor and a memory. Optionally, the electronic device may further include a transceiver. Among them, the processor is connected to the memory and the transceiver, for example, through a communication bus. Computer-readable instructions are stored on the memory, and when the computer-readable instructions are executed by the processor, the steps of the timing test method of the above-mentioned launch vehicle are implemented.

[0041] In a specific implementation, as an embodiment, the processor may include one or more CPUs.

[0042] In a specific implementation, as an embodiment, the electronic device may also include multiple processors. For example, each of the processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0043] Among them, the memory is used to store the software program for implementing the solution of the present invention and is controlled by the processor for execution. The specific implementation manner may refer to the above method embodiment and will not be elaborated here.

[0044] The transceiver is used to communicate with a network device or with a terminal device.

[0045] Optionally, the transceiver may include a receiver and a transmitter. Among them, the receiver is used to implement the receiving function, and the transmitter is used to implement the transmitting function.

[0046] Optionally, the transceiver may be integrated with the processor or exist independently and be coupled to the processor through the interface circuit of the electronic device. The embodiment of the present invention does not make a specific limitation on this.

[0047] It should be noted that the structure of the above-mentioned electronic device does not constitute a limitation on the electronic device. The actual electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements. In addition, the technical effects of the electronic device may refer to the technical effects of the above method embodiment and will not be elaborated here.

[0048] Figure 3The structural schematic diagram of a timing test device for an application launch vehicle is shown. Specifically, a single launch vehicle timing test device consists of 8 timing acquisition cards, 1 slot base plate, a timing synthesis card, a core board, a MASATA hard disk, a WX1860 chip, and installation structural parts, etc. Eight timing acquisition cards and a timing synthesis card are inserted into the slot base plate. The core board, MASATA hard disk, and WX1860 chip are installed on the timing synthesis card. The timing test device of a single launch vehicle can simultaneously test 224 timing signals. The timing signals are transmitted to the timing synthesis card through resistor voltage division and high-speed optocouplers. The timing synthesis card determines the timing acquisition card number based on the slot position. The FPGA on the timing synthesis card acquires the timing signals of the 8 timing acquisition cards once every 0.2 ms. If the same timing signal is in the same state for 5 consecutive times (1 ms) and is inconsistent with the previous state, the signal is determined to be valid and uploaded.

[0049] The core board runs the operating system, processes the displayed information, realizes functions such as network card expansion, data reception, and operation, etc. The hard disk is connected to the core board processor through a high-speed signal line. The hard disk is used for timing data storage, installing the operating system, saving executable programs, etc. While the acquired timing data is uploaded, it is stored in the hard disk in the form of a file. The 1588 network port is connected to the upper computer to achieve accurate time synchronization among multiple devices in the system, and multiple devices achieve accurate time synchronization relative to Beijing time.

[0050] Figure 3 The illustrated embodiment can have the following advantages: (1) The single device can simultaneously test up to 224 channels, and can be networked and synchronously expanded for testing. Multiple devices can achieve accurate time synchronization relative to Beijing time, which is suitable for distributed testing of large launch vehicles; (2) Regarding the characteristics of the timing signals, the device realizes timing test by acquiring the timing signals once every 0.2 ms. If the same state is maintained for 5 consecutive times (1 ms), the signal is determined to be valid, achieving accurate judgment of the timing signals; (3) The device has functions such as processing display, network card expansion, data reception, and storage, etc., facilitating the observation of the changes in the timing signals. The test data stored in the hard disk is convenient for reviewing the timing test data.

[0051] In an exemplary embodiment, the present invention also provides a computer-readable storage medium. At least one instruction is stored in the computer-readable storage medium, and the at least one instruction is loaded and executed by a processor to implement the steps of the timing test method for the launch vehicle as described above. For example, the computer-readable storage medium can be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0052] An embodiment of the present invention further provides an electronic device, which includes: a processor; a memory, on which computer-readable instructions are stored, and when the computer-readable instructions are executed by the processor, the above-mentioned timing test method of the launch vehicle is implemented.

[0053] An embodiment of the present invention provides a computer-readable storage medium, characterized in that program code is stored in the computer-readable storage medium, and the program code can be called by a processor to execute the above-mentioned timing test method of the launch vehicle.

[0054] It should also be understood that the memory in the embodiment of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM), and direct rambus random access memory (DR RAM).

[0055] It should be understood that the term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. Among them, A and B may be singular or plural. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after, but it may also represent an "and / or" relationship, which can be specifically understood with reference to the context.

[0056] It should be understood that in various embodiments of the present invention, the magnitudes of the sequence numbers of the above processes do not imply the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0057] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0058] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the devices, apparatuses, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0059] In several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces, and the indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0060] The above has described the embodiments of the present disclosure. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, the practical applications, or the technical improvements to the technologies in the market, or to enable other ordinary technicians in the technical field to understand the embodiments disclosed herein.

Claims

1. A timing test device for a launch vehicle, characterized in that, Including: A timing acquisition card, a slot baseboard, a timing synthesis card, a core board, a MASATA hard disk, and a WX1860 chip. Among them, the timing acquisition card and the timing synthesis card are inserted on the slot baseboard, and the core board, the MASATA hard disk, and the WX1860 chip are installed on the timing synthesis card; At least one timing signal is transmitted to the timing synthesis card through a resistor voltage division and an opto-isolation device; It further includes: a communication module, a control module, a time synchronization module, and a test module. Among them, The communication module is used to transmit the timing signals acquired by at least one timing acquisition card to the timing synthesis card, so that the FPGA chip on the timing synthesis card periodically acquires the timing signals, and uses the host computer software to send instructions to the control module; The control module includes: a core board, a data storage device, a WX1860 chip, and an input / output device. Among them, the data storage device is a MASATA hard disk, and the core board runs an operating system, processes the displayed information, realizes the expansion of the network card, and functions of data reception and operation; the control module is used to respond to instructions to control the core board processor, the opto-isolation device, and the timing synthesis card. The timing synthesis card is connected to the timing detection channels in the timer in the processor in a one-to-one correspondence; the opto-isolation device is connected to the timers in the processor in a one-to-one correspondence; during operation, the processor first performs self-checking using the timing detection channels of each timer, including: adding judgment logic to the timing detection channels of each timer. The judgment logic includes: for the timing detection channels of each timer, setting at least one target timing detection channel for timing detection, and acquiring the timing signals of at least one timing acquisition card at a period of 0.2 ms; The time synchronization module is used to power on each device of the system when the test module works, then perform network connection and time synchronization, and after completion, the test module starts to perform test work; The test module is used to acquire at least one timing signal. The timing synthesis card performs timing analysis by judging the timing acquisition card number through the slot position. If at least 5 consecutive times of the same timing signal on the same path are in the same state and are inconsistent with the previous state, it is determined that the signal is valid and uploaded to the network and stored in the storage device.

2. The timing test device for a launch vehicle according to claim 1, characterized in that It further includes: A power management module, which is used to manage the circuits and voltage conversion circuits in the timing test device of the launch vehicle, and provide corresponding working voltages. The working voltages at least include: 1.8V, 3.5V, and 5V for the working voltage of the control module.

3. The timing test device for a launch vehicle according to claim 1, characterized in that, The test module is used to acquire at least one timing signal, including: Receiving the at least one timing signal through the at least one timing acquisition card at a predetermined period; Measuring and calculating the at least one timing signal, making a preliminary judgment according to predetermined parameters, and encoding the at least one timing signal according to the predetermined communication protocol of the launch vehicle.

4. A timing test method for a launch vehicle, using the timing test device for a launch vehicle according to any one of claims 1 to 3, characterized in that, Including: Transmitting the timing signals acquired by at least one timing acquisition card to the timing synthesis card, so that the FPGA chip on the timing synthesis card periodically acquires the timing signals, and using the host computer software to send instructions to the control module; The control module responds to instructions to control the processor, the optocoupler isolation device, and the timing synthesis card. The timing synthesis card is connected to the timing detection channels in the timer of the processor in a one-to-one correspondence; the optocoupler isolation device is connected to the timers in the processor in a one-to-one correspondence; during operation, the processor first performs self-checking using the timing detection channels of the timer, including: adding judgment logic to the timing detection channels of the timer, and the judgment logic includes: for each timing detection channel of the timer, setting at least one target timing detection channel for timing detection, and collecting timing signals for the at least one timing acquisition card at a period of every 0.2 ms; When the test module is working, power on all devices of the system, then perform network connection and time synchronization. After completion, the test work can be started, and at the same time, data display, real-time data interpretation, and uploading the data to the network and storing it in the storage device after judging the data to be valid are realized; The test module acquires at least one timing signal, and the at least one timing signal is transmitted to the timing synthesis card through resistor voltage division and optocoupler. The timing synthesis card performs timing analysis by judging the timing acquisition card number according to the slot position. If the same state appears at least 5 consecutive times in the same path of timing signal and is inconsistent with the previous state, the signal is judged to be valid and uploaded.

5. An electronic device, characterized in that, The electronic device includes: A processor; A memory, on which computer-readable instructions are stored. When the computer-readable instructions are executed by the processor, the timing test method of the launch vehicle as described in claim 4 is realized.

6. A computer-readable storage medium, characterized in that, Program code is stored in the computer-readable storage medium, and the program code can be called by the processor to execute the timing test method of the launch vehicle as described in claim 4.

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