An overcurrent protection circuit for a low dropout linear regulator

Abstract

The application relates to an overcurrent protection circuit for a low dropout linear voltage regulator, which comprises a current comparison circuit, a current foldback circuit, a sampling circuit, a current limiting control circuit and an LDO circuit, the gate of a power tube in the LDO circuit is connected with the input end of the sampling circuit, the output end of the sampling circuit is connected with the sampling current input end of the current comparison circuit, the output end of the current comparison circuit is connected with the input end of the current limiting control circuit, the output end of the current limiting control circuit is connected with the gate of the power tube in the LDO circuit, the output end of the LDO is connected with the input end of the current foldback circuit, and the output end of the current foldback circuit is connected with the reference current input end of the current comparison circuit. The structure has the advantages that the LDO is suitable for low static current, can bear a large current load, the power consumption of the overcurrent protection circuit is low, and the foldback overcurrent protection can improve the risk that the power tube is burnt out when the traditional overcurrent protection circuit is short-circuited.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of LDO circuit, and particularly relates to an overcurrent protection circuit for low dropout linear regulator. BACKGROUND

[0002] With the improvement of semiconductor manufacturing process, the integration of chips is higher and higher, and high integration leads to higher and higher current density of the chip, and the risk of overcurrent increases. And the chip area is smaller and smaller, and it is not easy to dissipate heat, when overcurrent occurs, the chip is easy to burn out. LDO meets the requirement of power management chip towards miniaturization due to small size and less peripheral element requirement, and the overcurrent protection circuit can solve the problem of unstable output voltage or chip overheating caused by excessive output current, and has important research significance.

[0003] In smart phones, tablet computers, smart watches and other consumer electronics, many of them use LDO for power supply, and the power surge during falling, water entering or charging may cause overcurrent, causing damage to the chip, leading to equipment failure or information loss. Various sensors and controllers are distributed on the industrial production line, many of which are also powered by LDO, and there are many interference sources in the industrial environment, strong electromagnetic interference, voltage spikes caused by frequent motor start-stop, which are easy to cause line failure and overcurrent. There are also many LDO-powered chip modules inside the automotive electronics, and the automotive power supply environment is harsh, with large voltage fluctuations during start-up and shutdown, extreme temperature conditions such as high temperature in summer and cold in winter, and complex electromagnetic environment, all of which increase the risk of overcurrent. Therefore, improving the overcurrent protection of LDO can not only improve the reliability of the chip, but also reduce the cost in after-sales maintenance. SUMMARY

[0004] The present application provides an overcurrent protection circuit for low dropout linear regulator, which accurately samples the output current by using a sampling circuit, and compares it with a reference current. When overcurrent occurs, the result of the comparison changes the gate potential of the power tube through the current limiting control circuit, achieving the purpose of current limiting, thereby solving the technical problems mentioned in the background art.

[0005] The technical scheme of the present application is as follows: an overcurrent protection circuit for low dropout linear regulator, comprising: a current comparison circuit, a current foldback circuit, a sampling circuit, a current limiting control circuit and an LDO circuit.

[0006] The gate of the power tube in the LDO circuit is connected with the input end of the sampling circuit, the output end of the sampling circuit is connected with the sampling current input end of the current comparison circuit, the output end of the current comparison circuit is connected with the input end of the current limiting control circuit, the output end of the current limiting control circuit is connected with the gate of the power tube in the LDO circuit, the output end of the current comparison circuit is connected with the input end of the current comparison circuit, and the output end of the current comparison circuit is connected with the reference current input end of the current comparison circuit.

[0007] The sampling circuit is used for copying the current of the power tube in the LDO circuit in proportion to generate a sampling current.

[0008] The current comparison circuit is used for comparing the sampling current with the reference current, and when the sampling current is greater than the reference current, the current comparison circuit generates a control signal.

[0009] The current comparison circuit is used for comparing the sampling current with the reference current, and when the sampling current is greater than the reference current, the current comparison circuit generates a control signal.

[0010] Further, the current comparison circuit comprises a first resistor R1, a second resistor R2, a second PMOS tube MP2, a third PMOS tube MP3, a second NMOS tube MN2, a sixth resistor R6 and a third NMOS tube MN3.

[0011] One end of the first resistor R1 is connected with the input voltage VDD, the other end of the first resistor R1 is connected with the source of the second PMOS tube MP2, the gate of the second PMOS tube MP2 is connected with the gate of the third PMOS tube MP3, the drain of the second PMOS tube MP2 is connected with the drain of the second NMOS tube MN2, the gate of the second NMOS tube MN2 is connected with the gate of the third NMOS tube MN3, and the source of the second NMOS tube MN2 is connected with the source of the third NMOS tube MN3.

[0012] One end of the second resistor R2 is connected with the input voltage VDD, the other end of the second resistor R2 is connected with the source of the third PMOS tube MP3 and the output end of the sampling circuit, the drain of the third PMOS tube MP3 is connected with the drain of the third NMOS tube MN3 and the input end of the current limiting control circuit, and the source of the third NMOS tube MN3 is connected with the signal ground VSS.

[0013] Further, the current comparison circuit comprises an eighth PMOS tube MP8, a fourth NMOS tube MN4, a sixth resistor R6, a first PMOS tube MP1 and a first NMOS tube MN1.

[0014] a source of the first PMOS transistor MP1 is connected with an input voltage VDD, a gate of the first PMOS transistor MP1 is connected with a gate and a drain of the eighth PMOS transistor MP8, a drain of the first PMOS transistor MP1 is connected with a drain and a gate of the first NMOS transistor MN1 and another input terminal of the current comparison circuit, a source of the first NMOS transistor MN1 is connected with another terminal of the sixth resistance R6 and a signal ground VSS;

[0015] a source of the eighth PMOS transistor MP8 is connected with the input voltage VDD, a drain of the eighth PMOS transistor MP8 is connected with a drain of the fourth NMOS transistor MN4, a gate of the fourth NMOS transistor MN4 is connected with an output terminal of the LDO circuit, a source of the fourth NMOS transistor MN4 is connected with one terminal of the sixth resistance R6.

[0016] Further, the current limiting control circuit comprises a fifth PMOS transistor MP5, a gate of the fifth PMOS transistor MP5 is connected with an output terminal of the current comparison circuit, a source of the fifth PMOS transistor MP5 is connected with the input voltage VDD, and a drain of the fifth PMOS transistor MP5 is connected with a gate of a power transistor in the LDO circuit.

[0017] Further, the sampling circuit comprises a seventh PMOS transistor MP7, a gate of the seventh PMOS transistor MP7 is connected with the gate of the power transistor in the LDO circuit, a source of the seventh PMOS transistor MP7 is connected with a sampling current input terminal of the current comparison circuit, and a drain of the seventh PMOS transistor MP7 is connected with the output terminal of the LDO circuit.

[0018] Further, the LDO circuit comprises an error amplifier A1, a buffer circuit, a sixth PMOS transistor MP6 and a negative feedback circuit, the sixth PMOS transistor MP6 is a power transistor, and a drain of the sixth PMOS transistor MP6 is an output terminal of the LDO circuit.

[0019] a negative input terminal of the error amplifier A1 is connected with a reference voltage Vref, an output terminal of the error amplifier A1 is connected with an input terminal of the buffer circuit, an output terminal of the buffer circuit is connected with a gate of the sixth PMOS transistor MP6, a drain of the fifth PMOS transistor MP5 and a gate of the seventh PMOS transistor MP7, a source of the sixth PMOS transistor MP6 is connected with the input voltage VDD, a drain of the sixth PMOS transistor MP6 is connected with one terminal of the negative feedback circuit, and another terminal of the negative feedback circuit is connected with a positive input terminal of the error amplifier A1.

[0020] Further, the buffer circuit comprises a fourth PMOS transistor MP4 and a third resistance R3,

[0021] One end of the third resistor R3 is connected with the input voltage VDD, the other end of the third resistor R3 is connected with the source of the fourth PMOS MP4 and the gate of the sixth PMOS MP6, the gate of the fourth PMOS MP4 is connected with the output of the error amplifier A1, and the drain of the fourth PMOS MP4 is connected with the signal ground VSS.

[0022] Further, the negative feedback circuit comprises a fourth resistor R4 and a fifth resistor R5,

[0023] One end of the fourth resistor R4 is connected with the drain of the sixth PMOS MP6, the other end of the fourth resistor R4 is connected with the positive input end of the error amplifier A1 and one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected with the signal ground VSS.

[0024] The beneficial effects of the present application are as follows: the present application samples the current of the power tube of the LDO circuit, compares it with the reference current, adjusts the size of the current by changing the gate potential of the power tube through the current limiting control circuit, and simultaneously uses the current foldback circuit to reduce the current limit along with the output voltage, thereby realizing the overcurrent protection of the LDO. When the current is within the normal range, the current limiting control tube is not turned on, and the gate potential of the power tube is only controlled by the negative feedback of the LDO. As the output current increases, the gate potential of the power tube decreases, and more current is generated. When the load is too low to cause the output voltage to decrease, the current of the current foldback circuit decreases, and the current is copied as the reference current by the current mirror and compared with the sampling current. The reference current decreases, and a smaller sampling current can make the current limiting control tube conduct, thereby reducing the current limit. The advantage of this structure is that it is suitable for LDO with low quiescent current, can withstand large current load, and the current of the sampling tube also serves as part of the output current. The power consumption of the overcurrent protection circuit is low. At the same time, the foldback overcurrent protection can improve the risk of burning the power tube when the traditional overcurrent protection circuit is short-circuited. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 It is the circuit diagram of the overcurrent protection circuit for low dropout linear regulator of the present application. DETAILED DESCRIPTION

[0026] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. The described embodiments are only a part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0027] In the technical scheme of the present application, Figure 1 is a structural diagram provided by a specific structure of an over-current protection circuit for a low-dropout linear regulator according to the present application, as Figure 1 indicated, the present application comprises: a current comparison circuit, a current foldback circuit, a sampling circuit, a current limiting control circuit and an LDO circuit.

[0028] The gate of the power tube in the LDO circuit is connected with the input end of the sampling circuit, the output end of the sampling circuit is connected with the sampling current input end of the current comparison circuit, the output end of the current comparison circuit is connected with the input end of the current limiting control circuit, the output end of the current limiting control circuit is connected with the gate of the power tube in the LDO circuit, the output end of the LDO is connected with the input end of the current foldback circuit, and the output end of the current foldback circuit is connected with the reference current input end of the current comparison circuit;

[0029] The sampling circuit is used for copying the current of the power tube in the LDO circuit in proportion to generate a sampling current, and the sampling circuit contributes to the output current together with the power tube;

[0030] The current foldback circuit is used for generating a reference current according to the output voltage of the LDO circuit; specifically, the current foldback circuit is used for adjusting the size of the reference current according to the output voltage of the LDO circuit, for the current comparison circuit, so that the current limit of the over-current protection is reduced together with the output voltage of the LDO circuit.

[0031] The current comparison circuit is used for comparing the sampling current with the reference current, and when the sampling current is greater than the reference current, the current comparison circuit generates a control signal, and the current limiting control circuit is used for pulling up the voltage at the gate of the power tube in the LDO circuit according to the control signal, so as to limit the current.

[0032] In one technical scheme of the present application, the current comparison circuit comprises: a first resistor R1, a second resistor R2, a second PMOS tube MP2, a third PMOS tube MP3, a second NMOS tube MN2, a sixth resistor R6 and a third NMOS tube MN3.

[0033] One end of the first resistor R1 is connected with an input voltage VDD, the other end of the first resistor R1 is connected with the source of the second PMOS tube MP2, the gate of the second PMOS tube MP2 is connected with the gate of the drain of the second PMOS tube MP2 and the third PMOS tube MP3, the drain of the second PMOS tube MP2 is connected with the drain of the second NMOS tube MN2, the gate of the second NMOS tube MN2 is connected with the gate of the third NMOS tube MN3, and the source of the second NMOS tube MN2 is connected with the source of the third NMOS tube MN3.

[0034] One end of the second resistor R2 is connected to the input voltage VDD, the other end of the second resistor R2 is connected to the source of the third PMOS MP3 and the output of the sampling circuit, the drain of the third PMOS MP3 is connected to the drain of the third NMOS MN3 and the input of the current control circuit, the source of the third NMOS MN3 is connected to the signal ground VSS.

[0035] In one technical solution of the present application, the current folding circuit comprises an eighth PMOS MP8, a fourth NMOS MN4, a sixth resistor R6, a first PMOS MP1 and a first NMOS MN1.

[0036] The source of the first PMOS MP1 is connected to the input voltage VDD, the gate of the first PMOS MP1 is connected to the gate and drain of the eighth PMOS MP8, the drain of the first PMOS MP1 is connected to the drain, gate of the first NMOS MN1 and the other input of the current comparison circuit, the source of the first NMOS MN1 is connected to the other end of the sixth resistor R6 and the signal ground VSS.

[0037] The source of the eighth PMOS MP8 is connected to the input voltage VDD, the drain of the eighth PMOS MP8 is connected to the drain of the fourth NMOS MN4, the gate of the fourth NMOS MN4 is connected to the output of the LDO circuit, the source of the fourth NMOS MN4 is connected to one end of the sixth resistor R6.

[0038] In one technical solution of the present application, the current control circuit comprises a fifth PMOS MP5, the gate of the fifth PMOS MP5 is connected to the output of the current comparison circuit, the source of the fifth PMOS MP5 is connected to the input voltage VDD, the drain of the fifth PMOS MP5 is connected to the gate of the power tube in the LDO circuit.

[0039] In one technical solution of the present application, the sampling circuit comprises a seventh PMOS MP7, the gate of the seventh PMOS MP7 is connected to the gate of the power tube in the LDO circuit, the source of the seventh PMOS MP7 is connected to the sampling current input of the current comparison circuit, the drain of the seventh PMOS MP7 is connected to the output of the LDO circuit.

[0040] In one technical solution of the present application, the LDO circuit comprises an error amplifier A1, a buffer circuit, a sixth PMOS MP6 and a negative feedback circuit, the sixth PMOS MP6 is a power tube, the drain of the sixth PMOS MP6 is the output of the LDO circuit.

[0041] The negative input end of the error amplifier A1 is connected with a reference voltage Vref, the output end of the error amplifier A1 is connected with the input end of a buffer circuit, the output end of the buffer circuit is connected with the gate of the sixth PMOS tube MP6, the drain of the fifth PMOS tube MP5 and the gate of the seventh PMOS tube MP7, the source of the sixth PMOS tube MP6 is connected with an input voltage VDD, the drain of the sixth PMOS tube MP6 is connected with one end of a negative feedback circuit, and the other end of the negative feedback circuit is connected with the positive input end of the error amplifier A1.

[0042] In one technical scheme of the present application, the buffer circuit comprises a fourth PMOS tube MP4, a third resistor R3,

[0043] One end of the third resistor R3 is connected with the input voltage VDD, the other end of the third resistor R3 is connected with the source of the fourth PMOS tube MP4 and the gate of the sixth PMOS tube MP6, the gate of the fourth PMOS tube MP4 is connected with the output of the error amplifier A1, and the drain of the fourth PMOS tube MP4 is connected with a signal ground VSS.

[0044] In one technical scheme of the present application, the negative feedback circuit comprises a fourth resistor R4 and a fifth resistor R5,

[0045] One end of the fourth resistor R4 is connected with the drain of the sixth PMOS tube MP6, the other end of the fourth resistor R4 is connected with the positive input end of the error amplifier A1 and one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected with the signal ground VSS.

[0046] In the present application, the sixth PMOS tube MP6 is a power tube, the seventh PMOS tube MP7 is a sampling tube, the fifth PMOS tube MP5 is a current limiting control tube, the first resistor R1, the second resistor R2, the second PMOS tube MP2, the third PMOS tube MP3, the second NMOS tube MN2 and the third NMOS tube MN3 constitute a current comparison circuit, the fourth PMOS tube MP4 and the third resistor R3 constitute a buffer circuit, A1 is an error amplifier of an LDO circuit, the fourth resistor R4 and the fifth resistor R5 are feedback resistors, the fourth NMOS tube MN4, the sixth resistor R6, the eighth PMOS tube MP8, the first NMOS tube MN1 and the first PMOS tube MP1 are a current folding back circuit.

[0047] One pole of the LDO circuit is located at the output of the error amplifier A1, and the other pole is located at the output of the LDO circuit. When the load current is small, the two poles are relatively close, which affects the stability of the LDO circuit. The buffer circuit can pull the positions of the two poles away, increase the bandwidth of the LDO, and improve the stability and frequency response.

[0048] The seventh PMOS tube MP7 of the sampling tube inputs the current signal collected from the gate of the sixth PMOS tube MP6 of the power tube to the current comparison circuit, and the sampling current also contributes to the output current, which can meet the low static current requirement of the LDO circuit. The sampling current and the reference current copied by the third NMOS tube MN3 current mirror are compared, the first resistor R1 is a high value resistor, and the second resistor R2 is a low value resistor. The ratio of the sampling current and the reference current is R1:R2. The gate potentials of the second PMOS tube MP2 and the third PMOS tube MP3 are the same, and the sizes of the second PMOS tube MP2 and the third PMOS tube MP3 are the same. When the output current is within the normal range, the gate potential of the power tube is high, the source potential of the third PMOS tube MP3 is high, and the current flowing through the third PMOS tube MP3 is less than the reference current. The drain potential of the third PMOS tube MP3 is pulled up, the third PMOS tube MP3 is in the linear region, the output of the current comparison circuit is high, the gate potential of the fifth PMOS tube MP5 of the current control tube is high, V GS <V TH, in the off state, the power transistor is only affected by the negative feedback circuit of the LDO circuit. As the output current increases, the output voltage decreases, the output potential of the error amplifier A1 decreases, the gate potential of the fourth PMOS transistor MP4 decreases, and the fourth PMOS transistor MP4 and the third resistor R3 are source followers. The gate potential of the power transistor is the output of the buffer circuit. As the gate potential of the fourth PMOS transistor MP4 decreases, the current provided by the power transistor increases, and the output voltage remains constant. When the output current exceeds the normal range, the gate potential of the power transistor continues to decrease until the sampling current increases. When the current flowing through the third PMOS transistor MP3 is greater than the sampling current, the drain potential of the third PMOS transistor MP3 decreases, causing the gate-source voltage of the current limiting control transistor to exceed the threshold voltage. The current limiting control transistor turns on, raising the gate potential of the power transistor and limiting the output current, protecting the circuit from being burned out. Changing the value of the second resistor R2 can change the current limit. When the load is short-circuited, causing the output voltage to decrease, the current foldback circuit causes the source potential of the fourth NMOS transistor MN4 to decrease through the source follower, and the current value of the current foldback circuit also decreases. This current passes through the current mirror of the eighth PMOS transistor MP8 and the first PMOS transistor MP1, then passes through the PMOS-to-NMOS circuit, and finally passes through the first NMOS transistor MN1 and the second NMOS transistor MN2 current mirror to reduce the reference current. Smaller sampling current can make the output of the current comparison circuit decrease, causing the current limiting control transistor to turn on and raise the gate potential of the power transistor, thereby achieving a decrease in the current limit along with the output voltage. The current foldback circuit can prevent the transistor from being burned out by overcurrent caused by output short-circuit.

[0049] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present application and not to limit it. Although the present application has been described in detail with reference to the examples, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the spirit and scope of the present application, and they should be covered in the scope of the claims of the present application.

Claims

1. An overcurrent protection circuit for a low dropout linear regulator, characterized by, The application relates to a current comparison circuit, a current foldback circuit, a sampling circuit, a current limiting control circuit and an LDO circuit. The gate of a power tube in the LDO circuit is connected with the input end of the sampling circuit, the output end of the sampling circuit is connected with the sampling current input end of the current comparison circuit, the output end of the current comparison circuit is connected with the input end of the current limiting control circuit, the output end of the current limiting control circuit is connected with the gate of the power tube in the LDO circuit, the output end of the LDO is connected with the input end of the current foldback circuit, and the output end of the current foldback circuit is connected with the reference current input end of the current comparison circuit. The sampling circuit is used for copying the current of the power tube in the LDO circuit in proportion to generate a sampling current. The current foldback circuit is used for generating a reference current according to the output voltage of the LDO circuit. The current comparison circuit is used for comparing the sampling current with the reference current, and when the sampling current is greater than the reference current, the current comparison circuit generates a control signal, and the current limiting control circuit is used for pulling up the voltage of the gate of the power tube in the LDO circuit according to the control signal. The current foldback circuit comprises an eighth PMOS tube MP8, a fourth NMOS tube MN4, a sixth resistor R6, a first PMOS tube MP1 and a first NMOS tube MN1. The source of the first PMOS tube MP1 is connected with an input voltage VDD, the gate of the first PMOS tube MP1 is connected with the gate and the drain of the eighth PMOS tube MP8, the drain of the first PMOS tube MP1 is connected with the drain and the gate of the first NMOS tube MN1 and another input end of the current comparison circuit, and the source of the first NMOS tube MN1 is connected with another end of the sixth resistor R6 and a signal ground VSS. The source of the eighth PMOS tube MP8 is connected with the input voltage VDD, the drain of the eighth PMOS tube MP8 is connected with the drain of the fourth NMOS tube MN4, the gate of the fourth NMOS tube MN4 is connected with the output end of the LDO circuit, and the source of the fourth NMOS tube MN4 is connected with one end of the sixth resistor R6. The current comparison circuit comprises a first resistor R1, a second resistor R2, a second PMOS tube MP2, a third PMOS tube MP3, a second NMOS tube MN2 and a third NMOS tube MN3.

2. The over-current protection circuit for a low dropout linear regulator of claim 1, wherein, One end of the first resistor R1 is connected with the input voltage VDD, the other end of the first resistor R1 is connected with the source of the second PMOS tube MP2, the gate of the second PMOS tube MP2 is connected with the gate of the third PMOS tube MP3 and the drain of the second PMOS tube MP2, the drain of the second PMOS tube MP2 is connected with the drain of the second NMOS tube MN2, the gate of the second NMOS tube MN2 is connected with the gate of the third NMOS tube MN3, and the source of the second NMOS tube MN2 is connected with the source of the third NMOS tube MN3. ​ One end of the second resistor R2 is connected to the input voltage VDD, the other end of the second resistor R2 is connected to the source of the third PMOS MP3 and the output of the sampling circuit, the drain of the third PMOS MP3 is connected to the drain of the third NMOS MN3 and the input of the current control circuit, the source of the third NMOS MN3 is connected to the signal ground VSS.

3. The over-current protection circuit for a low dropout linear regulator of claim 1, wherein, The current control circuit includes a fifth PMOS MP5, the gate of the fifth PMOS MP5 is connected to the output of the current comparison circuit, the source of the fifth PMOS MP5 is connected to the input voltage VDD, and the drain of the fifth PMOS MP5 is connected to the gate of the power tube in the LDO circuit.

4. The over-current protection circuit for a low dropout linear regulator of claim 3, wherein, The sampling circuit includes a seventh PMOS MP7, the gate of the seventh PMOS MP7 is connected to the gate of the power tube in the LDO circuit, the source of the seventh PMOS MP7 is connected to the sampling current input of the current comparison circuit, and the drain of the seventh PMOS MP7 is connected to the output of the LDO circuit.

5. The over-current protection circuit for a low dropout linear regulator of claim 4, wherein, The LDO circuit includes an error amplifier A1, a buffer circuit, a sixth PMOS MP6, and a negative feedback circuit, the sixth PMOS MP6 is a power tube, and the drain of the sixth PMOS MP6 is the output of the LDO circuit; The negative input of the error amplifier A1 is connected to the reference voltage Vref, the output of the error amplifier A1 is connected to the input of the buffer circuit, the output of the buffer circuit is connected to the gate of the sixth PMOS MP6, the drain of the fifth PMOS MP5, and the gate of the seventh PMOS MP7, the source of the sixth PMOS MP6 is connected to the input voltage VDD, the drain of the sixth PMOS MP6 is connected to one end of the negative feedback circuit, and the other end of the negative feedback circuit is connected to the positive input of the error amplifier A1.

6. The over-current protection circuit for a low dropout linear regulator of claim 5, wherein, The buffer circuit includes a fourth PMOS MP4 and a third resistor R3, One end of the third resistor R3 is connected to the input voltage VDD, the other end of the third resistor R3 is connected to the source of the fourth PMOS MP4 and the gate of the sixth PMOS MP6, the gate of the fourth PMOS MP4 is connected to the output of the error amplifier A1, and the drain of the fourth PMOS MP4 is connected to the signal ground VSS.

7. The over-current protection circuit for a low dropout linear regulator of claim 6, wherein, The negative feedback circuit includes a fourth resistor R4 and a fifth resistor R5, One end of the fourth resistor R4 is connected to the drain of the sixth PMOS MP6, the other end of the fourth resistor R4 is connected to the positive input of the error amplifier A1 and one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the signal ground VSS.

Images