Board and server

Abstract

The present application provides a board and a server, which belongs to the field of server technology. The board provided by the present application is applied to a server; the board is any one of a 60 fan backplane, an 80 fan backplane or a PCIE adapter board; the board includes a first type connector, a second type connector, a third type connector and a CPLD; the first type connector is electrically connected to the third type connector through a voltage, current and power detection module and an electronic fuse in sequence; the second type connector is connected to the voltage, current and power detection module and the CPLD; the CPLD is also connected to the electronic fuse; when the board is the 60 fan backplane, the 80 fan backplane and the PCIE adapter board, the pin allocation rules of the CPLD are consistent, and the control logic of the CPLD firmware of the CPLD is consistent. The board and server provided by the present application can save source code development time and firmware maintenance costs.

Description

Technical Field

[0001] The present application relates to the technical field of servers, and in particular to a board and a server. Background Art

[0002] With the rapid development of artificial intelligence applications, GPU AI servers, as critical infrastructure supporting deep learning and large-scale data processing, are constantly evolving and innovating. Currently, mainstream GPU AI servers can be roughly divided into two categories: CPU-only and I / O-expansion. CPU-only servers, such as the Intel Eagle Stream platform, directly support a variety of high-performance PCIe devices. I / O-expansion servers, using I / O expansion chips like the Broadcom PEX89144, increase PCIe lanes to meet the demand for connecting more devices.

[0003] Current CPU-only servers offer multiple high-speed PCIe slots for connecting GPUs, accelerator cards, storage devices, and more to meet diverse computing needs. I / O-expandable servers utilize I / O expansion chips to increase the number of PCIe lanes, enabling simultaneous management and control of more devices. These two server types differ in fan backplane structure, hardware, and signal pin design, requiring separate firmware configuration maintenance for each board, increasing source code development time and firmware maintenance costs. Summary of the Invention

[0004] In view of this, the present application provides a board and a server to save source code development time and firmware maintenance costs.

[0005] Specifically, this application is implemented through the following technical solutions:

[0006] According to a first aspect of the present application, a board is provided, which is applied to a server; the board is any one of a 60 fan backplane, an 80 fan backplane or a PCIE adapter board; the board includes a first type connector, a second type connector, a third type connector and a CPLD; wherein the first type connector is a power input connector for providing power; the second type connector is a communication connector for communication; the third type connector is a slave device connector for connecting a slave device; the first type connector is electrically connected to the third type connector through a voltage, current and power detection module and an electronic fuse in sequence; the second type connector is connected to the voltage, current and power detection module and the CPLD; the CPLD is also connected to the electronic fuse; when the board is the 60 fan backplane, the 80 fan backplane and the PCIE adapter board, the pin allocation rules of the CPLD are consistent, and the control logic of the CPLD firmware of the CPLD is consistent;

[0007] Wherein, the control logic of the CPLD firmware includes:

[0008] Identify the type of the current board. The current board type includes a 60mm fan backplane, an 80mm fan backplane, or a PCIE adapter board.

[0009] When the server is powered on, based on the type of the current board, an electronic fuse corresponding to the type is enabled;

[0010] Information is exchanged with the BMC on the motherboard via the second type connector;

[0011] When the server is powered off, turn off the corresponding electronic fuse.

[0012] According to a second aspect of the present application, a server is provided, which includes a 60 fan backplane, an 80 fan backplane and a PCIE adapter board; any one of the 60 fan backplane, the 80 fan and the PCIE adapter board includes a first type connector, a second type connector, a third type connector and a CPLD; wherein the first type connector is a power connector for providing power; the second type connector is a communication connector for communication; the third type connector is a connector for connecting a slave device; the first type connector is electrically connected to the third type connector through a voltage, current and power detection module and an electronic fuse in sequence; the second type connector is connected to the voltage, current and power detection module and the CPLD; the CPLD is also connected to the electronic fuse; the pin allocation rules of the CPLD of the 60 fan backplane, the 80 fan backplane and the PCIE adapter board are consistent, and the CPLD of the 60 fan backplane, the 80 fan backplane and the PCIE adapter board share the CPLD firmware;

[0013] Wherein, the control logic of the CPLD firmware includes:

[0014] Identify the type of the current board. The current board type includes a 60mm fan backplane, an 80mm fan backplane, or a PCIE adapter board.

[0015] When the server is powered on, based on the type of the current board, an electronic fuse corresponding to the type is enabled;

[0016] Information is exchanged with the BMC on the motherboard via the second type connector;

[0017] Turn off the main power of the server and close the corresponding electronic fuse.

[0018] The boards and servers provided in this application, whether they are 60-fan backplanes, 80-fan backplanes, or PCIE adapter boards, are designed according to the aforementioned hardware structure, thereby ensuring consistent CPLD pin assignment rules. This allows each board to share the same CPLD firmware. This means that during development, there is no need to write and maintain multiple firmware versions for different board types. Instead, a universal set of CPLD firmware can be used, significantly reducing source code development time and firmware maintenance costs.

[0019] In addition, due to the consistency of the hardware structure and the commonality of the CPLD firmware, if other types of boards need to be added or replaced in the future, only a small amount of hardware adjustments and CPLD firmware configuration will be required, without the need to redevelop the firmware or make large-scale system modifications, which is highly flexible and scalable. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the board provided for this application;

[0021] Figure 2 Schematic diagram of the 60 fan backplane provided for this application;

[0022] Figure 3 Schematic diagram of the 80 fan backplane provided for this application;

[0023] Figure 4 Schematic diagram of the PCIE adapter board provided for this application;

[0024] Figure 5 A schematic diagram of the server provided for this application. DETAILED DESCRIPTION

[0025] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.

[0026] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in this application are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0027] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0028] Specific embodiments are given below to introduce the technical solutions of the present application in detail.

[0029] The following is a description of the components that may appear in this application:

[0030] BMC: Baseboard Management Controller;

[0031] CPLD: Complex Programming Logic Device;

[0032] GPU: Graphics Processing Unit;

[0033] PCIE: High-speed serial computer expansion bus standard (Peripheral Component Interconnect Express).

[0034] Figure 1 Schematic diagram of the board provided for this application. Please refer to Figure 1 The board provided in this embodiment is applied to a server; the board is any one of a 60 fan backplane, an 80 fan backplane or a PCIE adapter board; the board includes a first type connector, a second type connector, a third type connector and a CPLD; wherein the first type connector is a power input connector for providing power; the second type connector is a communication connector for communication; the third type connector is a slave device connector for connecting a slave device; the first type connector is electrically connected to the third type connector through a voltage, current and power detection module and an electronic fuse in sequence; the second type connector is connected to the voltage, current and power detection module and the CPLD; the CPLD is also connected to the electronic fuse; when the board is the 60 fan backplane, the 80 fan backplane and the PCIE adapter board, the pin allocation rules of the CPLD are consistent, and the control logic of the CPLD firmware of the CPLD is consistent;

[0035] Wherein, the control logic of the CPLD firmware includes:

[0036] Identify the type of the current board. The current board type includes a 60mm fan backplane, an 80mm fan backplane, or a PCIE adapter board.

[0037] When the server is powered on, based on the type of the current board, an electronic fuse corresponding to the type is enabled;

[0038] Information is exchanged with the BMC on the motherboard via the second type connector;

[0039] When the server is powered off, turn off the corresponding electronic fuse.

[0040] The following is an explanation of the overall structure of the board:

[0041] It should be noted that the 60 fan backplane can be a 6056 fan backplane, and the 80 fan backplane can be an 8080 fan backplane or an 8056 fan backplane. A PCIE adapter board is a device used to expand or transfer PCIE slots, typically used to connect a GPU, memory card, or other PCIE device to the motherboard. These adapter boards provide additional flexibility and scalability. In this embodiment, the PCIE adapter board is used to connect a GPU.

[0042] Specifically, the first type connector is used to provide power, that is, to provide power to the board. Furthermore, the first type connector is electrically connected to the third type connector via a voltage, current, and power detection module and an electronic fuse.

[0043] The second type connector is used for communication and connects to the voltage, current, and power detection module and the CPLD. It provides feedback to the CPLD regarding the voltage and current detected by the power supply, current, and power detection module. It should be noted that the second type connector also connects to the baseboard management (BMC) on the motherboard, allowing the card to exchange information with the motherboard's BMC via this second type connector.

[0044] The third type of connector is used to connect a slave device. It should be noted that when the board is a fan backplane, the slave device can be a fan; when the board is a PCIE adapter board, the slave device can be a GPU.

[0045] It should be noted that the electronic fuse is also connected to the CPLD, which can monitor the status of the electronic fuse and enable the electronic fuse (by enabling the electronic fuse, the on / off of the control circuit can be achieved).

[0046] It should be noted that the voltage, current and power detection modules are used to monitor voltage, current and power, and the electronic fuses are used to protect the circuit from overcurrent or other faults.

[0047] It should be noted that when the board is a 60 fan backplane, an 80 fan backplane, or a PCIE adapter board, the CPLD pin assignment rules are consistent, and the control logic of the CPLD firmware is consistent. The following describes the CPLD pin assignment principles and the CPLD firmware control logic:

[0048] It should be noted that the consistent pin allocation rules of CPLD mean that whether it is a 60 fan backplane, an 80 fan backplane or a PCIE adapter board, the pin connection method and layout used by CPLD on these different types of boards are consistent. CPLD ensures that signal pins with the same or similar functions are consistent.

[0049] In a specific implementation, the pin allocation rules of the CPLD are set according to actual needs and are not limited in this embodiment. For example, in a possible implementation, the pin allocation rules of the CPLD are shown in Table 1:

[0050] Table 1

[0051] Pins PCIE PIB signal FAN BP signal Source-compatible signal naming B7 I2C_CPLD_SCL I2C_CPLD_SCL iI2C_CPLD_SCL_REG C8 I2C_CPLD_SCL I2C_CPLD_SCL iI2C_CPLD_SCL_FW B8 I2C_CPLD_SDA I2C_CPLD_SDA ioI2C_CPLD_SDA_FW C9 I2C_CPLD_SDA I2C_CPLD_SDA ioI2C_CPLD_SDA_REG A12 NC_PSON NC_PSON iP12V_ON_N B14 FAN1_TACH FAN1A_TACH iFAN1A_TACH C13 FAN2_TACH FAN2A_TACH iFAN2A_TACH C14 FAN3_TACH FAN3A_TACH iFAN3A_TACH D12 FAN4_TACH FAN4A_TACH iFAN4A_TACH E12 N / A FAN5A_TACH iFAN5A_TACH E14 N / A FAN6A_TACH iFAN6A_TACH E13 N / A FAN1B_TACH iFAN1B_TACH F12 N / A FAN2B_TACH iFAN2B_TACH F13 P3V3_STBY_PG P3V3_STBY_PG iP3V3_STBY_PG F14 N / A FAN3B_TACH iFAN3B_TACH G12 N / A FAN4B_TACH iFAN4B_TACH G14 N / A FAN5B_TACH iFAN5B_TACH G13 N / A FAN6B_TACH iFAN6B_TACH J12 FAN1_PWM FAN1_PWM oFAN1_PWM J14 FAN2_PWM FAN2_PWM oFAN2_PWM J13 FAN3_PWM FAN3_PWM oFAN3_PWM K12 FAN4_PWM FAN4_PWM oFAN4_PWM K13 FAN5_PWM FAN5_PWM oFAN5_PWM K14 N / A FAN6_PWM oFAN6_PWM P2 EN_SLOT1 EN_FAN1 oEN_FAN1_SLOT1 N2 EN_SLOT2 EN_FAN2 oEN_FAN2_SLOT2 P3 EN_SLOT3 EN_FAN3 oEN_FAN3_SLOT3 M3 EN_SLOT4 EN_FAN4 oEN_FAN4_SLOT4 N3 EN_SLOT5 EN_FAN5 oEN_FAN5_SLOT5 P4 EN_SLOT6 EN_FAN6 oEN_FAN6_SLOT6 M4 EN_SLOT7 EN_FAN7 oEN_SLOT7 N4 EN_SLOT8 EN_FAN8 oEN_SLOT8 N6 EN_SLOT9 EN_SLOT9 oEN_SLOT9 P6 EN_SLOT10 EN_SLOT10 oEN_SLOT10 N5 EN_P12V EN_P12V oEN_P12V M7 GOK_SLOT1 GOK_FAN1 iGOK_FAN1_SLOT1 N8 GOK_SLOT2 GOK_FAN2 iGOK_FAN2_SLOT2 P7 GOK_SLOT3 GOK_FAN3 iGOK_FAN3_SLOT3 N7 GOK_SLOT4 GOK_FAN4 iGOK_FAN4_SLOT4 P8 GOK_SLOT5 GOK_FAN5 iGOK_FAN5_SLOT5 P9 GOK_SLOT6 GOK_FAN6 iGOK_FAN6_SLOT6 M9 GOK_SLOT7 N / A iGOK_SLOT7 M10 GOK_SLOT8 N / A iGOK_SLOT8 P11 GOK_SLOT9 N / A iGOK_SLOT9 M11 GOK_SLOT10 N / A iGOK_SLOT10 N12 GOK_P12V N / A iGOK_P12V C1 CPLD_ID1 CPLD_ID1 iCPLD_ID1 D1 CPLD_ID0 CPLD_ID0 iCPLD_ID0 E1 I2C_CALPRNT I2C_CALPRNT iI2C_CALPRNT F1 N / A FAN1_PRSNT_N iFAN1_PRSNT_N F3 N / A FAN2_PRSNT_N iFAN2_PRSNT_N G3 N / A FAN3_PRSNT_N iFAN3_PRSNT_N H2 N / A FAN4_PRSNT_N iFAN4_PRSNT_N H1 N / A FAN5_PRSNT_N iFAN5_PRSNT_N H3 N / A FAN6_PRSNT_N iFAN6_PRSNT_N

[0052] Furthermore, the board provided in this embodiment can achieve the purpose of sharing CPLD firmware based on the above hardware settings.

[0053] Specifically, the control logic of the CPLD firmware includes:

[0054] Identify the type of the current board. The current board type includes a 60mm fan backplane, an 80mm fan backplane, or a PCIE adapter board.

[0055] When the server is powered on, based on the type of the current board, an electronic fuse corresponding to the type is enabled;

[0056] Information is exchanged with the BMC on the motherboard via the second type connector;

[0057] When the server is powered off, turn off the corresponding electronic fuse.

[0058] It should be noted that, referring to Table 1, in a possible implementation, a designated pin of the CPLD is set as a type identification pin; the CPLD can determine the type of the current board through the type identification pin.

[0059] Specifically, the CPLD determines the specific type of the current board by reading and analyzing the input signal on the type identification pin. In specific implementation, this process may include:

[0060] (1) Signal analysis: CPLD reads the type of signal or level on the pin and converts it into a digital signal or state.

[0061] (2) Matching and identification: Based on the converted digital signal or state, the CPLD matches and identifies the predefined board type.

[0062] (3) Determine the board type: Based on the matching result, the CPLD determines the type of the current board. For example, it determines whether the current board is a 60 fan backplane, an 80 fan backplane, or a PCIE adapter board.

[0063] Refer to the previous description and Table 1. When pins C1 and D1 are specified, the board type can be determined based on Table 2:

[0064] Table 2

[0065] CPLD ID1 CPLD ID0 Board Type 0 0 PCIE riser card 0 1 8080 fan backplane 1 0 6056 fan backplane

[0066] Specifically, referring to Table 2, the signals on the pins are marked with 0 and 1, and the type of the current board is determined by different combinations of 0 and 1.

[0067] Specifically, once the current board type is determined, the electronic fuse corresponding to that type can be enabled to ensure safe operation of the board and the device. Furthermore, while the board is operating safely, the second-type connector can exchange information with the baseboard management (BMC) on the motherboard for remote management and monitoring of server status. Furthermore, when the server is powered off, the electronic fuse corresponding to that type can be disabled to conserve energy or enable a safe shutdown.

[0068] Specifically, the board provided in this embodiment provides power via a first-type connector and monitors and protects the power supply through voltage, current, and power detection modules and electronic fuses. This ensures stable power supply and safe operation of the board under different operating conditions. Furthermore, the second-type connector is used to exchange information with the base management controller (BMC) on the motherboard to monitor and manage server status and performance. This enables the server system to respond and adjust promptly to meet demand. Furthermore, the CPLD control logic includes identifying the current board type and controlling the enabling of the electronic fuse accordingly. During power-on and power-off of the server, the electronic fuse is dynamically opened or closed based on the board type to protect the board and server system from damage or failure that could result from power problems.

[0069] The board provided in this application is configured as the above structure and the pin allocation rules of the CPLD are made consistent, so that the CPLD firmware can be shared, saving source code development time and firmware maintenance costs.

[0070] The board provided in this embodiment, whether a 60mm fan backplane, an 80mm fan backplane, or a PCIE adapter board, is designed according to the aforementioned hardware structure, thereby aligning the CPLD pin assignment rules. This allows all boards to share the same CPLD firmware. This eliminates the need to write and maintain multiple firmware versions for different board types during development. Instead, a common set of firmware can be used, significantly reducing source code development time and firmware maintenance costs.

[0071] In addition, due to the consistency of the hardware structure and the commonality of the CPLD firmware, if other types of boards need to be added or replaced in the future, only a small amount of hardware adjustments and CPLD firmware configuration will be required, without the need to redevelop the firmware or make large-scale system modifications, which is highly flexible and scalable.

[0072] Figure 2 The schematic diagram of the 60 fan backplane provided for this application. Please refer to Figure 2 When the board is a 60mm fan backplane, the third type connector is connected to the CPLD; the first type connector includes two connectors; the power of the two connectors is the same or different; the third type connector includes six connectors, and the six connectors are used to connect six 60mm fans; the CPLD is specifically used to enable six electronic fuses connected to the six connectors; the CPLD is also used to control the six 60mm fans based on the fan control signal from the BMC through the third type connector, and to detect the status parameters of the six 60mm fans, and feed back the status parameters of the six 60mm fans to the BMC through the second type connector.

[0073] Specifically, refer to Figure 2 When the board is a 60 fan backplane, the third type of connector includes six connectors, which are used to connect six 60 fans. In addition, when the board is a 60 fan backplane, the third type of connector is connected to the CPLD, which is controlled by the CPLD. That is, the purpose of controlling the fan can be achieved through the CPLD.

[0074] For further information, please refer to Figure 2 When the board is a 60 fan backplane, the first type connector includes two connectors, and the power of the two first type connectors is the same or different. By setting two connectors, different power requirements can be met.

[0075] For further information, please refer to Figure 2 When the board is a 60 fan backplane, the CPLD is specifically used to enable six electronic fuses connected to six third connectors, that is, one electronic fuse corresponds to one third connector, such as Figure 2As shown, electronic fuse 1 is connected to third connector 1, electronic fuse 2 is connected to third connector 2, ..., electronic fuse 6 is connected to third connector 6. In this way, by enabling six fuses, each circuit can be controlled to be conductive.

[0076] For further information, please refer to Figure 2 The CPLD is also used to control the six 60mm fans based on the fan control signal from the BMC through the third type connector, detect the status parameters of the six 60mm fans, and feed back the status parameters of the six 60mm fans to the BMC through the second type connector.

[0077] It should be noted that the fan control signal comes from the BMC of the motherboard. The BMC on the motherboard can generate the fan control signal based on the status parameters of the fan. The specific generation principle of the fan control signal can be found in the description of the relevant technology and will not be repeated here.

[0078] Specifically, controlling the six 60mm fans may include adjusting the speed or starting and stopping the fans, and detecting the status parameters of the six 60mm fans may include detecting the fan speed and temperature. It should be noted that after detecting the fan status parameters, the fan status parameters can be fed back to the BMC via the second type connector. The BMC performs server management and monitoring based on the fan status parameters.

[0079] The board provided in this embodiment is Figure 2 The internal structure shown can effectively manage and control multiple fans to ensure the stability and reliability of the server. At the same time, it can monitor the operating status of the fans in real time and provide feedback information to the BMC so that the fan operation status of the entire server can be adjusted and managed in a timely manner.

[0080] Figure 3 Schematic diagram of the 80 fan backplane provided for this application. Please refer to Figure 3 When the board is an 80 fan backplane, the third type connector is connected to the CPLD; the first type connector includes two connectors; the power of the two connectors is the same or different; the third type connector includes five connectors, and the five connectors are used to connect five 80 fans; the CPLD is specifically used to enable five electronic fuses connected to the five connectors; the CPLD is also used to control the five 80 fans based on the fan control signal from the BMC through the third type connector, and feed back the status parameters of the five 80 fans to the BMC through the second type connector.

[0081] Please refer to Figure 3Similar to the 60 fan backplane, when the board is an 80 fan backplane, the third type of connector includes five connectors, which are used to connect five 80 fans. In addition, when the board is an 80 fan backplane, the third type of connector is connected to the CPLD, which is controlled by the CPLD. That is, the purpose of controlling the fan can be achieved through the CPLD.

[0082] For further information, please refer to Figure 3 When the board is an 80 fan backplane, the first type connector includes two connectors, and the power of the two first type connectors is the same or different. By setting two connectors, different power requirements can be met.

[0083] Please continue to refer to Figure 3 When the board is an 80 fan backplane, the CPLD is specifically used to enable five electronic fuses connected to five third connectors, that is, one electronic fuse corresponds to one third connector, such as Figure 3 As shown, electronic fuse 1 is connected to third connector 1, electronic fuse 2 is connected to third connector 2, ..., electronic fuse 5 is connected to third connector 5. In this way, by enabling six fuses, each circuit can be controlled to be conductive.

[0084] Furthermore, the CPLD is also used to control the five 80mm fans based on the fan control signal from the BMC through the third type connector, detect the status parameters of the five 80mm fans, and feed back the status parameters of the five 80mm fans to the BMC through the second type connector.

[0085] It should be noted that the fan control signal comes from the BMC of the motherboard. The BMC on the motherboard can generate the fan control signal based on the status parameters of the fan. The specific generation principle of the fan control signal can be found in the description of the relevant technology and will not be repeated here.

[0086] Furthermore, controlling the five 80mm fans can include adjusting their speed or starting and stopping them, and detecting their status parameters can include detecting their speed and temperature. It should be noted that after detecting the fan status parameters, they can be fed back to the BMC via the second-class connector. The BMC then manages and monitors the server based on the fan status parameters.

[0087] The board provided in this embodiment is Figure 3 The internal structure shown can effectively manage and control multiple fans to ensure the stability and reliability of the server. At the same time, it can monitor the operating status of the fans in real time and provide feedback information to the BMC so that the fan operation status of the entire server can be adjusted and managed in a timely manner.

[0088] Figure 4Schematic diagram of the PCIE adapter board provided for this application. Please refer to Figure 4 When the board is a PCIE adapter board, the first type of connector includes two connectors; the power of the two connectors is the same or different; the third type of connector includes multiple connectors, and the multiple connectors are used to connect multiple GPUs to power the multiple GPUs; wherein the multiple GPUs are controlled by the CPU on the motherboard; the CPLD is specifically used to enable multiple electronic fuses connected to the multiple connectors.

[0089] Specifically, refer to Figure 4 When the board is a PCIE adapter board, the first type connector is electrically connected to the third type connector through the voltage, current and power detection module and the electronic fuse in sequence.

[0090] Specifically, the first type connector may include two connectors, and the power of the two first type connectors may be the same or different. By providing two connectors, different power requirements can be met.

[0091] Further, refer to Figure 4 The third type of connector includes multiple connectors, and the multiple connectors are used to connect multiple GPUs to provide power to the multiple GPUs; it should be noted that the GPU is connected to the CPU on the motherboard and is controlled by the CPU on the motherboard.

[0092] Specifically, the CPLD is specifically used to enable multiple electronic fuses connected to the multiple connectors to conduct corresponding circuits.

[0093] It should be noted that each of the multiple connectors may include one type of connector or two types of connectors. When each connector includes two types of connectors, the two types of connectors have different output powers to provide different powers for the GPU.

[0094] Optional, please continue to refer to Figure 4 In one possible embodiment, when the board is a PCIE adapter board, the board further includes a fourth type connector; the fourth type connector is connected to the first type connector and the CPLD respectively; the fourth type connector is used to connect an external fan;

[0095] The CPLD is further configured to control the external fan and detect status parameters of the external fan when an external fan is detected through the Category 4 connector.

[0096] It should be noted that the Category 4 connector is used to connect an external fan, and the external fan is controlled by the CPLD. In other words, when the CPLD detects the presence of an external fan through the Category 4 connector, it controls the external fan and detects the status parameters of the external fan.

[0097] Optional, please continue to refer to Figure 4 In one possible implementation, the board further includes a Category 5 connector; the Category 5 connector is connected to the first Category 1 connector; wherein the Category 5 connector is a power output connector for supplying power to the fan backplane.

[0098] For details, see Figure 4 The fifth type of connector is a power output connector, which is used to power a fan backplane (which can be a 60 fan backplane or an 80 fan backplane). For example, in one possible implementation, it is used to power an 80 fan backplane.

[0099] The board provided in this embodiment is Figure 4 The internal structure shown enables the PCIE adapter board to effectively connect multiple GPUs. Furthermore, the CPLD enables control and monitoring of electronic fuses and external fans, thereby improving server stability and reliability. Furthermore, the fifth connector can also power the fan backplane.

[0100] Corresponding to the aforementioned embodiment of a board card, the present application also provides an embodiment of a server.

[0101] Figure 5 Schematic diagram of the server provided for this application. Please also refer to Figure 5 and Figure 1 , the server includes a 60 fan backplane, an 80 fan backplane and a PCIE adapter board; any one of the 60 fan backplane, the 80 fan and the PCIE adapter board includes a first type connector, a second type connector, a third type connector and a CPLD; wherein the first type connector is a power connector for providing power; the second type connector is a communication connector for communication; the third type connector is a connector for connecting a slave device; the first type connector is electrically connected to the third type connector through a voltage, current and power detection module and an electronic fuse in sequence; the second type connector is connected to the voltage, current and power detection module and the CPLD; the CPLD is also connected to the electronic fuse; the pin allocation rules of the CPLD of the 60 fan backplane, the 80 fan backplane and the PCIE adapter board are consistent, and the CPLD of the 60 fan backplane, the 80 fan backplane and the PCIE adapter board share the CPLD firmware;

[0102] Wherein, the control logic of the CPLD firmware includes:

[0103] Identify the type of the current board. The current board type includes a 60mm fan backplane, an 80mm fan backplane, or a PCIE adapter board.

[0104] When the server is powered on, based on the type of the current board, an electronic fuse corresponding to the type is enabled;

[0105] Information is exchanged with the BMC on the motherboard via the second type connector;

[0106] Turn off the main power of the server and close the corresponding electronic fuse.

[0107] Specifically, the specific structures of the 60 fan backplane, 80 fan backplane and PCIE adapter board in the server, as well as the control logic of the CPLD firmware, can be found in the previous description and will not be repeated here.

[0108] In this implementation, the server, whether it's a 60mm fan backplane, an 80mm fan backplane, or a PCIE adapter board, is designed according to the aforementioned hardware structure, resulting in consistent CPLD pin assignments. This allows the 60mm fan backplane, the 80mm fan backplane, and the PCIE adapter to share the same CPLD firmware. This eliminates the need to write and maintain multiple firmware versions for different board types during development. Instead, a common set of firmware can be used, significantly reducing source code development time and firmware maintenance costs.

[0109] In addition, due to the consistency of the hardware structure and the commonality of the CPLD firmware, if other types of boards need to be added or replaced in the future, only a small amount of hardware adjustments and CPLD firmware configuration will be required, without the need to redevelop the firmware or make large-scale system modifications, which is highly flexible and scalable.

[0110] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A board, characterized in that: The board is applied to a server; the board is any one of a 60 fan backplane, an 80 fan backplane or a PCIE adapter board; the board includes a first type connector, a second type connector, a third type connector and a CPLD; wherein the first type connector is a power input connector for providing power; the second type connector is a communication connector for communication; the third type connector is a slave device connector for connecting a slave device; the first type connector is electrically connected to the third type connector via a voltage, current and power detection module and an electronic fuse in sequence; the second type connector is connected to the voltage, current and power detection module and the CPLD; the CPLD is also connected to the electronic fuse; when the board is the 60 fan backplane, the 80 fan backplane and the PCIE adapter board, the pin allocation rules of the CPLD are consistent, and the control logic of the CPLD firmware of the CPLD is consistent; Wherein, the control logic of the CPLD firmware includes: Identify the type of the current board. The current board type includes a 60mm fan backplane, an 80mm fan backplane, or a PCIE adapter board. When the server is powered on, based on the type of the current board, an electronic fuse corresponding to the type is enabled; Information is exchanged with the BMC on the motherboard via the second type connector; When the server is powered off, turn off the electronic fuse corresponding to the type mentioned above; The CPLD has consistent pin connection methods and layouts on different types of boards, and signal pins with the same function are consistent; the first-type connector includes two connectors, and the two first-type connectors have the same or different power; the third-type connector includes multiple connectors, and the multiple connectors are used to connect multiple GPUs to provide power for the multiple GPUs; The board also includes a fourth type connector; the fourth type connector is connected to the first type connector and the CPLD respectively; the fourth type connector is used to connect an external fan; The board also includes a fifth category connector; the fifth category connector is connected to the first category connector; wherein the fifth category connector is a power output connector, which is used to supply power to the fan backplane.

2. The board according to claim 1, wherein: The board is a 60 fan backplane; the third type connector is connected to the CPLD; The first type of connector includes two connectors; the power of the two connectors is the same or different; The third type of connector includes six connectors, and the six connectors are used to connect six 60 fans; The CPLD is specifically configured to enable six electronic fuses connected to the six connectors; The CPLD is also used to control the six 60mm fans based on the fan control signal from the BMC through the third type connector, detect the status parameters of the six 60mm fans, and feed back the status parameters of the six 60mm fans to the BMC through the second type connector.

3. The board according to claim 1, wherein: The board is an 80 fan backplane; the third type connector is connected to the CPLD; The third type of connector includes five connectors, and the five connectors are used to connect five 80 fans; The CPLD is specifically configured to enable five electronic fuses connected to the five connectors; The CPLD is further configured to control the five 80mm fans based on fan control signals from the BMC via the third type connector, and feed back status parameters of the five 80mm fans to the BMC via the second type connector.

4. The board according to claim 1, wherein: The board is a PCIE adapter board; The CPLD is specifically used to enable multiple electronic fuses connected to the multiple connectors.

5. The board according to claim 1, wherein: Each of the plurality of connectors includes two types of connectors having different output powers to provide different powers to the GPU.

6. The board according to claim 4 or 5, characterized in that: The CPLD is further configured to control the external fan and detect status parameters of the external fan when an external fan is detected through the Category 4 connector.

7. The board according to claim 1, wherein: The designated pin of the CPLD is set as a type identification pin; wherein, The CPLD determines the type of the current board through the type identification pin.

8. The board according to claim 1, wherein: The 60 fan backplane is a 6056 fan backplane; the 80 fan backplane is an 8080 fan backplane or an 8056 fan backplane.

9. A server, characterized in that: The server includes a 60 fan backplane, an 80 fan backplane and a PCIE adapter board; any one of the 60 fan backplane, the 80 fan and the PCIE adapter board includes a first type connector, a second type connector, a third type connector and a CPLD; wherein the first type connector is a power connector for providing power; the second type connector is a communication connector for communication; the third type connector is a connector for connecting a slave device; the first type connector is electrically connected to the third type connector through a voltage, current and power detection module and an electronic fuse in sequence; the second type connector is connected to the voltage, current and power detection module and the CPLD; the CPLD is also connected to the electronic fuse; the pin allocation rules of the CPLD of the 60 fan backplane, the 80 fan backplane and the PCIE adapter board are consistent, and the CPLD of the 60 fan backplane, the 80 fan backplane and the PCIE adapter board share the CPLD firmware; Wherein, the control logic of the CPLD firmware includes: Identify the type of the current board. The current board type includes a 60mm fan backplane, an 80mm fan backplane, or a PCIE adapter board. When the server is powered on, based on the type of the current board, an electronic fuse corresponding to the type is enabled; Information is exchanged with the BMC on the motherboard via the second type connector; Turn off the main power of the server and close the electronic fuse corresponding to the type described; The CPLD has consistent pin connection methods and layouts on different types of boards, and signal pins with the same function are consistent; the first-type connector includes two connectors, and the two first-type connectors have the same or different power; the third-type connector includes multiple connectors, and the multiple connectors are used to connect multiple GPUs to provide power for the multiple GPUs; The board also includes a fourth type connector; the fourth type connector is connected to the first type connector and the CPLD respectively; the fourth type connector is used to connect an external fan; The board also includes a fifth category connector; the fifth category connector is connected to the first category connector; wherein the fifth category connector is a power output connector, which is used to supply power to the fan backplane.

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