Method and apparatus for non-volatile two-end memory data retention

Abstract

The invention discloses a method for data retention in a nonvolatile two-end memory, and the method is characterized in that the method comprises the steps: obtaining a detection time interval; judging whether the detection time interval reaches a preset duration or not; judging whether the storage unit meets an enhancement processing condition or not by judging whether the time interval reaches a preset duration or not; and performing enhancement processing on the storage unit in response to meeting the enhancement processing condition. According to the embodiment of the invention, the storage unit of the nonvolatile two-end memory is regularly enhanced, so that serious degradation of the storage unit of the nonvolatile two-end memory can be effectively prevented, and the serious problems of data errors or data loss and the like are avoided.

Description

Technical Field

[0001] The present disclosure generally relates to the field of non-volatile two-terminal memory data processing technology. More specifically, the present disclosure relates to a method and apparatus for non-volatile two-terminal memory data retention. Background Art

[0002] Non-volatile two-terminal memories represent a recent innovation in the field of integrated circuit technology. Although many non-volatile two-terminal memory technologies are in the development stage, a number of technical concepts proposed for non-volatile two-terminal memory devices have been demonstrated by the inventors and are in one or more verification stages to disprove related theories or technologies. The inventors believe that a variety of two-terminal memory technologies (e.g., resistive switch memory, magnetoresistive memory, ferroelectric memory, phase change memory, conductive bridge memory) have convincing evidence to show a number of advantages over competing technologies in the semiconductor electronics industry.

[0003] Non-volatile two-terminal memories generally include resistive memory and polarization state memory, both of which are likely to degrade.

[0004] Taking resistive random access memory as an example, in the prior art, data can be written, read and stored through resistive random access memory (RRAM). Resistive random access memory has the advantages of high density, low power consumption and fast read and write speed, so it has broad application prospects in the field of data storage.

[0005] However, the data in the resistive memory may experience degradation during the retention process. Specifically, the data is initially stored in a specific data storage unit (data cell) in the resistive memory in a highly reliable and accurate form. With the passage of time and the influence of external environmental factors (such as temperature fluctuations, electromagnetic interference, material aging, etc.), some data storage units (data cells) begin to experience a degradation process, and the data storage units (data cells) degenerate into resistive memory marginal cells (marginal cells). Resistive memory marginal cells (marginal cells) refer to those storage cells at the edge of the normal working range. Their data retention capabilities begin to weaken and their sensitivity to external interference and internal physical changes increases. Over time, this degradation trend tends to accelerate. When this degradation reaches a certain level, especially when the stability of the data is reduced to below the limit threshold of the sense amplifier (Sense Amplifier), the sense amplifier (Sense Amplifier) ​​may not be able to accurately distinguish between signals and noise, resulting in read errors.

[0006] Similarly, polarization state memory also has this type of degradation phenomenon, which will not be introduced in detail here.

[0007] In view of this, there is an urgent need to provide a solution for maintaining data in a non-volatile two-terminal memory, so as to strengthen the processing of edge units of the non-volatile two-terminal memory and improve the degradation problem of data in the non-volatile two-terminal memory during the storage process. Summary of the invention

[0008] In order to at least solve one or more of the technical problems mentioned above, the present disclosure proposes a solution for data retention in a non-volatile two-terminal memory in multiple aspects.

[0009] According to a first aspect of the present application, a method for maintaining data in a non-volatile two-terminal memory is provided, the method comprising: obtaining a detection time interval; determining whether the detection time interval reaches a preset duration; determining whether a storage unit satisfies an enhanced processing condition by determining whether the time interval reaches a preset duration; and in response to satisfying the enhanced processing condition, performing enhanced processing on the storage unit.

[0010] According to an embodiment of the present application, the detection time interval represents the time interval between the current time and the most recent time when the storage unit in the non-volatile two-terminal memory is successfully strengthened.

[0011] According to an embodiment of the present application, the detection time interval represents the time interval between the current time and the most recent time when the storage unit in the non-volatile two-terminal memory starts to be enhanced.

[0012] According to an embodiment of the present application, it further includes: in response to the occurrence of an interrupt condition, stopping the strengthening process of the storage unit in the non-volatile two-terminal memory.

[0013] According to one embodiment of the present application, the interrupt condition includes that a storage unit in the non-volatile two-terminal memory is occupied.

[0014] According to one embodiment of the present application, it further includes: using a state verification condition to determine whether the storage unit meets the enhanced processing condition, the state verification condition is used to determine whether the state of the storage unit is a weak state or a strong state; the storage unit meets the enhanced processing condition includes: the state of the storage unit is a weak state.

[0015] According to one embodiment of the present application, a state verification condition is first used to determine whether the storage unit meets the enhanced processing condition. If the state of the storage unit is a weak state, the storage unit in the non-volatile two-terminal memory is enhanced after the detection time interval reaches a preset duration.

[0016] According to one embodiment of the present application, after the detection time interval reaches a preset duration, a state verification condition is used to determine whether the storage unit meets the enhanced processing conditions. If the state of the storage unit is a weak state, the storage unit in the non-volatile two-terminal memory is enhanced.

[0017] According to one embodiment of the present application, it further includes: after the storage unit is enhanced, executing the following steps: determining again whether the storage unit after the enhanced processing meets the enhanced processing conditions; in response to meeting the enhanced processing conditions, continuing to enhance the storage unit until the storage unit no longer meets the enhanced processing conditions.

[0018] According to one embodiment of the present application, the non-volatile two-end memory stores the enhanced area address; before the storage unit is enhanced, the enhanced area address is loaded into the non-volatile two-end memory, and the enhanced area address stored in the non-volatile two-end memory is added by 1 to obtain the address of the storage unit.

[0019] According to one embodiment of the present application, when the state of the storage unit is a strong state, the address of the storage unit is recorded.

[0020] According to one embodiment of the present application, the state verification condition includes: a first storage state verification condition and a second storage state verification condition, the first storage state verification condition is used to verify that the storage unit is a first high state or a second high state, and the second storage state verification condition is used to verify that the storage unit is a first low state or a second low state.

[0021] According to one embodiment of the present application, the state verification condition includes: the non-volatile two-terminal memory is a resistive memory, and the state verification condition includes: a first resistance state verification condition and a second resistance state verification condition, the first resistance state verification condition is used to verify that the storage unit is a first high resistance state or a second high resistance state, and the second resistance state verification condition is used to verify that the storage unit is a first low resistance state or a second low resistance state.

[0022] According to one embodiment of the present application, the first resistance state verification condition includes an erase verification condition and an edge erase verification condition, and the current of the storage unit in the first high resistance state is greater than the erase verification current and less than the edge erase verification current.

[0023] According to one embodiment of the present application, the second resistance state verification condition includes a programming verification condition and a marginal programming verification condition, and the current of the memory cell in the first low resistance state is less than the programming verification current and greater than the marginal programming verification current.

[0024] According to one embodiment of the present application, performing enhanced processing on the storage cell includes: performing enhanced erasing operation processing on the storage cell when the state of the storage cell is a first high-resistance state; and / or performing enhanced programming operation processing on the storage cell when the state of the storage cell is a first low-resistance state.

[0025] According to one embodiment of the present application, the resistive memory includes one or more of an electric resistance switch memory, a phase change memory, a magnetoresistive memory and a conductive bridge memory.

[0026] According to one embodiment of the present application, the non-volatile two-terminal memory is a polarization state memory, and the state verification condition includes: a first polarization state verification condition and a second polarization state verification condition, the first polarization state verification condition is used to verify that the storage unit is a first negative polarization state or a second negative polarization state, and the second polarization state verification condition is used to verify that the storage unit is a first positive polarization state or a second positive polarization state.

[0027] According to one embodiment of the present application, the first polarization state verification condition includes a second erase verification condition and a second edge erase verification condition, and the polarization amount of the storage unit in the first negative polarization state is between the second erase verification polarization amount and the second edge erase verification polarization amount.

[0028] According to one embodiment of the present application, the second polarization state verification condition includes a second programming verification condition and a second edge programming verification condition, and the polarization amount of the storage cell in the first positive polarization state is between the second programming verification polarization amount and the second edge programming verification polarization amount.

[0029] According to one embodiment of the present application, performing enhanced processing on the storage cell includes: when the state of the storage cell is a first negative polarization state, performing enhanced erasing operation processing on the storage cell; when the state of the storage cell is a first positive polarization state, performing enhanced programming operation processing on the storage cell.

[0030] According to one embodiment of the present application, the polarization state memory includes a ferroelectric random access memory (FeRAM).

[0031] According to a second aspect of the present disclosure, there is provided an apparatus for maintaining data in a non-volatile two-terminal memory, comprising: a processor; a memory for storing a computer program; wherein the processor is configured to execute the computer program to implement the method as described above.

[0032] According to a third aspect of the present disclosure, there is provided a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by one or more processors, the method as described above is implemented.

[0033] With the aid of the scheme for maintaining data of the non-volatile two-terminal memory as provided above, the disclosed embodiment can effectively prevent serious degradation of the storage cells of the non-volatile two-terminal memory by regularly strengthening the storage cells of the non-volatile two-terminal memory, thereby avoiding serious problems such as data errors or data loss.

[0034] Furthermore, in some embodiments, before using the status verification condition to determine whether the storage unit meets the enhanced processing condition, the enhanced area address is loaded into the non-volatile two-terminal memory, and the enhanced area address is increased by 1, so that the address of the storage unit that currently needs to be judged for strength can be located, so that the storage units that meet the enhanced processing conditions can be enhanced in sequence.

[0035] Furthermore, in some embodiments, when the state of the storage unit is determined to be a strong state, the address of the storage unit is recorded, and a starting address can be provided for the next enhanced processing operation, so that the storage units that meet the enhanced processing conditions can be enhanced in sequence, ensuring that the strength judgment and enhanced processing operations can traverse the addresses of all storage units in the non-volatile two-end memory, avoiding the need to re-acquire the enhanced area address, thereby significantly improving the efficiency of the enhanced processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0037] Figure 1 An exemplary flow chart of a resistive memory in the prior art during a data writing process is shown;

[0038] Figure 2a A schematic diagram showing the principle of degradation of resistive random access memory is shown;

[0039] Figure 2b A schematic diagram showing degradation of polarization state memory is shown;

[0040] Figure 3 An exemplary flowchart of a method for maintaining data in a resistive memory according to an embodiment of the present application is shown;

[0041] Figures 4a to 4c A schematic diagram showing setting the time interval based on the storage unit being successfully reinforced is shown;

[0042] Figure 5An exemplary flowchart of a method for maintaining data in a resistive memory according to a preferred embodiment of the present disclosure is shown;

[0043] Figure 6 An exemplary structural block diagram of a device for maintaining data in a resistive memory according to an embodiment of the present application is shown;

[0044] Figure 7 An exemplary block diagram of a system for maintaining data in a resistive memory according to an embodiment of the present application is shown;

[0045] Figure 8 An exemplary structural block diagram of the resistive memory electronic operating environment of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0047] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present disclosure indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0048] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0049] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0050] The present invention relates to a nonvolatile two-terminal memory for digital information storage. In some embodiments, the nonvolatile two-terminal memory cell may include a memory based on resistance technology and a memory based on polarity technology, the former may be, for example, a nonvolatile resistance switch two-terminal memory cell, or may be, for example, a polarization state memory. The nonvolatile resistance two-terminal memory cell (also referred to as a resistance switch memory cell or a resistive memory) used herein includes a circuit element having two conductive contacts (also referred to as electrodes or terminals in this article), and having a storage functional area (also referred to as a switching layer) between the two conductive contacts. In the context of resistive memory, the storage functional area of ​​the two-terminal memory device exhibits multiple stable or semi-stable resistance states, each resistance state having a different resistance. Examples of resistance switch two-terminal memory devices may include, but are not limited to, a resistance random access memory currently being developed by the assignee of the present patent application.

[0051] In addition to the resistance characteristic, the corresponding state of the plurality of states can also be formed or activated in response to a suitable electrical signal applied to the two conductive contacts. The suitable electrical signal can be a voltage value, a current value, a pulse width, a pulse height or a current polarity, etc. or a suitable combination thereof.

[0052] Therefore, the non-volatile two-terminal memory of the present application mainly includes resistive random access memory and polarization state memory, wherein the resistive random access memory includes resistive random access memory (RRAM), phase change random access memory (PCRAM), magnetoresistive random access memory (MRAM) and conductive bridging random access memory (CBRAM) or their combination. Polarization state memory includes ferroelectric random access memory (FeRAM).

[0053] The specific implementation of the present disclosure is described in detail below with reference to the accompanying drawings.

[0054] Figure 1 An exemplary flow chart of a resistive memory in the prior art during a data writing process 100 is shown.

[0055] like Figure 1As shown, in the prior art, during the data writing process of the resistive memory, first, in step S110, the data writing state machine is started. Then, in step S120, the PGM stage or ERS stage is entered, that is, data programming or data erasure is performed. Specifically, data programming is the process of writing "1" to the storage cell of the resistive memory, at which time the storage cell of the resistive memory changes from a high resistance state to a low resistance state. The PGM stage covers the entire process of data programming, including writing data to the designated cell of the resistive memory and performing a verification process to ensure that the data is stored accurately. Data erasure is the process of writing "0" to the storage cell of the resistive memory, at which time the storage cell of the resistive memory changes from a low resistance state to a high resistance state. In the ERS stage, the target data is erased from the storage cell, and the thoroughness of the erasure operation is also verified through a verification process. After completing the above operations, in step S130, the data writing state machine will execute the end process, marking the successful completion of the entire data writing process.

[0056] However, in the process of writing data in the resistive memory shown above, as time goes by and due to the influence of external environmental factors (such as temperature fluctuations, electromagnetic interference, material aging, etc.), some data storage units (data cells) begin to experience a degradation process, and the data storage units (data cells) degenerate into marginal cells of the resistive memory, which gradually reduces the storage performance of the resistive memory. And this degradation phenomenon is continuous and aggravated. When the degree of degradation reaches below the limit threshold of the sense amplifier (Sense Amplifier), it will cause data reading errors, seriously affecting the integrity and reliability of the data.

[0057] Figure 2a A schematic diagram showing the principle of degradation of resistive random access memory is shown.

[0058] like Figure 2a As shown, the horizontal axis represents the schematic diagram of the current intensity in the storage unit. When "0" is stored in the storage unit of the resistive memory, it is in a high resistance state and the current is low; when "1" is stored in the storage unit of the resistive memory, it is in a low resistance state and the current is high.

[0059] Assume that the lower threshold of the current in the storage unit of the resistive memory is EV, and the upper threshold is PV. Then, when the storage unit of the resistive memory stores "0", ideally, its low current value should not be higher than the EV value (in Figure 2a When the RRAM cell stores “1”, the high current value should ideally be no less than the PV value (in Figure 2a is referred to as “strong 1”).

[0060] However, if the RRAM degrades, the following situation may occur: when "0" is stored in the storage cell of the RRAM, the low current value may gradually increase and exceed the lower threshold EV; and when "1" is stored in the storage cell of the RRAM, its high current value may gradually decrease and fall below the upper threshold PV. Therefore, if the RRAM degrades more and more seriously, the low current value and the high current value will gradually move closer to the middle, and when this convergence reaches a certain degree, it will be impossible to distinguish whether "0" or "1" is stored in the storage cell.

[0061] Assume that the lower critical threshold of the current in the storage cell of the resistive memory is MEV, and the upper critical threshold is MPV. Then, when the storage cell of the resistive memory stores "0", if its low current value exceeds the lower critical threshold MEV, the data stored in the storage cell may not be recognized and cannot be recovered; and when the storage cell of the resistive memory stores "1", if its high current value is lower than the upper critical threshold MPV, the data stored in the storage cell may not be recognized and cannot be recovered.

[0062] In order to prevent the memory cells of the resistive memory from further degradation to the point where they cannot be recognized or restored, a low current value between EV and MEV (at Figure 2a It is strengthened when the current value is between MPV and PV (referred to as "weak 0"), so that the low current value is restored to no higher than EV; further, the high current value can be between MPV and PV (in Figure 2a It is strengthened when the high current value is restored to not less than PV.

[0063] It can be seen that the degradation of the resistive memory will cause the low current value and the high current value to be close to each other and become indistinguishable; while strengthening the resistive memory will push the low current value and the high current value away from each other to make the distinction between the two greater.

[0064] Figure 2b A schematic diagram showing degradation of polarization state memory is shown.

[0065] like Figure 2b As shown, the vertical axis represents the schematic diagram of the electric field strength or electrode voltage in the storage unit, and the horizontal axis represents the polarization amount of the storage unit. When "0" is stored in the storage unit, it is negatively (this application Figure 2b When "1" is stored in the memory cell, it is polarized in the forward direction.

[0066] Assume that the negative threshold of negative polarization in the storage unit of the polarization state memory is P0, and the positive threshold is P1. Then, when the storage unit of the polarization state memory stores "0", ideally, its polarization should be on the left side of the P0 point (at Figure 2bIn the example, it is called "strong 0", at which point the absolute value of the polarization of the storage unit is greater than the absolute value of the polarization at P0), and when the storage unit of the polarization state memory stores "1", ideally its polarization should be to the right of point P1 (at Figure 2b It is called "strong 1" in the figure. At this time, the absolute value of the polarization of the storage unit is greater than the absolute value of the polarization at P1).

[0067] However, if the polarization memory degrades, the following situation may occur: when "0" is stored in the storage cell of the polarization memory, its negative polarization may gradually weaken and exceed the P0 point; and when "1" is stored in the storage cell of the polarization memory, its positive polarization may gradually weaken and exceed the P1 point. Therefore, if the degradation of the polarization memory becomes more and more serious, the negative polarization and the positive polarization will gradually move closer to the middle, and when this convergence reaches a certain degree, it will be impossible to distinguish whether the storage cell is "0" or "1".

[0068] Assume that the negative critical threshold of the current in the storage cell of the polarization state memory is MP0, and the positive critical threshold is MP1. Then, when the storage cell of the polarization state memory stores "0", if its negative polarization exceeds the negative critical threshold MP0, the data stored in the storage cell may not be recognized and cannot be recovered; and when the storage cell of the polarization state memory stores "1", if its positive polarization exceeds the positive critical threshold MP1, the data stored in the storage cell may not be recognized and cannot be recovered.

[0069] In order to prevent the storage unit of the polarization state memory from further degrading to the point where it cannot be recognized or restored, the negative polarization amount can be between P0 and MP0 (in Figure 2b It can be strengthened when the positive polarization is between MP1 and P1 (referred to as "weak 0"), so that the negative polarization does not exceed P0; further, it can be strengthened when the positive polarization is between MP1 and P1 (referred to as "weak 0" in Figure 2b It is strengthened when the forward polarization is at a value not exceeding P1 (referred to as "weak 1" in the text).

[0070] It can be seen that the degradation of the polarization state memory will cause the negative polarization amount and the positive polarization amount to be close to each other so that they cannot be distinguished; while strengthening the polarization state memory will push the negative polarization amount and the positive polarization amount away from each other to make the distinction between the two greater.

[0071] In view of this, the embodiments of the present disclosure provide a solution for maintaining data in a non-volatile two-terminal memory, which can regularly improve the degradation problem of data in the non-volatile two-terminal memory during the storage process.

[0072] According to one aspect of the present disclosure, a method for maintaining data in a non-volatile two-terminal memory is provided, characterized in that the method includes: obtaining a detection time interval; determining whether the detection time interval reaches a preset duration; determining whether a storage unit satisfies an enhanced processing condition based on whether the time interval reaches a preset duration; and in response to satisfying the enhanced processing condition, performing enhanced processing on the storage unit.

[0073] The following will first take the resistive random access memory as an example for introduction.

[0074] According to an embodiment of the present disclosure, the disclosed embodiment provides a solution for maintaining data of a resistive random access memory, which can regularly improve the degradation problem of data of the resistive random access memory during the storage process.

[0075] Figure 3 An exemplary flowchart of a method for maintaining data in a resistive random access memory according to an embodiment of the present application is shown.

[0076] like Figure 3 As shown, the method includes: in step S310, obtaining a detection time interval; in step S320, determining whether the detection time interval reaches a preset duration; in step S330, determining whether the storage unit meets enhanced processing conditions based on whether the time interval reaches a preset duration; and, in step S340, in response to meeting the enhanced processing conditions, performing enhanced processing on the storage unit.

[0077] In the present application, a time interval can be predetermined, and whenever the predetermined time interval expires, the enhanced processing of the storage unit can be automatically started. According to this embodiment, the approximate duration of the degradation of the storage unit can be estimated, and the storage unit can be regularly enhanced before the expiration of the approximate duration. It should be understood that the enhanced processing according to the above embodiment can be enforced, that is, whether the time interval reaches the preset duration can be used as the only criterion for judging whether the storage unit meets the enhanced processing conditions. This enforced enhanced processing ensures that the storage unit is always regularly enhanced, so that it is in an effective state for a long time, and prevents serious problems such as data loss caused by negligent enhancement of the storage unit.

[0078] According to an embodiment of the present disclosure, the detection time interval indicates the time interval between the current time and the most recent time when the memory cell in the resistive random access memory is successfully enhanced.

[0079] According to the above-mentioned embodiments of the present disclosure, after the memory cell is strengthened, after a period of use or due to aging, the memory cell will degrade to a certain extent. As long as the strengthening process is performed before the degradation degree of the memory cell reaches below the limit threshold of the read amplifier, the data can be continuously stored safely.

[0080] The above implementation method has a good effect on application scenarios with high data security requirements, that is, the storage unit can be regularly strengthened to avoid risks such as data loss due to untimely strengthening.

[0081] Figures 4a to 4c A schematic diagram showing setting the time interval based on whether the storage unit is successfully reinforced is shown.

[0082] like Figure 4a As shown, assuming that the enhanced processing starts at time T1, the duration of the enhanced processing is D1, the time when the enhanced processing is completed is T2, the detection time interval is set to D2, and the start time of the next enhanced processing is T3. In this embodiment, the enhanced processing is completed smoothly without any interruption, so the time when the next enhanced processing is T3 = T2 + D2 = T1 + D1 + D2.

[0083] like Figure 4b As shown, it is assumed that the enhanced processing starts at time T1, and after the enhanced processing is performed for a duration of D11, an interruption occurs, and the duration of the interruption is B1. After the interruption ends, the enhanced processing continues with the previous enhanced processing, and the duration is D12. The time when the enhanced processing is completed is T2, the detection time interval is set to D2, and the start time of the next enhanced processing is T3. In this embodiment, T3 = T2 + D2 = T1 + D11 + B1 + D12 + D2.

[0084] like Figure 4c As shown, it is assumed that the enhanced processing starts at time T1, and after the enhanced processing is performed for a duration of D11, an interruption occurs, and the duration of the interruption is B1. After the interruption ends, the enhanced processing is restarted for a duration of D1. The time when the enhanced processing is completed is T2, the detection time interval is set to D2, and the start time of the next enhanced processing is T3. In this embodiment, T3 = T2 + D2 = T1 + D11 + B1 + D1 + D2.

[0085] from Figures 4a to 4cIt can be seen that since the reinforcement process may be interrupted or the time of the reinforcement process may be extended, the time for the reinforcement process to be performed again may change significantly. In other words, since the time for each storage unit to complete the reinforcement may be different, the reinforcement time for each storage unit will change or drift significantly over time, so the time interval needs to be managed later.

[0086] It is important to understand that Figures 4a to 4c This is for illustration only and the proportions of the various time periods are not necessarily as shown.

[0087] According to an embodiment of the present disclosure, the detection time interval indicates the time interval between the current time and the most recent time when the memory cell in the resistive random access memory starts to be enhanced.

[0088] According to the above-mentioned embodiment of the present disclosure, a fixed time can be set to start the enhanced processing of the storage unit, and the enhanced processing can be performed again after a specific time when the enhanced processing starts. Compared with the previous embodiment, the present embodiment can arrange the start time of the enhanced processing relatively fixedly, and the start time of the enhanced processing can be arranged at a time when the system is not too busy or has a small burden, so as to facilitate the scheduling and management of the enhanced processing time. The solution provided by this embodiment has good applicability for application scenarios that facilitate regular enhancement.

[0089] According to an embodiment of the present disclosure, the method of the present application further includes: in response to the occurrence of an interrupt condition, terminating the strengthening process of the storage unit in the resistive random access memory.

[0090] The enhanced processing in the present application can be forcibly executed regardless of the occurrence of the interruption condition, or it can be suspended when the interruption occurs, and then continue or re-execute after the interruption condition ends.

[0091] There are many interruption conditions, for example, including but not limited to: the storage unit in the resistive memory is occupied; the storage unit has a bad area and is waiting to be repaired; the user forcibly prohibits the enhancement, etc. The interruption conditions of the present application are not limited to any known and future possible interruption conditions.

[0092] For example, if a storage unit is called by a user during the process of being enhanced, the enhanced process may be interrupted to prevent interference with the user's operation and degradation of the user experience.

[0093] According to one embodiment of the present disclosure, the method of the present application further includes: using a state verification condition to determine whether the storage unit meets the enhanced processing condition, the state verification condition is used to determine whether the state of the storage unit is a weak state or a strong state; the storage unit meets the enhanced processing condition including: the state of the storage unit is a weak state. The state verification condition includes: a first storage state verification condition and a second storage state verification condition, the first storage state verification condition is used to verify that the storage unit is a first high state or a second high state, and the second storage state verification condition is used to verify that the storage unit is a first low state or a second low state.

[0094] According to the above embodiments of the present disclosure, in addition to using whether the time interval reaches a preset duration as a criterion for determining whether the storage unit meets the enhanced processing conditions, a status verification condition may also be used to further determine whether the storage unit needs to be enhanced.

[0095] In the embodiment of the present application, taking the resistive memory as an example, combined with Figure 2a It can be understood from the description that the state of the memory cell may include a high resistance state (0) and a low resistance state (1). Specifically, the high resistance state (0) may include a first high resistance state (weak 0) and a second high resistance state (strong 0), and the low resistance state (1) may include a first low resistance state (weak 1) and a second low resistance state (strong 1).

[0096] According to one embodiment of the present application, the state verification condition includes: a first resistance state verification condition and a second resistance state verification condition, the first resistance state verification condition is used to verify that the storage unit is a first high resistance state or a second high resistance state, and the second resistance state verification condition is used to verify that the storage unit is a first low resistance state or a second low resistance state.

[0097] like Figure 2a As shown, when the state of the memory cell is in a weak state, for example, in the first high resistance state (weak 0) and / or in the first low resistance state (weak 1), it indicates that the memory cell needs to be strengthened. Otherwise, if the memory cell is further degraded and exceeds Figure 2a If the boundaries of MEV and MPV are exceeded, data may be completely lost and unrecoverable.

[0098] Further Figure 2a As shown, when the state of the storage unit is in a strong state, for example, in the second high resistance state (strong 0) and / or in the second low resistance state (strong 1), it means that the current state of the storage unit is good and there is no need to strengthen the storage unit.

[0099] There are many ways to verify the state of a storage unit, and any existing solution or any future solution may be used.

[0100] According to one embodiment of the present application, the current of the memory cell in the first high-resistance state is greater than the erase verification current and less than the edge erase verification current, and the current of the memory cell in the second high-resistance state is less than the erase verification current. The current of the memory cell in the first low-resistance state is less than the programming verification current and greater than the edge programming verification current, and the current of the memory cell in the second low-resistance state is greater than the programming verification current.

[0101] The erase verification current is the current threshold that the memory cell should reach after performing a data erase operation on the memory cell. The edge erase verification current is the current threshold that the memory cell reaches when over-erasing data is performed on the memory cell. The programming verification current is the current threshold that the memory cell should reach after performing a data programming operation on the memory cell. The edge programming verification current is the current threshold that the memory cell reaches when over-programming data is performed on the memory cell. In the embodiments of the present application, the values ​​of the erase verification current, the edge erase verification current, the programming verification current, and the edge programming verification current can be set according to actual needs and application scenarios, and are not limited here.

[0102] It can be seen that different states can show different characteristics, so the state can be determined by determining the current magnitude. However, it should be understood that determining the state of the memory cell by the current magnitude is only an optional solution, not a necessary solution.

[0103] When "detection time interval + status verification condition" is used to determine whether the storage unit needs to be strengthened, there may be multiple implementation methods.

[0104] According to one embodiment of the present disclosure, a state verification condition is first used to determine whether the storage unit meets the enhanced processing condition. If the state of the storage unit is a weak state, the storage unit in the resistive random access memory is enhanced after the detection time interval reaches a preset time length.

[0105] According to this embodiment, it is possible to judge whether the storage unit is in a weak state at any time before the detection time interval expires, but it is more preferable to judge in a short time before the detection time interval expires, so that the judgment can be more accurate and prevent accidental data loss due to untimely enhanced processing. If the storage unit is judged to be in a weak state, the storage unit in the resistive memory is enhanced after the detection time interval reaches a preset time length; and if the storage unit is judged to be in a strong state, the enhanced processing of the storage unit in the resistive memory can be ignored after the detection time interval reaches a preset time length. This helps to avoid too frequent enhanced processing of the storage unit and prevents affecting the user experience.

[0106] According to another embodiment of the present disclosure, after the detection time interval reaches a preset duration, a state verification condition is used to determine whether the storage unit meets the enhanced processing condition. If the state of the storage unit is a weak state, the storage unit in the resistive random access memory is enhanced.

[0107] According to this implementation, after the detection time interval reaches a preset time length, it can be determined whether the storage unit is in a weak state. If the storage unit is determined to be in a weak state, the storage unit in the resistive random access memory is strengthened; and if the storage unit is determined to be in a strong state, the strengthening of the storage unit in the resistive random access memory can be ignored. This helps to avoid strengthening the storage unit too frequently and prevents the user experience from being affected.

[0108] However, performing a strengthening process once cannot completely guarantee that the storage unit can be strengthened. In order to ensure that the processing unit can be strengthened successfully, the storage unit can be strengthened repeatedly until the storage unit is definitely strengthened.

[0109] Figure 5 An exemplary flowchart of a method for maintaining data in a resistive memory according to a preferred embodiment of the present disclosure is shown.

[0110] According to one embodiment of the present disclosure, the method of the present application further includes: after the storage unit is enhanced, executing the following steps: in step S350, determining again whether the storage unit after the enhanced processing meets the enhanced processing conditions; in step S360, in response to meeting the enhanced processing conditions, continuing to enhance the storage unit until the storage unit no longer meets the enhanced processing conditions.

[0111] According to this embodiment, if the strengthening process is unsuccessful, then strengthening will be performed again; and if the strengthening process is successful, then strengthening does not need to be performed again. According to this embodiment, it can be ensured that the storage unit can be successfully strengthened in each cycle, thereby preventing more serious accidents such as data loss.

[0112] According to one embodiment of the present application, the resistive random access memory stores the address of the enhanced region; before the storage unit is enhanced (or before determining whether the storage unit meets the enhanced processing conditions), the address of the enhanced region is loaded into the resistive random access memory, and the address of the enhanced region stored in the resistive random access memory is added by 1 to obtain the address of the storage unit. According to another embodiment of the present application, when the state of the storage unit is a strong state, the address of the storage unit is recorded.

[0113] In an embodiment of the present application, the aforementioned resistive random access memory stores a reinforced area address, and the reinforced area address is stored as user data in a specific area of ​​the resistive random access memory. Specifically, the specific area may be an area for recording user information. The reinforced area address is the address of the most recently recorded storage unit in a strong state, and when the address of the storage unit in a strong state has not yet been recorded, the reinforced area address is 0. Specifically, the storage unit in a strong state includes a storage unit that does not need to be reinforced after judgment and a storage unit in a weak state whose state is a strong state after reinforcement processing.

[0114] By storing the enhanced region address as user data in a specific region of the resistive random access memory, it is allowed to load the enhanced region address in the resistive random access memory before the storage unit is enhanced during the data writing process, and add 1 to the enhanced region address, so as to directly locate the storage unit that currently needs to be enhanced. For example, when the enhanced region address stored in the resistive random access memory is 15, before the storage unit is enhanced, the enhanced region address 15 is loaded, and then 1 is added to the enhanced region address 15, and the obtained region address 16 is the region that currently needs to be enhanced.

[0115] By directly locating the address of the storage unit that currently needs to be enhanced, if the storage unit to be enhanced is already in a strong state, there is no need to enhance it; if the storage unit to be enhanced is still in a weak state, it can be enhanced, thus avoiding the need to re-acquire the enhanced area address, thereby significantly improving the efficiency of the enhancement process.

[0116] The process of strengthening the storage unit will be described in detail below.

[0117] In principle, when the data write operation is data erasure, the charge of the storage cell will usually be reduced. After performing a data erase operation on a storage cell, if the current of the storage cell is less than the erase verification current, it means that the charge state of the storage cell is close to the logic 0 level. At this time, the storage cell changes from the second low resistance state to the second high resistance state, so that the state of the storage cell is the second high resistance state.

[0118] When the write data operation is data programming, the charge of the storage cell is usually increased. After performing a data programming operation on a storage cell, if the current of the storage cell is greater than the programming verification current, it means that the charge state of the storage cell is high enough to be reliably identified as logic 1. At this time, the storage cell changes from the second high resistance state to the second low resistance state, so that the state of the storage cell is the second low resistance state.

[0119] In the embodiment of the present application, during the process of strengthening the processing of the storage unit, when the state of the storage unit is the first high impedance state, the storage unit is subjected to the strengthened erasing operation processing. Specifically, the strengthened erasing operation processing refers to performing a data erasing operation again on the storage unit in the first high impedance state after the data erasing operation, so that the state of the storage unit in the first high impedance state changes to the second high impedance state.

[0120] Specifically, during the enhanced erase operation process, the voltage of the bit line (BL), the voltage of the word line (WL), the voltage of the source line (SL), and the pulse time can be set and adjusted according to actual needs.

[0121] In the embodiment of the present application, during the process of strengthening the memory cell, when the state of the memory cell is the first low resistance state, the memory cell is subjected to the strengthening programming operation. Specifically, the strengthening programming operation means that after the data programming operation, the memory cell in the state of the first low resistance state is subjected to the data programming operation again, so that the state of the memory cell in the state of the first low resistance state is changed to the second low resistance state.

[0122] Specifically, during the enhanced programming operation, the voltage of the bit line (BL), the voltage of the word line (WL), the voltage of the source line (SL), and the pulse time can be set and adjusted according to actual needs.

[0123] By changing the state of a memory cell in a first high resistance state to a second high resistance state, or changing the state of a memory cell in a first low resistance state to a second low resistance state, the problem of data degradation in the resistive memory during storage can be improved.

[0124] In summary, with the help of the scheme for data retention of resistive memory provided above, the disclosed embodiment can effectively prevent the serious degradation of the storage unit of the resistive memory by regularly strengthening the storage unit of the resistive memory, thereby avoiding serious problems such as data errors or data loss. Further, in some embodiments, before using the state verification condition to determine whether the storage unit meets the strengthening processing condition, the strengthening area address is loaded in the resistive memory, and the strengthening area address is added by 1, so that the address of the storage unit that currently needs to be judged strong or weak can be located, so that the storage unit that meets the strengthening processing condition can be strengthened in sequence. Further, in some embodiments, when the state of the storage unit is determined to be a strong state, the address of the storage unit is recorded, and the starting address can be provided for the next strengthening processing operation, so that the storage unit that meets the strengthening processing condition can be strengthened in sequence, ensuring that the strength judgment and strengthening processing operations can traverse the addresses of all storage units in the resistive memory, avoiding the need to re-acquire the strengthening area address, thereby significantly improving the efficiency of the strengthening processing.

[0125] Some embodiments of the present application are introduced above by taking resistive random access memory as an example. According to other embodiments of the present application, the non-volatile two-terminal memory may be a polarization state memory, and the state verification condition includes: a first polarization state verification condition and a second polarization state verification condition, wherein the first polarization state verification condition is used to verify that the storage unit is a first negative polarization state or a second negative polarization state, and the second polarization state verification condition is used to verify that the storage unit is a first positive polarization state or a second positive polarization state.

[0126] According to one embodiment of the present application, the first polarization state verification condition includes a second erasure verification condition (eg Figure 2b P0 shown in ) and the second edge erase verification condition (e.g. Figure 2b As shown in MP0), the polarization amount of the memory cell in the first negative polarization state is between the second erase verification polarization amount and the second edge erase verification polarization amount.

[0127] According to one embodiment of the present application, the second polarization state verification condition includes a second programming verification condition (for example, Figure 2b P1 shown in FIG. 1 and a second edge programming verification condition (eg Figure 2b As shown in MP1), the polarization amount of the memory cell in the first positive polarization state is between the second programming verification polarization amount and the second edge programming verification polarization amount.

[0128] According to one embodiment of the present application, performing enhanced processing on the storage cell includes: performing enhanced erasing operation processing on the storage cell when the state of the storage cell is a first negative polarization state; and performing enhanced programming operation processing on the storage cell when the state of the storage cell is a first positive polarization state.

[0129] According to one embodiment of the present application, the polarization state memory includes a ferroelectric random access memory (FeRAM).

[0130] It should be understood that in the present application, the negative polarization state is used to represent that the memory cell stores "0", and the positive polarization state is used to represent that the memory cell stores "1", but this is merely an example, and those skilled in the art may also use the negative polarization state to represent that the memory cell stores "1", and the positive polarization state to represent that the memory cell stores "0".

[0131] The resistive random access memory has been introduced in detail above, and the detailed description of the polarization state memory will be omitted here.

[0132] Figure 6 An exemplary structural block diagram of an apparatus 600 for maintaining data in a non-volatile two-terminal memory according to an embodiment of the present application is shown.

[0133] like Figure 6 As shown, the device 600 includes a processor 610 and a memory 620. The aforementioned memory 620 may include but is not limited to a resistive random access memory RRAM (Resistive Random Access Memory), a polarized state memory, a dynamic random access resistive memory DRAM (Dynamic Random Access Memory), a static random access resistive memory SRAM (Static Random Access Memory), and an enhanced dynamic random access resistive memory EDRAM (Enhanced Dynamic Random Access Memory). The aforementioned processor 610 may include, for example, a general-purpose processor ("CPU"), a dedicated graphics processor ("GPU") or a microcontroller ("MCU"), and the aforementioned memory 620 stores at least a computer program, which is executed by the aforementioned processor 610 to implement the method 200 for non-volatile two-terminal memory data retention as described above. As the method has been described in detail in the previous text, it will not be repeated here.

[0134] In another aspect of the present invention, a computer storage medium is provided, on which a computer program for non-volatile two-terminal memory data retention is stored, and the instruction is executed by one or more processors to implement the method 200 for non-volatile two-terminal memory data retention as described above. Specifically, the aforementioned readable storage medium can be any tangible medium containing or storing a program, and the computer program can be used by an instruction execution system, an apparatus or a device or used in combination with it. For example, the computer-readable storage medium can be any appropriate magnetic storage medium or magneto-optical storage medium, such as a resistive random access memory RRAM (Resistive Random Access Memory), a dynamic random access resistive memory DRAM (Dynamic Random Access Memory), a static random access resistive memory SRAM (Static Random-Access Memory), an enhanced dynamic random access resistive memory EDRAM (Enhanced Dynamic Random Access Memory), a high-bandwidth memory HBM (High-Bandwidth Memory), a hybrid memory cube HMC (Hybrid Memory Cube), etc., or any other medium that can be used to store the required information and can be accessed by an application, a module or both. Any such computer storage medium may be part of the device or accessible or connectable to the device.Any application or module described in the present invention may be implemented using computer readable / executable instructions that may be stored or otherwise maintained by such computer readable media.

[0135] Figure 7 An exemplary block diagram of a system 700 according to an embodiment of the present application is shown, the system comprising: a detection module 710 for acquiring a detection time interval; a first judgment module 720 for judging whether the detection time interval reaches a preset time length; a second judgment module 730 for judging whether a storage unit meets an enhanced processing condition by using whether the time interval reaches a preset time length; and an enhanced processing module 740 for performing enhanced processing on the storage unit in response to meeting the enhanced processing condition. .

[0136] Specifically, the system 700 may adopt an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microcontroller unit (MCU) or a digital signal processor (DSP), etc.

[0137] Figure 8 An exemplary structural block diagram of a resistive memory electronic operating environment 800 according to an embodiment of the present application is shown.

[0138] like Figure 8As shown, electronic operating environment 800 may be formed within a single semiconductor die, although the present disclosure is not limited thereto and in other embodiments, some components of electronic operating environment 800 may be formed on separate semiconductor dies.

[0139] The electronic operating environment 800 may include the aforementioned memory 620, column controller 810, sense amplifier 820, reference and control signal generator 830, row controller 840, input / output buffer 850, clock source 860, address register 870, write data state machine 880 and command interface 890.

[0140] Specifically, the column controller 810 and the sense amplifier 820 may be adjacent to the memory 620. The column controller 810 may be configured to activate (or identify to activate) a subset of the bit lines of the memory 620. The column controller 810 may utilize control signals provided by the reference and control signal generator 830 to activate and operate corresponding bit lines in the bit line subset, applying appropriate program, erase, or read voltages to these bit lines. Inactive bit lines in the memory 620 may be maintained at an inhibit voltage (also applied by the reference and control signal generator 830) to mitigate or avoid bit disturbance effects on these inactive bit lines.

[0141] Specifically, the row controller 840 can be adjacent to and electrically connected to the word lines of the memory 620. Also using the control signals of the reference and control signal generator 830, the row controller 840 can select a particular row of memory cells with an appropriate selection voltage. In addition, the row controller 840 can facilitate programming, erasing, or reading operations by applying an appropriate voltage at the selected word line.

[0142] Specifically, the sense amplifier 820 may read data from or write data to an activated memory cell of the memory 620 selected by the column controller 810 and the row controller 840. The data read from the memory 620 may be provided to the input / output buffer 850. Likewise, the data to be written to the memory 620 may be received from the input / output buffer 850 and written to the activated memory cell of the memory 620.

[0143] Specifically, the clock source 860 can provide corresponding clock pulses to facilitate the timing of read, write and programming operations of the row controller 840 and the column controller 810. The clock source 860 can be responsive to external or internal commands received by the electronic operating environment 800 to further facilitate the selection of word lines or bit lines. The input / output buffer 850 can include command and address inputs, and bidirectional data inputs and outputs. Instructions are provided through command and address inputs, and data to be written to the memory 620 and data read from the memory 620 are transmitted on the bidirectional data inputs and outputs, thereby facilitating connection to an external host device such as the device 600, such as the device 600.

[0144] Specifically, the input / output buffer 850 may be configured to receive write data, receive erase instructions, receive status or maintenance instructions, output read data, output status information, receive address data and command data, and address data of corresponding instructions. The address data may be transmitted to the row controller 840 and the column controller 810 through the address register 870. In addition, the input data is transmitted to the memory 620 through the signal input line between the sense amplifier 820 and the input / output buffer 850, and the output data is received from the memory 620 through the signal output line from the sense amplifier 820 to the input / output buffer 850. The input data may be received from a host device such as the device 600, and the output data may be transmitted to a host device such as the device 600 through the I / O bus.

[0145] Specifically, a command received from a host device such as the apparatus 600 may be provided to the command interface 890. The command interface 890 may be configured to receive an external control signal from a host device such as the apparatus 600 and determine whether the data input to the input / output buffer 850 is write data, a command, or an address. The input command may be transmitted to the write data state machine 880.

[0146] Specifically, the write data state machine 880 can manage the write data process of the resistive random access memory and other functions related to the resistive random access memory. Specifically, the write data process includes data programming, data erasure, data recovery and recording of enhanced area addresses, and during data programming and data erasure, verification conditions can be used to verify the state of each storage unit and the write data time, and the storage unit with a weak state can also be strengthened. Other functions related to the resistive random access memory include data reading, data writing, data input, data output, etc. In some aspects, the write data state machine 880 can send and receive confirmation and denial of successful reception or execution of various commands. In a further embodiment, the write data state machine 880 can decode and implement state-related commands, decode and implement configuration commands, etc.

[0147] Specifically, in order to implement functions such as read, write, erase, program, input, and output, the write data state machine 880 can control the clock source 860 or the reference and control signal generator 830. The control of the clock source 860 can generate output pulses configured to facilitate the row controller 840 and the column controller 810 to implement specific functions. For example, the output pulse can be transmitted to the selected bit line through the column controller 810. For another example, the output pulse can be transmitted to the selected word line through the row controller 840.

[0148] Although multiple embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may think of many changes, modifications, and alternatives without departing from the thought and spirit of the present disclosure. It should be understood that in the process of practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The attached claims are intended to define the scope of protection of the present disclosure, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for data retention in a non-volatile two-terminal memory, characterized in that: The method comprises: Get the detection time interval; Determine whether the detection time interval reaches a preset time length; Determining whether the storage unit meets the enhanced processing condition by determining whether the time interval reaches a preset time length; and In response to satisfying the strengthening processing condition, strengthening processing is performed on the storage unit.

2. The method according to claim 1, characterized in that The detection time interval indicates the time interval between the current time and the most recent time when the storage unit in the non-volatile two-terminal memory is successfully strengthened.

3. The method according to claim 1, characterized in that The detection time interval indicates the time interval between the current time and the most recent time when the storage unit in the non-volatile two-terminal memory starts to be enhanced.

4. The method according to any one of claims 1 to 3, characterized in that: Further including: In response to the occurrence of the interrupt condition, the strengthening process of the storage unit in the non-volatile two-terminal memory is suspended.

5. The method according to claim 4, characterized in that The interruption condition includes that a storage unit in the non-volatile two-terminal memory is occupied.

6. The method according to any one of claims 1 to 5, characterized in that: Further comprising: using a state verification condition to determine whether the storage unit meets the enhanced processing condition, the state verification condition being used to determine whether the state of the storage unit is a weak state or a strong state; The storage unit satisfies the enhanced processing condition, including: the state of the storage unit is a weak state.

7. The method according to claim 6, characterized in that First, a state verification condition is used to determine whether the storage unit meets the enhanced processing condition. If the state of the storage unit is a weak state, the storage unit in the non-volatile two-terminal memory is enhanced after the detection time interval reaches a preset time length.

8. The method according to claim 6, characterized in that After the detection time interval reaches a preset time length, a state verification condition is used to determine whether the storage unit meets the enhanced processing condition. If the state of the storage unit is a weak state, the storage unit in the non-volatile two-terminal memory is enhanced.

9. The method according to any one of claims 6 to 8, characterized in that: Further comprising: after the storage unit is enhanced, performing the following steps: Determine again whether the storage unit after the enhanced processing meets the enhanced processing condition; In response to satisfying the enhanced processing condition, the storage unit continues to be subjected to enhanced processing until the storage unit no longer satisfies the enhanced processing condition.

10. The method according to any one of claims 1 to 9, characterized in that: The non-volatile two-terminal memory stores the address of the enhanced area; Before the storage unit is enhanced, the address of the enhanced region is loaded into the non-volatile two-end memory, and 1 is added to the address of the enhanced region stored in the non-volatile two-end memory to obtain the address of the storage unit.

11. The method according to claim 10, characterized in that When the state of the memory cell is a strong state, the address of the memory cell is recorded.

12. The method according to claim 6, characterized in that The state verification condition includes: a first storage state verification condition and a second storage state verification condition, the first storage state verification condition is used to verify that the storage unit is a first high state or a second high state, and the second storage state verification condition is used to verify that the storage unit is a first low state or a second low state.

13. The method according to claim 12, characterized in that The state verification condition includes: the non-volatile two-terminal memory is a resistive memory, and the state verification condition includes: a first resistance state verification condition and a second resistance state verification condition, the first resistance state verification condition is used to verify that the storage unit is a first high resistance state or a second high resistance state, and the second resistance state verification condition is used to verify that the storage unit is a first low resistance state or a second low resistance state.

14. The method according to claim 13, characterized in that The first resistance state verification condition includes an erase verification condition and an edge erase verification condition, and the current of the memory cell in the first high resistance state is greater than the erase verification current and less than the edge erase verification current.

15. The method according to claim 13, characterized in that The second resistance state verification condition includes a program verification condition and a marginal program verification condition, and the current of the memory cell in the first low resistance state is smaller than the program verification current and larger than the marginal program verification current.

16. The method according to claim 13, characterized in that The step of performing enhanced processing on the storage unit includes: When the state of the memory cell is a first high impedance state, performing an enhanced erasing operation on the memory cell; and / or When the state of the memory cell is a first low-resistance state, an enhanced programming operation is performed on the memory cell.

17. The method according to any one of claims 13 to 16, characterized in that: The resistive memory includes one or more of an electric resistance switch memory, a phase change memory, a magnetoresistive memory and a conductive bridge memory.

18. The method according to claim 12, characterized in that The non-volatile two-terminal memory is a polarization state memory, and the state verification condition includes: a first polarization state verification condition and a second polarization state verification condition, the first polarization state verification condition is used to verify that the storage unit is a first negative polarization state or a second negative polarization state, and the second polarization state verification condition is used to verify that the storage unit is a first positive polarization state or a second positive polarization state.

19. The method according to claim 18, characterized in that The first polarization state verification condition includes a second erasure verification condition and a second edge erasure verification condition, and the polarization amount of the memory cell in the first negative polarization state is between the second erasure verification polarization amount and the second edge erasure verification polarization amount.

20. The method according to claim 18, characterized in that The second polarization state verification condition includes a second programming verification condition and a second edge programming verification condition, and the polarization amount of the memory cell in the first positive polarization state is between the second programming verification polarization amount and the second edge programming verification polarization amount.

21. The method according to claim 18, characterized in that The step of performing enhanced processing on the storage unit includes: When the state of the memory cell is a first negative polarization state, performing an enhanced erasing operation on the memory cell; When the state of the memory cell is the first positive polarization state, an enhanced programming operation is performed on the memory cell.

22. The method according to any one of claims 18 to 21, characterized in that: The polarization state memory includes a ferroelectric random access memory (FeRAM).

23. A device for maintaining data in a non-volatile two-terminal memory, characterized in that: include: processor; Memory for storing computer programs; The processor is configured to execute the computer program to implement the method according to any one of claims 1 to 22.

24. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by one or more processors, the method according to any one of claims 1 to 22 is implemented.

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