Signal transmission optimization method, device, equipment, medium and product

Abstract

The invention discloses a signal transmission optimization method and device, equipment, a medium and a product, and relates to the technical field of integrated circuit verification, and the method comprises the steps: obtaining a target time sequence diagram of a to-be-optimized FPGA system; carrying out primary iteration along a direction in which the physical resource reuse rate is close to the total number of system physical lines, obtaining an initial time division multiplexing rate of each path edge as an iteration initial value, and carrying out secondary iteration by taking the path edge on a time sequence path with longer system delay to allocate more physical resources as a target; and performing time division multiplexing configuration on the system according to the target time division multiplexing ratio of each path edge obtained by iteration. According to the method, resources of physical lines occupied by all time sequence paths tend to be equal through primary iteration, dynamic resource allocation according to the sum of time division multiplexing ratios is achieved through secondary iteration, resource allocation of key time sequence paths in a system is optimized, transmission delay is reduced, and transmission efficiency, the resource utilization rate of an FPGA and system performance are improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit verification technology, and in particular to a signal transmission optimization method, device, equipment, medium and product. Background Art

[0002] In recent years, with the growing demand for high efficiency and flexibility in fields such as deep learning, data centers, logic simulation, and rapid prototyping of large designs, the application demand for systems equipped with multiple field programmable gate arrays (FPGAs) has become increasingly high. In these multi-FPGA systems, the individual FPGAs are interconnected through direct hard-wired or programmable interconnect networks.

[0003] Although time-division multiplexing technology increases the number of logic pins for signal transmission between FPGAs and improves the utilization of logic resources by multiplexing input / output pins and lines between FPGAs, time-division multiplexing technology requires that each signal must wait for its allocated transmission time, resulting in increased communication delay between FPGAs. In the prior art, some reduce the negative impact of time-division multiplexing on delay by considering the delay caused by time-division multiplexing technology in the division, routing and post-routing stages, and some simultaneously perform time-division multiplexing ratio allocation and division to increase the system clock frequency, and place non-critical FPGA networks in time-division multiplexing lines to improve logic utilization without affecting system timing. However, these methods need to consider all actual time-division multiplexing constraints, still require a long FPGA system running time, and reduce the efficiency of signal transmission and FPGA resource utilization. Summary of the invention

[0004] The present invention provides a signal transmission optimization method, device, equipment, medium and product to solve the problems of long transmission delay, low transmission efficiency, low FPGA resource utilization and poor FPGA system performance when using time division multiplexing technology to transmit signals between FPGAs.

[0005] According to one aspect of an embodiment of the present invention, a signal transmission optimization method is provided, including:

[0006] Obtain a target timing diagram of the FPGA system to be optimized; wherein the target timing diagram contains multiple timing paths, and each timing path contains multiple path edges for connecting two FPGAs;

[0007] Perform one iteration in the iteration direction of moving the physical resource reuse rate closer to the total number of physical lines of the FPGA system to obtain the initial time division reuse ratio of each path edge in the target timing diagram;

[0008] The initial time division multiplexing ratio of each path edge at the end of one iteration is used as the initial value of the iteration, and a second iteration is performed with the goal of allocating more physical resources to the path edges on the timing paths with longer system delays, to determine the target time division multiplexing ratio of each path edge in the target timing diagram;

[0009] According to each target time division multiplexing ratio, the FPGA system is configured for time division multiplexing.

[0010] According to another aspect of an embodiment of the present invention, a signal transmission optimization device is provided, including:

[0011] A timing diagram acquisition module is used to acquire a target timing diagram of the FPGA system to be optimized; wherein the target timing diagram contains multiple timing paths, and each timing path contains multiple path edges for connecting two FPGAs;

[0012] A ratio acquisition module, used for performing one iteration along an iteration direction of moving the physical resource reuse rate closer to the total number of physical lines of the FPGA system, and obtaining an initial time division reuse ratio of each path edge in the target timing diagram;

[0013] A ratio determination module is used to use the initial time division multiplexing ratio of each path edge at the end of one iteration as the initial starting value of the iteration, and to perform a second iteration with the goal of allocating more physical resources to the path edge on the timing path with longer system delay, and determine the target time division multiplexing ratio of each path edge in the target timing diagram;

[0014] The system configuration module is used to configure the FPGA system for time division multiplexing according to each target time division multiplexing ratio.

[0015] According to another aspect of an embodiment of the present invention, an electronic device is provided, the electronic device comprising:

[0016] at least one processor; and

[0017] a memory communicatively connected to the at least one processor; wherein,

[0018] The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the signal transmission optimization method described in any embodiment of the present invention.

[0019] According to another aspect of an embodiment of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the signal transmission optimization method described in any embodiment of the present invention when executed.

[0020] According to another aspect of an embodiment of the present invention, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps of the method described in any embodiment of the present invention are implemented.

[0021] The technical solution of the embodiment of the present invention is to obtain the target timing diagram of the FPGA system to be optimized; perform one iteration along the iteration direction of approaching the physical resource reuse rate to the total number of physical lines of the FPGA system, and obtain the initial time division multiplexing ratio of each path edge in the target timing diagram; use the initial time division multiplexing ratio of each path edge at the end of one iteration as the initial starting value of the iteration, and perform a second iteration with the goal of allocating more physical resources to the path edge on the timing path with longer system delay, and determine the target time division multiplexing ratio of each path edge in the target timing diagram; and configure the FPGA system for time division multiplexing according to each target time division multiplexing ratio. The initial time division multiplexing ratio is allocated through one iteration, so that the resources of the physical lines occupied by each timing path are close to equal, and then the resources are dynamically allocated according to the total time division multiplexing ratio through the second iteration, so that more resources are allocated to the timing path with a larger total time division multiplexing ratio, and less resources are allocated to the timing path with a smaller total time division multiplexing ratio, so as to optimize the resource allocation of the key timing paths in the system, reduce the transmission delay, and improve the transmission efficiency, the resource utilization rate of the FPGA and the system performance.

[0022] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 is a flow chart of a signal transmission optimization method provided according to Embodiment 1 of the present invention;

[0025] Figure 2 is a flowchart of another signal transmission optimization method provided according to Embodiment 2 of the present invention;

[0026] Figure 3 It is a compilation flow chart of a multi-FPGA system using time division multiplexing technology applicable to an embodiment of the present invention;

[0027] Figure 4This is a schematic diagram of a time division multiplexing ratio optimization target applicable to an embodiment of the present invention;

[0028] Figure 5 is a structural schematic diagram of a signal transmission optimization device provided according to Embodiment 3 of the present invention;

[0029] Figure 6 It is a structural schematic diagram of an electronic device for implementing the signal transmission optimization method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0032] Embodiment 1

[0033] Figure 1 This is a flow chart of a signal transmission optimization method provided in the first embodiment of the present invention. This embodiment can be applied to the case of optimizing the time division multiplexing ratio of each path edge in each timing path in the FPGA system. The method can be executed by a signal transmission optimization device. The signal transmission optimization device can be implemented in the form of hardware and / or software and can generally be configured in an electronic device. Figure 1 As shown, the method includes:

[0034] S110, obtaining a target timing diagram of the FPGA system to be optimized.

[0035] The target timing diagram includes multiple timing paths, and each timing path includes multiple path edges for connecting two FPGAs.

[0036] In an embodiment of the present invention, the target timing diagram can be specifically understood as: a timing diagram corresponding to the FPGA system to be optimized. Each timing path in the timing diagram can be composed of a source clock path, a data path, and a destination clock path. Signal data starts from the source register, is transmitted through the data path, and finally reaches the destination register. Among them, the timing paths can be divided into four categories, including: the path from the external device to the internal register of the FPGA, the path from the internal register of the FPGA to the output pin, the path between the internal registers of the FPGA, and the path between adjacent FPGAs.

[0037] The embodiment of the present invention optimizes the time division multiplexing ratio of the timing path between adjacent FPGAs. The path edge can be specifically understood as: the path edge connecting the adjacent FPGAs in each timing path. For a multi-FPGA system with time-multiplexed hard-wired FPGA connections, if two FPGAs are directly connected in the system, they are logically adjacent. In such a system, each inter-FPGA timing path is assigned a time division multiplexing ratio, which indicates how many other signals share a physical line with the signal. When evaluating the delay of the FPGA system transmitting signals, the worst case is that an inter-FPGA signal needs to wait for the entire time division multiplexing cycle to obtain a transmission opportunity. Therefore, the transmission delay is proportional to the time division multiplexing ratio of the line.

[0038] S120, performing an iteration in an iteration direction of bringing the physical resource reuse rate closer to the total number of physical lines of the FPGA system, and obtaining an initial time division reuse ratio of each path edge in the target timing diagram.

[0039] In an embodiment of the present invention, the time division multiplexing ratio refers to the ratio of the initial time slices allocated to each signal or data stream in the time division multiplexing system. This ratio determines the length of time that each signal can use the timing path in a unit time. For example, if the time division multiplexing ratio of a timing path is 4, it means that there are 4 signals sharing this path, and each signal obtains a quarter of the path usage time in each time period. The physical resource reuse rate can be specifically understood as: the degree to which a physical line (such as a connection channel between FPGA chips) is shared by multiple signals or data streams, that is, how many different signals or data streams are used by the physical line in a unit time. The higher the physical resource reuse rate, the more signals share the same physical line, and the higher the utilization rate of the physical line. In an FPGA system, a physical line can include one or more timing paths, and the physical resource reuse rate between adjacent FPGAs can be calculated by the inverse and time division multiplexing ratio of the path edges of each timing path on the physical line. The physical resource reuse rate of the FPGA system can be obtained by summing the physical resource reuse rates between adjacent FPGAs.

[0040] Specifically, all available physical lines (for example, connection channels between FPGA chips) and all timing paths (including path edges connecting two FPGAs) in the FPGA system are identified, and the bandwidth requirements and transmission direction of each timing path are determined. Only networks with the same transmission direction and similar bandwidth requirements or the same time division multiplexing ratio can be allocated to the same physical line. Then, the time division multiplexing ratio of each path edge is adjusted iteratively so that the physical resource multiplexing rate of the entire system is close to the total number of physical lines. When the difference between the physical resource multiplexing rate and the total number of physical lines meets the preset threshold, the iteration is exited, and the time division multiplexing ratio of each path edge after the iteration is used as the initial time division multiplexing ratio. Through one iteration, the overall resource utilization of the system is improved.

[0041] S130, taking the initial time division multiplexing ratio of each path edge at the end of one iteration as the initial starting value of the iteration, performing a second iteration with the goal of allocating more physical resources to the path edges on the timing paths with longer system delays, and determining the target time division multiplexing ratio of each path edge in the target timing diagram.

[0042] Specifically, according to the initial value of the iteration, a timing analysis is performed on each timing path to determine the delay of each path and identify which paths have the longest delay. The larger the sum of the time division multiplexing ratios, the more signals share the same timing path, resulting in a decrease in the time slices allocated to each signal, so that it takes longer to wait for the transmission opportunity, increasing the time for signal processing and forwarding. At the same time, due to the limited bandwidth of the physical line, the larger the sum of the time division multiplexing ratios, the smaller the available bandwidth of each signal, which reduces the data transmission efficiency. Therefore, by calculating the sum of the time division multiplexing ratios of each path edge of the timing path, the timing path corresponding to the largest value in the sum of the time division multiplexing ratios of each timing path is selected as the timing path with the longest delay. For other timing paths, their time division multiplexing ratios are reduced accordingly to keep the total utilization of the physical line unchanged.

[0043] In a specific example, there are four timing paths on a physical line, and their time division multiplexing ratios are 1, 2, 3 and 4 respectively, and the total time division multiplexing ratio of the timing paths is 10. Select a reduction factor β, such as β = 0.5. According to the time division multiplexing ratio of the timing path * β, adjust the time division multiplexing ratios of other non-longest delay paths to 0.5, 1 and 1.5, and normalize the above results to obtain the iterative results of 0.714, 1.429, 2.143 and 5.714. Determine whether the time division multiplexing ratio of the longest delay path after iteration meets the preset threshold value. If not, use the result of this iteration as the initial value of the iteration and start the next iteration. If the preset threshold is met, the iterative result is rounded up. If the total time division multiplexing ratio after rounding is greater than the total number of physical lines, the minimum time division multiplexing ratio after rounding is continued to be reduced until each time division multiplexing ratio is an integer and the total time division multiplexing ratio is less than or equal to the total number of physical lines. The obtained time division multiplexing ratio result is determined as the target time division multiplexing ratio of each path edge in the target timing diagram.

[0044] S140 , configuring the FPGA system for time division multiplexing according to each target time division multiplexing ratio.

[0045] Specifically, according to each target time division multiplexing ratio, determine the time division multiplexing interface type and parameters, which may include the number of channels, sampling rate and bit depth, to generate the corresponding bit clock data. Then, configure the frame synchronization signal and bit clock polarity, use the hardware description language to design the time division multiplexer, and implement it on the FPGA, use the phase-locked loop inside the FPGA to generate an accurate clock signal, and manage the time slice allocation through the state machine to realize the configuration of time division multiplexing of the FPGA system.

[0046] The technical solution of the embodiment of the present invention is to obtain the target timing diagram of the FPGA system to be optimized; perform one iteration along the iteration direction of approaching the physical resource reuse rate to the total number of physical lines of the FPGA system, and obtain the initial time division multiplexing ratio of each path edge in the target timing diagram; use the initial time division multiplexing ratio of each path edge at the end of one iteration as the initial starting value of the iteration, and perform a second iteration with the goal of allocating more physical resources to the path edge on the timing path with longer system delay, and determine the target time division multiplexing ratio of each path edge in the target timing diagram; and configure the FPGA system for time division multiplexing according to each target time division multiplexing ratio. The initial time division multiplexing ratio is allocated through one iteration, so that the resources of the physical lines occupied by each timing path are close to equal, and then the resources are dynamically allocated according to the criticality of the timing path through the second iteration, so that more resources are allocated to the timing path with a larger total time division multiplexing ratio, and less resources are allocated to the timing path with a smaller total time division multiplexing ratio, so as to optimize the resource allocation of the key timing path in the system, reduce the transmission delay, and improve the transmission efficiency, the resource utilization rate of the FPGA and the system performance.

[0047] Optionally, based on the above embodiments, a second iteration is performed with the goal of allocating more physical resources to the path edge on the timing path with longer system delay, and a target time division multiplexing ratio of each path edge in the target timing diagram is determined, including:

[0048] In the current iteration round, the longest target timing path in the target timing graph is obtained, and the sum of the first time division multiplexing ratios of all path edges in the target timing path is calculated;

[0049] Calculating a target optimization value according to the first time division multiplexing ratio sum value and a current target factor, wherein the target factor has a preset initial value;

[0050] Traverse each path edge in the target timing graph, calculate the maximum sum of the time division multiplexing ratios of each path edge, and update the current time division multiplexing ratio of each path edge according to the maximum sum of the time division multiplexing ratios;

[0051] Recalculate the sum of the second time division multiplexing ratios of all path edges in the target timing path according to the current time division multiplexing ratio of each path edge;

[0052] If the second time division multiplexing ratio sum value and the first time division multiplexing ratio sum value do not meet the consistency condition, then update the target factor according to a preset update method;

[0053] Start a new iteration round as the current iteration round, and return to execute the operation of obtaining the current longest target timing path in the target timing diagram until the sum value of the second time division multiplexing ratio and the sum value of the first time division multiplexing ratio of the latest iteration meet the consistency condition;

[0054] The current time division multiplexing ratio of each path edge calculated at the end of the second iteration is determined as the target time division multiplexing ratio.

[0055] In the embodiment of the present invention, the longest target timing path can be specifically understood as: the timing path with the largest sum of the time division multiplexing ratios of all path edges in each timing path. The first sum of the time division multiplexing ratios is the sum of the time division multiplexing ratios of all path edges in the current longest target timing path.

[0056] Specifically, the first time division multiplexing ratio sum value r is calculated max After that, a target factor β is set to satisfy the constraint 0<β<1, and the β value will increase with the increase of the number of iterations. Preferably, the initial value can be set to 0.5, and the β value can increase by 10% with the increase of the number of iterations. Accordingly, the target optimization value t=r max *β. Traverse each path edge in the target timing graph. Each path edge has one or more timing paths on the physical line. Get all the timing paths to which the current edge belongs, and calculate the sum of the time division multiplexing ratios of the edges on these timing paths respectively. Get the maximum value as the maximum sum of the time division multiplexing ratios of each path edge r imax , update the current time division multiplexing ratio r of each path edge i ′=r i *c i , where r i ′ is the current time division multiplexing ratio of each path edge after update, r i is the current time division multiplexing ratio of each path edge before updating, corresponding to the time division multiplexing ratio of the path edge after one iteration, c i is the scaling ratio of the time division multiplexing ratio of the current edge, which can be obtained by Calculated.

[0057] Calculate the sum of the time division multiplexing ratios of all edges on the updated current longest timing path as the second time division multiplexing ratio sum value r′ max , if r′ max and r max The consistency conditions are not met, for example, If the condition is met or the preset upper limit of the number of secondary iterations is not reached, where Δ is a relatively small consistency condition threshold value preset based on experience, preferably, Δ can be 0.1, then a new iteration round is started as the current iteration round, and a new round of secondary iteration is performed based on the result of this iteration until the consistency condition is met or the preset upper limit of the number of secondary iterations is reached, and the current time division multiplexing ratio of each path edge calculated at the end of the second iteration is determined as the target time division multiplexing ratio. Through the second iteration, resources are dynamically allocated according to the criticality of the timing path, more resources are allocated to the timing path with a larger total time division multiplexing ratio, and fewer resources are allocated to the timing path with a smaller total time division multiplexing ratio, so as to optimize the resource allocation of the critical timing paths in the system, reduce transmission delay, and improve transmission efficiency, FPGA resource utilization and system performance.

[0058] Further, based on the above embodiments, before recalculating the second time division multiplexing ratio sum value of all path edges in the target timing path according to the current time division multiplexing ratio of each path edge, the method further includes:

[0059] The current time division multiplexing ratio of each path edge is legalized so that the physical resource multiplexing ratio between each FPGA pair does not exceed the total number of its physical lines, and the current time division multiplexing ratio of the corresponding path edge is updated.

[0060] In the embodiment of the present invention, the FPGA pair may be specifically understood as: two adjacent FPGAs in a multi-FPGA system having a time-multiplexed hard-wired inter-FPGA connection.

[0061] Specifically, the total number of available physical lines between each FPGA pair and the updated current time division multiplexing ratio of each path edge between each FPGA pair are determined, and each current time division multiplexing ratio is rounded by rounding down, rounding up, or rounding up. If the current time division multiplexing ratio of each path edge between the current FPGA pair is greater than the total number of physical lines between the current FPGA pair, all time division multiplexing ratios can be multiplied by a normalization factor so that the sum is equal to the total number of physical lines. If the result is a decimal, the legalized current time division multiplexing ratio of each path edge between each FPGA pair can be obtained by rounding down, and the current time division multiplexing ratio of the corresponding path edge is updated. By legalizing and updating the time division multiplexing ratio in the FPGA system, on the basis of ensuring that the physical resource multiplexing rate between each FPGA pair does not exceed the total number of its physical lines, the system resource utilization rate is improved, the system delay is reduced, the system stability is enhanced, and the signal transmission is optimized. In addition, the scalability of the system is improved, and the system can adapt to different load requirements to ensure the efficiency and reliability of the system design.

[0062] Embodiment 2

[0063] Figure 2 A flowchart of another signal transmission optimization method provided in the second embodiment of the present invention, this embodiment is a refinement of the operation of iterating once in the above embodiment along the iteration direction of approaching the physical resource reuse rate toward the total number of physical lines of the FPGA system to obtain the initial time division multiplexing ratio of each path edge in the target timing diagram, specifically including: in the current iteration round, according to the longest timing path to which each path edge belongs and the current target sum value, calculating the current time division multiplexing ratio of each path edge; according to the current time division multiplexing ratio of each path edge, calculating the current physical resource reuse rate; if the current FPG If the physical resource reuse rate of pair A and the total number of physical lines of the FPGA pair do not meet the consistency condition, the target total value is updated according to the current system physical resource reuse rate and the total number of system physical lines; a new iteration round is started as the current iteration round, and the operation of calculating the current time division multiplexing ratio of each path edge according to the longest timing path to which each path edge belongs and the current target total value is returned until the current physical resource reuse rate of the latest iteration and the total number of physical lines meet the consistency condition; the current time division multiplexing ratio of each path edge calculated at the end of one iteration is determined as the initial time division multiplexing ratio.

[0064] Correspondingly, such as Figure 2 As shown, the method includes:

[0065] S210: Obtain a target timing diagram of the FPGA system to be optimized.

[0066] The target timing diagram includes multiple timing paths, and each timing path includes multiple path edges for connecting two FPGAs.

[0067] S220 . In the current iteration round, the current time division multiplexing ratio of each path edge is calculated according to the longest timing path to which each path edge belongs and the current target sum value.

[0068] Among them, the target sum value has a set initial value.

[0069] In the embodiment of the present invention, the target sum value may be specifically understood as a unified value to which the sum of the time division multiplexing ratios of each timing path approaches.

[0070] Specifically, the target sum is set to an empirical maximum value goal, and this value will become smaller and smaller in subsequent iterations. In the current iteration round, traverse each path edge on the target timing diagram, and for each timing path to which the path edge belongs, calculate its total delay, which can include logic delay, routing delay, and any additional timing constraints, such as input delay and output delay. Determine the timing path with the largest delay as the longest timing path to which the path edge belongs, and obtain the length |P| of the longest timing path to which the current path edge belongs, which is equivalent to the number of path edges contained in the timing path. Then the current time division multiplexing ratio of each path edge is Among them, r i Represents the time division multiplexing ratio on the i-th edge.

[0071] S230: Calculate the current physical resource reuse rate according to the current time division reuse ratio of each path edge.

[0072] Specifically, the current physical resource reuse rate may include the current FPGA to physical resource reuse rate and the current system physical resource reuse rate. Among them, u pq Represents the FPGA pair FPGA p and FPGA q (with F pq represents the physical line resource utilization rate between i F pq The time division multiplexing ratio of the path edges of each timing path between. The current system physical resource multiplexing rate u=Σu pq .

[0073] S240: If the current FPGA pair physical resource reuse rate and the total number of physical lines of the FPGA pair do not meet the consistency condition, update the target sum value according to the current system physical resource reuse rate and the total number of system physical lines.

[0074] Specifically, if the current FPGA pair physical resource reuse rate and the total number of physical lines of the FPGA pair do not meet the consistency condition, for example, the absolute value of the difference between the current FPGA pair physical resource reuse rate and the total number of physical lines of the FPGA pair is greater than the preset threshold or does not reach the preset upper limit of the number of iterations, that is, if the physical line resource utilization rate of all FPGA pairs is not very close to the number of physical lines, the target sum value is updated to Among them, goal is the current target sum value, u is the current system physical resource reuse rate, and w represents the total number of physical lines in the entire system.

[0075] S250, start a new iteration round as the current iteration round, and return to execute the operation of calculating the current time division multiplexing ratio of each path edge according to the longest timing path to which each path edge belongs and the current target sum value, until the current physical resource multiplexing rate of the latest iteration and the total number of physical lines meet the consistency condition.

[0076] Specifically, a new iteration round is started as the current iteration round, and the result of the previous iteration round is used as the iteration initial value of the current iteration round, and iteration is performed until the current physical resource reuse rate and the total number of physical lines of the latest iteration meet the consistency condition.

[0077] S260: Determine the current time division multiplexing ratio of each path edge calculated at the end of one iteration as the initial time division multiplexing ratio.

[0078] Specifically, the current time division multiplexing ratio of each path edge calculated at the end of an iteration can be a calculation result that meets the consistency condition, or, when the total utilization rate of the system's physical line resources is greater than or equal to the number of physical lines of the system, the last calculation result is retained and determined as the initial time division multiplexing ratio.

[0079] S270, taking the initial time division multiplexing ratio of each path edge at the end of one iteration as the initial starting value of the iteration, performing a second iteration with the goal of allocating more physical resources to the path edges on the timing paths with longer system delays, and determining the target time division multiplexing ratio of each path edge in the target timing diagram.

[0080] S280 , configuring the FPGA system for time division multiplexing according to each target time division multiplexing ratio.

[0081] The technical solution of the embodiment of the present invention obtains the target timing diagram; in the current iteration round, according to the longest timing path to which each path edge belongs and the current target sum value, calculates the current time division multiplexing ratio and the current physical resource multiplexing rate of each path edge; if the current FPGA pair physical resource multiplexing rate and the total number of physical lines of the FPGA pair do not meet the consistency condition, then the target sum value is updated according to the current system physical resource multiplexing rate and the total number of system physical lines; starts a new iteration round, and returns the executed operation until the latest iteration result meets the consistency condition; uses the obtained current time division multiplexing ratio of each path edge as the initial starting value of the iteration, performs a second iteration with the goal of allocating more physical resources to the path edges on the timing path with longer system delay, and configures the FPGA system for time division multiplexing according to the obtained target time division multiplexing ratios. Through one iteration, the initial time division multiplexing ratio is allocated so that the resources of the physical lines occupied by each timing path are close to equal, avoiding the situation where some timing paths occupy too many resources while other timing paths have insufficient resources, thereby improving the overall resource utilization. Then, through a second iteration, resources are dynamically allocated according to the criticality of the timing path, optimizing the resource allocation of the key timing paths in the system, reducing transmission delays, and improving transmission efficiency, FPGA resource utilization, and system performance.

[0082] Optionally, based on the above embodiments, in the current iteration round, according to the longest timing path to which each path edge belongs and the current target sum value, the current time division multiplexing ratio of each path edge is calculated, including:

[0083] In the current iteration round, traverse the current path edge in sequence and obtain the current longest time sequence path to which the current path edge belongs;

[0084] The total number of path edges included in the current longest timing path is obtained, and the ratio of the current target sum value divided by the total number of path edges is calculated as the current time division multiplexing ratio of the current path edge.

[0085] Generally speaking, in FPGA design, the length of a timing path usually refers to the sum of the delays on the path, and the longest timing path is the path with the longest delay in the entire design. In most cases, the more path edges a timing path contains across FPGAs, the more likely it is to correspond to the longest timing path, because these path edges may involve more logic levels, longer wiring, and more input / output delays.

[0086] Specifically, in the current iteration round, the target timing graph is traversed in turn to obtain the current path edge and its timing path, and the current longest timing path is determined according to the number of path edges contained in the timing path, and the total number of path edges |P| contained in it is obtained, and the current time division multiplexing ratio of the current path edge is calculated. Compared with the calculation based on total delay, the method of estimating the longest timing path by the number of edges can simplify the calculation process, reduce the consumption of computing resources and improve the iteration efficiency of the design. It is especially helpful in reducing the demand for computing resources in resource-constrained environments and expanding the application scenarios of FPGA systems.

[0087] Optionally, based on the above embodiments, if the current FPGA pair physical resource reuse rate and the total number of physical lines of the FPGA pair do not meet the consistency condition, the target sum value is updated according to the current system physical resource reuse rate and the total number of system physical lines, including:

[0088] If the current FPGA pair physical resource reuse rate and the total number of physical lines of the FPGA pair do not meet the consistency condition According to Update the target sum value;

[0089] Among them, u pq is the current FPGA reuse rate of physical resources, w pq is the total number of physical lines of the FPGA pair, σ is the preset consistency condition threshold; goal is the current target sum value, u is the current system physical resource reuse rate, and w is the total number of physical lines of the system.

[0090] Specifically, if the physical line resource utilization of all FPGA pairs and their physical line quantity do not meet the consistency condition, for example, The condition or the preset upper limit of the number of iterations is not reached, where u pq is the current FPGA reuse rate of physical resources, w pq is the sum of the number of physical lines between the FPGA pair FPGA p and FPGA q, σ is a preset relatively small threshold, and the updated target sum is Among them, goal is the current target sum value, u is the current system physical resource reuse rate, and w represents the total number of physical lines in the entire system. The formula shows that if the sum of the utilization rates of physical line resources is less than the number of physical lines, the target value goal will decrease as the number of iterations increases. If the sum of the utilization rates of physical line resources is greater than or equal to the number of physical lines, it means that the result of the previous iteration meets the requirements, and the previous result is retained as the final result. The initial time division multiplexing ratio is allocated through one iteration, and the consistency conditions are set to make the resources of the physical lines occupied by each timing path approach equal, thereby improving the resource utilization of the system. Balanced resource allocation can reduce congestion and errors caused by resource competition and improve overall throughput.

[0091] Specific application scenarios

[0092] In a multi-FPGA system, time division multiplexing is a technology used to transmit signals between FPGAs. Although time division multiplexing can improve the logic utilization of the FPGA system, each signal must wait for its assigned time window to arrive before it can start transmission, and the delay between FPGAs will also become longer. Figure 3 The present invention is a compilation flow chart of a multi-FPGA system using time division multiplexing technology applicable to an embodiment of the present invention. In a modern compilation process, the negative impact of time division multiplexing on delay can be reduced by considering the delay caused by time division multiplexing technology in the division, routing and post-routing stages. For example, time division multiplexing ratio allocation and division are performed simultaneously to increase the system clock frequency; the time division multiplexing ratio allocation problem is formalized as an integer linear programming, and non-critical FPGA inter-networks are placed in the time division multiplexing lines to improve logic utilization without affecting system timing. However, these methods need to consider all actual time division multiplexing constraints, and still require a long FPGA system running time, which reduces the efficiency of signal transmission and the resource utilization of FPGA.

[0093] To solve the above problems, an embodiment of the present invention proposes a signal transmission optimization method, which may include: grouping signals based on timing paths to make initial time division multiplexing ratio allocation, and optimizing the sum of time division multiplexing ratios of signals in the group corresponding to the longest timing path (because the system delay is determined by the delay on the longest timing path). Introducing competitive factors, more resources are allocated to timing paths with larger total time division multiplexing ratios, and fewer resources are allocated to smaller timing paths.

[0094] For a multi-FPGA system with time-multiplexed hardwired inter-FPGA connections, where two FPGAs are logically adjacent if they are directly connected in the system, the two adjacent FPGAs are called an FPGA pair. Since the number of path edges of the timing path is much larger than the number of physical lines between FPGAs, time-division multiplexing lines are used to connect different FPGAs. In such a system, the path edge of each inter-FPGA timing path is assigned a time-division multiplexing ratio, which indicates how many other signals share a physical line with the path edge. Only networks with the same direction and the same time-division multiplexing ratio can be assigned to the same physical line. When estimating the delay of the signal in the target system, the worst case is assumed, that is, an inter-FPGA signal needs to wait for the entire time-division multiplexing cycle to get a transmission opportunity. Therefore, the transmission delay is proportional to the time-division multiplexing ratio of the line.

[0095] In system-level routing, given a signal transmission list and an FPGA system timing diagram, it is necessary to determine the routing topology of each network and estimate the time division multiplexing ratio of each inter-FPGA edge to maximize system performance. In order to optimize timing, it is necessary to minimize the total delay of the most critical signal path in the signal transmission list. To this end, some signal transmission groups are defined, each of which represents a set of signals on a critical path, and each signal belongs to at least one group. Since the delay of the signal path is mainly determined by the delay of the inter-FPGA signals on the path, it can be estimated by the sum of the time division multiplexing ratios of the signals in the corresponding signal transmission groups. Define the sum of the time division multiplexing ratios of the edges on the maximum timing path (the path edges between FPGAs on the timing path) r max , as the objective to be minimized. Figure 4 is a schematic diagram of a time division multiplexing ratio optimization target applicable to an embodiment of the present invention, such as Figure 4 As shown in the figure, F1, F2 to F6 represent FPGAs, the thick solid lines represent the physical lines between FPGA pairs, the thin lines of different forms represent a timing path, and the numbers represent their time division multiplexing ratios. Here, r max =2+2+4=8 (corresponding to the sum of the time division multiplexing ratios on the timing path of the thin solid line).

[0096] Specifically, after all transmission signals on a timing path are grouped together, the signals are grouped based on the timing path to perform initial time division multiplexing ratio allocation, which may include:

[0097] 1. Set the target value goal (equivalent to the target sum value in the previous text) that the sum of the time division multiplexing ratios in each group approaches to a larger value.

[0098] 2. Traverse each edge on the timing graph, obtain the length of the longest timing path to which the current edge belongs (equivalent to the number of edges on the timing path), express it as |P|, and set the time division multiplexing ratio of the current edge to Use r i To represent the time division multiplexing ratio on the i-th edge.

[0099] 3. Calculate the utilization of the physical lines between each FPGA pair, using To represent the FPGA pair FPGAp and FPGAq (with F pq represents the utilization rate of physical line resources between (equivalent to the physical resource reuse rate mentioned above), where r i F pq Calculate the total utilization of all physical line resources in the entire system u=Σu pq (Sum the physical line utilization on all FPGA pairs). Then update the target value goal to Where w represents the number of physical lines in the entire system (equivalent to the total number of physical lines mentioned above). The formula shows that if the total utilization of physical line resources is less than the number of physical lines, the target value goal will become smaller. When the total utilization of physical line resources is greater than or equal to the number of physical lines, it seems that the result of the previous iteration meets the requirements, and the previous result is directly retained.

[0100] 4. If the physical line resource utilization of all FPGA pairs is close to the number of physical lines, for example, When the condition is pq is the number of physical lines between the FPGA pair p and q, σ is a preset smaller one-iteration threshold, or when the preset iteration number threshold is reached, the initialization ends, otherwise returns to the second step.

[0101] The transmission signals are grouped based on the timing paths to make initial time division multiplexing ratio allocation, so that the resources of the physical lines occupied by each timing path are close to equal, avoiding the situation where some timing paths occupy too many resources while other timing paths have insufficient resources, thereby improving the overall resource utilization and providing a basis for subsequent optimization.

[0102] Specifically, optimizing the sum of time division multiplexing ratios of signals within the group corresponding to the longest timing path may include:

[0103] 1. Get the longest timing path in the timing graph and calculate the sum of the time division multiplexing ratios of all edges on this timing path. max (equivalent to the sum of the first time-division multiplexing ratios in the previous text). Set a target factor β to satisfy the constraint 0<β<1. The β value will increase with the increase of the number of iterations. Set the optimization target value to t=r max *β.

[0104] 2. Traverse each edge i, obtain all the timing paths to which the current edge belongs, and calculate the sum of the time-division reuse ratios of the edges on these timing paths respectively, and obtain the maximum value r among them imax The scaling ratio of the time-division reuse ratio of the current edge is calculated as Then update the time-division reuse ratio corresponding to the current edge to r i =r i *c i .

[0105] 3. Legalize the time-division multiplexing ratio of all edges so that the physical line resource utilization between each FPGA pair does not exceed the number of physical lines.

[0106] 4. Update the timing diagram and recalculate the sum of the time division multiplexing ratios of all edges on the current longest timing path r′ max(Equivalent to the second time division multiplexing ratio sum value mentioned above).

[0107] 5. If r′ max With r max Close to, for example, satisfy When the condition is met, Δ is a preset smaller secondary iteration threshold, preferably, the secondary iteration threshold is 0.1, or when the number of iterations reaches the preset threshold, the optimization ends. Otherwise, return to the first step.

[0108] A signal transmission optimization method proposed in an embodiment of the present invention performs initial time division multiplexing ratio allocation through one iteration so that the resources of the physical lines occupied by each timing path are close to equal. Then, through a second iteration, resources are dynamically allocated according to the criticality of the timing path, more resources are allocated to the timing path with a larger total time division multiplexing ratio, and fewer resources are allocated to the timing path with a smaller total time division multiplexing ratio. The resource allocation of the critical timing paths in the system is optimized, the transmission delay is reduced, and the transmission efficiency, the resource utilization rate of the FPGA and the system performance are improved.

[0109] Embodiment 3

[0110] Figure 5 This is a schematic diagram of the structure of a signal transmission optimization device provided in Embodiment 3 of the present invention. Figure 5 As shown, the device includes: a timing diagram acquisition module 510, a ratio acquisition module 520, a ratio determination module 530 and a system configuration module 540, wherein:

[0111] The timing diagram acquisition module 510 is used to acquire a target timing diagram of the FPGA system to be optimized; wherein the target timing diagram contains multiple timing paths, and each timing path contains multiple path edges for connecting two FPGAs;

[0112] The ratio acquisition module 520 is used to perform one iteration along the iteration direction of moving the physical resource reuse rate closer to the total number of physical lines of the FPGA system, and obtain the initial time division reuse ratio of each path edge in the target timing diagram;

[0113] A ratio determination module 530 is used to use the initial time division multiplexing ratio of each path edge at the end of one iteration as the initial starting value of the iteration, and to perform a second iteration with the goal of allocating more physical resources to the path edge on the timing path with longer system delay, and determine the target time division multiplexing ratio of each path edge in the target timing diagram;

[0114] The system configuration module 540 is used to configure the FPGA system for time division multiplexing according to each target time division multiplexing ratio.

[0115] The technical solution of the embodiment of the present invention is to obtain the target timing diagram of the FPGA system to be optimized; perform one iteration along the iteration direction of approaching the physical resource reuse rate to the total number of physical lines of the FPGA system, and obtain the initial time division multiplexing ratio of each path edge in the target timing diagram; use the initial time division multiplexing ratio of each path edge at the end of one iteration as the initial starting value of the iteration, and perform a second iteration with the goal of allocating more physical resources to the path edge on the timing path with longer system delay, and determine the target time division multiplexing ratio of each path edge in the target timing diagram; and configure the FPGA system for time division multiplexing according to each target time division multiplexing ratio. The initial time division multiplexing ratio is allocated through one iteration, so that the resources of the physical lines occupied by each timing path are close to equal, and then the resources are dynamically allocated according to the criticality of the timing path through the second iteration, so that more resources are allocated to the timing path with a larger total time division multiplexing ratio, and less resources are allocated to the timing path with a smaller total time division multiplexing ratio, so as to optimize the resource allocation of the key timing path in the system, reduce the transmission delay, and improve the transmission efficiency, the resource utilization rate of the FPGA and the system performance.

[0116] Based on the above embodiments, the ratio acquisition module 520 is specifically used for:

[0117] In the current iteration round, the current time division multiplexing ratio of each path edge is calculated according to the longest timing path to which each path edge belongs and the current target sum value, wherein the target sum value has a set initial value;

[0118] Calculate the current physical resource reuse rate based on the current time division reuse ratio of each path edge;

[0119] If the current FPGA pair physical resource reuse rate and the total number of physical lines of the FPGA pair do not meet the consistency condition, then update the target sum value according to the current system physical resource reuse rate and the total number of system physical lines;

[0120] Start a new iteration round as the current iteration round, and return to perform the operation of calculating the current time division multiplexing ratio of each path edge according to the longest timing path to which each path edge belongs and the current target sum value, until the current physical resource multiplexing ratio of the latest iteration and the total number of physical lines meet the consistency condition;

[0121] The current time division multiplexing ratio of each path edge calculated at the end of one iteration is determined as the initial time division multiplexing ratio.

[0122] Optionally, based on the above embodiments, the ratio acquisition module 520 may include: a path traversal unit and a ratio calculation unit, wherein:

[0123] A path traversal unit is used to traverse and obtain the current path edge in sequence in the current iteration round, and obtain the current longest time sequence path to which the current path edge belongs;

[0124] The ratio calculation unit is used to obtain the total number of path edges contained in the current longest timing path, and calculate the ratio of the current target sum value divided by the total number of path edges as the current time division multiplexing ratio of the current path edge.

[0125] Optionally, based on the above embodiments, the ratio acquisition module 520 may include: a condition judgment unit, wherein:

[0126] A conditional judgment unit is used to determine if the current FPGA pair physical resource reuse rate and the total number of physical lines of the FPGA pair do not meet the consistency condition. According to Update the target sum value;

[0127] Among them, w pq is the current FPGA reuse rate of physical resources, w pq is the total number of physical lines of the FPGA pair, σ is the preset consistency condition threshold; goal is the current target sum value, u is the current system physical resource reuse rate, and W is the total number of physical lines in the system.

[0128] Based on the above embodiments, the ratio determination module 530 is specifically used for:

[0129] In the current iteration round, the longest target timing path in the target timing graph is obtained, and the sum of the first time division multiplexing ratios of all path edges in the target timing path is calculated;

[0130] Calculating a target optimization value according to the first time division multiplexing ratio sum value and a current target factor, wherein the target factor has a preset initial value;

[0131] Traverse each path edge in the target timing graph, calculate the maximum sum of the time division multiplexing ratios of each path edge, and update the current time division multiplexing ratio of each path edge according to the maximum sum of the time division multiplexing ratios;

[0132] Recalculate the sum of the second time division multiplexing ratios of all path edges in the target timing path according to the current time division multiplexing ratio of each path edge;

[0133] If the second time division multiplexing ratio sum value and the first time division multiplexing ratio sum value do not meet the consistency condition, then update the target factor according to a preset update method;

[0134] Start a new iteration round as the current iteration round, and return to execute the operation of obtaining the current longest target timing path in the target timing diagram until the sum value of the second time division multiplexing ratio and the sum value of the first time division multiplexing ratio of the latest iteration meet the consistency condition;

[0135] The current time division multiplexing ratio of each path edge calculated at the end of the second iteration is determined as the target time division multiplexing ratio.

[0136] Further, based on the above embodiments, the ratio determination module 530 may further include: a ratio legalization unit, wherein:

[0137] The ratio legalization unit is used to legalize the current time division multiplexing ratio of each path edge so that the physical resource reuse rate between each FPGA pair does not exceed the total number of its physical lines before recalculating the second time division multiplexing ratio sum value of all path edges in the target timing path based on the current time division multiplexing ratio of each path edge, and update the current time division multiplexing ratio of the corresponding path edge.

[0138] The signal transmission optimization device provided in the embodiment of the present invention can execute the signal transmission optimization method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0139] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0140] Embodiment 4

[0141] Figure 6 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0142] like Figure 6As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0143] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0144] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as the signal transmission optimization method, that is:

[0145] Obtain a target timing diagram of the FPGA system to be optimized; wherein the target timing diagram contains multiple timing paths, and each timing path contains multiple path edges for connecting two FPGAs;

[0146] Perform one iteration in the iteration direction of moving the physical resource reuse rate closer to the total number of physical lines of the FPGA system to obtain the initial time division reuse ratio of each path edge in the target timing diagram;

[0147] The initial time division multiplexing ratio of each path edge at the end of one iteration is used as the initial value of the iteration, and a second iteration is performed with the goal of allocating more physical resources to the path edges on the timing paths with longer system delays, to determine the target time division multiplexing ratio of each path edge in the target timing diagram;

[0148] According to each target time division multiplexing ratio, the FPGA system is configured for time division multiplexing.

[0149] In some embodiments, the signal transmission optimization method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the signal transmission optimization method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the signal transmission optimization method in any other appropriate manner (e.g., by means of firmware).

[0150] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0151] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0152] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0153] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0154] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0155] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0156] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0157] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A signal transmission optimization method, characterized in that: include: Obtain a target timing diagram of the FPGA system to be optimized; wherein the target timing diagram contains multiple timing paths, and each timing path contains multiple path edges for connecting two FPGAs; Perform one iteration in the iteration direction of moving the physical resource reuse rate closer to the total number of physical lines of the FPGA system to obtain the initial time division reuse ratio of each path edge in the target timing diagram; The initial time division multiplexing ratio of each path edge at the end of one iteration is used as the initial value of the iteration, and a second iteration is performed with the goal of allocating more physical resources to the path edges on the timing paths with longer system delays, to determine the target time division multiplexing ratio of each path edge in the target timing diagram; According to each target time division multiplexing ratio, the FPGA system is configured for time division multiplexing.

2. The method according to claim 1, characterized in that Perform an iteration in the direction of moving the physical resource reuse rate closer to the total number of physical lines of the FPGA system to obtain the initial time division reuse ratio of each path edge in the target timing diagram, including: In the current iteration round, the current time division multiplexing ratio of each path edge is calculated according to the longest timing path to which each path edge belongs and the current target sum value, wherein the target sum value has a set initial value; Calculate the current physical resource reuse rate based on the current time division reuse ratio of each path edge; If the current FPGA pair physical resource reuse rate and the total number of physical lines of the FPGA pair do not meet the consistency condition, then update the target sum value according to the current system physical resource reuse rate and the total number of system physical lines; Start a new iteration round as the current iteration round, and return to perform the operation of calculating the current time division multiplexing ratio of each path edge according to the longest timing path to which each path edge belongs and the current target sum value, until the current physical resource multiplexing ratio of the latest iteration and the total number of physical lines meet the consistency condition; The current time division multiplexing ratio of each path edge calculated at the end of one iteration is determined as the initial time division multiplexing ratio.

3. The method according to claim 2, characterized in that In the current iteration round, the current time division multiplexing ratio of each path edge is calculated according to the longest timing path to which each path edge belongs and the current target sum value, including: In the current iteration round, traverse the current path edge in sequence and obtain the current longest time sequence path to which the current path edge belongs; The total number of path edges included in the current longest timing path is obtained, and the ratio of the current target sum value divided by the total number of path edges is calculated as the current time division multiplexing ratio of the current path edge.

4. The method according to claim 2, characterized in that: If the current FPGA pair physical resource reuse rate and the total number of physical lines of the FPGA pair do not meet the consistency condition, the target sum value is updated according to the current system physical resource reuse rate and the total number of system physical lines, including: If the current FPGA pair physical resource reuse rate and the total number of physical lines of the FPGA pair do not meet the consistency condition According to Update the target sum value; Among them, u pq is the current FPGA reuse rate of physical resources, w pq is the total number of physical lines of the FPGA pair, σ is the preset consistency condition threshold; goal is the current target sum value, u is the current system physical resource reuse rate, and w is the total number of physical lines of the system.

5. The method according to claim 1, characterized in that: A second iteration is performed with the goal of allocating more physical resources to the path edges on the timing paths with longer system delays, and the target time division multiplexing ratio of each path edge in the target timing diagram is determined, including: In the current iteration round, the longest target timing path in the target timing graph is obtained, and the sum of the first time division multiplexing ratios of all path edges in the target timing path is calculated; Calculating a target optimization value according to the first time division multiplexing ratio sum value and a current target factor, wherein the target factor has a preset initial value; Traverse each path edge in the target timing graph, calculate the maximum sum of the time division multiplexing ratios of each path edge, and update the current time division multiplexing ratio of each path edge according to the maximum sum of the time division multiplexing ratios; Recalculate the sum of the second time division multiplexing ratios of all path edges in the target timing path according to the current time division multiplexing ratio of each path edge; If the second time division multiplexing ratio sum value and the first time division multiplexing ratio sum value do not meet the consistency condition, then update the target factor according to a preset update method; Start a new iteration round as the current iteration round, and return to execute the operation of obtaining the current longest target timing path in the target timing diagram until the sum value of the second time division multiplexing ratio and the sum value of the first time division multiplexing ratio of the latest iteration meet the consistency condition; The current time division multiplexing ratio of each path edge calculated at the end of the second iteration is determined as the target time division multiplexing ratio.

6. The method according to claim 5, characterized in that Before recalculating the second time division multiplexing ratio sum value of all path edges in the target timing path according to the current time division multiplexing ratio of each path edge, the method further includes: The current time division multiplexing ratio of each path edge is legalized so that the physical resource multiplexing ratio between each FPGA pair does not exceed the total number of its physical lines, and the current time division multiplexing ratio of the corresponding path edge is updated.

7. A signal transmission optimization device, characterized in that: include: A timing diagram acquisition module is used to acquire a target timing diagram of the FPGA system to be optimized; wherein the target timing diagram contains multiple timing paths, and each timing path contains multiple path edges for connecting two FPGAs; A ratio acquisition module, used for performing one iteration along an iteration direction of moving the physical resource reuse rate closer to the total number of physical lines of the FPGA system, and obtaining an initial time division reuse ratio of each path edge in the target timing diagram; A ratio determination module is used to use the initial time division multiplexing ratio of each path edge at the end of one iteration as the initial starting value of the iteration, and to perform a second iteration with the goal of allocating more physical resources to the path edge on the timing path with longer system delay, and determine the target time division multiplexing ratio of each path edge in the target timing diagram; The system configuration module is used to configure the FPGA system for time division multiplexing according to each target time division multiplexing ratio.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the signal transmission optimization method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the signal transmission optimization method according to any one of claims 1 to 6 when executed.

10. A computer program product, characterized in that The computer program product comprises a computer program, which, when executed by a processor, implements the signal transmission optimization method according to any one of claims 1 to 6.

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