Waveform generation method, system and device, waveform generator and medium

Abstract

The embodiment of the invention discloses a waveform generation method, system and device, a waveform generator and a medium. The method comprises the following steps: acquiring debugging data packets transmitted by each FPGA in the cascaded FPGA system through a parallel transmission channel; according to each debugging data packet, generating an independent waveform file corresponding to each FPGA in the cascade FPGA system in parallel; index files corresponding to the cascade FPGA system are generated according to the independent waveform files, and the index files are associated with the independent waveform files corresponding to the FPGAs; and transmitting the index file to a waveform viewing tool so as to search each corresponding independent waveform file according to the index file, and viewing a target waveform corresponding to the cascade FPGA system. The method can shorten the waveform generation time and improve the debugging efficiency of the chip.

Description

Technical Field

[0001] The present invention relates to the field of digital integrated circuit technology, and in particular to a waveform generation method, system, device, waveform generator and medium. Background Art

[0002] With the advancement of integrated circuit technology, the scale of chip design is getting larger and larger, often reaching hundreds of millions or even billions of gate-level circuits. As the scale of chip design increases, it often needs to be divided into multiple field-programmable gate arrays (FPGAs) for verification and debugging. Multiple FPGAs are connected into a whole through cables to form a cascaded FPGA system.

[0003] The traditional waveform generation method is to aggregate the waveform data of all FPGAs in the cascaded FPGA system and generate a waveform file. The waveform viewing tool can open a waveform file generated by multiple FPGAs for waveform viewing.

[0004] However, the traditional waveform generation method has low performance and the generated waveform files are huge. All FPGA signals and waveform data are in one waveform file, and the signal volume and waveform data are huge, which will also cause low waveform viewing performance. The waveform generation speed and performance affect the debugging efficiency of the chip, making the existing waveform generation method unable to meet the debugging requirements of the cascaded FPGA system. Summary of the invention

[0005] The present invention provides a waveform generation method, system, device, waveform generator and medium to shorten the waveform generation time and improve the debugging efficiency of the chip.

[0006] According to one aspect of the present invention, a waveform generation method in a cascaded FPGA system is provided, the cascaded FPGA system comprising: at least two connected FPGAs; the waveform generation method comprises:

[0007] Obtaining debug data packets transmitted by each FPGA in the cascaded FPGA system through a parallel transmission channel;

[0008] Generate independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each of the debugging data packets;

[0009] Generate an index file corresponding to the cascaded FPGA system according to each of the independent waveform files, wherein the index file is associated with the independent waveform files corresponding to each FPGA;

[0010] The index file is transferred to a waveform viewing tool to search for the corresponding independent waveform files according to the index file, and view the target waveform corresponding to the cascaded FPGA system.

[0011] According to another aspect of the present invention, a waveform generation system is provided, wherein the waveform generation system is used for waveform generation of a cascaded FPGA system; the cascaded FPGA system comprises: at least two connected FPGAs; the waveform generation system comprises: each FPGA in the cascaded FPGA system, a waveform generator, and a waveform viewing tool; wherein:

[0012] Each FPGA is used to encapsulate the debugging data, generate a debugging data packet, and transmit the debugging data packet to the waveform generator through a parallel transmission channel;

[0013] The waveform generator is used to receive each of the debugging data packets transmitted through the parallel transmission channel, generate independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each of the debugging data packets, generate an index file corresponding to the cascaded FPGA system according to each of the independent waveform files, and transmit the index file to the waveform viewing tool;

[0014] Wherein, the index file is associated with the independent waveform files corresponding to each FPGA;

[0015] The waveform viewing tool is used to search for the corresponding independent waveform files according to the index file, integrate the waveforms in the independent waveform files to form a target waveform corresponding to the cascaded FPGA system; and display the target waveform.

[0016] According to another aspect of the present invention, a waveform generation method is provided, the waveform generation method is used for waveform generation in a cascaded FPGA system; the cascaded FPGA system comprises: at least two connected FPGAs; the waveform generation method comprises:

[0017] Encapsulating the debugging data through each FPGA in the cascaded FPGA system to generate a debugging data packet, and transmitting the debugging data packet to the waveform generator through a parallel transmission channel;

[0018] Receiving each of the debugging data packets transmitted through the parallel transmission channel through a waveform generator, generating independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each of the debugging data packets, generating an index file corresponding to the cascaded FPGA system according to each of the independent waveform files, and transmitting the index file to a waveform viewing tool;

[0019] Wherein, the index file is associated with the independent waveform files corresponding to each FPGA;

[0020] The waveform viewing tool searches for the corresponding independent waveform files according to the index file, integrates the waveforms in the independent waveform files, and forms a target waveform corresponding to the cascaded FPGA system; and displays the target waveform.

[0021] According to another aspect of the present invention, a waveform generating device in a cascaded FPGA system is provided, wherein the cascaded FPGA system comprises: at least two connected FPGAs; the waveform generating device comprises:

[0022] A debugging data packet acquisition module, used to acquire debugging data packets transmitted by each FPGA in the cascaded FPGA system through a parallel transmission channel;

[0023] An independent waveform file generation module, used for generating independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each of the debugging data packets;

[0024] An index file generating module, used to generate an index file corresponding to the cascaded FPGA system according to each of the independent waveform files, wherein the index file is associated with the independent waveform files corresponding to each FPGA;

[0025] An index file transmission module is used to transmit the index file to a waveform viewing tool, so as to search for the corresponding independent waveform files according to the index file and view the target waveform corresponding to the cascaded FPGA system.

[0026] According to another aspect of the present invention, there is provided a waveform generator, the waveform generator comprising:

[0027] at least one processor; and

[0028] a memory communicatively connected to the at least one processor; wherein,

[0029] The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the waveform generation method in the cascaded FPGA system described in any embodiment of the present invention.

[0030] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the waveform generation method in the cascaded FPGA system described in any embodiment of the present invention when executed.

[0031] According to another aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the waveform generation method in the cascaded FPGA system according to any embodiment of the present invention is implemented.

[0032] The technical solution of the embodiment of the present invention obtains debug data packets transmitted by each FPGA in the cascaded FPGA system through a parallel transmission channel; generates independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each debug data packet; generates an index file corresponding to the cascaded FPGA system according to each independent waveform file, wherein the index file is associated with the independent waveform file corresponding to each FPGA; transmits the index file to a waveform viewing tool to search for the corresponding independent waveform files according to the index file, and view the target waveform corresponding to the cascaded FPGA system, thereby solving the waveform generation problem when the cascaded FPGA system is debugged, shortening the waveform generation time, and improving the debugging efficiency of the chip.

[0033] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 is a flowchart of a waveform generation method in a cascaded FPGA system provided in Embodiment 1 of the present invention;

[0036] Figure 2 is a schematic diagram of a new waveform file format provided according to the first embodiment of the present invention;

[0037] Figure 3 is a structural schematic diagram of a waveform generation system provided according to Embodiment 2 of the present invention;

[0038] Figure 4 is a flow chart of a waveform generation method provided according to Embodiment 3 of the present invention;

[0039] Figure 5 is a schematic diagram of the structure of a waveform generating device in a cascaded FPGA system provided according to a fourth embodiment of the present invention;

[0040] Figure 6It is a structural schematic diagram of a waveform generator for implementing the waveform generation method in the cascaded FPGA system of an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] Embodiment 1

[0044] Figure 1 This is a flowchart of a waveform generation method in a cascaded FPGA system provided according to the first embodiment of the present invention. This embodiment is applicable to the case where a chip is debugged by generating a waveform when the chip is composed of cascaded FPGAs. The method can be executed by a waveform generation device in the cascaded FPGA system. The waveform generation device in the cascaded FPGA system can be implemented in the form of hardware and / or software. The waveform generation device in the cascaded FPGA system can be configured in an electronic device, which can be a personal computer (PC) or a waveform generator. The method can be applied to a cascaded FPGA system. The cascaded FPGA system includes: at least two connected FPGAs.

[0045] like Figure 1 As shown, the waveform generation method in the cascaded FPGA system includes:

[0046] Step 110: Obtain debug data packets transmitted by each FPGA in the cascaded FPGA system through a parallel transmission channel.

[0047] There are usually a large number of FPGAs in a cascaded FPGA system. The signals that need to be debugged usually come from different FPGAs, and a single FPGA also has a large amount of waveform data, which is a great challenge to the performance of waveform generation. Each FPGA can have its own transmission channel, such as a high-speed transmission channel. The high-speed transmission channel can be based on a high-speed physical channel. Multiple FPGAs can synchronously and parallelly capture the waveform data from each FPGA to generate a debug data packet. For example, a debug data packet can be a data packet encapsulated by data encoding. The debug data packet can include a data packet header, data content, and a data packet tail. Among them, the data packet header contains information such as data encoding mode, data channel number, data timestamp, and data length. The data content can be a combination of signals of multiple clock cycles, and the signal lists of multiple clock cycles are spliced ​​into a transceiver data packet through encoding.

[0048] Each FPGA can transmit debug data packets to electronic devices such as waveform generators in parallel through its own transmission channel. The parallel transmission method can increase the data transmission rate during waveform generation, thereby increasing the waveform generation speed and improving chip debugging performance.

[0049] In an optional implementation of an embodiment of the present invention, debug data packets transmitted by each FPGA in the cascaded FPGA system are obtained through parallel transmission channels, including: obtaining debug data packets transmitted by each FPGA in the cascaded FPGA system through parallel high-speed transmission channels; high-speed transmission channels include: PCIE channels, 10 Gigabit Ethernet, and USB channels.

[0050] Among them, PCIE channel is a high-speed serial computer expansion bus (Peripheral Component Interconnect Express). 10 Gigabit Ethernet is an Ethernet that supports a data transmission rate of 10 Gigabits per second (10Gbps). USB channel is a universal serial bus (Universal Serial Bus) used to establish connections and transmit data between computers and their external devices. The transmission performance of the high-speed channel is directly related to the transmission physical channel performance of the generated waveform.

[0051] Step 120 : Generate independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each debugging data packet.

[0052] Among them, an independent waveform file can be generated for a debug data packet of an FPGA. When waveform files are generated for multiple FPGAs, a parallel method can be adopted. For example, the multi-threading of the waveform generator is used to generate waveform files in parallel. Specifically, the waveform generator can process the debug data of each channel based on multi-threading or multi-process, receive the debug data in parallel, parse the debug data in parallel, and generate a waveform file for each channel in parallel.

[0053] Each independent waveform file corresponds only to the FPGA. There is no correlation between the independent waveform files. The independent waveform files can be in a mature, universal waveform file format. The waveform generation rate can be increased by generating independent waveform files corresponding to each FPGA in parallel.

[0054] Step 130: Generate an index file corresponding to the cascaded FPGA system according to each independent waveform file.

[0055] When the embodiment of the present invention generates multiple waveform files, it is necessary to generate a new file format so that the waveform viewing tool can open each independent waveform file for unified waveform viewing. Specifically, the embodiment of the present invention generates an index file based on each independent waveform file. The index file is associated with the independent waveform file corresponding to each FPGA. The index file is stored together with each independent waveform file to form a new waveform file format for the waveform viewing tool to open each independent waveform file for unified waveform viewing.

[0056] In an optional implementation of an embodiment of the present invention, an index file corresponding to the cascaded FPGA system is generated based on each independent waveform file, including: filling the storage path of each independent waveform file into the index file; verifying the number of storage paths in the index file according to the number of FPGAs in the cascaded FPGA system; and generating the index file when the number of FPGAs is consistent with the number of storage paths.

[0057] The index file can describe the storage path of all independent waveform files of the FPGA, so that the waveform viewing tool can generate the target waveform based on all the waveform data, allowing the user to perform a summarized unified waveform viewing. Figure 2 Schematic diagram of a new waveform file format provided according to the first embodiment of the present invention. Figure 2 As shown in FIG. 1 , the new waveform file format includes two parts: one part is an index file, and the other part is each independent waveform file. The index file can record the independent waveform files corresponding to all FPGAs in the cascaded FPGA system.

[0058] Step 140: transfer the index file to a waveform viewing tool to search for the corresponding independent waveform files according to the index file, and view the target waveform corresponding to the cascaded FPGA system.

[0059] When the waveform viewing tool receives the index file, it can read the index file to find the independent waveform files corresponding to all the associated FPGAs. For example, the waveform viewing tool reads the path data in the index file, and then obtains the storage path of the independent waveform files corresponding to all the associated FPGAs. The waveform viewing tool can open all the independent waveform files in parallel according to the storage path, and present the waveform data of all the FPGAs in a unified manner. For example, the waveform viewing tool can open the independent waveform files of all FPGAs in parallel based on multi-threading, and finally present the waveform data of all the FPGAs in a unified manner on a graphical user interface (GUI).

[0060] Among them, when unifying waveform data, the waveform viewing tool can integrate each waveform data within the same time threshold to form a target waveform corresponding to the cascaded FPGA system. By using a unified target waveform for waveform display, the waveform generation speed can be improved while maintaining the original waveform display method to achieve chip debugging performance.

[0061] The technical solution of this embodiment obtains debug data packets transmitted by each FPGA in the cascaded FPGA system through a parallel transmission channel; generates independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each debug data packet; generates an index file corresponding to the cascaded FPGA system according to each independent waveform file, wherein the index file is associated with the independent waveform file corresponding to each FPGA; transmits the index file to a waveform viewing tool to search for the corresponding independent waveform files according to the index file, and view the target waveform corresponding to the cascaded FPGA system, thereby solving the waveform generation problem when the cascaded FPGA system is debugged, shortening the waveform generation time, and improving the debugging efficiency of the chip.

[0062] Embodiment 2

[0063] Figure 3 1 is a schematic diagram of a waveform generation system according to a second embodiment of the present invention. The waveform generation system is used for waveform generation in a cascaded FPGA system. The cascaded FPGA system includes: at least two connected FPGAs.

[0064] like Figure 3 As shown, the waveform generation system includes: FPGAs 310 in the cascaded FPGA system, a waveform generator 320, and a waveform viewing tool 330. Among them:

[0065] Each FPGA 310 is used to encapsulate the debugging data, generate a debugging data packet, and transmit the debugging data packet to the waveform generator 320 through a parallel transmission channel.

[0066] Specifically, Figure 3As shown, each FPGA can set a debug data receiver (sample), a data encapsulator (package), and a data transmitter (tranceiver). Sample is responsible for summarizing the debug signals inside the FPGA into waveform data for data encapsulation. Package packages the sampled waveform data into an agreed communication protocol packet format. For example, the data packet format includes a data packet header, data packet content, and data packet tail. Each data packet consists of waveform data of multiple clock cycles, and invalid data is filled with 0. Tranceiver sends the data to the host computer such as a waveform generator.

[0067] like Figure 3 As shown, the waveform generator 320 is used to receive each debug data packet transmitted through a parallel transmission channel, generate an independent waveform file corresponding to each FPGA in the cascaded FPGA system in parallel according to each debug data packet, generate an index file corresponding to the cascaded FPGA system according to each independent waveform file, and transmit the index file to the waveform viewing tool; wherein the index file is associated with the independent waveform file corresponding to each FPGA.

[0068] Specifically, the waveform generator may include a debug data receiving port (recv), a waveform file generator (genwave), and a parallel processing thread. recv is used to receive debug data packets from a single FPGA into the memory for data parsing. genwave is used to generate a waveform file in a new format from the waveform data parsed from the debug data packet. The parallel processing thread is used to parallelly process the process of receiving, parsing, and generating waveform files for each FPGA debug data packet. The index file and each independent waveform file generated by the waveform generator can be kept in the memory. Among them, the index file can be transferred to the waveform viewing tool to debug the chip through waveform viewing.

[0069] like Figure 3 As shown, the waveform viewing tool 330 is used to search for corresponding independent waveform files according to the index file, integrate the waveforms in the independent waveform files, form a target waveform corresponding to the cascaded FPGA system, and display the target waveform.

[0070] Optional, waveform viewing tool, specifically used for: searching for corresponding independent waveform files according to the storage paths of the independent waveform files in the index file; reading the waveform data in each independent waveform file in parallel, and integrating each waveform data within the same time threshold to form a target waveform corresponding to the cascaded FPGA system; and displaying the target waveform.

[0071] The technical solution of the embodiment of the present invention is to set up a waveform generation system including each FPGA in the cascaded FPGA system, a waveform generator, and a waveform viewing tool, wherein each FPGA is used to encapsulate the debugging data, generate a debugging data packet, and transmit the debugging data packet to the waveform generator through a parallel transmission channel; the waveform generator is used to receive each debugging data packet transmitted through the parallel transmission channel, generate independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each debugging data packet, generate an index file corresponding to the cascaded FPGA system according to each independent waveform file, and transmit the index file to the waveform viewing tool; wherein the index file is associated with the independent waveform file corresponding to each FPGA; the waveform viewing tool is used to search for the corresponding independent waveform files according to the index file, integrate the waveforms in the independent waveform files, and form a target waveform corresponding to the cascaded FPGA system; the target waveform is displayed, so as to solve the problem of poor performance caused by a large amount of waveform generation data when the chip is composed of multiple FPGAs and debugging, and to improve the speed of waveform generation by generating waveform files in parallel, and to ensure that the waveform viewing tool can perform unified waveform viewing after summarizing multiple independent waveform files, thereby improving the chip debugging performance.

[0072] Embodiment 3

[0073] Figure 4 1 is a flow chart of a waveform generation method provided according to Embodiment 3 of the present invention. The waveform generation method is used for waveform generation in a cascaded FPGA system; the cascaded FPGA system includes: at least two connected FPGAs. Figure 4 As shown, the method includes:

[0074] Step 410: Encapsulate the debug data by cascading each FPGA in the FPGA system to generate a debug data packet, and transmit the debug data packet to the waveform generator through a parallel transmission channel.

[0075] Optionally, the debug data is encapsulated by each FPGA in the cascaded FPGA system to generate a debug data packet, and the debug data packet is transmitted to the waveform generator through a parallel transmission channel, including: transmitting the debug data packet to the waveform generator in parallel through the high-speed transmission channel of each FPGA in the cascaded FPGA system; the high-speed transmission channel includes: PCIE channel, 10 Gigabit Network, and USB channel.

[0076] Step 420: Receive each debug data packet transmitted through the parallel transmission channel through a waveform generator, generate independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each debug data packet, generate an index file corresponding to the cascaded FPGA system according to each independent waveform file, and transmit the index file to the waveform viewing tool.

[0077] The index file is associated with the independent waveform files corresponding to each FPGA. Optionally, receiving each debugging data packet transmitted through the parallel transmission channel by the waveform generator includes: receiving each debugging data packet transmitted through the parallel high-speed transmission channel by the waveform generator.

[0078] Optionally, an index file corresponding to the cascaded FPGA system is generated based on each independent waveform file, including: filling the storage path of each independent waveform file into the index file; verifying the number of storage paths in the index file based on the number of FPGAs in the cascaded FPGA system; and generating the index file when the number of FPGAs is consistent with the number of storage paths.

[0079] Step 430: Use a waveform viewing tool to search for corresponding independent waveform files according to the index file, integrate the waveforms in the independent waveform files, and form a target waveform corresponding to the cascaded FPGA system; and display the target waveform.

[0080] Optionally, using a waveform viewing tool to search for corresponding independent waveform files according to an index file, integrating the waveforms in the independent waveform files to form a target waveform corresponding to the cascaded FPGA system; displaying the target waveform, including: using a waveform viewing tool to search for corresponding independent waveform files according to the storage paths of the independent waveform files in the index file; reading waveform data in the independent waveform files in parallel, and integrating the waveform data within the same time threshold to form a target waveform corresponding to the cascaded FPGA system; and displaying the target waveform.

[0081] The waveform generation method provided by the embodiment of the present invention encapsulates the debugging data through each FPGA in the cascaded FPGA system to generate a debugging data packet, and transmits the debugging data packet to the waveform generator through a parallel transmission channel; the waveform generator receives each debugging data packet transmitted through the parallel transmission channel, generates independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each debugging data packet, generates an index file corresponding to the cascaded FPGA system according to each independent waveform file, and transmits the index file to a waveform viewing tool; wherein the index file is associated with the independent waveform file corresponding to each FPGA; the waveform viewing tool searches for the corresponding independent waveform files according to the index file, integrates the waveforms in the independent waveform files, and forms a target waveform corresponding to the cascaded FPGA system; and displays the target waveform, thereby solving the problem of poor performance caused by a large amount of waveform generation data when the chip is composed of multiple FPGAs and debugging, and by generating waveform files in parallel, the speed of waveform generation is improved, and it is ensured that the waveform viewing tool can perform unified waveform viewing after summarizing multiple independent waveform files, thereby improving the chip debugging performance.

[0082] Embodiment 4

[0083] Figure 5 1 is a schematic diagram of a waveform generating device in a cascaded FPGA system according to a fourth embodiment of the present invention. The cascaded FPGA system includes: at least two connected FPGAs. Figure 5 As shown, the waveform generating device includes: a debugging data packet acquisition module 510, an independent waveform file generating module 520, an index file generating module 530 and an index file transmission module 540. Among them:

[0084] The debugging data packet acquisition module 510 is used to acquire the debugging data packets transmitted by each FPGA in the cascaded FPGA system through a parallel transmission channel;

[0085] An independent waveform file generating module 520, for generating independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each debugging data packet;

[0086] An index file generating module 530, for generating an index file corresponding to the cascaded FPGA system according to each independent waveform file, wherein the index file is associated with the independent waveform file corresponding to each FPGA;

[0087] The index file transmission module 540 is used to transmit the index file to the waveform viewing tool, so as to search for the corresponding independent waveform files according to the index file and view the target waveform corresponding to the cascaded FPGA system.

[0088] Optionally, the debugging data packet acquisition module 510 includes:

[0089] A debug data packet acquisition unit, used to acquire debug data packets transmitted by each FPGA in the cascaded FPGA system through a parallel high-speed transmission channel;

[0090] High-speed transmission channels include: PCIE channel, 10 Gigabit Ethernet, and USB channel.

[0091] Optionally, the index file generating module 530 includes:

[0092] A storage path filling unit is used to fill the storage path of each independent waveform file into the index file;

[0093] A quantity verification unit, used for verifying the number of storage paths in the index file according to the number of FPGAs in the cascaded FPGA system;

[0094] The index file generating unit is used to generate an index file when the number of FPGAs is consistent with the number of storage paths.

[0095] The waveform generating device in the cascaded FPGA system provided in the embodiment of the present invention can execute the waveform generating method in the cascaded FPGA system provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0096] Embodiment 5

[0097] Figure 6 A schematic diagram of a waveform generator 10 that can be used to implement an embodiment of the present invention is shown. The waveform generator is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The waveform generator can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0098] like Figure 6 As shown, the waveform generator 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the waveform generator 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0099] A number of components in the waveform generator 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the waveform generator 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0100] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as the waveform generation method in the cascaded FPGA system.

[0101] In some embodiments, the waveform generation method in the cascaded FPGA system can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the waveform generator 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the waveform generation method in the cascaded FPGA system described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the waveform generation method in the cascaded FPGA system in any other appropriate manner (for example, by means of firmware).

[0102] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0103] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0104] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0105] To provide interaction with a user, the systems and techniques described herein can be implemented on a waveform generator having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the waveform generator. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0106] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0107] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0108] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0109] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A waveform generation method in a cascaded FPGA system, characterized in that: The cascaded FPGA system includes: at least two connected FPGAs; the waveform generation method includes: Obtaining debug data packets transmitted by each FPGA in the cascaded FPGA system through a parallel transmission channel; Generate independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each of the debugging data packets; Generate an index file corresponding to the cascaded FPGA system according to each of the independent waveform files, wherein the index file is associated with the independent waveform files corresponding to each FPGA; The index file is transferred to a waveform viewing tool to search for the corresponding independent waveform files according to the index file, and view the target waveform corresponding to the cascaded FPGA system.

2. The method according to claim 1, characterized in that Obtaining debug data packets transmitted by each FPGA in the cascaded FPGA system through a parallel transmission channel, including: Acquire debug data packets transmitted by each FPGA in the cascaded FPGA system through a parallel high-speed transmission channel; The high-speed transmission channels include: PCIE channel, 10 Gigabit Ethernet, and USB channel.

3. The method according to claim 1, characterized in that Generating an index file corresponding to the cascaded FPGA system according to each of the independent waveform files, including: Fill the storage path of each independent waveform file into the index file; Verify the number of storage paths in the index file according to the number of FPGAs in the cascaded FPGA system; When the number of FPGAs is consistent with the number of storage paths, the index file is generated.

4. A waveform generation system, characterized in that: The waveform generation system is used for waveform generation of a cascaded FPGA system; The cascaded FPGA system includes: at least two connected FPGAs; the waveform generation system includes: each FPGA in the cascaded FPGA system, a waveform generator, and a waveform viewing tool; wherein: Each FPGA is used to encapsulate the debugging data, generate a debugging data packet, and transmit the debugging data packet to the waveform generator through a parallel transmission channel; The waveform generator is used to receive each of the debugging data packets transmitted through the parallel transmission channel, generate independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each of the debugging data packets, generate an index file corresponding to the cascaded FPGA system according to each of the independent waveform files, and transmit the index file to the waveform viewing tool; Wherein, the index file is associated with the independent waveform files corresponding to each FPGA; The waveform viewing tool is used to search for the corresponding independent waveform files according to the index file, integrate the waveforms in the independent waveform files to form a target waveform corresponding to the cascaded FPGA system; and display the target waveform.

5. The waveform generation system according to claim 4, characterized in that: The waveform viewing tool is specifically used for: According to the storage path of each of the independent waveform files in the index file, searching for the corresponding independent waveform files; Reading the waveform data in each of the independent waveform files in parallel, and integrating each of the waveform data within the same time threshold to form a target waveform corresponding to the cascaded FPGA system; The target waveform is displayed.

6. A waveform generation method, characterized in that: The waveform generation method is used for waveform generation of a cascaded FPGA system; The cascaded FPGA system includes: at least two connected FPGAs; the waveform generation method includes: Encapsulating the debugging data through each FPGA in the cascaded FPGA system to generate a debugging data packet, and transmitting the debugging data packet to the waveform generator through a parallel transmission channel; Receiving each of the debugging data packets transmitted through the parallel transmission channel through a waveform generator, generating independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each of the debugging data packets, generating an index file corresponding to the cascaded FPGA system according to each of the independent waveform files, and transmitting the index file to a waveform viewing tool; Wherein, the index file is associated with the independent waveform files corresponding to each FPGA; The waveform viewing tool searches for the corresponding independent waveform files according to the index file, integrates the waveforms in the independent waveform files, and forms a target waveform corresponding to the cascaded FPGA system; and displays the target waveform.

7. A waveform generating device in a cascaded FPGA system, characterized in that: The cascaded FPGA system includes: at least two connected FPGAs; the waveform generating device includes: A debugging data packet acquisition module, used to acquire debugging data packets transmitted by each FPGA in the cascaded FPGA system through a parallel transmission channel; An independent waveform file generation module, used for generating independent waveform files corresponding to each FPGA in the cascaded FPGA system in parallel according to each of the debugging data packets; An index file generating module, used to generate an index file corresponding to the cascaded FPGA system according to each of the independent waveform files, wherein the index file is associated with the independent waveform files corresponding to each FPGA; An index file transmission module is used to transmit the index file to a waveform viewing tool, so as to search for the corresponding independent waveform files according to the index file and view the target waveform corresponding to the cascaded FPGA system.

8. A waveform generator, characterized in that: The waveform generator comprises: at least one processor; and a memory in communication with the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the waveform generation method in the cascaded FPGA system according to any one of claims 1 to 3.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the waveform generation method in the cascaded FPGA system according to any one of claims 1 to 3 when executed.

10. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the waveform generation method in the cascaded FPGA system according to any one of claims 1 to 3.

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