Quantum circuit layout method and related device

Abstract

The invention discloses a quantum circuit layout method and a related device, and belongs to the technical field of quantum computing, and the method comprises the steps: obtaining an initial mapping relation between logic bits in a logic circuit and physical bits in quantum hardware; generating a target constraint relation based on the initial mapping relation and the logic line; the insertion position of the SWAP door in each target time step is determined through the target constraint relation, and the target time step is the time step which is determined based on the initial mapping relation and needs to be inserted with the SWAP door; and based on the logic circuit and the determined insertion position, obtaining a quantum circuit after layout. By applying the embodiment of the invention, the consumption of computing resources is reduced.

Description

Technical Field

[0001] The present application belongs to the field of quantum computing technology, and in particular to a quantum circuit layout method and related devices. Background Art

[0002] Quantum circuit layout aims to map logical quantum circuits onto actual physical quantum processors while ensuring that all two-bit gates (such as CNOT gates) are executed only on physically connected bits. Due to the physical limitations of the NISQ (Noisy Intermediate-Scale Quantum) processor, SWAP gates need to be frequently inserted between logical bits to meet the connectivity of the hardware. For example, when a CNOT gate in a logic circuit cannot be directly executed on a physical bit, it is usually necessary to use three CNOT gates to form a SWAP gate to exchange bit positions and then perform the original CNOT operation. This additional insertion significantly increases the depth and number of gates of the circuit, which not only increases the error probability, but also leads to longer execution time, thereby reducing the fidelity of the circuit and the robustness of the calculation. Therefore, reducing the number of SWAP gates becomes the key to quantum circuit layout.

[0003] The existing quantum circuit layout method first determines the initial mapping relationship, which is the starting point for subsequent iterative optimization. Based on the initial mapping relationship, the routing transfer function (routing_pass) is used to perform full routing operations on the quantum circuit, and the quantum logic gates are arranged according to the connection relationship of the physical bits to obtain a temporary layout. In this process, some SWAP gates will be inserted. The temporary layout obtained in the previous step is used as the initial layout, and the reverse quantum circuit is routed. That is, starting from the end of the quantum circuit, the quantum logic gates are laid out and routed in the opposite order, and the necessary SWAP gates are also inserted. Compare the results obtained by forward routing and reverse routing, and select a better layout as the new current layout according to certain evaluation criteria. If the new layout is better than the previous layout, the current layout is updated to the new layout; otherwise, the current layout remains unchanged. Using this layout method, full routing operations and evaluation of different layout schemes are required multiple times during the iteration process. The computational cost will increase exponentially with the increase in the number of quantum bits and quantum logic gates, and the risk of falling into the local optimum will also increase. In addition, the consumption of computing resources will increase sharply, resulting in a significant decline in performance on large-scale problems and poor scalability. Summary of the invention

[0004] The purpose of this application is to provide a quantum circuit layout method and related devices, aiming to reduce the consumption of computing resources.

[0005] An embodiment of the present application provides a quantum circuit layout method, the method comprising:

[0006] Obtaining the initial mapping relationship between the logical bits in the logic circuit and the physical bits in the quantum hardware;

[0007] Based on the initial mapping relationship and the logic circuit, a target constraint relationship is generated, wherein the target constraint relationship includes a first constraint relationship and a second constraint relationship, the first constraint relationship is a constraint to ensure that the two-bit gate is executable in the quantum hardware according to the time step in the logic circuit; the second constraint relationship is a constraint to insert at most one SWAP gate per time step;

[0008] Determine the insertion position of the SWAP gate in each target time step by using the target constraint relationship, wherein the target time step is the time step where the SWAP gate needs to be inserted determined based on the initial mapping relationship;

[0009] Based on the logic circuit and the determined insertion position, a laid-out quantum circuit is obtained.

[0010] Optionally, one target time step corresponds to one target constraint relationship;

[0011] The target constraint relationship of the first target time step is generated based on the initial mapping relationship and the logic circuit;

[0012] The target constraint relationships of the remaining target time steps are generated based on the updated mapping relationship of the previous target time step and the logic circuit.

[0013] Optionally, the first constraint relationship includes a connection constraint, a mapping update constraint, and a two-bit gate execution timing constraint, wherein:

[0014] The connection constraint is a constraint that ensures that the two-bit gate is executable on the physical bit;

[0015] The mapping constraint is to ensure that the current mapping relationship is updated after the SWAP gate is inserted;

[0016] The two-bit gate execution timing constraint is a constraint that ensures that the two-bit gate is executed according to the time step in the logic circuit.

[0017] Optionally, the connection constraint is generated using the logic circuit, the initial mapping relationship and the topological structure of the physical bits of the quantum hardware;

[0018] The two-bit gate execution timing constraint is determined based on the relationship between nodes in the directed acyclic graph of the logic circuit, wherein the nodes of the directed acyclic graph represent the two-bit gates and the edges represent the logic bits.

[0019] Optionally, the two-bit gate execution timing constraint is determined by utilizing a connection relationship between two-bit gates in three connected time steps in a directed acyclic graph.

[0020] Optionally, the method further includes:

[0021] determining whether there is a commutative two-bit gate pair in the logic circuit;

[0022] If so, swapping the positions of the target two-bit gates in the logic circuit, wherein the target two-bit gate pair is a two-bit gate pair whose two-bit gates at the later time step can act on the connected physical bits;

[0023] The generating a target constraint relationship based on the initial mapping relationship and the logic circuit includes:

[0024] Based on the initial mapping relationship and the commuted logic circuit, a target constraint relationship is generated.

[0025] Optionally, the target constraint relationship also includes a third constraint relationship for inserting a CNOT gate; the third constraint relationship is to minimize the difference between the first topological distance and the second topological distance, wherein the first topological distance is the topological distance of the two-bit gate in the current mapping relationship in the specified time step, the second topological distance is the topological distance of the two-bit gate in the specified time step under the new mapping relationship between the SWAP gate and the parallel CNOT gate, and the specified time step is the nearest neighbor time step after the current target time step;

[0026] Using the target constraint relationship, determining the insertion position of the SWAP door includes:

[0027] The target constraint relationship is used to determine the insertion position of the SWAP gate and the insertion position of the CNOT gate, wherein within a target time step, the number of CNOT gates acting on any physical bit does not exceed 3, and the inserted CNOT gate is parallel to the inserted SWAP gate.

[0028] Optionally, when there are still physical bits in the quantum hardware that are not included in the initial mapping relationship, the target constraint relationship also includes a fourth constraint relationship, and the fourth constraint relationship is that when the number of logical bit exchanges caused by inserting the SWAP gate is reduced by using auxiliary bits, at least one of the bits acted on by the SWAP gate is a physical bit in the initial mapping relationship, and the auxiliary bit is a physical bit in the quantum hardware that is not included in the initial mapping relationship.

[0029] Optionally, the determining the insertion position of the SWAP door by using the target constraint relationship includes:

[0030] Taking the insertion position of the SWAP gate as a variable, the target constraint relationship is input into the SAT solver to obtain a feasible solution;

[0031] Select a solution from the feasible solutions as the insertion location of the SWAP gate.

[0032] Another embodiment of the present application provides a quantum circuit layout device, the device comprising:

[0033] A first acquisition module is used to obtain an initial mapping relationship between logical bits in the logic circuit and physical bits in the quantum hardware;

[0034] A generation module is used to generate a target constraint relationship based on the initial mapping relationship and the logic circuit, wherein the target constraint relationship includes a first constraint relationship and a second constraint relationship, the first constraint relationship is a constraint to ensure that the two-bit gate is executable in the quantum hardware according to the time step in the logic circuit; the second constraint relationship is a constraint to insert at most one SWAP gate per time step;

[0035] A determination module, used to determine the insertion position of the SWAP gate in each target time step by using the target constraint relationship, wherein the target time step is the time step where the SWAP gate needs to be inserted determined based on the initial mapping relationship;

[0036] The second obtaining module is used to obtain the laid-out quantum circuit based on the logic circuit and the determined insertion position.

[0037] Another embodiment of the present application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the quantum circuit layout method in any of the above embodiments is implemented.

[0038] Another embodiment of the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a computer, the computer executes the quantum circuit layout method in any of the above-mentioned embodiments.

[0039] Compared with the prior art, the present application provides a quantum circuit layout method, first obtains an initial mapping relationship, then generates a target constraint relationship based on the initial mapping relationship and the logic circuit, and then uses the target constraint relationship to determine the insertion position of the SWAP gate in each target time step, and finally obtains the quantum circuit after layout based on the logic circuit and the determined insertion position. The present application determines the insertion position of the SWAP gate by generating a target constraint relationship. This method is relatively more targeted. It first clarifies the first constraint relationship (ensuring that the two-bit gate can be executed in the quantum hardware according to the time step in the logic circuit) and the second constraint relationship (inserting at most one SWAP gate per time step). These two constraint relationships limit the scope of the operation, so that when determining the insertion position of the SWAP gate, it is not necessary to perform a full routing operation, reducing the consumption of computing resources. In addition, since the computing cost is relatively low and the local optimal problem can be effectively avoided through the target constraint relationship, it has better scalability when facing large-scale quantum bits and quantum logic gates. It can gradually build the quantum circuit after layout according to the constraint relationship, and it will not be like the prior art because the consumption of computing resources rises sharply and the performance drops significantly. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A network block diagram of a quantum circuit layout system provided in an embodiment of the present application;

[0041] Figure 2 A flowchart of a quantum circuit layout method provided in an embodiment of the present application;

[0042] Figure 3 A structural diagram of a quantum circuit layout device provided in an embodiment of the present application;

[0043] Figure 4 A schematic diagram of the structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.

[0045] Figure 1 1 is a network block diagram of a quantum circuit layout system provided by an embodiment of the present application. The system may include a network 110, a server 120, a wireless device 130, a client 140, a storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memories, classical processors, quantum processors, and other devices not shown.

[0046] The network 110 is a medium for providing communication links between various devices and computers connected together in the quantum circuit layout system, including but not limited to the Internet, corporate intranet, local area network, mobile communication network and their combination. The connection method can be wired, wireless communication links or optical fiber cables.

[0047] The server 120, the wireless device 130 and the client 140 are conventional data processing systems, which may contain data and applications or software tools for performing conventional computing processes. The client 140 may be a personal computer or a network computer, so the data may also be provided by the server 120. The wireless device 130 may be a smart phone, a tablet, a laptop, a smart wearable device, etc. The storage unit 150 may include a database 151, which may be configured to store data such as quantum bit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc.

[0048] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application 163 (application 173). The application 163 (application 173) may be used to implement a quantum algorithm compiled according to the quantum circuit layout method provided in an embodiment of the present application.

[0049] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0050] It should be noted that the real quantum computing platform is a hybrid structure, which includes at least Figure 1 There are two major parts in it: the classical computing unit 160, which is responsible for performing classical computing and control; the quantum computing unit 170, which is responsible for running quantum programs and thus realizing quantum computing.

[0051] The classical computing unit 160 and the quantum computing unit 170 may be integrated into one device or distributed in two different devices. For example, the first device including the classical computing unit 160 runs a classical computer operating system, on which quantum application development tools and services are provided, as well as storage and network services required for quantum applications. Users develop quantum programs through the quantum application development tools and services thereon, and send quantum programs to the second device including the quantum computing unit 170 through the network services thereon. The second device runs a quantum computer operating system, and the code of the quantum program is parsed and compiled into instructions that can be recognized and executed by the quantum processor 170 through the quantum computer operating system. The quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0052] The computing unit of the classic processor 161 in the classic computing unit 160 is a CMOS tube based on a silicon chip. This computing unit is not limited by time and coherence, that is, this computing unit is not limited by the length of use and can be used at any time. In addition, in the silicon chip, the number of such computing units is also sufficient. At present, the number of computing units in a classic processor 161 is tens of thousands. The number of computing units is sufficient and the computing logic that can be selected by the CMOS tube is fixed, such as: AND logic. When calculating with the help of CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the calculation effect.

[0053] The basic computing unit of the quantum processor 171 in the quantum computing unit 170 is a quantum bit. The input of the quantum bit is limited by coherence and coherence time, that is, the quantum bit is limited by the duration of use and is not available at any time. Making full use of the quantum bit within the available duration of use of the quantum bit is a key problem in quantum computing. In addition, the number of quantum bits in a quantum computer is one of the representative indicators of the performance of the quantum computer. Each quantum bit realizes the computing function through the logical function configured on demand. In view of the limited number of quantum bits, the logical functions in the field of quantum computing are diverse, such as: Hadamard gate (Hadamard gate, H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. In quantum computing, it is necessary to use limited quantum bits combined with a variety of logical function combinations to achieve the computing effect.

[0054] Based on these differences, the design of CMOS tubes by classical logic functions and the design of quantum bits by quantum logic functions are significantly and essentially different. The design of CMOS tubes by classical logic functions does not need to consider the individuality of CMOS tubes. For example, the representation of CMOS tubes in silicon chips is the individual identification, position, and usable life of each CMOS tube. Therefore, the classical algorithm composed of classical logic functions only expresses the operational relationship of the algorithm, but does not express the algorithm's dependence on individual CMOS tubes.

[0055] When quantum logic functions act on qubits, the individuality of qubits needs to be considered, such as the individual identification of the qubit in the quantum chip, its position, its relationship with surrounding qubits, and the usable time of each qubit. Therefore, the quantum algorithm composed of quantum logic functions not only expresses the computational relationship of the algorithm, but also expresses the algorithm's dependence on individual qubits.

[0056] Quantum chips can include quantum bits and channels for regulating quantum bits. Quantum logic gates are implemented through analog signals. Different combinations of analog signals are applied to quantum bits through channels for regulating quantum bits, thereby realizing quantum circuits with different functions and completing data processing. Therefore, the design of quantum logic functions acting on quantum bits (including the design of whether quantum bits are used or not and the design of the efficiency of each quantum bit) is the key to improving the computing performance of quantum computers, and special designs are required. This is also the uniqueness of quantum algorithms based on quantum logic functions, which is essentially and significantly different from classical algorithms based on classical logic functions. The above-mentioned design for quantum bits is a technical issue that ordinary computing devices do not need to consider or face.

[0057] See also Figure 2 , Figure 2 A quantum circuit layout method provided in an embodiment of the present application comprises the following steps:

[0058] S201: Obtaining an initial mapping relationship between logical bits in a logic circuit and physical bits in quantum hardware.

[0059] Obtaining the initial mapping relationship is the basis for the subsequent determination of the insertion of the SWAP gate. The initial mapping relationship can be randomly generated, or it can be generated by an algorithm based on the structure of the logic circuit and the topological relationship of the physical bits in the quantum hardware. Of course, there are other ways to obtain the initial mapping relationship. Regardless of the mapping method, it is necessary to ensure that each logical bit can be mapped to a physical bit, and each physical bit is occupied by at most one logical bit, that is, the logical bit corresponds to the physical bit one by one, there is no unmapped logical bit, and there is no one-to-many or many-to-one mapping.

[0060] It should be noted that a logic circuit is a quantum circuit in which the bits in the circuit are logic bits. The logic circuit can be called a quantum logic circuit.

[0061] S202: Generate a target constraint relationship based on the initial mapping relationship and the logic circuit, wherein the target constraint relationship includes a first constraint relationship and a second constraint relationship, the first constraint relationship is a constraint to ensure that the two-bit gate can be executed in the quantum hardware according to the time step in the logic circuit; the second constraint relationship is a constraint to insert at most one SWAP gate per time step.

[0062] The first constraint relationship is to ensure that the logic circuit can be correctly executed on the quantum hardware. To generate the first constraint relationship, it is necessary to analyze the time step execution characteristics of the two-bit gate in the logic circuit. First, it is necessary to clarify the time step sequence of each two-bit gate in the logic circuit and related preconditions. For example, some two-bit gates may depend on the results of other previous quantum logic gate operations, and there are requirements for the order of execution. Combined with the execution rules of quantum hardware, the first constraint relationship is determined. Different quantum hardware has its own specific physical implementation and operation restrictions. For example, some quantum hardware has restrictions on the number of two-bit gates that can be executed concurrently, or has requirements for the interval time between specific two-bit gates. Understand these physical constraints of quantum hardware on the operation of two-bit gates, and correspond them to the time step arrangement of two-bit gates in the logic circuit.

[0063] The time step can also be called the execution sequence, which is a discretized representation of the order and time sequence of quantum operations. The quantum circuit can be regarded as a sequence of quantum logic gate operations in order. Each time step represents a stage in which one or more quantum logic gate operations can be performed. For example, in a simple quantum circuit, the first time step may be to apply a single-bit gate (such as Pauli-X gate) operation to a quantum bit, and the second time step may be to apply a two-bit gate (such as CNOT gate) operation to two quantum bits. From the perspective of physical implementation, it is somewhat similar to the concept of classical computer instruction cycle. When quantum hardware performs quantum computing tasks, these time steps also roughly correspond to the order in which operations are executed. However, due to the characteristics of quantum physics, such as superposition and entanglement of quantum states, the order of quantum gate operations (i.e., the order of time steps) often has an important impact on the final result. Therefore, the first constraint relationship can limit the constraints related to the time step.

[0064] The second constraint relationship constrains the number of inserted SWAP gates. In the implementation of the present application, if the two-bit gates in a time step all act on directly connected physical bits, then no SWAP gate needs to be inserted in this time step. The constraint of inserting at most one SWAP gate per time step is to avoid over-complicating the circuit and maintain the executability of the circuit. Specifically, only one SWAP gate can be inserted per target time step. For this reason, one-hot encoding is used to ensure that only one SWAP gate is inserted in each target time step.

[0065] S203: Determine the insertion position of the SWAP gate in each target time step by using the target constraint relationship, wherein the target time step is the time step where the SWAP gate needs to be inserted determined based on the initial mapping relationship.

[0066] In the present application, the first target time step can be determined first. Specifically, the time step at which the SWAP gate needs to be inserted first can be determined based on the given initial mapping relationship by analyzing the layout of the logic bits in the logic circuit, the order of quantum logic gate operations, and the relevant characteristics of the quantum hardware. After determining the first target time step, the SWAP gate insertion position can be determined according to the first constraint relationship to ensure that the two-bit gate is executable in the quantum hardware according to the time step of the logic circuit. When determining the insertion position of the SWAP gate, it is necessary to ensure that the executable requirements of the two-bit gate will not be violated after the SWAP gate is inserted. For example, some two-bit gates may rely on the adjacent relationship of specific logic bits or existing quantum states to execute correctly. After inserting the SWAP gate to change the order of quantum bits, the subsequent two-bit gates cannot be implemented as planned. For each target time step, since it is limited to inserting at most one SWAP gate per time step, it is necessary to screen among all possible insertion positions of the time step. Specifically, the current arrangement of the physical bits of the time step and the requirements of the subsequent quantum logic gates to be executed for the physical bit connection relationship are analyzed. For example, if in a time step, there are multiple physical bit groups that need to perform two-bit gate operations later, and the current positions of some physical bits are not conducive to the execution of these two-bit gates (for example, the distance is too far, etc., which does not comply with the hardware connection or operation rules), but only one place can be selected to insert the SWAP gate to optimize the relative position of the quantum bits. It is necessary to comprehensively weigh which insertion can best meet the subsequent two-bit gate operation requirements and comply with the overall computing logic.

[0067] In addition to satisfying the target constraint relationship, we must also start from the overall perspective of the quantum circuit. Inserting a SWAP gate should not only solve the local physical bit layout problem faced by the current target time step, but also try to make the quantum logic gate operation of the subsequent time step smoother, reducing the need for additional SWAP gate insertion, so as to achieve the purpose of optimizing the quantum circuit and reducing computing resource consumption (such as the number of gate operations, computing time, etc.). For example, in a multi-qubit quantum circuit, after analyzing the target time step, it is found that in a certain target time step, there are three possible positions where the SWAP gate can be inserted in theory, which can improve the connection relationship of the current physical bit to facilitate the subsequent two-bit gate operation. However, combined with the operation plan of the subsequent time steps and the overall optimization considerations, after selecting one of the positions to insert the SWAP gate, it can make it unnecessary to frequently insert the SWAP gate to adjust the quantum bit layout in the subsequent multiple time steps, so it is determined to insert the SWAP gate at this position.

[0068] It should be noted that the target time step is determined in sequence according to the order of the time steps. The first time step is determined first to determine the insertion position of the SWAP gate, and then the next target time step is determined, and the step of determining the insertion position of the SWAP gate is executed until the last time step determines the position of inserting the SWAP gate.

[0069] S204: Based on the logic circuit and the determined insertion position, a laid-out quantum circuit is obtained.

[0070] According to the insertion position of the SWAP gate in each target time step determined before, insert the SWAP gate at the corresponding time step and the corresponding physical bit position. For example, if it is determined that the SWAP gate is inserted between the second and third physical bits in the third time step, according to this requirement, in the logical structure of the quantum circuit, the SWAP gate is accurately placed in the operation sequence corresponding to the time step, and the order of the two physical bits is changed to achieve the exchange of the physical bit positions. After inserting the SWAP gate, check from beginning to end whether the operation sequence of all quantum logic gates in the entire quantum circuit still meets the logical and physical implementation requirements. Ensure that the insertion of the SWAP gate does not destroy the execution order of the quantum logic gates specified in the original logic circuit, and does not violate the executable constraints of the quantum hardware for operations such as the two-bit gate, for example, there is no situation where the originally executable two-bit gate cannot be executed due to the quantum bit exchange because the distance between the quantum bits does not meet the hardware connection requirements. When all the SWAP gates are inserted according to the corresponding positions, the laid-out quantum circuit can be obtained.

[0071] In addition to meeting the basic requirements for inserting SWAP gates, the layout of quantum circuits can be further optimized as a whole. For example, since the function of the SWAP gate is composed of three CNOT gates, it can be determined whether there are situations where CNOT gates can be merged or simplified, or certain quantum logic gate operations can be rearranged according to the characteristics of quantum hardware to reduce the total number of gate operations or shorten the calculation time. Through these optimization measures, the resulting quantum circuit is more efficient, concise and meets the conditions for physical realization.

[0072] After the insertion, adjustment and optimization operations in the above steps, the final quantum circuit with inserted SWAP gates and reasonable layout that meets the requirements is the laid-out quantum circuit. It is recorded in a suitable form (such as circuit diagram form, operation sequence list form, etc.) for subsequent actual execution on quantum hardware or further analysis and research.

[0073] In the present application, the initial mapping relationship is first obtained, and then based on the initial mapping relationship and the logic circuit, the target constraint relationship is generated, and then the insertion position of the SWAP gate in each target time step is determined by using the target constraint relationship, and finally the quantum circuit after layout is obtained based on the logic circuit and the determined insertion position. The present application determines the insertion position of the SWAP gate by generating a target constraint relationship. This method is relatively more targeted. It first clarifies the first constraint relationship (ensuring that the two-bit gate can be executed in the quantum hardware according to the time step in the logic circuit) and the second constraint relationship (inserting at most one SWAP gate per time step). These two constraint relationships limit the scope of the operation, so that when determining the insertion position of the SWAP gate, it is not necessary to perform a full routing operation, reducing the consumption of computing resources. In addition, since the computing cost is relatively low and the local optimal problem can be effectively avoided through the target constraint relationship, it has better scalability when facing the situation of large-scale quantum bits and quantum logic gates. It can gradually build the quantum circuit after layout according to the constraint relationship, and it will not be like the prior art because the consumption of computing resources rises sharply and the performance drops significantly.

[0074] In some embodiments of the present application, the insertion position of the SWAP door may be determined in the following manner:

[0075] Taking the insertion position of the SWAP gate as a variable, the target constraint relationship is input into the SAT solver to obtain a feasible solution;

[0076] In an embodiment of the present application, the insertion position of the SWAP gate is used as a variable, and the target constraint relationship (including the connection constraint, mapping update constraint, two-bit gate execution timing constraint and second constraint relationship in the first constraint relationship) is converted into a corresponding Boolean logic expression according to the logic rules. The converted set of Boolean logic expressions (i.e., the overall logic expression representing the target constraint relationship) is input into the SAT (Boolean Satisfiability Problem) solver. The solver will use its internal algorithms, such as algorithms based on backtracking search, conflict-driven clause learning and other technologies, to try different assignment combinations for variables, and determine whether there is an assignment method that can make the value of the logical expression composed of the entire target constraint relationship true, that is, find a situation that satisfies all constraints. If there is such a feasible solution, the solver will output the corresponding variable assignment result.

[0077] Typically, a SAT solver may find multiple feasible solutions. This is because there may be multiple different arrangements for the insertion position of the SWAP gate that can satisfy the various conditions set by the target constraint relationship. For example, different SWAP gate insertion combinations can ensure that the two-bit gate is executable on the physical bit, meet the two-bit gate execution timing, and meet the requirements of inserting at most one SWAP gate per time step. When faced with multiple feasible solutions, one can be randomly selected, or one of the solutions can be selected as the final SWAP gate insertion position based on some additional criteria. These criteria can include line optimization objectives, the impact on subsequent time steps or computing resource consumption, etc., or a combination of these criteria.

[0078] Based on the circuit optimization goal, we can choose the solution that minimizes the number of gate operations in the quantum circuit. Inserting a SWAP gate may add additional operations. If a feasible solution can minimize the total number of gate operations while satisfying the constraints, it is more beneficial to improve computational efficiency, so we can choose such a solution.

[0079] Based on the impact on subsequent time steps, solutions that make the operations of subsequent time steps smoother and easier to execute can be selected. For example, the selected SWAP gate insertion position will not lead to the frequent need to insert more SWAP gates to adjust the quantum bit layout, or make the execution conditions of subsequent two-bit gate operations more relaxed and more in line with the physical characteristics of quantum hardware. Such solutions will be more suitable.

[0080] Based on the consumption of computing resources, solutions that can reduce the consumption of quantum bit control resources, computing time, etc. can be selected. If a feasible solution has lower hardware control complexity after inserting the SWAP gate, does not require complex pulse sequence regulation, or can reduce computing time, then this solution can be given priority as the final SWAP gate insertion position. It should be noted that the above-mentioned method of selecting solutions under different standards only explains what kind of solutions can be selected. Specific evaluation rules can be set for the specific selection of solutions to determine the quality of each solution under the current standard, so as to select the optimal solution.

[0081] Through the above steps, the SAT solver is used to find feasible solutions based on the target constraint relationship, and the appropriate solution is selected to determine the insertion position of the SWAP gate, thereby completing the layout optimization of the quantum circuit under various constraints.

[0082] In some embodiments of the present application, one target time step corresponds to one target constraint relationship;

[0083] The target constraint relationship of the first target time step is generated based on the initial mapping relationship and the logic circuit;

[0084] The target constraint relationships of the remaining target time steps are generated based on the updated mapping relationship of the previous target time step and the logic circuit.

[0085] When dealing with quantum circuit-related problems, a series of time steps that need to be focused on are determined, namely target time steps. Each target time step has a corresponding target constraint relationship, which is used to regulate the operations that can be performed and the conditions that must be met within the time step, thereby ensuring that the layout, optimization and execution of the entire quantum circuit meet the expected requirements and adapt to the characteristics of quantum hardware.

[0086] By combining the initial mapping relationship with the logic circuit, we can get the constraints that need to be met in the first target time step to ensure that the subsequent quantum logic to gate operations can be executed smoothly as planned. For example, to ensure that certain two-bit gates can be correctly executed on the corresponding physical bit pairs, it may be necessary to set constraints on the connectivity and operability of the physical bits. These constraints together constitute the target constraint relationship for the first target time step. This relationship is designed to ensure that the requirements of quantum hardware and logic calculations can be followed from the very beginning, laying the foundation for subsequent operations.

[0087] After the relevant operations (such as inserting SWAP gates to adjust the bit layout) are performed in the first target time step, the mapping relationship between the logical bits and the physical bits will change, that is, the updated mapping relationship. For each subsequent target time step, the updated mapping relationship obtained after the end of the immediately previous target time step is used as the basis. Because the operation of the previous time step will change the relative position and operability of the physical bits, the new mapping relationship reflects the current quantum bit state correspondence that is more in line with the actual situation.

[0088] The logic circuit itself is relatively fixed, and it specifies the operational process framework of the entire quantum computing task. Therefore, when considering the target constraint relationship of the remaining target time steps, it is still necessary to analyze it in conjunction with the logic circuit. Based on the updated mapping relationship and logic circuit, it is clear what new constraints need to be set in the current target time step, for example, in order to enable subsequent two-bit gate operations to proceed normally and meet the restrictions of quantum hardware on the order of quantum logic gate operations and quantum bit layout. In this way, the target constraint relationship corresponding to each remaining target time step is generated in turn, and the execution process of the entire quantum circuit is continuously adjusted and optimized so that it can be better implemented on quantum hardware. This method of gradually generating target constraint relationships can dynamically adapt to the changes of quantum circuits at different stages, ensuring that the entire quantum computing process can be carried out effectively and accurately.

[0089] In some embodiments of the present application, the first constraint relationship includes a connection constraint, a mapping update constraint, and a two-bit gate execution timing constraint, wherein:

[0090] The connection constraint is a constraint that ensures that the two-bit gate is executable on the physical bit;

[0091] The mapping constraint is to ensure that the current mapping relationship is updated after the SWAP gate is inserted;

[0092] The two-bit gate execution timing constraint is a constraint that ensures that the two-bit gate is executed according to the time step in the logic circuit.

[0093] In quantum computing, quantum circuits are ultimately executed on quantum hardware with a specific physical architecture. Quantum hardware is composed of multiple physical bits, and these physical bits have specific connections. The connection constraint is to ensure that the two-bit gate can be successfully executed on the corresponding physical bit. It takes into account the actual connectivity between the physical bits of quantum hardware. Specifically, it is generated using the logical circuit, the initial mapping relationship, and the topological structure of the physical bits of the quantum hardware. The specific operation of generating the connection constraint can be to first extract all the two-bit gate operations that need to be executed and the corresponding logical quantum bit pairs from the logical circuit. Then, based on the initial mapping relationship, determine the physical bit pairs corresponding to these logical quantum bit pairs. Then, according to the topological structure of the physical bits of the quantum hardware, determine whether there is a direct connection between these physical bit pairs. If there are physical bit pairs that are not directly connected, determine whether these physical bit pairs can be connected through other physical bits, so that these two-bit gates can eventually be executed on physical bit pairs that meet the requirements of the physical bit topological structure. Based on this logic, the connection constraint is to constrain the SWAP gate to be inserted only on the physical bit pairs that have a connection relationship. The connection relationship can be directly connected or indirectly connected.

[0094] When inserting SWAP gates and other operations in the quantum circuit to adjust the layout of physical bits, the mapping relationship between logical bits and physical bits will change. The mapping update constraint is to ensure that the current mapping relationship can be accurately and reasonably updated after the SWAP gate is inserted. For example, the original logical bit A in the logic circuit corresponds to physical bit 1, and the logical bit B corresponds to physical bit 2. When the SWAP gate is inserted to swap their positions, the mapping relationship needs to be updated accordingly so that subsequent operations can be performed correctly based on the new mapping situation. For example, taking a logic circuit containing 4 logical bits as an example, the initial mapping relationship is that logical bit 1 corresponds to physical bit a, logical bit 2 corresponds to physical bit b, logical bit 3 corresponds to physical bit c, and logical bit 4 corresponds to physical bit d. If a SWAP gate is inserted at a certain target time step and the positions of logical bits 2 and 3 are swapped, then according to the mapping update constraint, the mapping relationship must be updated in time to logical bit 1 corresponding to physical bit a, logical bit 2 corresponding to physical bit c, logical bit 3 corresponding to physical bit b, and logical bit 4 corresponding to physical bit d, so that subsequent operations such as dual-bit gates can be accurately performed based on the new mapping. The mapping update constraint ensures that the tracking of the corresponding relationship of quantum bits is always accurate throughout the quantum computing process, and there will be no confusion due to intermediate operation adjustments, thus providing a correct basis for subsequent various quantum gate operations and further circuit optimization.

[0095] The logic circuit specifies the order of operations of each quantum logic gate in the entire quantum computing task. The timing constraint of the two-bit gate execution is to ensure that the two-bit gate is executed strictly according to the time step set in the logic circuit. The results of quantum computing are often very sensitive to the operation order of quantum logic gates, and different orders may lead to completely different results. Therefore, it is crucial to ensure that the two-bit gate is executed at the correct time step, which maintains the coherence and correctness of the entire computing logic. For example, in the logic circuit of a quantum algorithm, it is stipulated that a specific two-bit gate is executed at a certain time step, the entangled state of the two quantum bits is adjusted, and then other subsequent quantum gate operations are executed. If the two-bit gate is not executed according to this timing, the subsequent quantum state evolution may not meet the expectations of the algorithm, which will ultimately affect the calculation results.

[0096] In some embodiments of the present application, the execution timing constraint of the two-bit gate may be determined based on the relationship between nodes in a directed acyclic graph of the logic circuit, wherein the nodes of the directed acyclic graph represent the two-bit gates and the edges represent the logic bits.

[0097] The logic circuit can be intuitively represented by a data structure called a directed acyclic graph. In this directed acyclic graph, each node represents a two-bit gate, because the two-bit gate is the key element in the logic circuit to perform specific operations and affect the change of quantum state. The edges in the graph represent logical bits, and the edges connect different nodes, which means that different two-bit gate operations are logically associated through logical bits, reflecting the flow and interaction of quantum bits between different two-bit gate operations.

[0098] In order to more comprehensively and accurately determine the execution timing constraints of the two-bit gates, some graph traversal analysis methods can be used, such as depth-first traversal. By performing a depth-first traversal on the directed acyclic graph corresponding to the logic circuit, each node (i.e., two-bit gate) can be visited in sequence, a complete execution path can be sorted out, and the execution sequence of each two-bit gate relative to other two-bit gates can be clearly determined. During the traversal process, the sequence information is recorded each time a node is visited, so that the strict execution sequence of all two-bit gates can be sorted out, ensuring that the two-bit gates in the entire logic circuit act on the quantum bits in the correct order to achieve the expected quantum computing function.

[0099] In short, with the help of the relationship between nodes in the directed acyclic graph corresponding to the logic circuit, the execution timing constraints of the two-bit gate can be accurately determined to ensure that the quantum circuit operates in a reasonable and correct order, thereby improving the accuracy and effectiveness of quantum computing.

[0100] In some implementations of the present application, the two-bit gate execution timing constraint may be determined by utilizing the connection relationship between the two-bit gates in three connected time steps in a directed acyclic graph.

[0101] Because one target time step corresponds to one target constraint relationship, the three connected time steps are the target time step of the target constraint relationship to be generated, the time step immediately before the target time step, and the time step after the target time step.

[0102] The focus is on the three connected time steps because such a range can fully reflect the key relationship between the two-bit gate operations in the process of connection, while not being too complicated to be sorted out. Through the connection relationship between the two-bit gates in these three time steps, it can be clear how the quantum state gradually evolves in the continuous operation, and the impact of the execution order of each two-bit gate on the subsequent results.

[0103] Consider the connection between the two-bit gate in the previous time step (for example, the t-1th time step) and the two-bit gate in the current time step (the tth time step). If in the directed acyclic graph, the output qubit of a two-bit gate in the previous time step is connected to the input qubit of a two-bit gate in the current time step through an edge, it means that the two-bit gate in the previous time step must be executed first, and its operation result can be used as input for the two-bit gate in the current time step. If the output qubit of the two-bit gate in the current time step is connected to the input qubit of the two-bit gate in the subsequent time step, this means that these two-bit gates in the current time step must be executed first to ensure that the two-bit gates in the subsequent time step have the correct input and are then executed as planned, thereby constraining the execution order of the two-bit gates and ensuring that the logic circuit proceeds in the correct sequence.

[0104] In addition to the above-mentioned influences between two time steps, the overall interaction between the three connected time steps must also be considered. Sometimes, the two-bit gate in the previous time step not only directly affects the two-bit gate in the current time step, but may also indirectly affect the two-bit gate in the subsequent time step through the change of the quantum state by the two-bit gate in the current time step. Based on the connection relationship between the two-bit gates in the three connected time steps in the directed acyclic graph, the dependency constraints between the time steps are ensured to be met by bidirectionally propagating the two-bit gate dependency. The timing constraints of the two-bit gate execution can be systematically and accurately determined, so that the two-bit gate operations in the quantum circuit are strictly executed in a reasonable order, thereby ensuring that the quantum computing task can be carried out smoothly according to the expectations of the logical circuit design.

[0105] In some implementations of the present application, before generating the target constraint, the logic circuit may be optimized. The specific optimization method may be:

[0106] determining whether there is a commutative two-bit gate pair in the logic circuit;

[0107] If so, the positions of the target di-bit gates in the logic circuit are swapped, wherein the target di-bit gate pair is a di-bit gate pair whose di-bit gate at the later time step can act on the connected physical bits.

[0108] To determine whether there are commutative two-bit gate pairs in the logic circuit, it is necessary to determine the type of each two-bit gate and the logical bit they act on. Different types of two-bit gates have different mathematical representations and different ways of acting on quantum states, which can be judged by the algebraic operation rules of two-bit gates and the relevant theories of quantum state transformation. For example, common two-bit gates include CNOT gates and SWAP gates. According to their matrix representations and the evolution laws of quantum states, it is examined whether the two two-bit gates satisfy the commutative relationship. All two-bit gates in the logic circuit can be checked in pairs, and their commutators (a mathematical expression used to measure the commutative relationship) can be calculated. If the commutator is a zero operator, it means that the two two-bit gates are commutative.

[0109] The target two-bit gate pair selected here has specific requirements, that is, the two-bit gate with a later time step can act on the two-bit gate pair on the connected physical bits. This means that not only the basic condition of commutativity must be met, but also factors at the physical implementation level must be considered. In quantum hardware, there is a specific connection relationship (topological structure) between physical bits. If the two-bit gate with a later time step can directly act on the connected physical bits, then exchanging the positions of the two two-bit gates is physically feasible and will not be inoperable due to the connection restrictions of the physical bits.

[0110] Once the qualified target two-bit gate pairs are determined, their positions in the logic circuit can be commuted. The advantage of this is that by reasonably adjusting the order of the two-bit gates, the effects of some two-bit gates may be offset, so that the corresponding two-bit gates can be deleted from the logic circuit, which may optimize the execution efficiency of the quantum circuit. For example, the number of SWAP gates that need to be inserted later may be reduced, because after changing the order of the two-bit gates, the situation where the quantum bit position needs to be adjusted through the SWAP gate to meet the two-bit gate operation has been improved, so that the quantum circuit can meet the computing function while being more adapted to the physical characteristics of the quantum hardware, reducing unnecessary operations, shortening the computing time or reducing resource consumption, etc. By determining the two-bit gate pairs that can be commuted as described above and commuting the positions of the qualified target two-bit gate pairs, the logic circuit can be effectively optimized and the performance and effect of quantum computing related processes can be improved.

[0111] After the logic circuit is optimized, the target constraint relationship can be generated based on the initial mapping relationship and the commuted logic circuit. There are many ways to optimize the logic circuit, commutation is one of them, and some quantum logic gates in the logic circuit can also be synthesized, or optimized using a machine learning model.

[0112] In some embodiments of the present application, the target constraint relationship may also include a third constraint relationship for inserting a CNOT gate; the third constraint relationship is to minimize the difference between the first topological distance and the second topological distance, wherein the first topological distance is the topological distance of the two-bit gate in the current mapping relationship in the specified time step, and the second topological distance is the topological distance of the two-bit gate in the specified time step under the new mapping relationship of the SWAP gate and the parallel CNOT gate, and the specified time step is the adjacent time step after the current target time step.

[0113] In the embodiment of the present application, a parallel plan is used to allow multiple non-conflicting CNOT gates and one SWAP gate to be executed in the same time step, minimizing the number of operations in each time step and significantly reducing the total number of time steps. Inserting a CNOT gate needs to satisfy certain constraints, which is the third constraint relationship. The third constraint relationship constrains the change in the topological distance of the two-bit gate in the specified time step mainly to reduce the impact on the specified time step. If the current target time step is the tth time step, the specified time step is the t+1th time step.

[0114] When the target constraint relationship includes the third constraint relationship, in addition to determining the position where the SWAP is inserted, it is also necessary to determine the insertion position of the CNOT gate. Specifically, the target constraint relationship can be used to determine the insertion position of the SWAP gate and the insertion position of the CNOT gate, wherein, within a target time step, the number of CNOT gates acting on any physical bit does not exceed 3, and the inserted CNOT gate is parallel to the inserted SWAP gate.

[0115] There are requirements for the number and position of the inserted CNOT gates. A SWAP gate can be equivalent to a combination of three CNOT gates. In the implementation of the present application, at most one SWAP gate is inserted in one time step, so the number of CNOT gates inserted in the target time step cannot be too many. For a target time step, the sum of the number of CNOT gates inserted and the number of CNOT gates that originally existed and acted on the same physical bit does not exceed 3. Assuming that at the tth time step, there was originally one CNOT gate acting on the physical bit E, at most two CNOT gates can be inserted on the physical bit E. In order not to increase additional time steps, the inserted CNOT gate needs to be parallel to the inserted SWAP gate.

[0116] In some embodiments of the present application, when there are physical bits in the quantum hardware that are not included in the initial mapping relationship, the target constraint relationship also includes a fourth constraint relationship, and the fourth constraint relationship is to reduce the number of logical bit exchanges caused by inserting a SWAP gate by using auxiliary bits, at least one of the bits acted on by the SWAP gate is a physical bit in the initial mapping relationship, and the auxiliary bit is a physical bit in the quantum hardware that is not included in the initial mapping relationship.

[0117] In order to optimize SWAP insertion, auxiliary bits (Ancillary Qubits) are allowed to be used. These auxiliary bits do not carry logical information and are only used for SWAP operations, thereby reducing unnecessary exchanges between physical bits. For example, according to the current mapping relationship, the logical bits acted on by the two-bit gate are mapped to P1 and P4, but P1 and P4 are not directly connected, P1 and P5 are connected, P5 and P4 are connected, and P5 is not included in the initial mapping relationship. P5 can be used as an auxiliary bit, and a SWAP gate is first inserted on P4 and P5, and then a two-bit gate is applied to P5 and P1, or a SWAP gate is first inserted on P1 and P5, and then a two-bit gate is applied to P5 and P4. Compared with exchanging P1 and P2, P4 and P3, and then applying a two-bit gate to P2 and P3, the number of exchanges between physical bits is reduced, and after two exchanges, the constraint of inserting a SWAP gate at each time step is not satisfied.

[0118] See also Figure 3 , Figure 3 A quantum circuit layout device provided in an embodiment of the present application may include:

[0119] A first obtaining module 301 is used to obtain an initial mapping relationship between logical bits in a logic circuit and physical bits in quantum hardware;

[0120] A generating module 302 is used to generate a target constraint relationship based on the initial mapping relationship and the logic circuit, wherein the target constraint relationship includes a first constraint relationship and a second constraint relationship, the first constraint relationship is a constraint to ensure that the two-bit gate is executable in the quantum hardware according to the time step in the logic circuit; the second constraint relationship is a constraint to insert at most one SWAP gate per time step;

[0121] A determination module 303 is used to determine the insertion position of the SWAP gate in each target time step by using the target constraint relationship, wherein the target time step is the time step where the SWAP gate needs to be inserted determined based on the initial mapping relationship;

[0122] The second obtaining module 304 is used to obtain the laid-out quantum circuit based on the logic circuit and the determined insertion position.

[0123] The specific functions and effects achieved by the above-mentioned quantum circuit layout device can be explained with reference to other embodiments of the present application, and will not be repeated here. Each module in the quantum circuit layout device can be implemented in whole or in part by software, hardware, and a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0124] See also Figure 4 The present application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the quantum circuit layout method in any of the above embodiments when executing the computer program. Figure 4 , the computer device may be a classical computer. The computer device may also be a quantum computer.

[0125] The embodiments of the present application also provide a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a computer, the computer executes the quantum circuit layout method in any of the above embodiments.

[0126] The embodiments of the present application also provide a computer program product comprising instructions, which, when executed by a computer, enables the computer to execute the quantum circuit layout method in any of the above embodiments.

[0127] It can be understood that in the various implementations of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of the present application.

[0128] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0129] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms of "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0130] It can be understood that the processor of the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method implementation can be completed by the hardware integrated logic circuit or software instructions in the processor. The above processor can be a general processor, a digital signal processor (DigitalSignal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiment of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor are combined and executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0131] It is understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory may be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0132] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0133] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method implementation methods and will not be repeated here.

[0134] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device implementation described above is only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0135] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0136] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0137] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0138] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A quantum circuit layout method, characterized in that: The method comprises: Obtaining the initial mapping relationship between the logical bits in the logic circuit and the physical bits in the quantum hardware; Based on the initial mapping relationship and the logic circuit, a target constraint relationship is generated, wherein the target constraint relationship includes a first constraint relationship and a second constraint relationship, the first constraint relationship is a constraint to ensure that the two-bit gate is executable in the quantum hardware according to the time step in the logic circuit; the second constraint relationship is a constraint to insert at most one SWAP gate per time step; Determine the insertion position of the SWAP gate in each target time step by using the target constraint relationship, wherein the target time step is the time step where the SWAP gate needs to be inserted determined based on the initial mapping relationship; Based on the logic circuit and the determined insertion position, a laid-out quantum circuit is obtained.

2. The method according to claim 1, characterized in that One target time step corresponds to one target constraint relationship; The target constraint relationship of the first target time step is generated based on the initial mapping relationship and the logic circuit; The target constraint relationships of the remaining target time steps are generated based on the updated mapping relationship of the previous target time step and the logic circuit.

3. The method according to claim 2, characterized in that The first constraint relationship includes connection constraints, mapping update constraints and dual-bit gate execution timing constraints, wherein: The connection constraint is a constraint that ensures that the two-bit gate is executable on the physical bit; The mapping constraint is to ensure that the current mapping relationship is updated after the SWAP gate is inserted; The two-bit gate execution timing constraint is a constraint that ensures that the two-bit gate is executed according to the time step in the logic circuit.

4. The method according to claim 3, characterized in that The connection constraint is generated by using the logic circuit, the initial mapping relationship and the topological structure of the physical bits of the quantum hardware; The two-bit gate execution timing constraint is determined based on the relationship between nodes in the directed acyclic graph of the logic circuit, wherein the nodes of the directed acyclic graph represent the two-bit gates and the edges represent the logic bits.

5. The method according to claim 4, characterized in that The two-bit gate execution timing constraint is determined by utilizing the connection relationship between the two-bit gates in three connected time steps in the directed acyclic graph.

6. The method according to claim 1, characterized in that The method further comprises: determining whether there is a commutative two-bit gate pair in the logic circuit; If so, swapping the positions of the target two-bit gates in the logic circuit, wherein the target two-bit gate pair is a two-bit gate pair whose two-bit gates at the later time step can act on the connected physical bits; The generating a target constraint relationship based on the initial mapping relationship and the logic circuit includes: Based on the initial mapping relationship and the commuted logic circuit, a target constraint relationship is generated.

7. The method according to claim 1, characterized in that The target constraint relationship also includes a third constraint relationship for inserting a CNOT gate; the third constraint relationship is to minimize the difference between the first topological distance and the second topological distance, wherein the first topological distance is the topological distance of the two-bit gate under the current mapping relationship in the specified time step, the second topological distance is the topological distance of the two-bit gate under the new mapping relationship between the SWAP gate and the parallel CNOT gate in the specified time step, and the specified time step is the nearest neighbor time step after the current target time step; Using the target constraint relationship, determining the insertion position of the SWAP door includes: The target constraint relationship is used to determine the insertion position of the SWAP gate and the insertion position of the CNOT gate, wherein within a target time step, the number of CNOT gates acting on any physical bit does not exceed 3, and the inserted CNOT gate is parallel to the inserted SWAP gate.

8. The method according to any one of claims 1 to 7, characterized in that: When there are still physical bits in the quantum hardware that are not included in the initial mapping relationship, the target constraint relationship further includes a fourth constraint relationship, and the fourth constraint relationship is that when the number of logical bit exchanges caused by inserting the SWAP gate is reduced by using auxiliary bits, at least one of the bits acted on by the SWAP gate is a physical bit in the initial mapping relationship, and the auxiliary bit is a physical bit in the quantum hardware that is not included in the initial mapping relationship.

9. The method according to claim 1, characterized in that Determining the insertion position of the SWAP door by using the target constraint relationship includes: Taking the insertion position of the SWAP gate as a variable, the target constraint relationship is input into the SAT solver to obtain a feasible solution; Select a solution from the feasible solutions as the insertion location of the SWAP gate.

10. A quantum circuit layout device, characterized in that: The device comprises: A first acquisition module is used to obtain an initial mapping relationship between logical bits in the logic circuit and physical bits in the quantum hardware; A generation module is used to generate a target constraint relationship based on the initial mapping relationship and the logic circuit, wherein the target constraint relationship includes a first constraint relationship and a second constraint relationship, the first constraint relationship is a constraint to ensure that the two-bit gate is executable in the quantum hardware according to the time step in the logic circuit; the second constraint relationship is a constraint to insert at most one SWAP gate per time step; A determination module, used to determine the insertion position of the SWAP gate in each target time step by using the target constraint relationship, wherein the target time step is the time step where the SWAP gate needs to be inserted determined based on the initial mapping relationship; The second obtaining module is used to obtain the laid-out quantum circuit based on the logic circuit and the determined insertion position.

11. A computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the quantum circuit layout method according to any one of claims 1 to 9 when executing the computer program.

12. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a computer, the computer executes the quantum circuit layout method according to any one of claims 1 to 9.

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