Pixel circuit and driving method thereof, display panel, and display device

Abstract

The present disclosure provides a pixel circuit, a driving method thereof, a display panel and a display device. The pixel circuit comprises: a driving sub-circuit electrically connected between a first node and a second node; a first light-emitting control sub-circuit configured to transmit a driving current to a first electrode and drive a light-emitting unit to emit light based on a signal of a first light-emitting control terminal; a first reset sub-circuit configured to electrically connect a first reset signal terminal with the second node based on a signal of a first reset control terminal; and a second reset sub-circuit configured to electrically connect a second reset signal terminal with the first node based on a signal of a second reset control terminal. The signal inputted to the second reset control terminal and the signal inputted to the first reset control terminal are different output signal lines from the same group of gate driving circuits, and the signal inputted to the second reset control terminal is a signal delayed by N H from the signal inputted to the first reset control terminal. The embodiments provided by the present disclosure reduce the frame width.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit and a driving method thereof, a display panel, and a display device. BACKGROUND

[0002] In the field of display, in order to achieve better frequency conversion effect, currently, a pixel architecture based on oxide process is usually adopted. However, the display product based on oxide process currently has a wide frame. SUMMARY

[0003] To solve at least one of the above problems, a first aspect of the present disclosure provides a pixel circuit, comprising: a driving sub-circuit, a first light-emitting control sub-circuit, a first reset sub-circuit, a second reset sub-circuit, and a light-emitting unit,

[0004] The driving sub-circuit comprises a driving transistor electrically connected between a first node and a second node, and configured to generate a driving current from a first power signal terminal to a first pole of the light-emitting unit,

[0005] The first light-emitting control sub-circuit is electrically connected to the second node, the first pole of the light-emitting unit, and a first light-emitting control terminal, and is configured to transmit the driving current to the first pole and drive the light-emitting unit to emit light based on a signal of the first light-emitting control terminal,

[0006] The first reset sub-circuit is electrically connected between a first reset signal terminal, a first reset control terminal, and the second node, and is configured to electrically connect the first reset signal terminal and the second node based on a signal of the first reset control terminal,

[0007] The second reset sub-circuit is electrically connected between a second reset signal terminal, a second reset control terminal, and the first node, and is configured to electrically connect the second reset signal terminal and the first node based on a signal of the second reset control terminal,

[0008] The signal input to the second reset control terminal and the signal input to the first reset control terminal are from different output signal lines of the same group of gate driving circuits, the signal input to the second reset control terminal is a signal delayed by N H from the signal input to the first reset control terminal, H is the time for the signal input to the first reset control terminal to scan a row of light-emitting units, and N is an integer greater than or equal to 1.

[0009] Optionally, the pixel circuit further comprises a third reset sub-circuit electrically connected between the first pole of the light-emitting unit, a third reset control terminal, and a third reset signal terminal, and configured to electrically connect the third reset signal terminal and the first pole based on a signal of the third reset control terminal,

[0010] The signal input to the third reset control terminal is the same as the signal input to the second reset control terminal.

[0011] Optionally, the first reset sub-circuit comprises a first transistor, a first electrode of the first transistor being electrically connected to the first reset signal terminal, a second electrode of the first transistor being electrically connected to the second node, and a control electrode of the first transistor being electrically connected to the first reset control terminal,

[0012] The second reset sub-circuit comprises a second transistor, a first electrode of the second transistor being electrically connected to the second reset signal terminal, a second electrode of the second transistor being electrically connected to the first node, and a control electrode of the second transistor being electrically connected to the second reset control terminal,

[0013] The third reset sub-circuit comprises a third transistor, a first electrode of the third transistor being electrically connected to the third reset signal terminal, a second electrode of the third transistor being electrically connected to the first electrode of the light-emitting unit, and a control electrode of the third transistor being electrically connected to the third reset control terminal,

[0014] The first transistor, the second transistor, and the third transistor are of the same type.

[0015] Optionally, the pixel circuit further comprises a compensation sub-circuit and a write-in sub-circuit,

[0016] The compensation sub-circuit is electrically connected to the second node, a third node corresponding to the control electrode of the driving transistor, and a compensation control terminal, and is configured to electrically connect the second node and the third node based on a signal of the compensation control terminal,

[0017] The write-in sub-circuit is electrically connected to the first node, a data signal terminal, and a data control terminal, and is configured to transmit a data signal input by the data signal terminal to the first node based on a signal of the data control terminal.

[0018] Optionally, the first light-emitting control sub-circuit comprises a fourth transistor, a first electrode of the fourth transistor being electrically connected to the second node, a second electrode of the fourth transistor being electrically connected to the first electrode, and a control electrode of the fourth transistor being electrically connected to the first light-emitting control terminal,

[0019] The compensation sub-circuit comprises a fifth transistor, a first electrode of the fifth transistor being electrically connected to the second node, a second electrode of the fifth transistor being electrically connected to the third node, and a control electrode of the fifth transistor being electrically connected to the compensation control terminal,

[0020] The write-in sub-circuit comprises a sixth transistor, a first electrode of the sixth transistor being electrically connected to the data signal terminal, a second electrode of the sixth transistor being electrically connected to the first node, and a control electrode of the sixth transistor being electrically connected to the data control terminal,

[0021] The pixel circuit further comprises a first capacitor, a first electrode of the first capacitor being electrically connected to the first power signal terminal, and a second electrode of the first capacitor being electrically connected to the third node.

[0022] Optionally, the pixel circuit further comprises a second light-emitting control sub-circuit, the second light-emitting control sub-circuit comprising a seventh transistor, a first electrode of the seventh transistor being electrically connected to the first power signal terminal, a second electrode of the seventh transistor being electrically connected to the first node, and a control electrode of the seventh transistor being electrically connected to the second light-emitting control terminal.

[0023] The second aspect of the present disclosure provides a display panel comprising the pixel circuit as described above.

[0024] Optionally, the display panel further comprises a plurality of first shift registers cascaded and a plurality of second shift registers cascaded,

[0025] The number of the first shift registers is less than the number of rows of the pixel circuits and the number of the second shift registers is less than N, or the number of the first shift registers is equal to the number of rows of the pixel circuits and the number of the second shift registers is equal to N.

[0026] The first shift registers are cascaded and then cascaded with the plurality of second shift registers to form a first gate driving circuit, and the first gate driving circuit provides signals to the second reset control end and the first reset control end.

[0027] Optionally, the display panel comprises a display area and a non-display area surrounding the display area,

[0028] The non-display area comprises an extension region arranged in the extension direction of the rows of pixel circuits,

[0029] The number of the first shift registers is half of the number of rows of the pixel circuits, and each first shift register occupies a range corresponding to two rows of pixel circuits in the arrangement direction of the rows of pixel circuits.

[0030] Optionally, the display panel comprises a display area and a non-display area surrounding the display area, the display area comprises a first side and a second side and a third side intersecting the first side, and the non-display area comprises a first side region adjacent to the first side, a second side region adjacent to the second side, and a third side region adjacent to the third side,

[0031] The second shift register is arranged in a corner region between the first side region and the second side region or in a corner region between the first side region and the third side region.

[0032] Optionally, the display panel further comprises a plurality of third shift registers cascaded and a plurality of fourth shift registers cascaded, and the display panel comprises a display area and a non-display area surrounding the display area,

[0033] The display panel comprises M rows of pixel circuits arranged in the display area, and the pixel circuit comprises a write sub-circuit, the write sub-circuit transmits a signal input by a data signal end to a first node based on a signal of a data control end,

[0034] The non-display area comprises a first side region close to one end of the row of pixel circuits and a fourth side region close to the other end of the row of pixel circuits.

[0035] The third shift register is arranged in one of the first side region and the fourth side region, and an output terminal of an nth third shift register is electrically connected with a data control terminal in an (2n-1)th pixel circuit row,

[0036] The fourth shift register is arranged in the other of the first side region and the fourth side region, and an output terminal of an nth fourth shift register is electrically connected with a data control terminal in an (2n)th pixel circuit row,

[0037] n is an integer greater than or equal to 1, and M is an integer greater than or equal to 2.

[0038] Optionally, the display panel comprises a display area and a non-display area surrounding the display area,

[0039] The non-display area comprises an extension region arranged in an extension direction of the pixel circuit row,

[0040] The range occupied by each third shift register in the arrangement direction of the pixel circuit row overlaps with the extension regions of two pixel circuit rows,

[0041] The range occupied by each fourth shift register in the arrangement direction of the pixel circuit row overlaps with the extension regions of two pixel circuit rows.

[0042] Optionally, the number of the first shift registers is half of the number of the pixel circuit rows, and the display panel further comprises a display area and a non-display area surrounding the display area,

[0043] The display panel further comprises: M pixel circuit rows arranged in the display area, the pixel circuit comprising a write sub-circuit, the write sub-circuit transmitting a signal input by a data signal terminal to a first node based on a signal of a data control terminal;

[0044] The M third shift registers are cascaded, and the M fourth shift registers are cascaded,

[0045] The non-display area comprises a first side region close to one end of the pixel circuit row and a fourth side region close to the other end of the pixel circuit row,

[0046] One of the third shift register and the fourth shift register is arranged in the first side region, and the other is arranged in the fourth side region,

[0047] The output terminals of the nth third shift register and the nth fourth shift register are both electrically connected with the data control terminal in the nth pixel circuit row,

[0048] n is an integer greater than or equal to 1, and M is an integer greater than or equal to 2.

[0049] Optionally, the display panel further comprises a display area and a non-display area surrounding the display area,

[0050] The display panel further comprises:

[0051] The M pixel circuit rows arranged in the display area include pixel circuits, and each pixel circuit includes a compensation sub-circuit, the compensation sub-circuit electrically connects the second node and a third node corresponding to a control electrode of the driving transistor based on a signal of a compensation control terminal; and

[0052] M / 2 fifth shift registers in cascade and M / 2 sixth shift registers in cascade,

[0053] The non-display area includes a first side region close to one end of the pixel circuit rows and a fourth side region close to the other end of the pixel circuit rows,

[0054] One of the fifth shift registers and the sixth shift registers is arranged in the first side region, and the other is arranged in the fourth side region,

[0055] The output end of each fifth shift register is electrically connected to the compensation control terminals of the pixel circuits of two adjacent rows at the same time,

[0056] The output end of each sixth shift register is electrically connected to the first light-emitting control terminals of the pixel circuits of two adjacent rows at the same time,

[0057] M is an integer greater than or equal to 2.

[0058] A third aspect of the present disclosure provides a display device, including the display panel as described above.

[0059] A fourth aspect of the present disclosure provides a driving method of the pixel circuit as described above, including:

[0060] In a first reset stage, a first reset sub-circuit transmits a potential of a first reset signal terminal to the second node based on a signal of a first reset control terminal being an effective level;

[0061] In a second reset stage, a second reset sub-circuit transmits a potential of a second reset signal terminal to the first node based on a signal of a second reset control terminal being an effective level, and a time period of the second reset stage is delayed by N H from a time period of the first reset stage.

[0062] In a light-emitting control stage, a driving current is transmitted to the first electrode and the light-emitting unit is driven to emit light based on a signal of the first light-emitting control terminal being an effective level.

[0063] The present disclosure has the following beneficial effects:

[0064] The present disclosure is directed to the current existing problems, and formulates a pixel circuit and a driving method thereof, a display panel, and a display device. The pixel circuit and the driving method thereof, the display panel, and the display device can reduce the number of groups of gate driving circuits required by the pixel circuit, reduce the frame width of the display product, facilitate the realization of narrow frame design, reduce the power consumption of the driving chip, and have a wide application prospect. BRIEF DESCRIPTION OF DRAWINGS

[0065] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0066] Figure 1 An exemplary block diagram of a pixel circuit according to an embodiment of the present disclosure is shown.

[0067] Figure 2 An exemplary circuit schematic diagram of a pixel circuit according to an embodiment of the present disclosure is shown.

[0068] Figure 3 An exemplary timing diagram of key ports of a pixel circuit according to an embodiment of the present disclosure is shown.

[0069] Figure 4 A connection relationship of a clock signal line in a gate driving circuit and a timing example thereof are shown.

[0070] Figures 5 to 7 A schematic diagram of a display panel according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0071] In order to more clearly illustrate the present disclosure, the present disclosure will be further described in combination with preferred embodiments and drawings. In the drawings, similar components are denoted by the same reference numerals. It should be understood by those skilled in the art that the specific description below is illustrative rather than limiting, and should not limit the protection scope of the present disclosure.

[0072] It should be noted that the technical terms or scientific terms used in the present disclosure should be understood as the general meaning understood by those skilled in the art to which the present disclosure belongs, unless otherwise defined. The terms "first", "second", and similar words used in the present disclosure do not represent any order, number or importance, but are only used to distinguish different components. Similarly, the terms "one", "a" or "the" and similar words do not represent a quantity limitation, but represent the presence of at least one. The terms "include" or "contain" and similar words mean that the elements or objects before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. In addition, in the present disclosure, the electrical connection can be a direct connection or a connection through a conducting transistor.

[0073] The transistor used in the embodiments of the present disclosure can be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, when the transistor is an N-type transistor, the drain is referred to as the first electrode, the source is referred to as the second electrode, and the gate is referred to as the control electrode. When the gate input is high, the source and drain are turned on. In addition, when the gate and the source are both high, the source and drain are not turned on. When the transistor is a P-type transistor, the source is referred to as the first electrode, the drain is referred to as the second electrode, and the gate is referred to as the control electrode. When the gate input is low, the source and drain are turned on. In addition, when the gate and the drain are both high, the source and drain are not turned on.

[0074] The pixel circuit based on the oxide process represents that the pixel circuit contains a low temperature polycrystalline oxide (LTPO) transistor, in other words, the pixel circuit contains both N-type transistor and P-type transistor. However, the pixel circuit with such architecture needs a large number of gate driving circuit groups, which is not conducive to narrow frame design, and the power consumption of the driving chip is large.

[0075] In order to achieve at least one of the above purposes, with reference to Figure 1 An embodiment of the present disclosure provides a pixel circuit, comprising: a driving sub-circuit 10, a first light emitting control sub-circuit 20, a first reset sub-circuit 31, a second reset sub-circuit 32, and a light emitting unit 40,

[0076] The driving sub-circuit 10 comprises a driving transistor electrically connected between the first node N1 and the second node N2, and is configured to generate a driving current from the first power signal end VDD to the first electrode of the light emitting unit 40,

[0077] The first light-emitting control sub-circuit 20 is electrically connected to the second node N2, the first electrode of the light-emitting unit 40, and the first light-emitting control end EM, and is configured to transmit a driving current to the first electrode and drive the light-emitting unit 40 to emit light based on a signal of the first light-emitting control end EM,

[0078] The first reset sub-circuit 31 is electrically connected between the first reset signal end Vinit1, the first reset control end ResetP, and the second node N2, and is configured to electrically connect the first reset signal end Vinit1 and the second node N2 based on a signal of the first reset control end ResetP,

[0079] The second reset sub-circuit 32 is electrically connected between the second reset signal end Vinit2, the second reset control end ResetPn, and the first node N1, and is configured to electrically connect the second reset signal end Vinit2 and the first node N1 based on a signal of the second reset control end ResetPn,

[0080] The signal input to the second reset control end ResetPn and the signal input to the first reset control end ResetP are from different output signal lines of the same group of gate driving circuits, and the signal input to the second reset control end ResetPn is a signal delayed by N H from the signal input to the first reset control end ResetP, H is the time for the signal input to the first reset control end ResetP to scan a row of light-emitting units, and N is an integer greater than or equal to 1.

[0081] In the embodiment, by using signals with time delay from the same group of signal lines to input the first reset sub-circuit and the second reset sub-circuit respectively, the number of groups of gate driving circuits required by the pixel circuit can be reduced, the frame width of the display product is reduced, the narrow frame design is facilitated, and the power consumption of the driving chip is reduced.

[0082] The structure and function of the pixel circuit of the embodiment of the present disclosure will be described in detail below with reference to a specific circuit structure.

[0083] Figure 2 A circuit schematic diagram of a pixel circuit in a specific example is shown, wherein the control end of a transistor is denoted as "(n)" to indicate that the pixel circuit is a pixel circuit located in the nth row of the corresponding display panel.

[0084] In a specific example, referring to Figure 2 As shown, the pixel circuit includes a driving sub-circuit 10, a first light-emitting control sub-circuit 20, a first reset sub-circuit 31, a second reset sub-circuit 32, and a light-emitting unit 40.

[0085] Specifically, the light emitting unit 40 may be an organic light emitting diode (OLED), a quantum dot light emitting diode (QLED), or a micro light emitting diode (Micro LED). In the embodiments of the present disclosure, any light emitting element that can emit light under a driving current and can emit light when a power supply voltage of a certain amplitude is provided at the anode may be used. In addition, although Figure 2 A light-emitting element is shown in the figure, but it is for illustration only. The light-emitting unit 40 may also include multiple light-emitting elements connected in series. When multiple light-emitting elements are connected in series, the anode of the light-emitting element at the first position in the series represents the anode of the light-emitting unit 40.

[0086] Continue to refer to Figure 2 As shown, the driver sub-circuit 10 includes a driver transistor DTFT. The driver sub-circuit 10 is electrically connected between a first node N1 and a second node N2 and is configured to generate a drive current from the first power signal terminal VDD to the light-emitting unit 40. Specifically, the cathode of the light-emitting unit 40 is electrically connected to the power supply terminal VSS. In essence, the driver sub-circuit 10 is used to generate a drive current that flows from the first power signal terminal VDD through the first node N1 and the second node N2, and finally to the power supply terminal VSS via the light-emitting unit 40. This drive current is directly generated by the driver transistor DTFT and flows in the path from the first power signal terminal VDD to the power supply terminal VSS, causing the light-emitting unit 40 to emit light.

[0087] Specifically, the first electrode of the driving transistor DTFT is electrically connected to the first node N1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to Figure 2 The third node N3 in the transistor is configured to generate a driving current based on a signal of the control electrode.

[0088] Continue to refer to Figure 2 As shown, the first light-emission control sub-circuit 20 is electrically connected to the second node N2, the first electrode of the light-emitting unit 40, and the first light-emission control terminal EM. Based on the signal from the first light-emission control terminal EM, the first light-emitting current is transmitted to the first electrode of the light-emitting unit 40, thereby driving the light-emitting unit 40 to emit light. In this example, the first electrode of the light-emitting unit 40 serves as the anode. In other words, when the signal from the first light-emission control terminal EM is at an active level, a light-emitting path is established for the branch in which the drive transistor DTFT is located.

[0089] Reference Figure 2 As shown, in the embodiment of the present disclosure, the pixel circuit further includes a first reset sub-circuit 31 and a second reset sub-circuit 32 .

[0090] The first reset sub-circuit 31 is electrically connected between the first reset signal terminal Vinit1, the first reset control terminal ResetP(n) and the second node N2, and is configured to electrically connect the first reset signal terminal Vinit1 and the second node N2 based on the signal of the first reset control terminal ResetP(n), so that the signal input into the second node N2 by the first reset signal terminal Vinit1 is reset. The second reset sub-circuit 32 is electrically connected between the second reset signal terminal Vinit2, the second reset control terminal ResetPn(n) and the first node N1, and is configured to electrically connect the second reset signal terminal Vinit2 and the first node N1 based on the signal of the second reset control terminal ResetPn(n), so that the signal of the second reset signal terminal Vinit2 is input into the first node N1 to reset it.

[0091] It is worth mentioning that in the embodiments of the present disclosure, the first node N1 and the second node N2 are the first pole and the second pole of the driving transistor DTFT respectively, and in the driving process of the pixel circuit, no matter how the structure of data writing and threshold voltage compensation is, one of the first pole and the second pole of the driving transistor DTFT will be related to data writing and maintaining, and the other will be related to threshold voltage compensation, so the reset timing of the two is different.

[0092] In particular, the signal input into the second reset control terminal ResetPn(n) and the signal input into the first reset control terminal ResetP(n) come from the same group of output signal lines of the gate driving circuit, and the signal input into the second reset control terminal ResetPn(n) is the signal input into the first reset control terminal ResetP(n) delayed by N H, H is the time for the signal input into the first reset control terminal ResetP(n) to scan a row of light emitting units, and N is an integer greater than or equal to 1.

[0093] It should be pointed out that the output signal lines from the same group of gate driving circuits are not intended to be limited, and a signal line providing a signal for the first reset control terminal ResetP will also necessarily provide a signal for the second reset control terminal ResetPn of another row of pixel circuits. The embodiments of the present disclosure allow the signal line providing a signal for all second reset control terminals ResetPn to be different from the signal line providing a signal for all first reset control terminals ResetP.

[0094] Through the arrangement, by using the feature that different signal lines of the output signal lines of the group of gate driving circuits have time delay before and after, the first control end and the second reset control end which need to access effective signals in different time periods are connected to different output signal lines of the group of gate driving circuits, so that the group of circuits can provide signals for the two reset control ends which access different signals, thereby facilitating the narrow frame design, and further facilitating the reduction of the power consumption of the driving chip, and the specific effects will be further described below.

[0095] Specifically, referring to Figure 2 , the first reset sub-circuit 31 includes a first transistor T1, the first electrode of the first transistor T1 is electrically connected to the first reset signal end Vinit1, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the first reset control end ResetP(n). When the signal of the first reset control end ResetP(n) is at an effective level, the first transistor T1 is turned on, and the signal of the first reset signal end Vinit1 is transmitted to the second node N2, so as to reset the potential of the second node N2 (i.e. the first electrode of the driving transistor DTFT).

[0096] The second reset sub-circuit 32 includes a second transistor T2, the first electrode of the second transistor T2 is electrically connected to the second reset signal end Vinit2, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the second reset control end ResetPn(n). When the signal of the second reset control end ResetPn(n) is at an effective level, the second transistor T2 is turned on, and the signal of the second reset signal end Vinit2 is transmitted to the first node N1, so as to reset the potential of the first node N1 (i.e. the second electrode of the driving transistor DTFT).

[0097] Optionally, continuing to refer to Figure 2 , the pixel circuit further includes a third reset sub-circuit 33 electrically connected between the first electrode of the light emitting unit 40, the third reset control end ResetPn(n) and the third reset signal end Vinit3, and configured to electrically connect the third reset signal end vinit3 and the first electrode of the light emitting unit 40 based on the signal of the third reset control end ResetPn(n). The signal accessed by the third reset control end is the same as the signal accessed by the second reset control end. Correspondingly, because the signals accessed by the two are the same, the two signal ends are represented by the same reference sign "ResetPn(n)" in this paper.

[0098] Specifically, referring to Figure 2As shown, the third reset sub-circuit 33 includes a third transistor T3, a first electrode of the third transistor T3 is electrically connected to the third reset signal terminal Vinit3, a second electrode is electrically connected to the anode of the light emitting unit 40, and a control electrode is electrically connected to the third reset control terminal ResetPn(n). When the signal of the third reset control terminal ResetPn(n) is at a valid level, the third transistor T3 is turned on, and the signal of the third reset signal terminal Vinit3 is transmitted to the anode of the light emitting unit 40, thereby resetting the potential of the anode.

[0099] Through the above arrangement, the output signal lines of a group of gate drive circuits can be used to simultaneously provide control signals for the first reset sub-circuit 31, the second reset sub-circuit 32, and the third reset sub-circuit 33, thereby reducing the number of gate drive circuits, facilitating narrow frame design, and reducing the power consumption of the driving chip.

[0100] It should be noted that, in order to ensure that the pixel circuit can work normally, the first transistor T1, the second transistor T2, and the third transistor T3 should be the same type of transistor.

[0101] In addition, the first light emitting control sub-circuit 20 is electrically connected to the second node N2, the first electrode of the light emitting unit 40, and the first light emitting control terminal EM, and is configured to transmit a driving current to the first electrode based on the signal of the first light emitting control terminal EM and drive the light emitting unit 40 to emit light.

[0102] Specifically, referring to Figure 2 As shown, the first light emitting control sub-circuit 20 includes a fourth transistor T4, a first electrode of the fourth transistor T4 is electrically connected to the second node N2, a second electrode is electrically connected to the anode of the light emitting unit 40, and a control electrode is electrically connected to the first light emitting control terminal EM. When the first light emitting control terminal EM is connected to a valid level signal, the fourth transistor T4 is turned on, and a driving current is transmitted to the anode to drive the light emitting unit 40 to emit light.

[0103] Optionally, referring to Figure 2 As shown, the pixel circuit further includes a compensation sub-circuit 50 and a writing sub-circuit 60.

[0104] The compensation sub-circuit 50 is electrically connected to the second node N2, a third node N3 corresponding to the control electrode of the driving transistor DTFT, and a compensation control terminal GateN(n), and is configured to electrically connect the second node N2 and the third node N3 based on the signal of the compensation control terminal GateN(n).

[0105] The write sub-circuit 60 is electrically connected to the first node N1, the data signal terminal Data and the data control terminal GateP(n), and is configured to transmit the data signal connected to the data signal terminal Data to the first node N1 based on the signal of the data control terminal GateP(n), thereby writing the data signal to the first electrode of the driving transistor DTFT.

[0106] Specifically, the compensation sub-circuit 50 includes a fifth transistor T5. A first electrode of the fifth transistor T5 is electrically connected to the second node N2, a second electrode is electrically connected to the third node N3, and a control electrode is electrically connected to the compensation control terminal GateN(n). When the signal input to the compensation control terminal GateN(n) is at an active level, the fifth transistor T5 is turned on, thereby connecting the second node N2 and the third node N3.

[0107] The write sub-circuit 60 includes a sixth transistor T6. A first electrode of the sixth transistor T6 is electrically connected to the data signal terminal Data, a second electrode is electrically connected to the first node N1, and a control electrode is electrically connected to the data control terminal GateP(n). When the signal input to the data control terminal GateP(n) is at an active level, the sixth transistor T6 is turned on, connecting the first node N1 to the data signal terminal Data, thereby transmitting the signal from the data signal terminal Data to the first node N1.

[0108] In addition, based on the structure of the fifth transistor T5 and the sixth transistor T6, the pixel circuit also includes a first capacitor Cst, a first electrode of the first capacitor Cst is electrically connected to the first power signal terminal VDD, and a second electrode is electrically connected to the third node N3, so as to ensure that after the writing sub-circuit 60 transmits the data signal of the data signal terminal Data to the third node N3 via the fifth transistor T5, it can be compensated based on its potential holding ability and the driving transistor DTFT can be continuously turned on during the stage when the driving transistor DTFT generates a driving current to drive the light-emitting unit 40 to emit light.

[0109] Alternatively, refer to Figure 2 As shown, the pixel circuit also includes: a second light-emitting control subcircuit 70, the second light-emitting control subcircuit 70 includes a seventh transistor T7, the first electrode of the seventh transistor T7 is electrically connected to the first power signal terminal VDD, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the second light-emitting control terminal EM.

[0110] In this example, the timing of the signal connected to the second light-emitting control terminal is consistent with the timing of the signal connected to the first light-emitting control terminal, so the two use the same label "EM". It should be understood by those skilled in the art that the present disclosure is not limited to this. When the structure and position of the writing sub-circuit and the compensation sub-circuit in the pixel circuit are different Figure 2The timing of the signal input to the second light-emitting control terminal may need to be different from the timing of the signal input to the first light-emitting control terminal to cooperate with the threshold compensation function, which is not described herein.

[0111] To further understand the structure and function of the pixel circuit of the embodiments of the present disclosure, the following describes the working principle of the pixel circuit of the embodiments of the present disclosure with reference to the circuit structure shown in Figure 3 The circuit structure shown is taken as an example, and the working principle of the pixel circuit of the embodiments of the present disclosure is described with reference to the timing diagram shown in Figure 3 The circuit structure shown is taken as an example, and the working principle of the pixel circuit of the embodiments of the present disclosure is described with reference to the timing diagram shown in

[0112] In this example, the fifth transistor T5 is an N-type transistor, and the other transistors are P-type transistors. In addition, for ease of understanding, the data signal input to the data signal terminal Data is denoted as Vdata, and the potentials of the other ports are denoted by the corresponding port names. In addition, it should be noted that in the embodiments of the present disclosure, the signal level of the control electrode that makes the transistor conductive is the effective level of the transistor regardless of the conduction type.

[0113] The driving process of the pixel circuit includes the first stage to the fourth stage t1-t4, as shown in Figure 4 The driving process of the pixel circuit includes the first stage to the fourth stage t1-t4, as shown in

[0114] In the first stage t1, the first reset control terminal ResetP(n) is at a low level, the compensation control terminal GateN(n) is at a high level, and the other signal terminals are at a high level. Only the first transistor T1 and the fifth transistor T5 are conductive in this stage. The first reset signal terminal Vinit1 is electrically connected to the second node N2, and the first reset signal is transmitted to the second node N2 to reset the potential of the node. At the same time, because the fifth transistor T5 is conductive, the second node N2 and the third node N3 are electrically connected, so that the potential of the third node N3 is also reset.

[0115] In the second stage t2, the data control terminal GateP(n) becomes low, and the other signal terminals remain high at this time. The sixth transistor T6 is conductive, and the data signal Vdata of the data signal terminal Data is transmitted to the first node N1. At the same time, because the compensation control terminal GateN(n) is still at a high level, the fifth transistor T5 is still conductive, the second node 2 and the third node N3 are electrically connected, and the driving transistor DTFT is also conductive under the action of the first capacitor Cst. The data signal Vdata of the first node N1 is transmitted to the third node N3 and charges the control electrode of the driving transistor DTFT. When the potential of the driving transistor DTFT is charged to the potential difference Vgs=Vth between the gate and the source, the charging is stopped. At this time, the potential of the third node N3 corresponding to the driving transistor DTFT is Vg=Vdata+Vth.

[0116] In the third stage t3, the second reset control terminal and the third reset control terminal ResetPn(n) are low, the compensation control terminal GateN(n) is low, and the other signal terminals are high. Only the second transistor T2 and the third transistor T3 are turned on in this stage. The second reset signal terminal Vinit2 is electrically connected with the first node N1, and the second reset signal is transmitted to the first node N1 to reset the potential of the node. The third reset signal terminal Vinit3 is electrically connected with the anode of the light emitting unit 40, and the third reset signal is transmitted to the anode to reset the potential of the node.

[0117] In the fourth node t4, the first reset control terminal ResetP(n), the second reset control terminal and the third reset control terminal ResetPn(n) are high, the data control terminal GateP(n) is high, the compensation control terminal GateN(n) is low, and the first light emitting control terminal and the second light emitting control terminal EM are low. The fourth transistor T4 and the seventh transistor T7 are turned on, and the driving transistor DTFT is also turned on under the holding action of the first capacitor Cst. The other transistors are turned off, forming a path from the first power signal terminal VDD to the anode of the light emitting unit 40. The driving current generated by the driving transistor DTFT is transmitted to the light emitting unit 40 to drive it to emit light. The driving circuit Id=k×(Vgs-Vth) 2 =k×(Vdata-VDD) 2 Wherein, k represents the gain parameter of the driving transistor DTFT.

[0118] Through the above process, it can be seen that the effective level of the signal input into the second reset control terminal and the third reset control terminal ResetPn(n) is delayed compared with the effective level of the signal input into the first reset control terminal ResetP(n). The time difference of the signals output by different output signal lines of the same group of gate driving circuits can achieve the above requirements, so that the number of groups of gate driving circuits providing gate driving signals in the pixel circuit can be reduced from at least 5 groups to 4 groups, thereby facilitating the narrow frame design of the display product. In addition, when the number of groups of gate driving circuits is reduced, the time length of the time during which no light is emitted is shortened while ensuring the margin between the timing of the gate driving circuit, thereby improving the display flicker.

[0119] Continuing to combine Figure 4 As shown in the figure, when the first reset control terminal and the second reset control terminal are provided with signals by two groups of gate driving circuits respectively, the connection relationship between the clock signal line in each group of gate driving circuits and the circuit unit in the gate driving circuit, and the timing diagram are shown.

[0120] Figure 4The left and right halves, separated by a dotted line, each represent a gate drive circuit. Assume the left half is gate drive circuit 1 and the right half is gate drive circuit 2. Each gate drive circuit group includes cascaded shift registers (rectangles arranged sequentially in the figure). Two clock signal lines provide clock signals to the odd-numbered and even-numbered shift register circuits, respectively. These clock signals come from the driver chip.

[0121] like Figures 5 to 7 As shown, for gate drive circuit 1, the power consumption of a single clock signal line in a cycle of 4H is P = ΔU*I = ΔU*Q / t = 2*ΔU*ΔU*C1 / t = 2*ΔU*ΔU*C1 / 4H = ΔU*ΔU*C1 / 2H, so the total clock signal line power consumption of gate drive circuit 1 is ΔU*ΔU*C1 / H, where C1 is the equivalent capacitance of the clock signal line and ΔU represents the low-level potential of the clock signal line. For gate drive circuit 2, the power consumption of a single clock signal line in a cycle of 4H should be P = ΔU*I = ΔU*Q / t = 2*ΔU*ΔU*C2 / t = 2*ΔU*ΔU*C2 / 4H = ΔU*ΔU*C2 / 2H, so the total clock signal line power consumption of gate drive circuit 2 is ΔU*ΔU*C1 / H, where C2 is the equivalent capacitance of the clock signal line and ΔU represents the low-level potential of the clock signal line.

[0122] It can be seen that, assuming that the circuit structures of gate drive circuit 1 and gate drive circuit 2 are the same, when the pixel circuit in the display product is a structure according to an embodiment of the present disclosure, the power consumption of the clock signal lines of the gate drive circuits at the first reset control terminal, the second reset control terminal and the third reset control terminal will be reduced by half, which means that the power consumption of the driving chip is reduced.

[0123] Corresponding to the pixel circuit, the present disclosure further provides a display panel, including the pixel circuit described in the above embodiment.

[0124] In this embodiment, by including the above pixel circuit, a group of gate driving circuits can provide signals to the first reset control terminal and the second reset control terminal of the pixel circuit, thereby reducing the border width and the power consumption of the driving chip.

[0125] The specific structure and function of the above pixel circuit, as well as the principle of the change in power consumption caused thereby, have been described in detail in the above embodiments and will not be repeated here.

[0126] Considering the time delay relationship between the first reset control terminal ResetP and the second reset control terminal ResetPn, if only a set of shift register circuits providing signals to one of the reset control terminals in each row of pixel circuits is used, and the time interval output signal line is electrically connected to the first reset control terminal ResetP and the second reset control terminal ResetPn in each pixel circuit in the display panel, then the first reset control terminal ResetP of N rows of pixel circuits or the second reset control terminal ResetPn of N rows of pixel circuits will have no signal input.

[0127] Therefore, in the embodiments of the present disclosure, a plurality of shift registers are additionally added as pre-stage or post-stage circuits to ensure that the first reset control terminal ResetP and the second reset control terminal ResetPn in all rows of pixel circuits can have signal input.

[0128] Alternatively, the display panel further comprises a plurality of first shift registers and a plurality of second shift registers in cascade, the number of the first shift registers is less than the number of rows of pixel circuits, and the number of the second shift registers is less than N, or the number of the first shift registers is equal to the number of rows of pixel circuits, and the number of the second shift registers is equal to N, the first shift registers are cascaded and then cascaded with the plurality of second shift registers to form a first gate drive circuit, and the first gate drive circuit provides signals to the second reset control terminal and the first reset control terminal. In the embodiment, the second shift registers are additional pre-stage or post-stage circuits. The number of the pre-stage second shift registers depends on the number of the first shift registers and the signal providing mode, which will be described below.

[0129] Further reference is made below to Figures 5 to 7 to describe the structure of the display panel of the present disclosure.

[0130] It should be noted that, for the convenience of understanding, Figures 5 to 7 the shift registers providing signals to the corresponding ports are denoted by the same reference numerals as the signal ports in the pixel circuits. Meanwhile, a box marked with a reference numeral represents a shift register. In addition, in order to clearly show the shift registers in the non-display area, Figure 5 the proportional relationship of the display area AA to the non-display area is reduced; in addition, only two rows of shift registers are exemplarily shown in the figure, and those skilled in the art should understand that this is not intended to be limiting, the number of shift registers in each set of gate drive circuits depends on the number of rows of pixel circuits in the display area AA, which will not be described below.

[0131] Alternatively, reference is made to Figure 6As shown, the display panel includes a display area AA and a non-display area NA surrounding the display area. The display area AA includes a first side and a second side and a third side intersecting the first side, and the non-display area NA includes a first side region NA1 adjacent to the first side, a second side region NA2 adjacent to the second side, and a third side region NA3 adjacent to the third side. The first gate drive circuit is composed of a plurality of first shift registers ResetP cascaded and N second shift registers ResetPn cascaded, and the second shift register ResetP is arranged in a corner region between the first side region NA1 and the second side region NA2.

[0132] Alternatively, referring to Figure 5 As shown, the display panel includes a display area AA and a non-display area NA surrounding the display area. The display area AA includes a first side and a second side and a third side intersecting the first side, and the non-display area NA includes a first side region NA1 adjacent to the first side, a second side region NA2 adjacent to the second side, and a third side region NA3 adjacent to the third side. The first gate drive circuit is composed of a plurality of first shift registers ResetP cascaded and N second shift registers ResetPn cascaded, and the second shift register ResetPn is arranged in a corner region between the first side region NA1 and the third side region NA3.

[0133] In other words, the second shift register as a front-end circuit or a back-end circuit in the embodiments of the present disclosure can be located in a corner region on the upper side of the display panel or in a corner region on the lower side.

[0134] In addition, because the second shift register is used to supplement the insufficient shift registers due to the delay time interval between the second reset control terminal ResetPn and the first reset control terminal ResetP, the role of the second shift register is different according to the location of the second shift register. For example, Figure 6 Or Figure 5 As shown, if the second shift register is in the region above the cascaded first stage shift register, the second shift register in the corner region between the first side region NA1 and the second side region NA2 provides a signal to the first reset control terminal ResetP, indicated by the label "ResetP", and if the second shift register is in the region below the cascaded first stage shift register, the second shift register in the corner region between the first side region NA1 and the third side region NA3 provides a signal to the second reset control terminal ResetPn, indicated by the label "ResetPn"; in order to distinguish the first shift register located in the first side region NA1, the other of ResetPn and ResetP is used accordingly.

[0135] Alternatively, continuing to refer to Figure 5As shown, the non-display area NA includes an extension area P1 arranged in the extension direction of the pixel circuit row (X direction in the figure), wherein Figure 5 The white square located in the display area AA represents the range occupied by the pixel circuit. The number of first shift registers ResetPn is half the number of rows of pixel circuits. The range occupied by each first shift register ResetPn in the arrangement direction of the pixel circuit rows overlaps with the extended areas corresponding to the two pixel circuit rows.

[0136] In other words, in this example, a first shift register ResetPn simultaneously provides a signal to the first reset control terminal ResetP in two adjacent rows of pixel circuits or simultaneously provides a signal to the second reset control terminal ResetPn in two adjacent rows, or a first shift register ResetPn simultaneously provides a signal to the first reset control terminal ResetP in two adjacent rows of pixel circuits and simultaneously provides a signal to the second reset control terminal ResetPn of two adjacent rows separated from the two rows of pixel circuits by multiple Hs, so that when a first shift register ResetPn outputs a valid level, the transistors corresponding to the first reset control terminal ResetP and / or the second reset control terminal ResetPn in the two rows of pixel circuits electrically connected thereto are turned on at the same time.

[0137] With this arrangement, a first shift register can occupy two rows of space in the longitudinal direction (ie, Y direction) of the non-display area AA, thereby increasing the longitudinal arrangement space of components of the first shift register and further reducing the border width.

[0138] Of course, the present disclosure is not intended to limit the extending direction and the arrangement direction of the pixel circuit rows, and the two may also be interchangeable.

[0139] Continue to refer to Figure 7 As shown, the display panel also includes: M cascaded third shift registers and M cascaded fourth shift registers, where M is the same as the number of pixel circuit rows. The third shift register is located in the first side area NA1, and the fourth shift register is located in the fourth side area NA4. The fourth side area is the area of ​​the non-display area NA adjacent to the fourth side of the display area AA. The third and fourth shift registers are both shift registers that provide signals to the data control terminal GateP in the pixel circuit and are therefore both denoted by the label "GateP."

[0140] Considering that the write sub-circuit 60 writes the data signal of the data signal terminal Data into the corresponding first node N1 based on the signal received by the data control terminal GateP, if the output signal from the shift register is only input from one end of the signal line, the signal attenuation of the signal line may cause driving attenuation, thereby causing uneven display.

[0141] In the example, the output terminals of the nth third shift register and the nth fourth shift register GateP are electrically connected to the data control terminals in the nth row of pixel circuits, so that driving signals can be simultaneously provided to the data control terminals GateP in the same row from both sides, thereby improving the driving capability and the display uniformity of the display panel.

[0142] When the double-side area data control terminals are used, the display uniformity is improved, but the frame width is increased due to the addition of a set of gate driving circuit, which is not conducive to narrow frame design.

[0143] Further optionally, as shown in Figure 7 , the display panel includes a plurality of third shift registers connected in cascade and a plurality of fourth shift registers connected in cascade, the third shift registers are located in one of the first side area NA1 and the fourth side area NA4, the fourth shift registers are located in the other of the first side area NA1 and the fourth side area NA4, and the fourth side area is an area adjacent to the fourth side of the display area AA in the non-display area NA. The third shift registers and the fourth shift registers are both shift registers for providing signals to the data control terminals GateP in the pixel circuits, and are therefore both denoted by the reference numeral "GateP".

[0144] The output terminal of the nth third shift register GateP is electrically connected to the data control terminal GateP(2n-1) in the 2n-1th row of pixel circuits, and the output terminal of the nth fourth shift register is electrically connected to the data control terminal GateP(2n) in the 2nth row of pixel circuits, where n is a positive integer greater than or equal to 1.

[0145] That is, the signals of the data control terminals GateP in the pixel circuits in the odd-numbered rows are accessed from one side of the non-display area NA, and the signals of the data control terminals GateP in the pixel circuits in the even-numbered rows are accessed from the other side of the non-display area NA, as shown by the arrows in Figure 7 , which achieves a snake-shaped driving winding, equivalent to the signals of the data control terminals GateP in one row of pixel circuits decaying from left to right, and the signals of the data control terminals GateP in the next row of pixel circuits decaying from right to left, thereby achieving the purpose of improving the display uniformity of the display panel.

[0146] Further optionally, as shown in Figures 5 to 7 , the non-display area NA includes an extension area P1 arranged in the extension direction of the rows of pixel circuits (the X direction in the figure), each third shift register GateP occupies a range in the arrangement direction of the rows of pixel circuits (the Y direction in the figure) that overlaps the extension areas of two rows of pixel circuits, and each fourth shift register occupies a range in the arrangement direction of the rows of pixel circuits (the Y direction in the figure) that overlaps the extension areas of two rows of pixel circuits.

[0147] Of course, the present disclosure does not intend to limit the extending direction of the pixel circuit row and the arrangement direction thereof, and the two can be interchangeable.

[0148] Through the arrangement, one third shift register can occupy two row spaces in the longitudinal direction (i.e., the Y direction) of the non-display area AA, and one fourth shift register can occupy two row spaces in the longitudinal direction (i.e., the Y direction) of the non-display area AA, so as to increase the arrangement space of the third shift register and the fourth shift register in the longitudinal direction, and further reduce the frame width.

[0149] In principle, the other control terminals in the pixel circuit except the data control terminal GateP can be driven by one shift register to drive two rows of pixel circuits.

[0150] Further optionally, referring to ​ As shown in the figure, the display panel further includes a plurality of cascaded fifth shift registers GateN and a plurality of cascaded sixth shift registers EM arranged in the non-display area NA. When the number of pixel circuit rows is M, the number of fifth shift registers GateN is M / 2, the number of sixth shift registers EM is M / 2, and M is an integer greater than or equal to 2.

[0151] The non-display area includes a first side area NA1 close to one end of the pixel circuit row and a fourth side area NA4 close to the other end of the pixel circuit row, one of the fifth shift registers and the sixth shift registers is arranged in the first side area NA1, and the other is arranged in the fourth side area NA4.

[0152] The output terminal of each fifth shift register GateN is electrically connected to the compensation control terminals GateN of two adjacent rows of pixel circuits at the same time, and the output terminal of each sixth shift register EM is electrically connected to the first light-emitting control terminals EM of two adjacent rows of pixel circuits at the same time.

[0153] Through the arrangement, the range occupied by each fifth shift register GateN and each sixth shift register EM can overlap with the extending area P1 of two rows of pixel circuit rows, so as to further reduce the frame width.

[0154] A third aspect of the present disclosure provides a display device including the display panel of the present disclosure. The display device can be electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any display product or component including the display panel, and the present disclosure does not limit the display device.

[0155] The specific structure and functions of the display panel and the pixel circuit included in the display panel have been described in detail in the above embodiments, and will not be repeated here.

[0156] In the embodiment, by providing the display panel, the display device with an extremely narrow frame can be realized, and the user experience is improved.

[0157] A fourth aspect of the present disclosure provides a driving method of the pixel circuit using the embodiments of the present disclosure, comprising:

[0158] In the first reset stage, the first reset sub-circuit transmits the potential of the first reset signal end to the second node based on the signal inputted by the first reset control end being at a valid level.

[0159] In the second reset stage, the second reset sub-circuit transmits the potential of the second reset signal end to the first node based on the signal inputted by the second reset control end being at a valid level, and the time period of the second reset stage is N H longer than the first reset period.

[0160] In the light emitting control stage, the driving current is transmitted to the first electrode based on the signal of the first light emitting control end being at a valid level, and the light emitting unit is driven to emit light.

[0161] In the above manner, the number of gate driving circuits required by the pixel circuit can be reduced, the frame width of the display product is reduced, the narrow frame design is facilitated, the power consumption of the driving chip is reduced, and higher display quality is provided.

[0162] Obviously, the above embodiments of the present disclosure are only examples for clearly illustrating the present disclosure, and are not intended to limit the implementation manners of the present disclosure. For those skilled in the art, on the basis of the above description, other different forms of changes or modifications can also be made, and it is impossible to enumerate all the implementation manners here. Any changes or modifications that are obvious to those skilled in the art and fall within the scope of the technical solutions of the present disclosure are still within the protection scope of the present disclosure.

Claims

1. A pixel circuit, characterized in that: include: a driving subcircuit, a first light-emitting control subcircuit, a first reset subcircuit, a second reset subcircuit, and a light-emitting unit, The driving sub-circuit includes a driving transistor electrically connected between a first node and a second node, and configured to generate a driving current from a first power signal terminal to a first electrode of the light emitting unit. The first light-emitting control subcircuit is electrically connected to the second node, the first electrode of the light-emitting unit, and the first light-emitting control terminal, and is configured to transmit the driving current to the first electrode based on the signal of the first light-emitting control terminal and drive the light-emitting unit to emit light. The first reset sub-circuit is electrically connected to the first reset signal terminal, the first reset control terminal and the second node, and is configured to electrically connect the first reset signal terminal to the second node based on a signal of the first reset control terminal. The second reset sub-circuit is electrically connected to the second reset signal terminal, the second reset control terminal and the first node, and is configured to electrically connect the second reset signal terminal to the first node based on a signal of the second reset control terminal. The signal connected to the second reset control terminal and the signal connected to the first reset control terminal come from different output signal lines of the same group of gate drive circuits, and the signal connected to the second reset control terminal is a signal connected to the first reset control terminal delayed by N Hs, where H is the time it takes for the signal connected to the first reset control terminal to scan a row of light-emitting units, and N is an integer greater than or equal to 1.

2. The pixel circuit according to claim 1, wherein: Also includes: The third reset sub-circuit is electrically connected between the first electrode of the light-emitting unit, the third reset control terminal, and the third reset signal terminal, and is configured to electrically connect the third reset signal terminal to the first electrode based on the signal of the third reset control terminal. The signal received by the third reset control terminal is the same as the signal received by the second reset control terminal.

3. The pixel circuit according to claim 2, wherein: The first reset sub-circuit includes: a first transistor, a first electrode of the first transistor is electrically connected to the first reset signal terminal, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the first reset control terminal. The second reset sub-circuit includes: a second transistor, a first electrode of the second transistor is electrically connected to the second reset signal terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the second reset control terminal. The third reset subcircuit includes: a third transistor, a first electrode of the third transistor is electrically connected to the third reset signal terminal, a second electrode is electrically connected to the first electrode of the light emitting unit, and a control electrode is electrically connected to the third reset control terminal. The first transistor, the second transistor, and the third transistor are of the same transistor type.

4. The pixel circuit according to claim 1, wherein: Also includes: Compensation subcircuit and write subcircuit, The compensation sub-circuit is electrically connected to the second node, a third node corresponding to the control electrode of the driving transistor, and a compensation control terminal, and is configured to electrically connect the second node and the third node based on a signal from the compensation control terminal. The write sub-circuit is electrically connected to the first node, the data signal terminal and the data control terminal, and is configured to transmit the data signal connected to the data signal terminal to the first node based on the signal of the data control terminal.

5. The pixel circuit according to claim 4, wherein: The first light emitting control subcircuit includes a fourth transistor, wherein a first electrode of the fourth transistor is electrically connected to the second node, a second electrode is electrically connected to the first electrode, and a control electrode is electrically connected to the first light emitting control terminal. The compensation sub-circuit includes a fifth transistor, a first electrode of the fifth transistor is electrically connected to the second node, a second electrode is electrically connected to the third node, and a control electrode is electrically connected to the compensation control terminal. The write sub-circuit includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the data signal terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the data control terminal. The pixel circuit further includes a first capacitor, wherein a first electrode of the first capacitor is electrically connected to the first power signal terminal, and a second electrode of the first capacitor is electrically connected to the third node.

6. The pixel circuit according to claim 1, wherein: Also includes: The second light-emitting control subcircuit includes a seventh transistor, a first electrode of the seventh transistor is electrically connected to the first power signal terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the second light-emitting control terminal.

7. A display panel, characterized in that: The device comprises a pixel circuit as claimed in any one of claims 1 to 6.

8. The display panel according to claim 7, wherein: Also includes: a plurality of cascaded first shift registers and a plurality of cascaded second shift registers, The number of the first shift registers is less than the number of rows of the pixel circuits and the number of the second shift registers is less than N, or the number of the first shift registers is equal to the number of rows of the pixel circuits and the number of the second shift registers is equal to N; The first shift registers are cascaded and then cascaded with the plurality of cascaded second shift registers to form a first gate driving circuit. The first gate driving circuit provides signals to the second reset control terminal and the first reset control terminal.

9. The display panel according to claim 8, wherein: The display panel includes a display area and a non-display area surrounding the display area. The non-display area includes an extension area arranged in an extension direction of the pixel circuit row, The number of the first shift registers is half the number of the rows of pixel circuits, and the range occupied by each of the first shift registers in the arrangement direction of the pixel circuit rows overlaps with the extension areas corresponding to two of the pixel circuit rows.

10. The display panel according to claim 8, wherein The display area includes a display area and a non-display area surrounding the display area, wherein the display area includes a first side and a second side and a third side intersecting the first side, and the non-display area includes a first side region adjacent to the first side, a second side region adjacent to the second side, and a third side region adjacent to the third side. The second shift register is disposed in a corner region between the first side region and the second side region or in a corner region between the first side region and the third side region.

11. The display panel according to claim 8, wherein: Also includes: A plurality of cascaded third shift registers and a plurality of cascaded fourth shift registers, the display panel comprising a display area and a non-display area surrounding the display area, The display panel includes M pixel circuit rows arranged in the display area, the pixel circuit includes a writing subcircuit, and the writing subcircuit transmits a signal connected to the data signal terminal to the first node based on a signal from the data control terminal. The non-display area includes a first side region close to one end of the pixel circuit row and a fourth side region close to the other end of the pixel circuit row. The third shift register is disposed in one of the first side region and the fourth side region, and an output terminal of the nth third shift register is electrically connected to the data control terminal in the 2n-1th pixel circuit row. The fourth shift register is disposed in the other of the first side region and the fourth side region, and an output terminal of the nth fourth shift register is electrically connected to the data control terminal in the 2nth pixel circuit row. n is an integer greater than or equal to 1, and M is an integer greater than or equal to 2.

12. The display panel according to claim 11, wherein: The display panel includes a display area and a non-display area surrounding the display area. The non-display area includes an extension area arranged in an extension direction of the pixel circuit row, The range occupied by each of the third shift registers in the arrangement direction of the pixel circuit rows overlaps with the extension areas of two of the pixel circuit rows. The range occupied by each of the fourth shift registers in the arrangement direction of the pixel circuit rows overlaps with the extension areas of two of the pixel circuit rows.

13. The display panel according to claim 8, wherein: The number of the first shift registers is half the number of rows of the pixel circuits, and the display panel further includes a display area and a non-display area surrounding the display area. The display panel further includes: M pixel circuit rows arranged in the display area, the pixel circuit including a writing subcircuit, the writing subcircuit transmitting a signal connected to the data signal terminal to the first node based on a signal from the data control terminal; cascaded M third shift registers and cascaded M fourth shift registers, The non-display area includes a first side region close to one end of the pixel circuit row and a fourth side region close to the other end of the pixel circuit row. One of the third shift register and the fourth shift register is arranged in the first side region, and the other is arranged in the fourth side region. The output terminals of the nth third shift register and the nth fourth shift register are both electrically connected to the data control terminal in the nth pixel circuit row. n is an integer greater than or equal to 1, and M is an integer greater than or equal to 2.

14. The display panel according to claim 8, wherein It also includes a display area and a non-display area surrounding the display area, The display panel further includes: M pixel circuit rows are provided in the display area, the pixel circuits including a compensation subcircuit, the compensation subcircuit electrically connecting the second node and a third node corresponding to the control electrode of the driving transistor based on a signal from a compensation control terminal; and cascaded M / 2 fifth shift registers and cascaded M / 2 sixth shift registers, The non-display area includes a first side region close to one end of the pixel circuit row and a fourth side region close to the other end of the pixel circuit row. One of the fifth shift register and the sixth shift register is arranged in the first side region, and the other is arranged in the fourth side region. The output terminal of each of the fifth shift registers is electrically connected to the compensation control terminals of two adjacent rows of pixel circuits at the same time. The output end of each of the sixth shift registers is electrically connected to the first light emitting control ends of two adjacent rows of pixel circuits at the same time. M is an integer greater than or equal to 2.

15. A display device, characterized in that: The device comprises a display panel as claimed in any one of claims 7 to 14.

16. A driving method for a pixel circuit according to any one of claims 1 to 6, characterized in that: include: In the first reset stage, the first reset sub-circuit transmits the potential of the first reset signal terminal to the second node based on the signal connected to the first reset control terminal being at a valid level; In a second reset phase, the second reset sub-circuit transmits the potential of the second reset signal terminal to the first node based on the signal connected to the second reset control terminal being at a valid level, and the duration of the second reset phase is delayed by N Hs compared to the first reset phase; In the light emitting control stage, based on the signal of the first light emitting control terminal being at a valid level, the driving current is transmitted to the first electrode and the light emitting unit is driven to emit light.

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