Storage chip testing method and device, computer device, and storage medium

Abstract

The present disclosure provides a storage chip test method and device, computer equipment and storage medium, and relates to the technical field of semiconductors. The method comprises the following steps: performing M times of burn-in cycle tests on a storage chip, M being a positive integer greater than 0, each burn-in cycle test comprising the following steps: performing N times of write operations on the storage chip, wherein N is a positive integer greater than 1; verifying the storage chip after the N times of write operations are performed to obtain a verification result; and obtaining a burn-in test result based on M verification results of the storage chip after the burn-in cycle test. The present disclosure obtains the burn-in test result based on the M verification results after performing the M times of burn-in cycle tests, thereby reducing the probability of misjudging the storage chip as a failed product due to slight poor contact. In addition, the storage chip is verified after the N times of write operations are performed, thereby reducing the number of verifications in the burn-in test process, and further reducing the burn-in test duration and test cost.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method, apparatus, computer equipment, and computer-readable storage medium for testing memory chips. Background Technology

[0002] In the field of semiconductor technology, semiconductor products such as memory chips require multiple processing steps. To ensure the quality of semiconductor products, testing is performed after manufacturing to detect any damage during the manufacturing process and identify defective products. This is known as burn-in testing. Burn-in testing typically places the product under test in a high-temperature environment to detect products that are on the verge of damage or have poor quality under stringent testing conditions. The goal is for the product to pass the early testing and enter a stable period, so that it can provide stable product characteristics when used by consumers.

[0003] Existing collapse tests are time-consuming, costly, and have a high false positive rate for defective products.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] This disclosure provides a method, apparatus, equipment, and medium for testing memory chips, which at least to some extent overcomes the problems of long testing time, high testing cost, and high false positive rate of failed products in stress testing.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a method for testing a memory chip is provided, the method comprising:

[0008] The memory chip is subjected to M collapse cycle tests, where M is a positive integer greater than 0. Each collapse cycle test includes the following steps:

[0009] Perform N write operations on the memory chip, where N is a positive integer greater than 1;

[0010] After performing N write operations, the memory chip is verified to obtain the verification results;

[0011] Based on the M verification results of the memory chip after the collapse cycle test, the collapse test result is obtained.

[0012] In one embodiment of this disclosure, the memory chip includes a function configuration storage area, the function configuration storage area including at least one frequency selection bit, the frequency selection bit storing an N value.

[0013] In one embodiment of this disclosure, N write operations are performed on the memory chip, each write operation including at least one of the following: performing an erase operation on the memory chip; performing a programming operation on the memory chip.

[0014] In one embodiment of this disclosure, the step of verifying the memory chip after performing N write operations to obtain a verification result includes: performing a programming operation on the memory chip after performing N write operations, and verifying the memory chip after the programming operation is completed to obtain a first verification result; and / or performing an erase operation on the memory chip after performing N write operations, and verifying the memory chip after the erase operation is completed to obtain a second verification result; and obtaining a verification result based on the first verification result and / or the second verification result.

[0015] In one embodiment of this disclosure, the collapse test result is obtained based on the M verification results of the memory chip after the collapse cycle test, including: if the i-th verification result and all subsequent verification results of the memory chip after the i-th verification result are all verified as passed, the collapse test result is passed, where i is a positive integer less than or equal to M.

[0016] In one embodiment of this disclosure, the memory chip includes a programmable memory region for storing the verification results corresponding to each crash cycle test.

[0017] In one embodiment of this disclosure, each collapse cycle test further includes: obtaining the number Q of write operations performed in the current collapse cycle test, where Q is a positive integer less than or equal to N; if Q is less than N, then activating the write operation circuit, which is used to perform write operations on the memory chip; if Q is equal to N, then activating the verification circuit and storing the verification result in the programmable memory area, wherein the activation of the verification circuit is used to verify the memory chip.

[0018] In one embodiment of this disclosure, before obtaining the collapse test result based on the M verification results of the memory chip after the collapse cycle test, the method further includes: when the verification result corresponding to the Mth collapse cycle test is obtained from the programmable memory region, ending the collapse cycle test.

[0019] According to another aspect of this disclosure, a memory chip testing apparatus is provided, the apparatus comprising:

[0020] The collapse cycle test module is used to perform M collapse cycle tests on the memory chip, where M is a positive integer greater than 0. Each collapse cycle test includes the following steps:

[0021] Perform N write operations on the memory chip, where N is a positive integer greater than 1;

[0022] After performing N write operations, the memory chip is verified to obtain the verification results;

[0023] The test result calculation module is used to obtain the collapse test result based on the M verification results of the memory chip after the collapse cycle test.

[0024] According to another aspect of this disclosure, a computer device is provided, including one or more processors; and a memory configured to store one or more programs, which, when executed by the one or more processors, cause the computer device to implement the memory chip testing method of any embodiment of this disclosure.

[0025] According to another aspect of this disclosure, a computer-readable storage medium is provided that stores a computer program adapted to be loaded and executed by a processor, such that a computer device having the processor performs a memory chip testing method according to any embodiment of this disclosure.

[0026] According to another aspect of this disclosure, a computer program product is provided, the computer program product comprising a computer program or computer instructions, the computer program or computer instructions being loaded and executed by a processor to enable a computer to implement any of the memory chip testing methods described above.

[0027] The memory chip testing method, apparatus, device, and medium provided in the embodiments of this disclosure perform M collapse cycle tests on the memory chip. Each collapse cycle test performs N write operations on the memory chip. After completing N write operations, the memory chip is verified to obtain verification results. In other words, M collapse cycle tests are performed on the memory chip to obtain M verification results. After all M collapse cycle tests are completed, a collapse test result is obtained based on the M verification results. This disclosure reduces the probability of a memory chip being falsely identified as a defective product due to minor contact defects. Furthermore, verifying the memory chip after N write operations reduces the number of verification operations during the collapse test, thereby reducing the collapse test duration and lowering testing costs.

[0028] Furthermore, this disclosure stores the N value in the functional configuration area of ​​the memory chip, thereby preventing the N value from being arbitrarily changed, ensuring the security of the N value while guaranteeing the reliability of the collapse test.

[0029] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0030] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0031] Figure 1 This diagram illustrates a memory chip testing system architecture according to an embodiment of the present disclosure.

[0032] Figure 2 A flowchart of a memory chip testing method according to an embodiment of this disclosure is shown.

[0033] Figure 3 This diagram illustrates the distribution of the storage regions of the memory chip in an embodiment of the present disclosure.

[0034] Figure 4 A schematic diagram of a memory chip testing apparatus is shown in an embodiment of this disclosure.

[0035] Figure 5 A schematic diagram of the structure of a computer device according to an embodiment of the present disclosure is shown.

[0036] Figure 6 This illustration shows a schematic diagram of a computer-readable storage medium provided in an embodiment of the present disclosure. Detailed Implementation

[0037] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0038] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0039] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0040] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0041] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0042] To facilitate understanding, the following is an explanation of several terms used in this disclosure:

[0043] The function configuration storage area stores the function configuration information of the memory chip. For example, the function configuration information can be data stored in the trim bit, and the frequency selection bit can be one bit in the trim bit. The value of the frequency selection bit is programmed at the factory.

[0044] Programmable memory regions are used to store various status flag information within the memory chip. For example, a programmable memory region can be a fuse array of the memory chip. The programmable memory region includes multiple storage bits, which can store the verification results corresponding to each collapse cycle test.

[0045] In the field of semiconductor technology, in order to evaluate the performance of memory chips under extreme operating conditions, it is necessary to perform stress tests on semiconductor chips.

[0046] In related technologies, multiple erase and programming operations are performed on the memory chip, and a full chip read verification is required after each erase and programming operation to determine whether the erase and programming were successful. If the erase and programming verification fails, the process stops, and the chip is identified as a defective product. This technology requires a full chip read verification after each erase and programming operation, which is time-consuming, costly, and has a high false positive rate for defective products.

[0047] The inventors discovered that in collapse stress testing, due to the need for large-scale testing, the testing cycle is relatively long. Furthermore, errors often occur midway through the test due to reasons not related to the product itself (such as poor contact on the test board), leading to premature termination and a high false positive rate for failed products. It should be noted that poor contact on the test board can be due to poor contact between the memory chip and the socket on the test board, or other types of contact problems. Therefore, a memory chip testing method is provided that can shorten the test time, reduce testing costs, and lower the false positive rate for failed products.

[0048] The following detailed description of this exemplary implementation method is provided in conjunction with the accompanying drawings and embodiments.

[0049] To facilitate a comprehensive understanding of the technical solutions provided in the embodiments of this disclosure, the memory testing system provided in the embodiments of this disclosure will be described first.

[0050] Figure 1 A schematic diagram of a memory chip testing system architecture according to an embodiment of this disclosure is shown. Figure 1 As shown, the memory chip testing system 10 may include a control device 11 and a test board 12.

[0051] The control device 11 can be a host computer with control functions (such as a test bench), which can control the memory chip testing of one or more test boards 12. The control device 11 can send various instructions to the test boards 12, such as stress test commands and data read commands. In some embodiments, the control device 11 can also receive selection operations from operators for the memory chip to be tested, so as to flexibly select the memory chip to be tested from the memory chips 13 connected to the test board 12 as needed, thereby improving the flexibility of memory chip testing.

[0052] The test board 12 can be connected to one or more memory chips 13, wherein the memory chip 13 can be a single memory die or multiple memory dies. The test board 12 can be used to perform at least one collapse cycle test on the memory chip 13, and can also, after performing all collapse cycle tests, obtain collapse test results based on multiple verification results of the memory chip 13 after the collapse cycle tests. The test board 12 can be an Automatic Test Equipment (ATE), but this disclosure is not limited to this; any device that can implement the above functions is acceptable.

[0053] For example, several memory chips 13 (e.g., the number of memory chips is 10K) are configured on the same test board 12. The test board 12 receives a collapse test command, performs parallel tests on the memory chips 13, performs multiple collapse cycle tests on the memory chips 13 in parallel, and after the test, obtains the collapse test result corresponding to the memory chip 13 based on the test results of the multiple collapse cycle tests (hereinafter referred to as the verification result).

[0054] The test board 12 can respond to a stress test command sent by the control device 11, locate the memory chip to be tested in the connected memory chip 13, and then test it. It should be noted that the memory chip 13 may include at least one physical memory bank 131, the physical memory bank 131 includes multiple dies 132, the dies 132 may include multiple banks, the banks may include multiple arrays, and each array includes multiple cells.

[0055] In terms of connection method, in some exemplary embodiments, the control device 11 and the test board 12 can communicate via wired connection. For example, to save communication costs, the control device 11 and the test board 12 can communicate via serial port. It should be noted that the control device 11 and the test board 12 can also choose parallel communication or wireless communication, etc., depending on the actual application scenario and specific application requirements; no specific limitations are imposed on this.

[0056] In the exemplary embodiments of this disclosure, the memory chip is placed on a test board 12, which is connected to a testing machine controlled by a computer system. After the operator writes the test program, the testing machine sends corresponding instructions to each pin of the memory chip on the test board (disruption test board) at different test time points according to the program settings to perform operations such as erase / program / verify. The testing machine can output a log file (a text file used to record events, states, and error information generated during the operation of a system or application) in txt (a text format) notepad format to record relevant information during each disruption test cycle, which can be saved in the computer system of the testing machine. A complete memory chip test can output one or more log files, and this disclosure is not limited to this. The log file records a lot of information throughout the test process, including the testing machine number, time, temperature, memory chip number, disruption test results, etc. In addition, the log file records the results of operations such as erase / program / verify during the test using different letters or symbols.

[0057] This disclosure provides a method for testing memory chips, which can be executed by any electronic device with computing capabilities. For example, the method can be executed by semiconductor manufacturing equipment such as automated testing equipment, or by other processing devices communicatively connected to the semiconductor manufacturing equipment; no specific limitations are imposed.

[0058] Figure 2 A flowchart of a memory chip testing method according to an embodiment of this disclosure is shown, as follows: Figure 2 As shown, the memory chip testing method provided in this embodiment may include performing M collapse cycle tests on the memory chip, where M is a positive integer greater than 0. Each collapse cycle test may include the following steps S201 and S202.

[0059] S201 performs N write operations on the memory chip, where N is a positive integer greater than 1.

[0060] In the embodiments of this disclosure, N write operations are performed on the memory chip. Each write operation may include at least one of the following: performing an erase operation on the memory chip; performing a programming operation on the memory chip. For example, performing N write operations on the memory chip may include: first performing an erase operation on the memory chip, and then performing a programming operation on the memory chip. As another example, performing N write operations on the memory chip may include: first performing a programming operation on the memory chip, and then performing an erase operation on the memory chip. The embodiments of this disclosure are not limited to these examples.

[0061] This disclosure does not limit the value of N. For example, the value of N can be in the range of 2-50, and the value of N can be any value among 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 14, 15, 18, 20, 26, 28, 30, 32, 34, 36, 40, 42, 44, 48, and 50.

[0062] For example, when performing a write operation on a memory chip, it can be performed on the entire memory array of the memory chip, or it can be performed sequentially after partitioning the memory array of the memory chip.

[0063] It should be noted that the memory chip in this embodiment can be NOR FLASH. For NOR FLASH memory cells, whether the information recorded by the memory cell is 0 or 1 depends on whether a large amount of charge is stored in the gate oxide layer. The programming process is to send the charge into the gate oxide layer, and the erasing process is to remove the charge from the gate oxide layer.

[0064] This disclosure allows for the detection of memory chips that are on the verge of damage or have poor quality (failed products) during the testing phase by performing multiple write operations on the memory chip. Early detection of failed products can improve the reliability of the memory chip.

[0065] S202, after performing N write operations, verifies the memory chip and obtains the verification result.

[0066] In this embodiment of the disclosure, after performing N write operations, verifying the memory chip to obtain a verification result may include: after performing N write operations, performing a programming operation on the memory chip, and verifying the memory chip after the programming operation is completed to obtain a first verification result; and / or, after performing N write operations, performing an erase operation on the memory chip, and verifying the memory chip after the erase operation is completed to obtain a second verification result; and obtaining a verification result based on the first verification result and / or the second verification result.

[0067] In one exemplary embodiment, after N write operations are performed, a programming operation is performed on the memory chip. After the programming operation is completed, the memory chip is verified to obtain a first verification result, and a final verification result is obtained based on the first verification result. For example, after N write operations are performed, a programming operation is performed on the memory chip, that is, "1" is written into the memory chip. Then, a read operation is performed on the memory chip for verification. If the read result is "1", the verification result is considered successful. If the read result is "0", which is different from the data "1" written during programming, the verification result is considered unsuccessful.

[0068] In this embodiment of the disclosure, the memory chip is programmed and verified after N write operations are performed, thereby reducing the total number of verification operations, shortening the test time, and reducing the test cost.

[0069] In another exemplary embodiment, after N write operations are performed, an erase operation is performed on the memory chip. After the erase operation is completed, the memory chip is verified to obtain a second verification result. Based on the second verification result, a verification result is obtained. For example, after N write operations are performed, an erase operation is performed on the memory chip, that is, "0" is written to the memory chip. Then, a read operation is performed on the memory chip for verification. If the read result is "0", it means that the verification result is passed. If the read result is "1", it is different from the data "0" written in the program, so the verification result is failed.

[0070] In this embodiment of the disclosure, after performing N write operations, the memory chip is then erased and verified, thereby reducing the total number of verification operations, shortening the test time, and reducing the test cost.

[0071] In another exemplary embodiment, after N write operations are performed, a programming operation is performed on the memory chip. After the programming operation is completed, the memory chip is verified to obtain a first verification result. Then, an erase operation is performed on the memory chip. After the erase operation is completed, the memory chip is verified to obtain a second verification result. Based on the first and second verification results, a verification result is obtained. For example, after N write operations are performed, a programming operation is performed on the memory chip, that is, "1" is written into the memory chip. Then, a read operation is performed on the memory chip for verification. If the read result is "1", it means the first verification result is passed. Then, an erase operation is performed on the memory chip, that is, "0" is written into the memory chip. Then, a read operation is performed on the memory chip for verification. If the read result is "0", it means the second verification result is passed. When both the first and second verification results are passed, the verification result is passed.

[0072] It should be noted that the information in the memory chip is different after the programming operation and the erasure operation. Therefore, verification should be performed separately after the programming operation and the information verified is different. Performing separate verification after the programming operation and the erasure operation helps to improve the reliability of the verification results and improve the accuracy of identifying defective products.

[0073] In this embodiment of the present disclosure, after performing N write operations, a verification result is obtained based on the first verification result and the second verification result. The reliability of the verification result is higher, thereby improving the accuracy of identifying defective products.

[0074] Based on the M verification results of the memory chip after the collapse cycle test, the collapse test results are obtained.

[0075] This disclosure does not limit the value of M. The value of M can be set according to the actual application scenario and specific application requirements. For example, the range of M can be 2-100, and the value of M can be any value among 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 16, 18, 20, 24, 26, 28, 30, 32, 34, 36, 40, 42, 44, 48, 50, 55, 60, 65, 70, 75, 80, 85, 90, 95, and 100.

[0076] In an exemplary embodiment, obtaining the collapse test result based on the M verification results of the memory chip after the collapse cycle test may include: if the i-th verification result and all subsequent verification results among the M verification results of the memory chip after the collapse cycle test are verified as passed, the collapse test result is considered passed, where i is a positive integer less than or equal to M.

[0077] Regarding the value of i, this disclosure does not limit it. The value of i can be set according to the actual application scenario and specific application requirements. For example, the value of i is in the range of 2-80, and the value of M can be any value among 2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 16, 18, 20, 26, 28, 30, 32, 34, 36, 40, 42, 44, 48, 50, 55, 60, 65, 70, 75, and 80.

[0078] For example, if all verification results after the third verification result out of 20 verification results for the memory chip following the collapse cycle test are passed, the collapse test result is considered passed. For instance, if all verification results from the third to the twentieth are passed, the collapse test result is considered passed. The 20 verification results are shown in Table 1 below.

[0079] Table 1 Verification Results

[0080] 1st time 2nd time 3rd time 4th … 19th 20th Not approved Not approved pass pass pass pass pass

[0081] For example, if the 5th verification result and all subsequent verification results out of 20 verification results after the collapse cycle test are all passed, the collapse test result is considered passed. For instance, if the 5th to 20th verification results are consecutively passed, the collapse test result is considered passed. The 20 verification results are shown in Table 2 below.

[0082] Table 2 Validation Results

[0083] 1st time 2nd time 3rd time 4th 5th … 20th Not approved Not approved pass Not approved pass pass pass

[0084] It should be noted that if, after the collapse cycle test, the i-th verification result and all subsequent verification results pass consecutively out of the M verification results of the memory chip, the collapse test result is considered passed. This embodiment of the present disclosure will not stop the testing of the memory chip due to a failed collapse cycle test, thereby reducing the probability of a normal memory chip being mistakenly identified as a failed memory chip due to minor contact defects. It should also be noted that in related technologies, during the BI (Burn-In) process, memory chips may experience sporadic and intermittent errors during the collapse process due to minor contact defects, thus being considered as FAIL products.

[0085] This disclosure reduces the total number of judgments / verifications without reducing the number of programming and erasing operations. While ensuring measurement quality, it reduces the probability of a memory chip being falsely identified as a defective product due to minor contact issues, thus lowering the false defect rate. Furthermore, verifying the memory chip after N write operations reduces the number of verifications / judgments during stress testing, thereby reducing stress testing time and lowering testing costs.

[0086] The storage areas of the memory chip are described below.

[0087] like Figure 3 As shown, the storage area of ​​the memory chip includes a main storage area 31, which is the memory cell array of the memory chip. The main storage area 31 is used to store user data. The memory cell array other than the main storage area 23 is called a fixed area. That is, the memory cell array can include multiple storage areas. The storage area used to store user data is the main storage area 31, and the other storage areas are the storage areas outside the main storage area 31 (also called fixed areas). The main storage area 31 can include a main array 311, a specific area 312, and a function configuration storage area 313. Among them, the main storage array 311 is the storage area used to store user data, and the specific area 312 can be a fuse array in a mini array. Various information of registers (such as the SR (Set-Reset, SR) register) is also stored in the fuse array, which can be understood as a register area. The function configuration storage area 313 is used to store the function configuration information of the memory chip.

[0088] In one exemplary embodiment, the memory chip may include a function configuration memory area, which may include at least one frequency selection bit storing an N value.

[0089] In this embodiment, the function configuration storage area is used to store the function configuration information of the memory chip. For example, the function configuration information can be data stored in the trim bit, and the frequency selection bit can be one bit in the trim bit. The value of the frequency selection bit is programmed at the factory, meaning that the value of the frequency selection bit is not easily changed and has good stability.

[0090] In the memory chip testing process, this disclosure first performs N programming-erase operations, then performs programming-verification-erase-verification operations, and repeats these operations M times in a loop. A corresponding speed switch (frequency selection bit) is designed inside the memory chip to adjust the number of programming-erase operations performed in a single crash cycle test, that is, to adjust the frequency of inserting read verification operations after the memory chip's erase and programming operations. This disclosure allows for the selection of different speed settings for memory chips of different qualities.

[0091] In this embodiment, the value programmed into the frequency selection bit is used to determine the value of N. That is, the adjustment of different levels is achieved by configuring different values ​​of the frequency selection bit. The memory chip reserves corresponding frequency selection bits to adjust the frequency of the verification operation. For example, two frequency selection bits are reserved, and the two frequency selection bits can have four values, namely 00 / 01 / 10 / 11. 00 / 01 / 10 / 11 can be configured to four frequencies. "00" corresponds to 4 erase operations - programming operation followed by 1 erase operation - verification - programming operation - verification, and so on, meaning the value of N is 4; "01" corresponds to 8 erase operations - programming operation followed by 1 erase operation - verification - programming operation - verification, and so on, meaning the value of N is 8; "10" corresponds to 12 erase operations - programming operation followed by 1 erase operation - verification - programming operation - verification, and so on, meaning the value of N is 12; "11" corresponds to 16 erase operations - programming operation followed by 1 erase operation - verification - programming operation - verification, and so on, meaning the value of N is 16. For example, 3 frequency selection bits can be combined to produce 8 frequencies. The number of frequency selection bits can be set according to the actual application scenario and application needs, and this disclosure is not limited to this.

[0092] This disclosure allows different values ​​to be configured on the frequency selection bit according to the quality of the memory chip, thereby performing different numbers of write operations on the memory chip in each collapse cycle test. This saves test time and reduces test costs while meeting testing requirements. Furthermore, this disclosure allows different values ​​to be configured on the frequency selection bit, thus improving testing flexibility.

[0093] In related technologies, the log files output by the collapse test are stored on the test machine, and there is a lot of redundant information, which is not conducive to timely viewing and analysis of the required content (such as the verification results of programming operations and erasure operations).

[0094] In another exemplary embodiment, the memory chip may include a programmable memory region for storing the verification results corresponding to each crash cycle test.

[0095] In this embodiment of the disclosure, the information in the programmable storage area can be rewritten by instructions, and the manufacturer / designer can choose whether to provide customers with the ability to rewrite this information.

[0096] The programmable storage area may include multiple storage bits, which can be used to store the verification result corresponding to each collapse cycle test, and can also be used to store the number M of collapse cycle tests, but this disclosure is not limited thereto. This disclosure does not limit the number of storage bits. For example, the number of storage bits in the programmable storage area may be greater than or equal to M. It should be noted that this disclosure needs to ensure that there are sufficient storage bits in the programmable storage area to record complete information even when performing the maximum number of collapse cycle tests.

[0097] For example, the programmable storage region has M storage bits, and each storage bit corresponds to storing a verification result. For instance, the 5th storage bit is used to store the verification result corresponding to the 5th collapse loop test. If the data in the 5th storage bit is 1, it indicates that the verification result corresponding to the 5th collapse loop test is passed. If the data in the 5th storage bit is 0, it indicates that the verification result corresponding to the 5th collapse loop test is failed.

[0098] It should be noted that even if the verification result fails midway through the embodiment of this disclosure, the test will continue until the set number of M times is reached. The result of each test will be recorded. If a few fail midway but then pass continuously, it can be considered as a poor contact midway and the memory chip will not be considered a defective product.

[0099] This embodiment of the disclosure stores the verification results through the storage bits of the programmable storage area. When the verification result is unsuccessful during the test, the test will not stop. The erase and programming operations in the next collapse cycle test will still be performed normally and the information will be recorded, thereby preventing verification failure caused by contact problems and reducing the probability of the memory chip being mistakenly judged as a defective product.

[0100] Furthermore, this embodiment of the disclosure does not require viewing and analyzing the crash test results from a large amount of redundant information through log files. This embodiment of the disclosure only uses the storage verification results stored on the storage bits of the programmable storage area to view and analyze the verification results in a timely manner, thereby obtaining the crash test results and shortening the crash test time.

[0101] The termination conditions for the collapse cycle test and the memory chip test are explained below.

[0102] In an exemplary embodiment, each collapse cycle test may further include: obtaining the number Q of write operations performed in the current collapse cycle test, where Q is a positive integer less than or equal to N; if Q is less than N, then initiating a write operation circuit, which is used to perform write operations on the memory chip; if Q is equal to N, then initiating a verification circuit and storing the verification result in a programmable memory area, wherein initiating the verification circuit is used to verify the memory chip.

[0103] In this embodiment, obtaining Q is helpful in determining whether the N write operations in the collapse cycle test have been completed. If Q equals N, it means that the N write operations have been completed, and the memory chip can then be verified. If Q is less than N, it means that the N write operations have not been completed, and further write operations need to be performed on the memory chip.

[0104] In this embodiment of the disclosure, the write operation circuit is used to perform a write operation on the memory chip, and the verification circuit can perform an erase operation before performing verification on the memory chip, and / or perform a programming operation before performing verification on the memory chip.

[0105] It should be noted that the value (gear) configured on the frequency selection bit corresponds to the working circuit to achieve the above functions. Each gear naturally requires different circuit logic and digital signal support, and the specific frequency can also be adjusted during the circuit design process according to different projects.

[0106] For example, assuming the verification frequency is 4 times for every 1 verification, and the cycle is 5 times, then the memory chip testing process is "erase operation - programming operation - erase operation - programming operation - erase operation - programming operation - erase operation - verification - programming operation - verification" repeated 5 times, for a total of 40 crash cycles. The purpose of multiple loops is to achieve the expected number of crash cycles, in order to quickly pass through the early high-failure stage in the bathtub curve.

[0107] In this embodiment of the disclosure, for the N write operations (programming operation-erase operation) in each collapse cycle test and the erase operation-verification operation-programming operation-verification operation inserted after the N write operations are completed, there are two circuit implementation forms:

[0108] One approach is to implement this through internal circuit logic. Before the number of program-erase cycles reaches N, the verification circuit is not enabled. After the number of program-erase cycles reaches N, the verification circuit is enabled and then disabled after the collapse cycle test is completed until the next write operation reaches N.

[0109] Another method is to control it using digital signals. This can be achieved using two digital signals: digital signal A controls the circuit for programming-erasing operations (write operation circuit), and digital signal B controls the circuit for programming-verification-erasing-verification operations (verification circuit). Signal A is active until the number of programming-erasing operations reaches N. Signal B becomes active after the number of programming-erasing operations reaches N, and this cycle repeats.

[0110] It should be noted that the frequency of read verification after a write operation during the collapse loop test is adjustable. In other words, the value of N is adjustable.

[0111] This embodiment of the disclosure determines whether N write operations have been completed by obtaining the total number of write operations from the first write operation to the current write operation, thereby realizing the testing of the memory chip. This embodiment of the disclosure can save testing time and cost, is highly flexible, and has wide applicability. Different read verification frequencies can be flexibly selected for memory chips of different qualities, reducing the number of judgments, reducing the probability of false judgments, and improving product yield.

[0112] In another exemplary embodiment, before obtaining the collapse test result based on the M verification results of the memory chip after the collapse cycle test, the method may further include: when the verification result corresponding to the Mth collapse cycle test is obtained from the programmable memory region, the collapse cycle test is terminated.

[0113] For example, if the programmable memory area stores the verification result corresponding to the Mth collapse cycle test, then the collapse cycle test ends. Based on the M verification results of the memory chip after the collapse cycle test, the collapse test result is obtained.

[0114] This disclosure, through different combinations of verification frequency (N) and cycle count (M), can cover the needs of tens to hundreds of collapse tests, offering high flexibility. It should be noted that, through different combinations of verification frequency and cycle count, this disclosure can also be used for collapse tests exceeding several hundred or more times; this disclosure does not limit this application.

[0115] Based on the same inventive concept, this disclosure also provides a memory chip testing device, as described in the following embodiments. Since the principle by which this device solves the problem is similar to that of the method embodiments described above, the implementation of this device embodiment can refer to the implementation of the method embodiments described above, and repeated details will not be elaborated further.

[0116] Figure 4 This diagram illustrates a memory chip testing apparatus according to an embodiment of the present disclosure, such as... Figure 4 As shown, the memory chip testing device may include a collapse cycle test module 41 and a test result calculation module 42.

[0117] The collapse loop test module 41 can be used to perform M collapse loop tests on the memory chip, where M is a positive integer greater than 0. Each collapse loop test includes the following steps:

[0118] Perform N write operations on the memory chip, where N is a positive integer greater than 1;

[0119] After performing N write operations, the memory chip is verified to obtain the verification results;

[0120] The test result calculation module 42 can be used to obtain the collapse test result based on the M verification results of the memory chip after the collapse cycle test.

[0121] In one embodiment, the memory chip includes a function configuration storage area, which includes at least one frequency selection bit storing an N value.

[0122] In one embodiment, the collapse cycle test module 41 can also be used to perform N write operations on the memory chip, each write operation including at least one of the following:

[0123] Perform an erase operation on the memory chip;

[0124] Perform programming operations on the memory chip.

[0125] In one embodiment, the collapse cycle test module 41 can also be used to program the memory chip after N write operations have been performed, and to verify the memory chip after the programming operation is completed to obtain a first verification result; and / or,

[0126] After N write operations are performed, an erase operation is performed on the memory chip, and after the erase operation is completed, the memory chip is verified to obtain a second verification result.

[0127] The verification result is obtained based on the first verification result and / or the second verification result.

[0128] In one embodiment, the test result calculation module 42 can also be used to determine the collapse test result as passed if the i-th verification result and all subsequent verification results among the M verification results of the memory chip after the collapse cycle test are verified as passed, where i is a positive integer less than or equal to M.

[0129] In one embodiment, the memory chip includes a programmable memory region for storing the verification results corresponding to each crash cycle test.

[0130] In one embodiment, the collapse cycle test module 41 can also be used to obtain the number of write operations Q performed in the current collapse cycle test, where Q is a positive integer less than or equal to N; if Q is less than N, the write operation circuit is started, and the write operation circuit is used to perform write operations on the memory chip; if Q is equal to N, the verification circuit is started, and the verification result is stored in the programmable memory area, wherein the start verification circuit is used to verify the memory chip.

[0131] In one embodiment, before obtaining the collapse test result based on the M verification results of the memory chip after the collapse cycle test, the collapse cycle test module 41 can also be used to end the collapse cycle test when the verification result corresponding to the Mth collapse cycle test is obtained from the programmable memory area.

[0132] In this embodiment, the memory chip testing device performs M collapse cycle tests before obtaining the collapse test result based on M verification results, thereby reducing the probability of a memory chip being mistakenly identified as a defective product due to minor contact defects. Furthermore, the memory chip is verified after N write operations, reducing the number of verifications during the collapse test, thus reducing the collapse test duration and lowering testing costs.

[0133] Furthermore, in this embodiment of the storage chip testing device, the N value is stored in the functional configuration area of ​​the storage chip, so that the N value cannot be changed arbitrarily, thus ensuring the security of the N value while ensuring the reliability of the collapse test.

[0134] Those skilled in the art will understand that various aspects of this disclosure can be implemented as a system, method, or program product. Therefore, various aspects of this disclosure can be specifically implemented in the following forms: a completely hardware implementation, a completely software implementation (including firmware, microcode, etc.), or a combination of hardware and software aspects, collectively referred to herein as a "circuit," "module," or "system."

[0135] See below. Figure 5 , Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of this disclosure. Figure 5As shown, the computer device in this embodiment may include one or more processors 501, a memory 502, and an input / output interface 503. The processor 501, memory 502, and input / output interface 503 are connected via a bus 504. The memory 502 stores a computer program, which includes program instructions. The input / output interface 503 receives and outputs data, such as for data interaction between the host machine and the computer device, or for data interaction between various virtual machines within the host machine. The processor 501 executes the program instructions stored in the memory 502.

[0136] The processor 501 can perform the following operations: perform M collapse loop tests on the memory chip, where M is a positive integer greater than 0. Each collapse loop test includes the following steps: perform N write operations on the memory chip, where N is a positive integer greater than 1; after performing N write operations, verify the memory chip and obtain the verification result; based on the M verification results of the memory chip after the collapse loop test, obtain the collapse test result.

[0137] The memory 502 may include read-only memory and random access memory, and provides instructions and data to the processor 501 and the input / output interface 503. A portion of the memory 502 may also include non-volatile random access memory. In implementation, the computer device can execute the implementation methods provided by the steps in any of the above method embodiments through its built-in functional modules, as shown in the figures of the above method embodiments, which will not be repeated here.

[0138] This disclosure provides a computer device including a processor, an input / output interface, and a memory. The processor retrieves a computer program from the memory and executes the steps of the method shown in any of the above embodiments.

[0139] This disclosure also provides a computer-readable storage medium storing a computer program. Figure 6 This illustration shows a schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure, such as... Figure 6 As shown, the computer-readable storage medium 600 stores a program product capable of implementing the methods described above. This computer program is adapted to be loaded by the processor and executed by the processor to perform the memory chip testing methods provided in any of the above embodiments.

[0140] In some possible implementations, various aspects of this disclosure may also be implemented as a program product comprising program code that, when run on a terminal device, causes the terminal device to perform the steps described in the foregoing “Detailed Description” section of this specification according to various exemplary embodiments of this disclosure.

[0141] More specific examples of computer-readable storage media in this disclosure may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0142] In this disclosure, a computer-readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of transmitting, propagating, or transmitting a program for use by or in connection with an instruction execution system, apparatus, or device.

[0143] Optionally, the program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0144] In practical implementation, program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0145] This disclosure provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the memory chip testing method provided in various alternative embodiments of this disclosure.

[0146] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0147] Furthermore, although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0148] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of this disclosure.

[0149] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope of this disclosure is indicated by the appended claims.

Claims

1. A method for testing memory chips, characterized in that, include: The memory chip is subjected to M collapse cycle tests, where M is a positive integer greater than 0. Each collapse cycle test includes the following steps: Perform N write operations on the memory chip, where N is a positive integer greater than 1; After performing N write operations, the memory chip is verified to obtain the verification results; Based on the M verification results of the memory chip after the collapse cycle test, the collapse test result is obtained; The step of verifying the memory chip after N write operations to obtain the verification result includes: After N write operations are performed, the memory chip is programmed, and after the programming operation is completed, the memory chip is verified to obtain a first verification result; and / or, After N write operations are performed, an erase operation is performed on the memory chip, and after the erase operation is completed, the memory chip is verified to obtain a second verification result. Based on the first verification result and / or the second verification result, a verification result is obtained.

2. The memory chip testing method according to claim 1, characterized in that, The memory chip includes a function configuration storage area, which includes at least one frequency selection bit, and the frequency selection bit stores an N value.

3. The memory chip testing method according to claim 1, characterized in that, Perform N write operations on the memory chip, each write operation including at least one of the following: Perform an erase operation on the memory chip; Perform programming operations on the memory chip.

4. The memory chip testing method according to claim 1, characterized in that, Based on the M verification results of the memory chip after the collapse cycle test, the collapse test results are obtained, including: The collapse test result is considered passed if all verification results of the memory chip after the collapse cycle test are passed, where i is a positive integer less than or equal to M.

5. The memory chip testing method according to claim 1, characterized in that, The memory chip includes a programmable memory area for storing the verification results corresponding to each crash cycle test.

6. The memory chip testing method according to claim 5, characterized in that, Each stress cycle test also includes: Get the number of write operations Q performed in the current crash loop test, where Q is a positive integer less than or equal to N; If Q is less than N, then the write operation circuit is activated, which is used to perform a write operation on the memory chip. If Q equals N, the verification circuit is activated and the verification result is stored in the programmable memory area, wherein the activation verification circuit is used to verify the memory chip.

7. The memory chip testing method according to claim 5 or 6, characterized in that, Before obtaining the collapse test result based on the M verification results of the memory chip after the collapse cycle test, the method further includes: When the verification result corresponding to the Mth collapse cycle test is obtained from the programmable storage area, the collapse cycle test ends.

8. A memory chip testing device, characterized in that, The device includes: The collapse cycle test module is used to perform M collapse cycle tests on the memory chip, where M is a positive integer greater than 0. Each collapse cycle test includes the following steps: Perform N write operations on the memory chip, where N is a positive integer greater than 1; After performing N write operations, the memory chip is verified to obtain the verification results; The test result calculation module is used to obtain the collapse test result based on the M verification results of the memory chip after the collapse cycle test; The collapse cycle test module is further configured to perform a programming operation on the memory chip after N write operations are completed, and verify the memory chip after the programming operation is completed to obtain a first verification result; and / or, perform an erase operation on the memory chip after N write operations are completed, and verify the memory chip after the erase operation is completed to obtain a second verification result; and obtain a verification result based on the first verification result and / or the second verification result.

9. A computer device, characterized in that, include: One or more processors; A memory configured to store one or more programs, which, when executed by the one or more processors, cause the computer device to perform the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is run on a computer, it causes the computer to perform the method as described in any one of claims 1 to 7.

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