Boot capacitor charging circuit, buck-boost converter, chip and electronic device

Abstract

The application provides a bootstrap capacitor charging circuit, a buck-boost converter, a chip and an electronic device. A detection circuit detects whether the voltage across the bootstrap capacitor is lower than a preset voltage, and transmits a third signal to a control circuit. The control circuit performs logical operation on the first signal, the second signal and the third signal to obtain a fourth signal, and transmits the fourth signal to the charging circuit to control the opening or closing of the charging circuit. Further, the charging circuit charges the bootstrap capacitor by using the power supply voltage provided by the positive voltage power supply according to the fourth signal until the voltage across the bootstrap capacitor is higher than the preset voltage, and stops charging. Since the bootstrap capacitor is charged by using the power supply voltage provided by the positive voltage power supply, the voltage across the bootstrap capacitor can be stabilized around the power supply voltage during the high resistance stage. Therefore, the bootstrap capacitor charging circuit does not need to additionally increase the complex timing logic, and can simplify the circuit structure and reduce the cost.

Description

Technical Field

[0001] This application relates to the field of power management chip technology, and in particular to a bootstrap capacitor charging circuit, a buck-boost converter, a chip, and electronic equipment. Background Technology

[0002] Switching power supplies are widely used in electronic products due to their high efficiency and high voltage regulation capabilities. A switching power supply can include a low-side power transistor, a high-side power transistor, and a bootstrap capacitor. Based on their basic topology, switching power supplies can be divided into three basic types: buck converters (Buck), boost converters (Boost), and buck-boost converters (Buck-Boost). For a Buck converter with a positive output voltage, during the turn-on phase of the low-side power transistor, the potential of the switching node between the source and drain of the high-side power transistor is directly pulled to ground, making the potential of the lower plate of the bootstrap capacitor grounded. This allows the Buck to directly charge the bootstrap capacitor during this phase. Therefore, the voltage across the charged bootstrap capacitor is approximately equal to the charging voltage, allowing the high-side power transistor to turn on normally. For a Buck-Boost converter with a negative output voltage, during the turn-on phase of the low-side power transistor, the potential of the lower plate of the bootstrap capacitor is approximately equal to the output voltage. Therefore, Buck-Boost requires a power supply with a negative output voltage to charge the bootstrap capacitor. In this case, the power supply is a negative voltage supply.

[0003] When the Buck-Boost converter is under light load, it operates in discontinuous conduction mode (DCM). In this mode, when both the high-side and low-side power transistors are off—that is, during the high-impedance phase of DCM—the lower plate of the bootstrap capacitor has a potential of 0, while the upper plate has a positive potential, preventing the negative power supply from charging the bootstrap capacitor. Even under extremely light load, the Buck-Boost switching cycle can be very long, potentially causing the charge stored in the bootstrap capacitor to dissipate. Consequently, when the high-side power transistor needs to be turned on in the next switching cycle, the voltage across the bootstrap capacitor is insufficient, preventing the high-side power transistor from turning on properly and causing the Buck-Boost converter to malfunction.

[0004] Therefore, if Buck-Boost still uses a negative voltage supply to charge the bootstrap capacitor, it requires more complex timing logic and corresponding charging circuitry. This results in the complexity and high cost of Buck-Boost circuits. The high-impedance stage refers to the stage where both the high-side and low-side power transistors are turned off. Summary of the Invention

[0005] This application provides a bootstrap capacitor charging circuit, a buck-boost converter, a chip, and an electronic device that can charge a bootstrap capacitor using a positive voltage power supply without adding complex timing logic, thus simplifying the bootstrap capacitor charging circuit and reducing costs.

[0006] In a first aspect, this application provides a bootstrap capacitor charging circuit, which is applied in a half-bridge buck-boost converter. The bootstrap capacitor charging circuit includes: a detection circuit, a control circuit, and a charging circuit;

[0007] The first input terminal of the detection circuit and the output terminal of the charging circuit are both electrically connected to the upper plate of the bootstrap capacitor in the buck-boost converter. The second input terminal of the detection circuit is electrically connected to the lower plate of the bootstrap capacitor. The output terminal of the detection circuit is electrically connected to the first input terminal of the control circuit. The second input terminal of the control circuit is used to receive a first signal, which is used to drive the low-side power transistor in the buck-boost converter to turn on or off. The third input terminal of the control circuit is used to receive a second signal, which is used to characterize whether the buck-boost converter has entered the high-impedance stage. The first output terminal of the control circuit is electrically connected to the control terminal of the charging circuit. The input terminal of the charging circuit is electrically connected to the positive voltage power supply.

[0008] When the buck-boost converter enters the high-impedance phase, or when the low-side power transistor is in the turn-on phase, wherein:

[0009] The detection circuit is used to detect whether the voltage across the bootstrap capacitor is lower than a preset voltage, obtain a third signal, and transmit the third signal to the control circuit.

[0010] The control circuit is used to perform logical operations on the first signal, the second signal, and the third signal to obtain a fourth signal when the second signal indicates that the buck-boost converter has entered the high impedance stage, and to transmit the fourth signal to the charging circuit. The fourth signal is used to control the charging circuit to turn on or off.

[0011] The charging circuit is used to charge the bootstrap capacitor using the power supply voltage provided by the positive voltage power supply according to the fourth signal, until the voltage across the bootstrap capacitor is higher than the preset voltage, and then stop charging.

[0012] The control circuit includes: a delay, a first AND gate, a second AND gate, a NAND gate, a NOR gate, a first inverter, and a second inverter.

[0013] The input terminal of the delay device is used to receive the first signal. The output terminal of the delay device is electrically connected to the first input terminal of the first AND gate and the first input terminal of the NAND gate. The second input terminal of the NAND gate and the input terminal of the first inverter are both electrically connected to the output terminal of the detection circuit. The output terminal of the NAND gate is electrically connected to the second input terminal of the first AND gate. The output terminal of the first AND gate is electrically connected to the first input terminal of the NOR gate. The output terminal of the first inverter is electrically connected to the first input terminal of the second AND gate. The second input terminal of the second AND gate is used to receive the second signal. The output terminal of the second AND gate is electrically connected to the second input terminal of the NOR gate. The output terminal of the NOR gate is electrically connected to the input terminal of the second inverter. The output terminal of the second inverter is electrically connected to the control terminal of the charging circuit.

[0014] The bootstrap capacitor charging circuit provided in the first aspect allows the detection circuit to detect whether the voltage across the bootstrap capacitor is lower than a preset voltage when the buck-boost converter enters the high-impedance stage or when the low-side power transistor is in the on stage. Upon receiving this third signal, the detection circuit obtains a third signal and transmits it to the control circuit, enabling the control circuit to acquire the third signal. The control circuit then performs logical operations on the first, second, and third signals to obtain a fourth signal, which is transmitted to the charging circuit to control its on / off state, allowing the charging circuit to acquire the fourth signal. Furthermore, the charging circuit can charge the bootstrap capacitor using the power supply voltage provided by the positive voltage source based on the fourth signal, until the voltage across the bootstrap capacitor exceeds the preset voltage, at which point charging stops. Because the charging circuit uses the power supply voltage provided by the positive voltage source to charge the bootstrap capacitor, the voltage across the bootstrap capacitor remains stable near the power supply voltage even when the buck-boost converter enters the high-impedance stage. Therefore, the bootstrap capacitor charging circuit does not require additional complex timing logic, thus simplifying the circuit structure and reducing costs.

[0015] In one possible design, the detection circuit includes: a voltage detection circuit, a pull-up current output circuit, a pull-down current output circuit, and a third signal output circuit;

[0016] The first input terminal of the voltage detection circuit is electrically connected to the upper plate of the bootstrap capacitor. The second input terminal of the voltage detection circuit and the input terminal of the pull-down current output circuit are both electrically connected to the lower plate of the bootstrap capacitor. The output terminal of the voltage detection circuit is electrically connected to the control terminal of the pull-down current output circuit. The output terminal of the pull-down current output circuit is electrically connected to the output terminal of the pull-up current output circuit. The input terminal of the pull-up current output circuit and the input terminal of the third signal output circuit are both electrically connected to the positive voltage power supply. The control terminal of the pull-up current output circuit is used to connect to the first bias current. The control terminal of the third signal output circuit is electrically connected between the output terminal of the pull-down current output circuit and the output terminal of the pull-up current output circuit. The output terminal of the third signal output circuit is electrically connected to the first input terminal of the control circuit.

[0017] The pull-up current output circuit is used to generate a pull-up current according to the power supply voltage under the action of the first bias current, and to transmit the pull-up current to the third signal output circuit.

[0018] The voltage detection circuit is used to detect whether the voltage across the bootstrap capacitor is lower than the preset voltage, obtain the control voltage, and transmit the control voltage to the pull-down current output circuit.

[0019] The pull-down current output circuit is used to generate a pull-down current under the action of the control voltage and transmit the pull-down current to the third signal output circuit.

[0020] The third signal output circuit is used to determine the potential of the control terminal of the third signal output circuit to be raised or lowered according to the relationship between the pull-up capability of the pull-up current and the pull-down capability of the pull-down current, so as to generate the third signal.

[0021] In one possible design, the detection circuit further includes a clamping circuit;

[0022] The first input terminal of the clamping circuit is electrically connected to the upper plate of the bootstrap capacitor, the second input terminal of the clamping circuit is electrically connected to the lower plate of the bootstrap capacitor, and the output terminal of the clamping circuit is electrically connected to the output terminal of the pull-down current output circuit.

[0023] The clamping circuit is used to pull up the potential of the control terminal of the third signal output circuit when the voltage across the bootstrap capacitor is equal to the clamping voltage, so as to clamp the voltage across the bootstrap capacitor to the clamping voltage.

[0024] In one possible design, the detection circuit further includes a hysteresis current output circuit;

[0025] The input terminal of the hysteresis current output circuit is electrically connected to the positive voltage power supply, the control terminal of the hysteresis current output circuit is electrically connected to the second output terminal of the control circuit, and the output terminal of the hysteresis current output circuit is electrically connected to the output terminal of the pull-up current output circuit.

[0026] The hysteresis current output circuit is used to obtain a fifth signal from the control circuit, and under the action of the fifth signal, generate the hysteresis current according to the power supply voltage, and transmit the hysteresis current to the pull-up current output circuit. The level of the fifth signal is opposite to the level of the fourth signal.

[0027] The pull-up current output circuit is used to increase the current value of the pull-up current under the action of the hysteresis current, so as to keep the third signal constant and avoid the third signal from floating at the flip point. The flip point refers to the moment when the third signal flips from the first level to the second level.

[0028] In one possible design, the hysteresis current output circuit includes: a first P-type transistor, a second P-type transistor, and a third P-type transistor;

[0029] The source of the first P-type transistor and the source of the second P-type transistor are both electrically connected to the positive voltage power supply. The gate of the first P-type transistor, the gate of the second P-type transistor, and the drain are all used to connect to the first bias current. The drain of the first P-type transistor is electrically connected to the source of the third P-type transistor. The gate of the third P-type transistor is electrically connected to the second output terminal of the control circuit. The drain of the third P-type transistor is electrically connected to the output terminal of the pull-up current output circuit.

[0030] In one possible design, the voltage detection circuit includes: a first N-type transistor, a second N-type transistor, and a first resistor;

[0031] The drain and gate of the first N-type transistor are both electrically connected to the upper plate of the bootstrap capacitor. The source of the first N-type transistor is electrically connected to the drain and gate of the second N-type transistor. The source of the second N-type transistor is electrically connected to the first terminal of the first resistor. The control terminal of the pull-down current output circuit is electrically connected between the source of the second N-type transistor and the first terminal of the first resistor. The second terminal of the first resistor is electrically connected to the lower plate of the bootstrap capacitor.

[0032] In one possible design, the clamping circuit includes: a diode, a second resistor, and a third N-type transistor;

[0033] The negative terminal of the diode is electrically connected to the upper plate of the bootstrap capacitor, the positive terminal of the diode is electrically connected to the first end of the second resistor, the second end of the second resistor and the source of the third N-type transistor are both electrically connected to the lower plate of the bootstrap capacitor, the gate of the third N-type transistor is electrically connected between the positive terminal of the diode and the first end of the second resistor, and the drain of the third N-type transistor is electrically connected to the output terminal of the pull-down current output circuit.

[0034] In one possible design, the third signal output circuit includes: a fourth P-type transistor and a buffer;

[0035] The source of the fourth P-type transistor is electrically connected to the positive voltage power supply, the gate of the fourth P-type transistor is electrically connected between the output terminal of the pull-down current output circuit and the output terminal of the pull-up current output circuit, the drain of the fourth P-type transistor and the input terminal of the buffer are both used to connect to the second bias current, and the output terminal of the buffer is electrically connected to the first input terminal of the control circuit.

[0036] In one possible design, the pull-up current output circuit includes: a fifth P-type transistor;

[0037] The source of the fifth P-type transistor is electrically connected to the positive voltage power supply, the gate of the fifth P-type transistor is used to connect to the first bias current, and the drain of the fifth P-type transistor is electrically connected to the output terminal of the pull-down current output circuit.

[0038] In one possible design, the pull-up current output circuit further includes: a sixth P-type transistor and a fourth N-type transistor;

[0039] The source of the sixth P-type transistor is electrically connected to the drain of the fifth P-type transistor, the gate of the sixth P-type transistor is grounded, the drain of the sixth P-type transistor is electrically connected to the source and gate of the fourth N-type transistor, and the drain of the fourth N-type transistor is electrically connected to the output terminal of the pull-down current output circuit.

[0040] In one possible design, the pull-down current output circuit includes: a fifth N-type transistor;

[0041] The drain of the fifth N-type transistor is electrically connected to the output terminal of the pull-up current output circuit, the gate of the fifth N-type transistor is electrically connected to the output terminal of the voltage detection circuit, and the source of the fifth N-type transistor is electrically connected to the lower plate of the bootstrap capacitor.

[0042] In one possible design, the charging circuit includes: a switching circuit, a charging tube, and a field-effect transistor;

[0043] The control terminal of the switching circuit is electrically connected to the first output terminal of the control circuit. The first terminal of the switching circuit and the source of the charging tube are both electrically connected to the positive voltage power supply. The second terminal of the switching circuit is electrically connected to the gate of the charging tube. The drain of the charging tube is electrically connected to the gate and source of the field-effect transistor, respectively. The drain of the field-effect transistor is electrically connected to the upper plate of the bootstrap capacitor.

[0044] The switching circuit is used to control the charging tube to turn on according to the fourth signal, so that the power supply voltage charges the bootstrap capacitor through the body diode of the field-effect transistor.

[0045] In one possible design, the switching circuit includes: a seventh P-type transistor and a sixth N-type transistor;

[0046] The gate of the seventh P-type transistor and the gate of the sixth N-type transistor are both electrically connected to the first output terminal of the control circuit. The source of the seventh P-type transistor is electrically connected to the positive voltage power supply. The drain of the seventh P-type transistor is electrically connected to the drain of the sixth N-type transistor. The gate of the charging transistor is electrically connected between the drain of the seventh P-type transistor and the drain of the sixth N-type transistor. The source of the sixth N-type transistor is grounded.

[0047] In a second aspect, this application provides a half-bridge buck-boost converter, comprising: a high-side power transistor, a low-side power transistor, an inductor, a bootstrap capacitor, and a bootstrap capacitor charging circuit in the first aspect and various possible designs of the first aspect.

[0048] The drain of the high-side power transistor is used to connect to the input voltage of the buck-boost converter. The source of the high-side power transistor is electrically connected to the drain of the low-side power transistor and the first terminal of the inductor. The source of the low-side power transistor is used to output the output voltage of the buck-boost converter. A switching node is provided between the source of the high-side power transistor and the drain of the low-side power transistor. The upper plate of the bootstrap capacitor is electrically connected to the output terminal of the bootstrap capacitor charging circuit. The lower plate of the bootstrap capacitor is electrically connected to the switching node. The gates of both the high-side power transistor and the low-side power transistor are used to connect to a drive signal. The drive signal is used to drive the gate of the high-side power transistor and the low-side power transistor to turn on or off. The second terminal of the inductor is grounded.

[0049] The beneficial effects of the buck-boost converter provided in the second aspect and the various possible designs of the second aspect can be found in the first aspect and the various possible implementations of the first aspect, and will not be repeated here.

[0050] Thirdly, this application provides a chip comprising: the bootstrap capacitor charging circuit in the first aspect and various possible designs of the first aspect, and / or the buck-boost converter in the second aspect.

[0051] Fourthly, this application provides an electronic device that includes the chip described in the third aspect above.

[0052] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of this application are described below. Attached Figure Description

[0053] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of a bootstrap capacitor charging circuit provided in an embodiment of this application;

[0055] Figure 2 This is a schematic diagram of a half-bridge buck-boost converter provided in an embodiment of this application. Detailed Implementation

[0056] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c alone can mean: a alone, b alone, c alone, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0057] The terms “center,” “longitudinal,” “lateral,” “up,” “down,” “left,” “right,” “front,” and “rear,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0058] The terms "connected" and "connected" should be interpreted broadly. For example, in circuit structures, "connected" or "connected" can refer not only to physical connections but also to electrical or signal connections. This could be a direct connection (physical connection) or an indirect connection via at least one intermediate component, as long as the circuit is connected. It could also refer to the internal connection between two components. Similarly, a signal connection can refer to a connection via a circuit or a medium, such as radio waves. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0059] First, the technical terms involved in the embodiments of this application will be explained.

[0060] DCM refers to the phenomenon where, in certain application scenarios, the inductor current in a buck-boost converter drops to zero during certain switching cycles. In this mode, to prevent the inductor current from continuing to flow and becoming a negative current, the buck-boost converter simultaneously turns off both the high-side and low-side power transistors when the inductor current is 0, keeping the inductor current at 0A to reduce power consumption waste.

[0061] The high-impedance stage refers to the stage where both the high-side power transistor and the low-side power transistor are turned off.

[0062] Next, combined Figure 1 The circuit structure of the bootstrap capacitor charging circuit 100 is described in detail.

[0063] Reference Figure 1 , Figure 1 This is a schematic diagram of a bootstrap capacitor charging circuit provided in an embodiment of this application. Figure 1 As shown, the bootstrap capacitor charging circuit 100 may include: a detection circuit 110, a control circuit 120, and a charging circuit 130.

[0064] The first input terminal of the detection circuit 110 and the output terminal of the charging circuit 130 are both electrically connected to the upper plate of the bootstrap capacitor CBST in the buck-boost converter 1000. The second input terminal of the detection circuit 110 is electrically connected to the lower plate of the bootstrap capacitor CBST. The output terminal of the detection circuit 110 is electrically connected to the first input terminal of the control circuit 120. The second input terminal of the control circuit 120 is used to input the first signal LSON_FB. The first signal LSON_FB is used to drive the low-side power transistor LS in the buck-boost converter 1000 to turn on or off. The third input terminal of the control circuit 120 is used to input the second signal HZ. The second signal HZ is used to characterize whether the buck-boost converter 1000 has entered the high-impedance stage. The first output terminal of the control circuit 120 is electrically connected to the control terminal of the charging circuit 130. The input terminal of the charging circuit 130 is electrically connected to the positive voltage power supply.

[0065] The detection circuit 110, control circuit 120 and charging circuit 130 can be set separately or integrated. This application embodiment does not make specific limitations on this.

[0066] For example, when the first signal LSON_FB is high, it drives the low-side power transistor LS to turn on. When the first signal LSON_FB is low, it drives the low-side power transistor LS to turn off.

[0067] For example, when the second signal HZ is high, it indicates that the buck-boost converter 1000 has entered the high-impedance stage. When the second signal HZ is low, it indicates that the buck-boost converter 1000 has not entered the high-impedance stage.

[0068] When the buck-boost converter 1000 enters the high-impedance stage, or when the low-side power transistor LS is in the turn-on stage:

[0069] The detection circuit 110 can detect whether the voltage across the bootstrap capacitor CBST is lower than a preset voltage, and obtain the third signal BOOT_CHG_OFF. Furthermore, the detection circuit 110 can transmit the third signal BOOT_CHG_OFF to the control circuit 120, enabling the control circuit 120 to acquire the third signal BOOT_CHG_OFF.

[0070] For example, when the voltage across the bootstrap capacitor CBST is detected to be lower than a preset voltage, the third signal BOOT_CHG_OFF is at a low level. When the voltage across the bootstrap capacitor CBST is detected to be higher than the preset voltage, the third signal BOOT_CHG_OFF is at a high level.

[0071] Thus, the control circuit 120 can perform logical operations on the first signal LSON_FB, the second signal HZ, and the third signal BOOT_CHG_OFF to obtain the fourth signal EN_CHG. Furthermore, the control circuit 120 can transmit the fourth signal EN_CHG to the charging circuit 130, enabling the charging circuit 130 to acquire the fourth signal EN_CHG.

[0072] The fourth signal EN_CHG is used to control the charging circuit 130 to turn on or off. For example, when the fourth signal EN_CHG is high, it controls the charging circuit 130 to turn on. When the fourth signal EN_CHG is low, it controls the charging circuit 130 to turn off.

[0073] The logic processing performed by the control circuit 120 includes AND, NOR, and AND-NOT combinational logic.

[0074] Then, the charging circuit 130 can be turned on according to the fourth signal EN_CHG. In this way, the charging circuit 130 can use the power supply voltage VDD provided by the positive voltage supply to charge the bootstrap capacitor CBST, causing the voltage across the bootstrap capacitor CBST to rise. Until the voltage across the bootstrap capacitor CBST exceeds a preset voltage, the third signal BOOT_CHG_OFF goes high, causing the fourth signal EN_CHG to go low, thus turning off the charging circuit 130. In this way, the charging circuit 130 stops charging.

[0075] Since the charging circuit 130 uses the power supply voltage VDD provided by the positive voltage supply to charge the bootstrap capacitor CBST, the voltage across the bootstrap capacitor CBST remains stable near the power supply voltage even when the buck-boost converter 1000 enters the high-impedance stage. Based on this, the bootstrap capacitor charging circuit 100 does not require additional complex timing logic, thus simplifying its circuit structure and reducing cost.

[0076] The bootstrap capacitor charging circuit, buck-boost converter, chip, and electronic device provided in this application, when the buck-boost converter enters the high-impedance stage or the low-side power transistor is in the on stage, the detection circuit can detect whether the voltage across the bootstrap capacitor is lower than a preset voltage, obtain a third signal, and transmit the third signal to the control circuit so that the control circuit can acquire the third signal. Thus, the control circuit can perform logical operations on the first, second, and third signals to obtain a fourth signal, and transmit the fourth signal to the charging circuit to control the on or off of the charging circuit so that the charging circuit can acquire the fourth signal. Furthermore, the charging circuit can charge the bootstrap capacitor using the power supply voltage provided by the positive voltage source according to the fourth signal until the voltage across the bootstrap capacitor is higher than the preset voltage, at which point charging stops. Because the charging circuit uses the power supply voltage provided by the positive voltage source to charge the bootstrap capacitor, the voltage across the bootstrap capacitor can remain stable near the power supply voltage even when the buck-boost converter enters the high-impedance stage. Based on this, the bootstrap capacitor charging circuit does not require additional complex timing logic. Therefore, the circuit structure of the bootstrap capacitor charging circuit can be simplified and the cost reduced.

[0077] Based on the description of the above embodiments, an exemplary possible implementation of the detection circuit 110 is provided. For example... Figure 1 As shown, the detection circuit 110 includes: a voltage detection circuit 111, a pull-up current output circuit 112, a pull-down current output circuit 113, and a third signal output circuit 114.

[0078] The first input terminal of the voltage detection circuit 111 is electrically connected to the upper plate of the bootstrap capacitor CBST. The second input terminal of the voltage detection circuit 111 and the input terminal of the pull-down current output circuit 113 are both electrically connected to the lower plate of the bootstrap capacitor CBST. The output terminal of the voltage detection circuit 111 is electrically connected to the control terminal of the pull-down current output circuit 113. The output terminal of the pull-down current output circuit 113 is electrically connected to the output terminal of the pull-up current output circuit 112. The input terminal of the pull-up current output circuit 112 and the input terminal of the third signal output circuit 114 are both electrically connected to the positive voltage power supply. The control terminal of the pull-up current output circuit 112 is used to connect the first bias current IB1. The control terminal of the third signal output circuit 114 is electrically connected between the output terminal of the pull-down current output circuit 113 and the output terminal of the pull-up current output circuit 112. The output terminal of the third signal output circuit 114 is electrically connected to the first input terminal of the control circuit 120.

[0079] Wherein, the first input terminal of the voltage detection circuit 111 is the first input terminal of the detection circuit 110, the second input terminal of the voltage detection circuit 111 is the second input terminal of the detection circuit 110, and the output terminal of the third signal output circuit 114 is the output terminal of the detection circuit 110.

[0080] Under the action of the first bias current IB1, the pull-up current output circuit 112 can generate a pull-up current according to the power supply voltage VDD. Furthermore, the pull-up current output circuit 112 can transmit the pull-up current to the third signal output circuit 114, enabling the third signal output circuit 114 to obtain the pull-up current.

[0081] The voltage detection circuit 111 can detect whether the voltage across the bootstrap capacitor CBST is lower than a preset voltage, thereby obtaining a control voltage. Furthermore, the voltage detection circuit 111 can transmit the control voltage to the pull-down current output circuit 113, enabling the pull-down current output circuit 113 to acquire the control voltage.

[0082] Thus, under the control voltage, the pull-down current output circuit 113 can generate a pull-down current. Furthermore, the pull-down current output circuit 113 can transmit the pull-down current to the third signal output circuit 114, enabling the third signal output circuit 114 to acquire the pull-down current.

[0083] Furthermore, the third signal output circuit 114 can determine whether to raise or lower the potential of its control terminal based on the relationship between the pull-up capability of the pull-up current and the pull-down capability of the pull-down current, so that the third signal output circuit 114 can generate the third signal BOOT_CHG_OFF. Thus, the detection circuit 110 can obtain the third signal BOOT_CHG_OFF.

[0084] Specifically, when the pull-up capability of the pull-up current is greater than the pull-down capability of the pull-down current, the potential of the control terminal of the third signal output circuit 114 is pulled high. Thus, the third signal BOOT_CHG_OFF is at a high level. When the pull-up capability of the pull-up current is less than the pull-down capability of the pull-down current, the potential of the control terminal of the third signal output circuit 114 is pulled low. Thus, the third signal BOOT_CHG_OFF is at a low level.

[0085] In summary, under the action of the first bias current, the pull-up current output circuit can generate a pull-up current based on the power supply voltage and transmit this pull-up current to the third signal output circuit, enabling the third signal output circuit to obtain the pull-up current. The voltage detection circuit can detect whether the voltage across the bootstrap capacitor is lower than a preset voltage, obtain a control voltage, and transmit this control voltage to the pull-down current output circuit, enabling the pull-down current output circuit to obtain the control voltage. Thus, under the action of the control voltage, the pull-down current output circuit can generate a pull-down current and transmit it to the third signal output circuit, enabling the third signal output circuit to obtain the pull-down current. Furthermore, the third signal output circuit can determine whether to raise or lower the potential of its control terminal based on the relationship between the pull-up and pull-down capabilities of the pull-up and pull-down currents to generate the third signal. Therefore, the detection circuit can obtain the third signal.

[0086] Based on the description of the above embodiments, another possible implementation of the detection circuit 110 is exemplarily described. For example... Figure 1 As shown, the detection circuit 110 may further include a clamping circuit 115.

[0087] The first input terminal of the clamping circuit 115 is electrically connected to the upper plate of the bootstrap capacitor CBST, the second input terminal of the clamping circuit 115 is electrically connected to the lower plate of the bootstrap capacitor CBST, and the output terminal of the clamping circuit 115 is electrically connected to the output terminal of the pull-down current output circuit 113.

[0088] When the voltage across the bootstrap capacitor CBST equals the clamping voltage, the clamping circuit 115 pulls up the potential of the control terminal of the third signal output circuit 114, making the third signal BOOT_CHG_OFF high. This causes the fourth signal EN_CHG to go low, turning off the charging circuit 130. Consequently, the charging circuit 130 stops charging the bootstrap capacitor CBST. Thus, the clamping circuit 115 clamps the voltage across the bootstrap capacitor CBST to the clamping voltage.

[0089] Based on the description of the above embodiments, another possible implementation of the detection circuit 110 is exemplarily described. For example... Figure 1 As shown, the detection circuit 110 may further include a hysteresis current output circuit 116.

[0090] The input terminal of the hysteresis current output circuit 116 is electrically connected to the positive voltage power supply, the control terminal of the hysteresis current output circuit 116 is electrically connected to the second output terminal of the control circuit 120, and the output terminal of the hysteresis current output circuit 116 is electrically connected to the output terminal of the pull-up current output circuit 112.

[0091] The hysteresis current output circuit 116 can obtain the fifth signal CHG_Z from the control circuit 120. Furthermore, under the action of the fifth signal CHG_Z, the hysteresis current output circuit 116 can generate a hysteresis current according to the power supply voltage VDD, and transmit the hysteresis current to the pull-up current output circuit 112, so that the pull-up current output circuit 112 can obtain the hysteresis current.

[0092] Among them, the level of the fifth signal CHG_Z is opposite to the level of the fourth signal EN_CHG.

[0093] Thus, under the action of the hysteresis current, the pull-up current output circuit 112 can increase the current value of the pull-up current, so that the third signal BOOT_CHG_OFF remains constant and avoids the third signal BOOT_CHG_OFF from floating at the flip point.

[0094] The flip point refers to the moment when the third signal BOOT_CHG_OFF flips from the first level to the second level. For example, the first level is high and the second level is low. Or, the first level is low and the second level is high.

[0095] Based on the description of the above embodiments, an exemplary possible implementation of the hysteresis current output circuit 116 is provided. Figure 1 As shown, the hysteresis current output circuit 116 may include: a first P-type transistor MP1, a second P-type transistor MP2, and a third P-type transistor MP3.

[0096] The source of the first P-type transistor MP1 and the source of the second P-type transistor MP2 are both electrically connected to the positive voltage power supply. The gate of the first P-type transistor MP1, the gate of the second P-type transistor MP2, and the drain are all used to connect to the first bias current IB1. The drain of the first P-type transistor MP1 is electrically connected to the source of the third P-type transistor MP3. The gate of the third P-type transistor MP3 is electrically connected to the second output terminal of the control circuit 120. The drain of the third P-type transistor MP3 is electrically connected to the output terminal of the pull-up current output circuit 112.

[0097] The source of the first P-type transistor MP1 and the source of the second P-type transistor MP2 are both input terminals of the hysteresis current output circuit 116, and the drain of the third P-type transistor MP3 is the output terminal of the hysteresis current output circuit 116.

[0098] The first P-type transistor MP1, the second P-type transistor MP2, and the third P-type transistor MP3 can be metal-oxide-semiconductor field-effect transistors or gallium nitride transistors; this application does not specifically limit them.

[0099] Based on the description of the above embodiments, an exemplary possible implementation of the voltage detection circuit 111 is provided. For example... Figure 1 As shown, the voltage detection circuit 111 may include: a first N-type transistor MN1, a second N-type transistor MN2, and a first resistor R1.

[0100] The drain and gate of the first N-type transistor MN1 are electrically connected to the upper plate of the bootstrap capacitor CBST. The source of the first N-type transistor MN1 is electrically connected to the drain and gate of the second N-type transistor MN2. The source of the second N-type transistor MN2 is electrically connected to the first terminal of the first resistor R1. The control terminal of the pull-down current output circuit 113 is electrically connected between the source of the second N-type transistor MN2 and the first terminal of the first resistor R1. The second terminal of the first resistor R1 is electrically connected to the lower plate of the bootstrap capacitor CBST.

[0101] In this circuit, the drain of the first N-type transistor MN1 and the gate of the second N-type transistor MN2 are both the first input terminals of the voltage detection circuit 111, the second terminal of the first resistor R1 is the second input terminal of the voltage detection circuit 111, and the output terminal of the voltage detection circuit 111 is located between the source of the second N-type transistor MN2 and the first terminal of the first resistor R1.

[0102] The first N-type transistor MN1 and the second N-type transistor MN2 can be metal-oxide-semiconductor field-effect transistors or gallium nitride transistors, and this application does not specifically limit them.

[0103] Based on the description of the above embodiments, an exemplary possible implementation of the clamping circuit 115 is provided. Figure 1 As shown, the clamping circuit 115 may include: diode Z0, second resistor R2 and third N-type transistor MN3.

[0104] The negative terminal of diode Z0 is electrically connected to the upper plate of bootstrap capacitor CBST, the positive terminal of diode Z0 is electrically connected to the first end of second resistor R2, the second end of second resistor R2 and the source of third N-type transistor MN3 are both electrically connected to the lower plate of bootstrap capacitor CBST, the gate of third N-type transistor MN3 is electrically connected between the positive terminal of diode Z0 and the first end of second resistor R2, and the drain of third N-type transistor MN3 is electrically connected to the output terminal of pull-down current output circuit 113.

[0105] In this circuit, the negative terminal of diode Z0 is the first input terminal of clamping circuit 115, the second terminal of second resistor R2 is the second input terminal of clamping circuit 115, and the drain of third N-type transistor MN3 is the output terminal of clamping circuit 115.

[0106] The clamping voltage is the clamping voltage of diode Z0.

[0107] The third N-type transistor MN3 can be a metal-oxide-semiconductor field-effect transistor or a gallium nitride transistor; this application does not specifically limit this.

[0108] Based on the description of the above embodiments, an exemplary possible implementation of the third signal output circuit 114 is provided. Figure 1 As shown, the third signal output circuit 114 may include: a fourth P-type transistor MP4 and a buffer BUF.

[0109] The source of the fourth P-type transistor MP4 is electrically connected to the positive voltage power supply. The gate of the fourth P-type transistor MP4 is electrically connected between the output terminal of the pull-down current output circuit 113 and the output terminal of the pull-up current output circuit 112. The drain of the fourth P-type transistor MP4 and the input terminal of the buffer BUF are both used to connect the second bias current IB2. The output terminal of the buffer BUF is electrically connected to the first input terminal of the control circuit 120.

[0110] Among them, the gate of the fourth P-type transistor MP4 is the control terminal of the third signal output circuit 114, the source of the fourth P-type transistor MP4 is the input terminal of the third signal output circuit 114, and the output terminal of the buffer BUF is the output terminal of the third signal output circuit 114.

[0111] The fourth P-type transistor MP4 can be a metal-oxide-semiconductor field-effect transistor or a gallium nitride transistor; this application does not specifically limit this.

[0112] Based on the description of the above embodiments, an exemplary possible implementation of the pull-up current output circuit 112 is provided. Figure 1 As shown, the pull-up current output circuit 112 may include: a fifth P-type transistor MP5.

[0113] The source of the fifth P-type transistor MP5 is electrically connected to the positive voltage power supply, the gate of the fifth P-type transistor MP5 is used to connect the first bias current IB1, and the drain of the fifth P-type transistor MP5 is electrically connected to the output terminal of the pull-down current output circuit 113.

[0114] Among them, the source of the fifth P-type transistor MP5 is the input terminal of the pull-up current output circuit 112, the gate of the fifth P-type transistor MP5 is the control terminal of the pull-up current output circuit 112, and the drain of the fifth P-type transistor MP5 is the output terminal of the pull-up current output circuit 112.

[0115] The fifth P-type transistor MP5 can be a metal-oxide-semiconductor field-effect transistor or a gallium nitride transistor; this application does not specifically limit this.

[0116] Based on the description of the above embodiments, an exemplary, other possible implementation of the pull-up current output circuit 112 is provided. Figure 1 As shown, the pull-up current output circuit 112 may also include: a sixth P-type transistor MP6 and a fourth N-type transistor MN4.

[0117] The source of the sixth P-type transistor MP6 is electrically connected to the drain of the fifth P-type transistor MP5. The gate of the sixth P-type transistor MP6 is grounded. The drain of the sixth P-type transistor MP6 is electrically connected to the source and gate of the fourth N-type transistor MN4. The drain of the fourth N-type transistor MN4 is electrically connected to the output terminal of the pull-down current output circuit 113.

[0118] Among them, the sixth P-type transistor MP6 has a higher withstand voltage value. Therefore, the sixth P-type transistor MP6 is a high-voltage transistor used to withstand high voltage.

[0119] The sixth P-type transistor MP6 can be a metal-oxide-semiconductor field-effect transistor or a gallium nitride transistor; this application does not specifically limit this.

[0120] Among them, the fourth N-type transistor MN4 is, for example, a metal-oxide-semiconductor field-effect transistor.

[0121] When the high-side power transistor HS is turned on, the voltage at the switching node SW is approximately equal to the input voltage VIN of the buck-boost converter 1000. Thus, the voltage at the upper plate of the bootstrap capacitor CBST, i.e., the voltage at the BOOT terminal, is equal to the input voltage VIN and the voltage across the bootstrap capacitor CBST. Since the voltage at the switching node SW and the voltage at the BOOT terminal may be higher than the power supply voltage VDD in some applications, the body diode of the fourth N-type transistor MN4, i.e., the parasitic PN junction of the fourth N-type transistor MN4, effectively prevents the charge in the bootstrap capacitor CBST from flowing back into the power supply voltage VDD.

[0122] Based on the description of the above embodiments, an exemplary possible implementation of the pull-down current output circuit 113 is provided. Figure 1 As shown, the pull-down current output circuit 113 may include: a fifth N-type transistor MN5.

[0123] The drain of the fifth N-type transistor MN5 is electrically connected to the output terminal of the pull-up current output circuit 112, the gate of the fifth N-type transistor MN5 is electrically connected to the output terminal of the voltage detection circuit 111, and the source of the fifth N-type transistor MN5 is electrically connected to the lower plate of the bootstrap capacitor CBST.

[0124] In this circuit, the source of the fifth N-type transistor MN5 is the input terminal of the pull-down current output circuit 113, the gate of the fifth N-type transistor MN5 is the control terminal of the pull-down current output circuit 113, and the drain of the fifth N-type transistor MN5 is the output terminal of the pull-down current output circuit 113.

[0125] The fifth N-type transistor MN5 can be a metal-oxide-semiconductor field-effect transistor or a gallium nitride transistor; this application does not specifically limit this.

[0126] Based on the description of the above embodiments, an exemplary possible implementation of the control circuit 120 is provided. For example... Figure 1 As shown, the control circuit 120 may include: a delay 121, a first AND gate 123, a second AND gate 125, a NAND gate 122, a NOR gate 126, a first inverter 124, and a second inverter 127.

[0127] The input terminal of delay unit 121 is used to receive the first signal LSON_FB. The output terminal of delay unit 121 is electrically connected to the first input terminal of first AND gate device 123 and the first input terminal of NAND gate device 122. The second input terminal of NAND gate device 122 and the input terminal of first inverter 124 are both electrically connected to the output terminal of detection circuit 110. The output terminal of NAND gate device 122 is electrically connected to the second input terminal of first AND gate device 123. The output terminal of first AND gate device 123 is electrically connected to the first input terminal of NOR gate device 126. The output terminal of first inverter 124 is electrically connected to the first input terminal of second AND gate device 125. The second input terminal of second AND gate device 125 is used to receive the second signal HZ. The output terminal of second AND gate device 125 is electrically connected to the second input terminal of NOR gate device 126. The output terminal of NOR gate device 126 is electrically connected to the input terminal of second inverter 127. The output terminal of second inverter 127 is electrically connected to the control terminal of charging circuit 130.

[0128] In this circuit, the second input terminal of the NAND gate 122 and the input terminal of the first inverter 124 are both the first input terminals of the control circuit 120, the input terminal of the delay unit 121 is the second input terminal of the control circuit 120, the second input terminal of the second AND gate 125 is the third input terminal of the control circuit 120, the output terminal of the second inverter 127 is the second input terminal of the control circuit 120, the output terminal of the second inverter 127 is the first output terminal of the control circuit 120, and the output terminal of the NOR gate 126 is the first output terminal of the control circuit 120.

[0129] Among them, the first AND gate 123 and the second AND gate 125 perform AND operations. The NAND gate 122 performs NAND operations. The NOR gate 126 performs NOR operations.

[0130] Based on the description of the above embodiments, an exemplary possible implementation of the charging circuit 130 is provided. Figure 1 As shown, the charging circuit 130 may include: a switching circuit 131, a charging tube MP0, and a field-effect transistor MN0.

[0131] The control terminal of the switching circuit 131 is electrically connected to the first output terminal of the control circuit 120. The first terminal of the switching circuit 131 and the source of the charging transistor MP0 are both electrically connected to the positive voltage power supply. The second terminal of the switching circuit 131 is electrically connected to the gate of the charging transistor MP0. The drain of the charging transistor MP0 is electrically connected to the gate and the source of the field-effect transistor MN0, respectively. The drain of the field-effect transistor MN0 is electrically connected to the upper plate of the bootstrap capacitor CBST.

[0132] In this circuit, the control terminal of the switching circuit 131 is the control terminal of the charging circuit 130, the first terminal of the switching circuit 131 and the source of the charging transistor MP0 are both input terminals of the charging circuit 130, and the drain of the field-effect transistor MN0 is the output terminal of the charging circuit 130.

[0133] The preset voltage is the sum of the gate-source voltage of the first N-type transistor MN1, the gate-source voltage of the second N-type transistor MN2, and the gate-source voltage of the fifth N-type transistor MN5.

[0134] Switching circuit 131 can control charging transistor MP0 to turn on according to the fourth signal EN_CHG, so that the power supply voltage VDD charges the bootstrap capacitor CBST through the body diode of field-effect transistor MN0, i.e., the parasitic PN junction of field-effect transistor MN0. Thus, charging circuit 130 can charge bootstrap capacitor CBST through the parasitic PN junction of field-effect transistor MN0.

[0135] In summary, the switching circuit can control the charging transistor to turn on based on the fourth signal, allowing the power supply voltage to charge the bootstrap capacitor through the body diode of the field-effect transistor. Therefore, the charging circuit charges the bootstrap capacitor according to the fourth signal.

[0136] Based on the description of the above embodiments, an exemplary possible implementation of the switching circuit 131 is provided. Figure 1 As shown, the switching circuit 131 may include a seventh P-type transistor MP7 and a sixth N-type transistor MN6.

[0137] The gate of the seventh P-type transistor MP7 and the gate of the sixth N-type transistor MN6 are both electrically connected to the output terminal of the control circuit 120. The source of the seventh P-type transistor MP7 is electrically connected to the positive voltage power supply. The drain of the seventh P-type transistor MP7 is electrically connected to the drain of the sixth N-type transistor MN6. The gate of the charging transistor MP0 is electrically connected between the drain of the seventh P-type transistor MP7 and the drain of the sixth N-type transistor MN6. The source of the sixth N-type transistor MN6 is grounded.

[0138] In this circuit, the gate of the seventh P-type transistor MP7 and the gate of the sixth N-type transistor MN6 are both control terminals of the switching circuit 131. The source of the seventh P-type transistor MP7 is the first terminal of the switching circuit 131, and the second terminal of the switching circuit 131 is located between the drain of the seventh P-type transistor MP7 and the drain of the sixth N-type transistor MN6.

[0139] Among them, the seventh P-type transistor MP7 and the sixth N-type transistor MN6 can be metal-oxide-semiconductor field-effect transistors or gallium nitride transistors, and the embodiments of this application do not specifically limit them.

[0140] The working principle of the bootstrap capacitor charging circuit 100 is explained in detail below:

[0141] When the buck-boost converter 1000 enters the high-impedance stage, if the voltage across the bootstrap capacitor CBST is lower than a preset voltage, the voltage across CBST, after subtracting the voltages across the first N-type transistor MN1 and the second N-type transistor MN2, drops to a smaller voltage across the first resistor R1. This results in the fifth N-type transistor MN5 generating less current than the fifth P-type transistor MP5. Consequently, the drain potential of the fifth P-type transistor MP5 is pulled high, turning off the fourth P-type transistor MP4 and causing the third signal BOOT_CHG_OFF to flip low.

[0142] When the buck-boost converter 1000 enters the high-impedance stage, the second signal HZ is high, the first signal LSON_FB is low, and the third signal BOOT_CHG_OFF is low. Therefore, the fourth signal EN_CHG is high, and the fifth signal CHG_Z is low. This turns off the seventh P-type transistor MP7 and turns on the sixth N-type transistor MN6, enabling the control charging transistor MP0 to turn on. This allows the power supply voltage VDD to charge the bootstrap capacitor CBST through the body diode of the field-effect transistor MN0.

[0143] Furthermore, if the buck-boost converter 1000 operates in the high-impedance stage for an extended period, the voltage across the bootstrap capacitor CBST will charge up to VDD-VBD0. Here, VDD is the power supply voltage, and VBD0 is the forward voltage drop of the body diode of the field-effect transistor MN0.

[0144] Simultaneously, the fifth signal CHG_Z is at a low level, turning on the third P-type transistor MP3 and providing a hysteresis current to the drain of the fifth P-type transistor MP5. This hysteresis current increases the pull-up current value, keeping the third signal BOOT_CHG_OFF constant and preventing it from fluctuating at the topping point.

[0145] When the voltage across the bootstrap capacitor CBST reaches the preset voltage, the current generated by the fifth N-type transistor MN5 is greater than that generated by the fifth P-type transistor MP5. Consequently, the drain potential of the fifth P-type transistor MP5 is pulled low, turning on the fourth P-type transistor MP4 and causing the third signal BOOT_CHG_OFF to flip high. This makes the fourth signal EN_CHG low, turning on the seventh P-type transistor MP7 and turning off the sixth N-type transistor MN6, thus turning off the control charging transistor MP0 and stopping the power supply voltage VDD from charging the bootstrap capacitor CBST.

[0146] Furthermore, when the voltage across the bootstrap capacitor CBST reaches the clamping voltage of diode Z0, the third N-type transistor MN3 turns on, pulling down the source potential of the sixth P-type transistor MP6, which in turn pulls down the drain potential of the fifth P-type transistor MP5. This causes the fourth P-type transistor MP4 to turn on, causing the third signal BOOT_CHG_OFF to flip to a high level. Thus, the fourth signal EN_CHG is low, the seventh P-type transistor MP7 turns on, the sixth N-type transistor MN6 turns off, and the control charging transistor MP0 turns off, stopping the power supply voltage VDD from charging the bootstrap capacitor CBST. This prevents excessive voltage across the bootstrap capacitor CBST from damaging subsequent circuitry.

[0147] Based on this, theoretically, the voltage across the bootstrap capacitor CBST will be controlled to be the sum of the gate-source voltage of the fifth N-type transistor MN5, the gate-source voltage of the first N-type transistor MN1, and the gate-source voltage of the second N-type transistor MN2.

[0148] With the high-side power transistor HS turned on, in some applications, the voltage at the switching node SW and the voltage at the BOOT terminal may be higher than the power supply voltage VDD. The body diodes of the field-effect transistor MN0 and the fourth N-type transistor MN4 effectively prevent the charge in the bootstrap capacitor CBST from flowing back into the power supply voltage VDD. Furthermore, since the drain voltage of the fourth N-type transistor MN4 may be higher than its source voltage, no current flows through it. This pulls the source potential of the sixth P-type transistor MP6 high, causing the third signal BOOT_CHG_OFF to go low.

[0149] In this way, the third signal BOOT_CHG_OFF is masked by the delayed signal of the first signal LSON_FB. Furthermore, when the low-side power transistor LS is turned on each time, the fourth signal EN_CHG is prevented from being high for a period of time, thus avoiding the shutdown of the charging transistor MP0. This prevents the voltage across the bootstrap capacitor CBST from uncontrollably increasing cycle by cycle. Otherwise, regardless of how high the voltage across the bootstrap capacitor CBST is, when the low-side power transistor LS is turned on each time, the fourth signal EN_CHG will be high for a period of time, turning on the charging transistor MP0. This would cause the voltage across the bootstrap capacitor CBST to uncontrollably increase cycle by cycle.

[0150] With the low-side power transistor LS turned on, when the voltage across the bootstrap capacitor CBST is low, the voltage across CBST minus the voltages across the first N-type transistor MN1 and the second N-type transistor MN2 results in a smaller voltage drop across the first resistor R1. This makes the current-generating capability of the fifth N-type transistor MN5 less than that of the fifth P-type transistor MP5. Consequently, the drain potential of the fifth P-type transistor MP5 is pulled high, turning off the fourth P-type transistor MP4 and causing the third signal BOOT_CHG_OFF to flip low.

[0151] When the low-side power transistor LS is turned on, the second signal HZ is low, the first signal LSON_FB is high, and the third signal BOOT_CHG_OFF is low. Therefore, the fourth signal EN_CHG is high. This turns off the seventh P-type transistor MP7 and turns on the sixth N-type transistor MN6, which in turn turns on the control charging transistor MP0. This allows the power supply voltage VDD to charge the bootstrap capacitor CBST through the body diode of the field-effect transistor MN0.

[0152] When the voltage across the bootstrap capacitor CBST increases to a level where the current generated by the fifth N-type transistor MN5 exceeds that generated by the fifth P-type transistor MP5, the drain potential of the fifth P-type transistor MP5 is pulled low, turning on the fourth P-type transistor MP4 and causing the third signal BOOT_CHG_OFF to flip high. This then turns the fourth signal EN_CHG low, turning on the seventh P-type transistor MP7, turning off the sixth N-type transistor MN6, and turning off the control charging transistor MP0, thus stopping the power supply voltage VDD from charging the bootstrap capacitor CBST.

[0153] This application also provides a buck-boost converter. (See also...) Figure 2 , Figure 2 This is a schematic diagram of a half-bridge buck-boost converter provided in an embodiment of this application. Figure 2 As shown, the buck-boost converter 1000 may include: a high-side power transistor HS, a low-side power transistor LS, an inductor L, a bootstrap capacitor CBST, and a bootstrap capacitor charging circuit 100.

[0154] The drain of the high-side power transistor HS is used to connect to the input voltage VIN of the buck-boost converter 1000. The source of the high-side power transistor HS is electrically connected to the drain of the low-side power transistor LS and the first terminal of the inductor L. The source of the low-side power transistor LS is used to output the output voltage of the buck-boost converter 1000. A switching node SW is provided between the source of the high-side power transistor HS and the drain of the low-side power transistor LS. The upper plate of the bootstrap capacitor CBST is electrically connected to the output terminal of the bootstrap capacitor charging circuit 100, and the lower plate of the bootstrap capacitor CBST is electrically connected to the switching node SW. The gates of the high-side power transistor HS and the low-side power transistor LS are both used to connect to the drive signal. The drive signal is used to drive the gate of the high-side power transistor HS and the low-side power transistor LS to turn on or off. The second terminal of the inductor L is grounded.

[0155] For example, the drive signals may include: a first drive signal HSGATE and a second drive signal LSGATE. The first drive signal HSGATE is used to turn the high-side power transistor HS on or off. The second drive signal LSGATE is used to turn the low-side power transistor LS on or off.

[0156] Specifically, when the first drive signal HSGATE is high, the second drive signal LSGATE is low. Thus, the high-side power transistor HS is turned on, and the low-side power transistor LS is turned off.

[0157] Specifically, when the first drive signal HSGATE is low, the second drive signal LSGATE is high. Thus, the high-side power transistor HS is turned off, and the low-side power transistor LS is turned on.

[0158] Furthermore, since the power supply domains of the second drive signal LSGATE and the first signal LSON_FB are different, the second drive signal is represented by the letters LSGATE, and the first signal is represented by the letters LSON_FB.

[0159] Specifically, when the low-side power transistor LS is on, the voltage at the switching node SW is approximately equal to the output voltage of the buck-boost converter 1000. At this time, the output voltage is negative. When the high-side power transistor HS is on, the voltage at the switching node SW is approximately equal to the input voltage of the buck-boost converter 1000. When both the high-side power transistor HS and the low-side power transistor LS are off, that is, when the buck-boost converter 1000 enters the high-impedance stage, the voltage at the switching node SW is approximately ground voltage, i.e., zero voltage.

[0160] In some embodiments, the buck-boost converter 1000 may further include: a capacitor C1, a first resistor R1, and a second resistor R2.

[0161] The upper plate of capacitor C1 and the first terminal of the first resistor R1 are both electrically connected to the source of the low-side power transistor LS. The second terminal of the first resistor R1 is electrically connected to the first terminal of the second resistor R2. The upper plate of capacitor C1 and the second terminal of the second resistor R2 are both grounded.

[0162] The buck-boost converter provided in this application embodiment has the same beneficial effects as the bootstrap capacitor charging circuit provided in this application embodiment, and will not be described again here.

[0163] This application also provides a chip, including: a bootstrap capacitor charging circuit, and / or, a buck-boost converter.

[0164] The bootstrap capacitor charging circuit and the buck-boost converter can be integrated into one chip or into different chips; this application does not specifically limit this.

[0165] The chip provided in this application embodiment has the same beneficial effects as the bootstrap capacitor charging circuit provided in this application embodiment, and will not be described again here.

[0166] This application also provides an electronic device, including: a chip.

[0167] In this application, electronic devices may include, but are not limited to: tablet computers, laptop computers, navigation systems, wearable devices, and smart home devices.

[0168] The electronic device provided in this application embodiment has the same beneficial effects as the chip provided in this application embodiment, and will not be described again here.

[0169] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A bootstrap capacitor charging circuit, characterized in that, The bootstrap capacitor charging circuit is used in a half-bridge buck-boost converter; The bootstrap capacitor charging circuit includes: a detection circuit, a control circuit, and a charging circuit; The first input terminal of the detection circuit and the output terminal of the charging circuit are both electrically connected to the upper plate of the bootstrap capacitor in the buck-boost converter. The second input terminal of the detection circuit is electrically connected to the lower plate of the bootstrap capacitor. The output terminal of the detection circuit is electrically connected to the first input terminal of the control circuit. The second input terminal of the control circuit is used to receive a first signal, which is used to drive the low-side power transistor in the buck-boost converter to turn on or off. The third input terminal of the control circuit is used to receive a second signal, which is used to characterize whether the buck-boost converter has entered the high-impedance stage. The first output terminal of the control circuit is electrically connected to the control terminal of the charging circuit. The input terminal of the charging circuit is electrically connected to the positive voltage power supply. When the buck-boost converter enters the high-impedance phase, or when the low-side power transistor is in the turn-on phase, wherein: The detection circuit is used to detect whether the voltage across the bootstrap capacitor is lower than a preset voltage, obtain a third signal, and transmit the third signal to the control circuit. The control circuit is used to perform logical operations on the first signal, the second signal and the third signal to obtain a fourth signal, and transmit the fourth signal to the charging circuit. The fourth signal is used to control the charging circuit to turn on or off. The charging circuit is used to charge the bootstrap capacitor using the power supply voltage provided by the positive voltage power supply according to the fourth signal, until the voltage across the bootstrap capacitor is higher than the preset voltage, and then stop charging. The control circuit includes: a delay, a first AND gate, a second AND gate, a NAND gate, a NOR gate, a first inverter, and a second inverter. The input terminal of the delay device is used to receive the first signal. The output terminal of the delay device is electrically connected to the first input terminal of the first AND gate and the first input terminal of the NAND gate. The second input terminal of the NAND gate and the input terminal of the first inverter are both electrically connected to the output terminal of the detection circuit. The output terminal of the NAND gate is electrically connected to the second input terminal of the first AND gate. The output terminal of the first AND gate is electrically connected to the first input terminal of the NOR gate. The output terminal of the first inverter is electrically connected to the first input terminal of the second AND gate. The second input terminal of the second AND gate is used to receive the second signal. The output terminal of the second AND gate is electrically connected to the second input terminal of the NOR gate. The output terminal of the NOR gate is electrically connected to the input terminal of the second inverter. The output terminal of the second inverter is electrically connected to the control terminal of the charging circuit.

2. The bootstrap capacitor charging circuit according to claim 1, characterized in that, The detection circuit includes: a voltage detection circuit, a pull-up current output circuit, a pull-down current output circuit, and a third signal output circuit; The first input terminal of the voltage detection circuit is electrically connected to the upper plate of the bootstrap capacitor. The second input terminal of the voltage detection circuit and the input terminal of the pull-down current output circuit are both electrically connected to the lower plate of the bootstrap capacitor. The output terminal of the voltage detection circuit is electrically connected to the control terminal of the pull-down current output circuit. The output terminal of the pull-down current output circuit is electrically connected to the output terminal of the pull-up current output circuit. The input terminal of the pull-up current output circuit and the input terminal of the third signal output circuit are both electrically connected to the positive voltage power supply. The control terminal of the pull-up current output circuit is used to connect to the first bias current. The control terminal of the third signal output circuit is electrically connected between the output terminal of the pull-down current output circuit and the output terminal of the pull-up current output circuit. The output terminal of the third signal output circuit is electrically connected to the first input terminal of the control circuit. The pull-up current output circuit is used to generate a pull-up current according to the power supply voltage under the action of the first bias current, and to transmit the pull-up current to the third signal output circuit. The voltage detection circuit is used to detect whether the voltage across the bootstrap capacitor is lower than the preset voltage, obtain the control voltage, and transmit the control voltage to the pull-down current output circuit. The pull-down current output circuit is used to generate a pull-down current under the action of the control voltage and transmit the pull-down current to the third signal output circuit. The third signal output circuit is used to determine the potential of the control terminal of the third signal output circuit to be raised or lowered according to the relationship between the pull-up capability of the pull-up current and the pull-down capability of the pull-down current, so as to generate the third signal.

3. The bootstrap capacitor charging circuit according to claim 2, characterized in that, The detection circuit further includes: a clamping circuit; The first input terminal of the clamping circuit is electrically connected to the upper plate of the bootstrap capacitor, the second input terminal of the clamping circuit is electrically connected to the lower plate of the bootstrap capacitor, and the output terminal of the clamping circuit is electrically connected to the output terminal of the pull-down current output circuit. The clamping circuit is used to pull up the potential of the control terminal of the third signal output circuit when the voltage across the bootstrap capacitor is equal to the clamping voltage, so as to clamp the voltage across the bootstrap capacitor to the clamping voltage.

4. The bootstrap capacitor charging circuit according to claim 2, characterized in that, The detection circuit also includes: a hysteresis current output circuit; The input terminal of the hysteresis current output circuit is electrically connected to the positive voltage power supply, the control terminal of the hysteresis current output circuit is electrically connected to the second output terminal of the control circuit, and the output terminal of the hysteresis current output circuit is electrically connected to the output terminal of the pull-up current output circuit. The hysteresis current output circuit is used to obtain a fifth signal from the control circuit, and under the action of the fifth signal, generate the hysteresis current according to the power supply voltage, and transmit the hysteresis current to the pull-up current output circuit. The level of the fifth signal is opposite to the level of the fourth signal. The pull-up current output circuit is used to increase the current value of the pull-up current under the action of the hysteresis current, so as to keep the third signal constant and avoid the third signal from floating at the flip point. The flip point refers to the moment when the third signal flips from the first level to the second level.

5. The bootstrap capacitor charging circuit according to claim 4, characterized in that, The hysteresis current output circuit includes: a first P-type transistor, a second P-type transistor, and a third P-type transistor; The source of the first P-type transistor and the source of the second P-type transistor are both electrically connected to the positive voltage power supply. The gate of the first P-type transistor, the gate of the second P-type transistor, and the drain are all used to connect to the first bias current. The drain of the first P-type transistor is electrically connected to the source of the third P-type transistor. The gate of the third P-type transistor is electrically connected to the second output terminal of the control circuit. The drain of the third P-type transistor is electrically connected to the output terminal of the pull-up current output circuit.

6. The bootstrap capacitor charging circuit according to claim 2, characterized in that, The voltage detection circuit includes: a first N-type transistor, a second N-type transistor, and a first resistor; The drain and gate of the first N-type transistor are both electrically connected to the upper plate of the bootstrap capacitor. The source of the first N-type transistor is electrically connected to the drain and gate of the second N-type transistor. The source of the second N-type transistor is electrically connected to the first terminal of the first resistor. The control terminal of the pull-down current output circuit is electrically connected between the source of the second N-type transistor and the first terminal of the first resistor. The second terminal of the first resistor is electrically connected to the lower plate of the bootstrap capacitor.

7. The bootstrap capacitor charging circuit according to claim 3, characterized in that, The clamping circuit includes: a diode, a second resistor, and a third N-type transistor; The negative terminal of the diode is electrically connected to the upper plate of the bootstrap capacitor, the positive terminal of the diode is electrically connected to the first end of the second resistor, the second end of the second resistor and the source of the third N-type transistor are both electrically connected to the lower plate of the bootstrap capacitor, the gate of the third N-type transistor is electrically connected between the positive terminal of the diode and the first end of the second resistor, and the drain of the third N-type transistor is electrically connected to the output terminal of the pull-down current output circuit.

8. The bootstrap capacitor charging circuit according to claim 2, characterized in that, The third signal output circuit includes: a fourth P-type transistor and a buffer; The source of the fourth P-type transistor is electrically connected to the positive voltage power supply, the gate of the fourth P-type transistor is electrically connected between the output terminal of the pull-down current output circuit and the output terminal of the pull-up current output circuit, the drain of the fourth P-type transistor and the input terminal of the buffer are both used to connect to the second bias current, and the output terminal of the buffer is electrically connected to the first input terminal of the control circuit.

9. The bootstrap capacitor charging circuit according to claim 2, characterized in that, The pull-up current output circuit includes: a fifth P-type transistor; The source of the fifth P-type transistor is electrically connected to the positive voltage power supply, the gate of the fifth P-type transistor is used to connect to the first bias current, and the drain of the fifth P-type transistor is electrically connected to the output terminal of the pull-down current output circuit.

10. The bootstrap capacitor charging circuit according to claim 9, characterized in that, The pull-up current output circuit also includes: a sixth P-type transistor and a fourth N-type transistor; The source of the sixth P-type transistor is electrically connected to the drain of the fifth P-type transistor, the gate of the sixth P-type transistor is grounded, the drain of the sixth P-type transistor is electrically connected to the source and gate of the fourth N-type transistor, and the drain of the fourth N-type transistor is electrically connected to the output terminal of the pull-down current output circuit.

11. The bootstrap capacitor charging circuit according to claim 2, characterized in that, The pull-down current output circuit includes: a fifth N-type transistor; The drain of the fifth N-type transistor is electrically connected to the output terminal of the pull-up current output circuit, the gate of the fifth N-type transistor is electrically connected to the output terminal of the voltage detection circuit, and the source of the fifth N-type transistor is electrically connected to the lower plate of the bootstrap capacitor.

12. The bootstrap capacitor charging circuit according to any one of claims 1-11, characterized in that, The charging circuit includes: a switching circuit, a charging tube, and a field-effect transistor; The control terminal of the switching circuit is electrically connected to the first output terminal of the control circuit. The first terminal of the switching circuit and the source of the charging tube are both electrically connected to the positive voltage power supply. The second terminal of the switching circuit is electrically connected to the gate of the charging tube. The drain of the charging tube is electrically connected to the gate and source of the field-effect transistor, respectively. The drain of the field-effect transistor is electrically connected to the upper plate of the bootstrap capacitor. The switching circuit is used to control the charging tube to turn on according to the fourth signal, so that the power supply voltage charges the bootstrap capacitor through the body diode of the field-effect transistor.

13. The bootstrap capacitor charging circuit according to claim 12, characterized in that, The switching circuit includes: a seventh P-type transistor and a sixth N-type transistor; The gate of the seventh P-type transistor and the gate of the sixth N-type transistor are both electrically connected to the first output terminal of the control circuit. The source of the seventh P-type transistor is electrically connected to the positive voltage power supply. The drain of the seventh P-type transistor is electrically connected to the drain of the sixth N-type transistor. The gate of the charging transistor is electrically connected between the drain of the seventh P-type transistor and the drain of the sixth N-type transistor. The source of the sixth N-type transistor is grounded.

14. A half-bridge buck-boost converter, characterized in that, include: High-side power transistor, low-side power transistor, inductor, bootstrap capacitor, and bootstrap capacitor charging circuit as described in any one of claims 1-13; The drain of the high-side power transistor is used to connect to the input voltage of the buck-boost converter. The source of the high-side power transistor is electrically connected to the drain of the low-side power transistor and the first terminal of the inductor. The source of the low-side power transistor is used to output the output voltage of the buck-boost converter. A switching node is provided between the source of the high-side power transistor and the drain of the low-side power transistor. The upper plate of the bootstrap capacitor is electrically connected to the output terminal of the bootstrap capacitor charging circuit. The lower plate of the bootstrap capacitor is electrically connected to the switching node. The gates of both the high-side power transistor and the low-side power transistor are used to connect to a drive signal. The drive signal is used to drive the gate of the high-side power transistor and the low-side power transistor to turn on or off. The second terminal of the inductor is grounded.

15. A chip, characterized in that, include: The bootstrap capacitor charging circuit as described in any one of claims 1-13, and / or the buck-boost converter as described in claim 14.

16. An electronic device, characterized in that, include: The chip as described in claim 15.

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