Optimization method and device of multiplexer tree, equipment and medium

Abstract

The invention discloses a multiplexer tree optimization method and device, equipment and a medium, and the method comprises the steps: obtaining a to-be-optimized multiplexer tree, screening a selector path from the multiplexer tree, and enabling the selector path to be a signal transmission path with the maximum stage number of the multiplexer tree; and iterative optimization is carried out on the multiplexer tree according to the selector path until operation parameters of the multiplexer tree do not meet a parameter range, an optimized selector tree is obtained, the operation parameters comprise resource parameters and series parameters, and iterative optimization is to repeatedly truncate and join the multiplexer tree. The whole process is rapid and simple, only the connection structure of the multiplexer is modified in optimization, a small number of resources are used, the number of stages of the multiplexer tree is greatly reduced, the cost is effectively reduced, and the calculation efficiency is improved.

Description

Background Art

[0002] A binary multiplexer (binary-mux) is a multiplexer with binary-coded input at the selection end. It is a common circuit element in the process of digital circuit logic synthesis, and is used to describe the logical behavior of selecting a group of data from multiple groups of data as output by a selection signal. The selection end of a binary multiplexer is generally represented by sel, the bit width of the selection end is n, and the number of its data ends is 2n.

[0003] A multiplexer tree can be constructed by connecting multiple binary multiplexers. In the "technology mapping" of FPGA, mapping the multiplexer tree to a LUT (lookup table) is a common synthesis scenario in the digital circuit logic synthesis process.

[0004] However, the commonly used multiplexer tree has the following technical problems: "Technical mapping" depends on the number of levels of the multiplexer tree. If the number of levels of the multiplexer tree is too high, the number of levels of the mapped LUT (lookup table) groups will also increase accordingly, and the number of multiplexers required will also increase accordingly, which not only increases the cost, but also increases the energy consumption required for calculation, reducing the calculation efficiency. Summary of the invention

[0005] The present invention provides a method, device, equipment and medium for optimizing a multiplexer tree, which can solve the technical problem that the prior art requires a large number of binary multiplexers, increases costs and energy consumption, and reduces efficiency.

[0006] A first aspect of an embodiment of the present invention provides a method for optimizing a multiplexer tree, the method comprising:

[0007] After obtaining the multiplexer tree to be optimized, screening a selector path from the multiplexer tree, the selector path being a signal transmission path of the maximum level of the multiplexer tree;

[0008] The multi-way selector tree is iteratively optimized according to the selector path until the operation parameters of the multi-way selector tree do not meet the parameter range, thereby obtaining an optimized selector tree, wherein the operation parameters include resource parameters and level parameters, and the iterative optimization is to repeatedly truncate and connect the multi-way selector tree.

[0009] In combination with the first aspect, in one implementation, filtering a selector path from the multi-way selector tree includes:

[0010] Determine a plurality of transmission level values ​​corresponding to the multiplexer tree, each of the transmission level values ​​being the number of multiplexers that a signal passes through after being input at a data end of the multiplexer tree;

[0011] Selecting the transmission level value with the largest value from the plurality of transmission level values ​​as the target base value;

[0012] According to the number of the target cardinality values, one of the paths where the multiplexers corresponding to the target cardinality values ​​are located is selected as a selector path.

[0013] In combination with the first aspect, in an implementation manner, selecting, according to the number of the target cardinality values, one of the paths where the multi-way selectors corresponding to the target cardinality values ​​are located as a selector path includes:

[0014] If the number of the target cardinality values ​​is equal to 1, the path where the multi-way selector corresponding to the target cardinality value is located is the selector path;

[0015] If the number of the target cardinality values ​​is greater than or equal to 2, a path that satisfies a selection port preset by the user is selected from the paths where the multiplexers corresponding to the target cardinality values ​​are located as the selector path.

[0016] In combination with the first aspect, in one implementation, the iterative optimization of the multi-way selector tree according to the selector path until the operation parameters of the multi-way selector tree do not satisfy the parameter range to obtain the optimized selector tree includes:

[0017] After determining the midpoint of the selector path, truncating the multi-way selector tree at the midpoint to obtain a first tree to be optimized and a second tree to be optimized;

[0018] Connecting the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree;

[0019] If the operation parameters of the multi-way combination tree meet the parameter range, iterating repeatedly with the multi-way combination tree as the multi-way selector tree to be optimized;

[0020] If the operation parameters of the multi-way combination tree do not satisfy the parameter range, the multi-way selector tree to be optimized is used as the optimized selector tree.

[0021] In combination with the first aspect, in one implementation, determining the midpoint of the selector path includes:

[0022] If the number of multiplexers in the selector path is an odd number, then the average value of the number of multiplexers is rounded to an integer, and the output end of the multiplexer corresponding to the integer is taken as the midpoint;

[0023] If the number of multiplexers in the selector path is an even number, the output end of the multiplexer corresponding to the average value of the number of multiplexers is taken as the midpoint.

[0024] In combination with the first aspect, in an implementation manner, after the step of connecting the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree, the method further includes:

[0025] A constant signal is input to an input end of the first tree to be optimized or an input end of the second tree to be optimized, wherein the input end of the first tree to be optimized or the input end of the second tree to be optimized is a port of the midpoint.

[0026] In combination with the first aspect, in an implementation manner, after the step of connecting the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree, the method further includes:

[0027] The preset AND gate signal is input to the selection end of the preset selector.

[0028] A second aspect of an embodiment of the present invention provides a device for optimizing a multiplexer tree, the device comprising:

[0029] An acquisition module, configured to, after acquiring a multiplexer tree to be optimized, filter a selector path from the multiplexer tree, wherein the selector path is a signal transmission path of a maximum level of the multiplexer tree;

[0030] An optimization module is used to iteratively optimize the multi-way selector tree according to the selector path until the operation parameters of the multi-way selector tree do not meet the parameter range, thereby obtaining an optimized selector tree, wherein the operation parameters include resource parameters and level parameters, and the iterative optimization is to repeatedly truncate and connect the multi-way selector tree.

[0031] In conjunction with the second aspect, in one implementation, the acquisition module is further used to:

[0032] Determine a plurality of transmission level values ​​corresponding to the multiplexer tree, each of the transmission level values ​​being the number of multiplexers that a signal passes through after being input at a data end of the multiplexer tree;

[0033] Selecting the transmission level value with the largest value from the plurality of transmission level values ​​as the target base value;

[0034] According to the number of the target cardinality values, one of the paths where the multiplexers corresponding to the target cardinality values ​​are located is selected as a selector path.

[0035] In conjunction with the second aspect, in one implementation, the acquisition module is further used to:

[0036] If the number of the target cardinality values ​​is equal to 1, the path where the multi-way selector corresponding to the target cardinality value is located is the selector path;

[0037] If the number of the target cardinality values ​​is greater than or equal to 2, a path that satisfies a selection port preset by the user is selected from the paths where the multiplexers corresponding to the target cardinality values ​​are located as the selector path.

[0038] In conjunction with the second aspect, in one implementation, the optimization module is further configured to:

[0039] After determining the midpoint of the selector path, truncating the multi-way selector tree at the midpoint to obtain a first tree to be optimized and a second tree to be optimized;

[0040] Connecting the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree;

[0041] If the operation parameters of the multi-way combination tree meet the parameter range, iterating repeatedly with the multi-way combination tree as the multi-way selector tree to be optimized;

[0042] If the operation parameters of the multi-way combination tree do not satisfy the parameter range, the multi-way selector tree to be optimized is used as the optimized selector tree.

[0043] In conjunction with the second aspect, in one implementation, the optimization module is further configured to:

[0044] If the number of multiplexers in the selector path is an odd number, then the average value of the number of multiplexers is rounded to an integer, and the output end of the multiplexer corresponding to the integer is taken as the midpoint;

[0045] If the number of multiplexers in the selector path is an even number, the output end of the multiplexer corresponding to the average value of the number of multiplexers is taken as the midpoint.

[0046] In conjunction with the second aspect, in one implementation, the optimization module is further configured to:

[0047] After the step of connecting the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree, a constant signal is input to the input end of the first tree to be optimized or the input end of the second tree to be optimized, wherein the input end of the first tree to be optimized or the input end of the second tree to be optimized is the port of the midpoint.

[0048] In conjunction with the second aspect, in one implementation, the optimization module is further configured to:

[0049] After the step of connecting the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree, a preset AND gate signal is input to a selection end of the preset selector.

[0050] Compared with the prior art, the optimization method, device, equipment and medium of a multi-way selector tree provided by the embodiment of the present invention have the following beneficial effects: after obtaining the multi-way selector tree to be optimized, the present invention can filter the selector path from the multi-way selector tree, and the selector path is the signal transmission path of the maximum level of the multi-way selector tree; the multi-way selector tree is iteratively optimized according to the selector path until the operation parameters of the multi-way selector tree do not meet the parameter range, and the optimized selector tree is obtained. The whole process is not only fast and simple, but also the optimization only modifies the connection structure of the multi-way selector, uses a small amount of resources, greatly reduces the level of the multi-way selector tree, effectively reduces the cost and improves the computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a structural schematic diagram of a two-choose-one multiplexer provided in one embodiment of the present invention;

[0052] Figure 2 The structure of a multiplexer tree provided by an embodiment of the present invention is shown in FIG. Figure 1 ;

[0053] Figure 3 The structure of a multiplexer tree provided by an embodiment of the present invention is shown in FIG. Figure 2 ;

[0054] Figure 4 It is a flowchart of a method for optimizing a multiplexer tree provided by an embodiment of the present invention;

[0055] Figure 5 The structure of an illegal multi-way selector tree provided by an embodiment of the present invention is shown in FIG. Figure 1 ;

[0056] Figure 6 The structure of an illegal multi-way selector tree provided by an embodiment of the present invention is shown in FIG. Figure 2 ;

[0057] Figure 7 It is a schematic diagram of the structure of a multi-way selector tree corresponding to a selector path provided by an embodiment of the present invention;

[0058] Figure 8 is a schematic diagram of the structure of a first tree to be optimized provided by an embodiment of the present invention;

[0059] Fig. 9 is a schematic diagram of the structure of a second tree to be optimized provided by an embodiment of the present invention;

[0060] Fig.10 is a schematic diagram of the structure of a multi-way combination tree provided by an embodiment of the present invention;

[0061] Fig.11is an operation flow chart of a method for optimizing a multiplexer tree provided by an embodiment of the present invention;

[0062] Fig.12 is a calculation diagram of the wa1 logic level in a multiplexer tree provided by an embodiment of the present invention;

[0063] Fig.13 is a calculation diagram of the number of wc1 logic levels in a multiplexer tree provided by an embodiment of the present invention;

[0064] Fig.14 is a schematic diagram of the structure of a multiplexer tree provided by an embodiment of the present invention after several iterations of optimization;

[0065] Fig.15 It is a structural schematic diagram of a multi-way selector tree optimization device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0066] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0067] A binary multiplexer (binary-mux) is a multiplexer with binary-coded input at the selection end. It is a common circuit element in the process of digital circuit logic synthesis, and is used to describe the logical behavior of selecting a group of data from multiple groups of data as output by a selection signal. The selection end of a binary multiplexer is generally represented by sel, the bit width of the selection end is n, and the number of its data ends is 2n.

[0068] Reference Figure 1 , shows a schematic diagram of the structure of a two-to-one multiplexer provided by an embodiment of the present invention. One common binary multiplexer is a two-to-one multiplexer (2-to-1 Multiplexer, abbreviated as mux21). A multiplexer with only 1 selection terminal and 2 data terminals. The circuit diagram is shown as follows. When the selection terminal input signal sel is 0, the value of the output signal out is d0; when the selection terminal input signal sel is 1, the value of out is d1.

[0069] Reference Figure 2-3 , respectively showing the structure of a multiplexer tree provided by an embodiment of the present invention Figure 1 A schematic diagram of the structure of a multiplexer tree provided by an embodiment of the present invention Figure 2A multiplexer tree can be constructed by connecting multiple binary multiplexers. In the "technology mapping" of FPGA, mapping the multiplexer tree to a LUT (lookup table) is a common synthesis scenario in the process of digital circuit logic synthesis.

[0070] However, the commonly used multiplexer tree has the following technical problems: "Technical mapping" depends on the number of levels of the multiplexer tree. If the number of levels of the multiplexer tree is too high, the number of levels of the mapped LUT (lookup table) groups will also increase accordingly, and the number of multiplexers required will also increase accordingly, which not only increases the cost, but also increases the energy consumption required for calculation, reducing the calculation efficiency.

[0071] In order to solve the above problems, a method, device, equipment and medium for optimizing a multi-way selector tree provided in an embodiment of the present application will be introduced and explained in detail through the following specific embodiments.

[0072] Reference Figure 4 , showing a flow chart of a method for optimizing a multi-way selector tree provided in one embodiment of the present invention.

[0073] In one embodiment, the method is applicable to a computer, specifically a circuit simulation system of the computer, such as MATLAB, and the circuit simulation system can be used to simulate the multiplexer tree and then optimize it, thereby effectively reducing the number of multiplexer levels and thus reducing the number of multiplexers.

[0074] Wherein, as an example, the optimization method of the multiplexer tree may include:

[0075] S11. After obtaining a multiplexer tree to be optimized, filter a selector path from the multiplexer tree, where the selector path is a signal transmission path of the maximum level of the multiplexer tree.

[0076] In one embodiment, a multiplexer tree to be optimized may be obtained. For the convenience of analysis and explanation, Figure 3 Taking the multiplexer tree of as an example, the multiplexer tree to be optimized can be obtained as follows Figure 3 shown.

[0077] After obtaining the multi-way selector tree to be optimized, each signal transmission path of the multi-way selector tree can be identified, and the level of each signal transmission path can be counted, and then the signal transmission path with the maximum level can be filtered to obtain the selector path. Subsequently, the structure of the multi-way selector tree can be modified according to the selector path to complete the optimization process.

[0078] In order to quickly simplify the structure of the multiplexer tree, the optimization may be performed from the path where the signal passes through the most multiplexers, wherein, as an example, the selecting the selector path from the multiplexer tree may include the following sub-steps:

[0079] S111. Determine multiple transmission level values ​​corresponding to the multiplexer tree, each of the transmission level values ​​being the number of multiplexers a signal passes through after being input at a data end of the multiplexer tree.

[0080] S112: Filter the transmission level value with the largest value from the plurality of transmission level values ​​as the target base value.

[0081] S113. According to the number of the target cardinality values, select one path as a selector path from the paths where the multiplexers corresponding to the target cardinality values ​​are located.

[0082] In one operation mode, multiple transmission level values ​​corresponding to the multiplexer tree may be determined, each transmission level value being the number of multiplexers that a signal passes through after being input at a data end of the multiplexer tree.

[0083] It should be noted that the obtained multiplexer tree to be optimized is a legal multiplexer tree. Figure 5-6 , respectively showing the structure of an illegal multi-way selector tree provided by an embodiment of the present invention Figure 1 A schematic diagram of the structure of an illegal multi-way selector tree provided by an embodiment of the present invention Figure 2 . Reference Figure 5 Illegal multiplexer tree with multiple fanouts on its output; see Figure 6 The illegal multiplexer tree, when first input, its external input is not the starting point of the timing, but other combinational logic.

[0084] In one embodiment, the signal input conditions of a legal multiplexer tree are as follows:

[0085] First, the multiplexer tree consists of multiple multiplexers (mux21), and the fanout of each multiplexer output must be 1.

[0086] Second, in the first algorithm iteration, the external signal of the mux21 tree (not the out output of mux21) must be the module input (or the output of the register, which only needs to be the timing starting point). This restriction is not imposed when the mux21 tree is used as the input in the second algorithm iteration.

[0087] Signals can be input from different input terminals. After the signals are input, the number of multiplexers through which the signals pass can be determined to obtain multiple transmission level values, and then the corresponding selector path can be selected according to the numerical values ​​of the transmission level values.

[0088] During optimization, in order to improve optimization efficiency and simplify the structure of the mux21 tree, a transmission level value with the largest value may be selected from multiple transmission level values ​​as a target base value.

[0089] Finally, according to the number of target cardinality values, a path is selected as the selector path in the path where the multiplexer corresponding to the target cardinality value is located.

[0090] by Figure 3 Take the multiplexer tree of as an example, the signal is input from a0, and the multiplexers it passes through are mux0->mux1->mux2->mux3->mux4->mux8->mux9->mux10, the number is 8. The signal is input from b0, and the multiplexers it passes through are mux5->mux6->mux7->mux4->mux8->mux9->mux10, the number is 7. There are two transmission level values, and the transmission level value 8 with the largest value is selected as the target level value, and the path where the multiplexer corresponding to 8 is located (mux0->mux1->mux2->mux3->mux4->mux8->mux9->mux10) is the selector path.

[0091] It should be noted that the selector path is the deepest selector path or the path with the maximum number of levels. It does not actually count the number of mux21s in the transmission direction of the sel signal at the selection end, but only counts the deepest path (maximum number of levels) at the data end of mux21.

[0092] In one embodiment, there may be one or more target cardinality values ​​with the largest numerical value. In order to filter the selector path that meets the requirements from the one or more target cardinality values, for example, selecting one of the paths where the multi-way selectors corresponding to the target cardinality values ​​are located as the selector path according to the number of the target cardinality values ​​may include the following sub-steps:

[0093] S1131. If the number of the target cardinality values ​​is equal to 1, the path where the multiplexer corresponding to the target cardinality value is located is the selector path.

[0094] S1132: If the number of the target cardinality values ​​is greater than or equal to 2, a path that satisfies a selection port preset by the user is selected as a selector path from the paths where the multiplexers corresponding to the target cardinality values ​​are located.

[0095] If the number of target cardinality values ​​is equal to 1, the path where the multiplexer corresponding to the target cardinality value is located can be used as the selector path.

[0096] If the number of target cardinality values ​​is greater than or equal to 2, a path that satisfies a selection port preset by the user can be selected from the path where the multiplexer corresponding to the target cardinality value is located as the selector path.

[0097] For convenience of explanation, refer to Figure 7 , showing a schematic diagram of the structure of a multi-way selector tree corresponding to a selector path provided in an embodiment of the present invention.

[0098] like Figure 7 As shown, there are two selector paths, path 1: mux0->mux2->mux3 and path 2: mux1->mux2->mux3. The target cardinality values ​​of the two selector paths are both 3, and the number of target cardinality values ​​is equal to 2, so there are two satisfying paths.

[0099] Both paths are the deepest paths, and there are three mux21s on the paths. You can choose either path 1 or path 2, but based on the topological order and the need for algorithm stability, at the same depth, you can select the paths with port "1" in sequence. So here you can first select path 2: mux1->mux2->mux3 as the selector path, and then select path 1: mux0->mux2->mux3.

[0100] If you need to exchange the priority of the selected port, you can also select the path with the selected port "0" at one time. Then the path priority here is: first select path 1: mux0->mux2->mux3 as the selector path, and then select path 2: mux1->mux2->mux3. The specific selection method can be adjusted according to actual needs.

[0101] S12. Iteratively optimize the multi-way selector tree according to the selector path until the operation parameters of the multi-way selector tree do not meet the parameter range, and obtain an optimized selector tree, wherein the operation parameters include resource parameters and level parameters, and the iterative optimization is to repeatedly truncate and connect the multi-way selector tree.

[0102] In one embodiment, the multi-way selector tree may be iteratively optimized according to the position of the selector path, wherein the iterative optimization is to repeatedly truncate and connect the multi-way selector tree.

[0103] Specifically, the multi-way selector tree can be truncated at the position of the selector path, and then the truncated multi-way selector tree can be connected to form a new multi-way selector tree. After the new multi-way selector tree is formed, the operation parameters of the new multi-way selector tree can be calculated, and the operation parameters include resource parameters and level parameters.

[0104] If the operation parameters of the new multi-way selector tree meet the parameter range, the new multi-way selector tree can be used as the multi-way selector tree to be optimized, and the above operation can be performed again. Then the selector path of the new multi-way selector tree is obtained, and then the new multi-way selector tree is truncated at the position of the selector path until the operation parameters of the new multi-way selector tree do not meet the parameter range, and the optimized selector tree is obtained, and the iterative optimization process is completed.

[0105] By continuously cutting and connecting, only the structure and connection mode of the multi-way selector tree to be optimized are adjusted and reorganized until its operation parameters do not meet the parameter range. In this process, the number of multi-way selectors in the multi-way selector tree does not change, and the computing energy consumption remains unchanged, but its computing parameters are continuously optimized. On the basis of improving the number of levels, computing parameters and computing efficiency of the multi-way selector tree, there is no need to increase the number of multi-way selectors, which can reduce costs and achieve optimization effects.

[0106] In order to accurately adjust the structure and connection of the multi-way selector tree according to the position of the multi-way selector of the selector path, as an example, the iterative optimization of the multi-way selector tree according to the selector path until the operation parameters of the multi-way selector tree do not meet the parameter range to obtain the optimized selector tree may include the following sub-steps:

[0107] S121. After determining the midpoint of the selector path, truncate the multi-way selector tree at the midpoint to obtain a first tree to be optimized and a second tree to be optimized.

[0108] S122: Connect the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree.

[0109] S123: If the operation parameters of the multi-way combination tree satisfy the parameter range, iterating repeatedly with the multi-way combination tree as the multi-way selector tree to be optimized.

[0110] S124: If the operation parameters of the multi-way combination tree do not satisfy the parameter range, the multi-way selector tree to be optimized is used as the optimized selector tree.

[0111] In one operation mode, the midpoint of the selector path may be determined, wherein the midpoint may be the middle position of the selector path, and then the multi-way selector tree is truncated at the midpoint to obtain a first tree to be optimized and a second tree to be optimized.

[0112] Reference Figure 3 For example, the selector path is: mux0->mux1->mux2->mux3->mux4->mux8->mux9->mux10. Then the truncated midpoint can be the connection point of multiplexer mux3 and multiplexer mux4, or the connection point of multiplexer mux4 and multiplexer mux8.

[0113] Optionally, the connection point between the multiplexer mux3 and the multiplexer mux4 can be used as the midpoint, and the Figure 3 After the multiplexer tree is constructed, the first tree to be optimized and the second tree to be optimized can be obtained.

[0114] Reference Figure 8-9 , respectively showing a schematic diagram of the structure of a first tree to be optimized provided by an embodiment of the present invention and a schematic diagram of the structure of a second tree to be optimized provided by an embodiment of the present invention.

[0115] After truncating the multiplexer tree, the first tree to be optimized can be Figure 8 As shown, the second tree to be optimized can be Fig. 9 shown.

[0116] Next, the first tree to be optimized and the second tree to be optimized may be connected to a preset selector to obtain a multi-way combination tree.

[0117] The first tree to be optimized can be linked to the newly created preset selector port "1". The second tree to be optimized can be linked to the newly created preset selector port "0". The positions where the first tree to be optimized and the second tree to be optimized are connected can also be interchanged, which can be adjusted according to actual needs.

[0118] Reference Fig.10 , which shows a schematic diagram of the structure of a multi-way combination tree provided by an embodiment of the present invention. The multi-way combination tree after connecting the first tree to be optimized and the second tree to be optimized can be as follows Fig.10 As shown, the preset selector can be a newly created multiplexer (mux21), and the preset selector is used as a link point to connect the first tree to be optimized and the second tree to be optimized. Fig.10 It is a multiplexer (mux11).

[0119] After constructing the multi-way combination tree, the operation parameters of the multi-way combination tree can be obtained. The operation parameters include: resource parameters and level parameters.

[0120] If the operation parameters of the multi-way combination tree meet the parameter range, it means that the multi-way combination tree can continue to be truncated and connected, then the multi-way combination tree is used as the multi-way selector tree to be optimized, and then the step S11 is repeated to iterate continuously until the operation parameters of the multi-way combination tree do not meet the parameter range.

[0121] If the operation parameters of the multi-way combination tree do not meet the parameter range, it means that the multi-way combination tree cannot be truncated and connected any further, and the multi-way selector tree to be optimized before truncating and connecting is used as the optimized selector tree. Specifically, the multi-way selector tree that was truncated and connected last time can be used as the optimized selector tree.

[0122] In one operation mode, the operation of determining whether the operation parameters meet the parameter range may include the following steps:

[0123] The first step is to calculate the resources (logic gates) of the optimized multi-way combination tree / the resources (logic gates) of the multi-way selector tree to be optimized before optimization, and obtain the resource increase value. Similarly, calculate the number of levels of the optimized multi-way combination tree / the number of levels of the multi-way selector tree to be optimized before optimization, and obtain the number of levels increase value.

[0124] In the second step, if the level increase value is less than or equal to 1 (the level remains unchanged or there is a benefit), and the resource increase value is less than or equal to 1.5, it is considered to be within a reasonable range, and the operation parameters are determined to meet the parameter range.

[0125] In the third step, if the level increase value is greater than 1 (the level has not changed or there is a benefit) or the resource increase value is greater than 1.5, it is considered to be an unreasonable range, and it is determined that the operation parameters do not meet the parameter range. The last recorded optimization result can be returned, and the last multi-way selector tree to be optimized before the optimization is used as the optimized selector tree.

[0126] In one embodiment, the selector path may have multiple multiplexers, which may be an odd number or an even number. In order to determine the position of the midpoint from the selector path according to the number of multiplexers, as an example, the determining of the midpoint of the selector path may include the following sub-steps:

[0127] S1211. If the number of multiplexers in the selector path is an odd number, round the average value of the number of multiplexers and take the output end of the multiplexer corresponding to the integer as the midpoint.

[0128] S1212: If the number of multiplexers in the selector path is an even number, the output end of the multiplexer corresponding to the average value of the number of multiplexers is taken as the midpoint.

[0129] Specifically, if the number value of the multiplexers of the selector path is an odd number, the average value of the number value of the multiplexers is calculated, and after the average value is rounded, the output end of the multiplexer corresponding to the integer value is taken as the midpoint.

[0130] by Figure 7 Take the selector path (mux0->mux2->mux3) as an example. The number of multiplexers in the selector path is 3, which is an odd number. The average value is 1.5, which is rounded to 1. The output end of the first multiplexer is taken as the midpoint, that is, the connection end of multiplexer mux0 and multiplexer mux2.

[0131] Similarly, if the number of multiplexers in the selector path is an even number, the output end of the multiplexer corresponding to the average value of the number of multiplexers is the midpoint.

[0132] by Figure 3 Take the selector path (mux0->mux1->mux2->mux3->mux4->mux8->mux9->mux10) as an example. The number of multiplexers in the selector path is 8, which is an even number. The average value is 4. The output end of the fourth multiplexer is taken as the midpoint, that is, the connection end of multiplexer mux3 and multiplexer mux4.

[0133] After the multi-way selector tree to be optimized is truncated, the truncated end needs to re-input a signal in order to detect various parameters of the multi-way combination tree. As an example, after the step of connecting the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree, the method further includes the following sub-steps:

[0134] S21. Input a constant signal to an input end of the first tree to be optimized or an input end of the second tree to be optimized.

[0135] The input end of the first tree to be optimized or the input end of the second tree to be optimized is the port of the midpoint.

[0136] Specifically, refer to Fig.10 , after the multiplexer tree to be optimized is truncated, there is no signal at the input end of the second tree to be optimized (the input end of the multiplexer mux4 at the truncated position), and a constant signal can be input to the input end. Alternatively, if the input end of the first tree to be optimized is the input end of the multiplexer mux4 at the truncated position, a digital signal can also be input to the input end.

[0137] Specifically, the constant signal may be 1'b0, and 1'b0 may be a constant 0.

[0138] Similarly, after the multi-way selector tree to be optimized is truncated, the newly added preset selector also needs to set the signal of the selection end in order to detect various parameters of the multi-way combination tree. As an example, after the step of connecting the first tree to be optimized and the second tree to be optimized to the preset selector to obtain the multi-way combination tree, the method further includes the following sub-steps:

[0139] S31, inputting a preset AND gate signal to a selection end of the preset selector.

[0140] A signal may be input into the selection end of the preset selector, and the input signal may be a preset AND gate signal.

[0141] Reference Fig.10 , the signal input to the selection end can be "sc0, sc1, sc2, sc3" in the figure. The signal "sc_or_0" can be the output result of the connection of the sel and gate of the subsequent mux21 of "~sc0&&~sc1&&~sc2&&~sc3".

[0142] Reference Fig.11 , shows an operation flow chart of a multi-way selector tree optimization method provided by an embodiment of the present invention.

[0143] Specifically, the operation of the multi-way selector tree optimization method may include the following steps:

[0144] The first step is to obtain the multiplexer tree to be optimized.

[0145] In the second step, the deepest multiplexer path is selected in the multiplexer tree to be optimized.

[0146] In the third step, the multiplexer tree to be optimized is disconnected at the midpoint of the deepest multiplexer path to form two trees, namely the first tree to be optimized and the second tree to be optimized.

[0147] The fourth step is to connect the first tree to be optimized and the second tree to be optimized to obtain a multi-way combination tree.

[0148] The fifth step is to calculate the operation parameters of the multi-way combination tree, including the parameters related to the level and resource changes.

[0149] The sixth step is to determine whether the operation parameters of the multi-way combination tree meet the requirements. If so, return to the first step and re-execute the operation with the multi-way combination tree as the multi-way selector tree to be optimized until the optimized selector tree is obtained. If not, the multi-way selector tree to be optimized before the multi-way combination tree is connected is used as the optimized selector tree.

[0150] By splitting and reorganizing the multiplexer tree in an iterative manner, the number of logical levels of the multiplexer tree can be reduced. Moreover, the entire process uses small resources in exchange for a reduction in the number of levels of the multiplexer tree.

[0151] In order to further compare the number of levels and resources of the multiplexer tree before and after optimization, in one embodiment, Figure 3 Take the multiplexer tree as an example, in the figure, a0~a4, b0~b3, c1~c3 can be the data input of the multiplexer (mux21), the data source is the input port of the module, and the logic level is regarded as 0 (module input has no logic level). wa1~wa4, wb1~wb3, wc1~wc3 can be the data input of the multiplexer (mux21), specifically, it can be the data output of the previous mux21, with logic level, which depends on the logic level of the data input of the previous mux21 plus the logic gates through which the data passes through mux21.

[0152] sa1~sa4, sb1~sb3, sc0~sc3 can be the selection signal data input of the multiplexer (mux21). The data source is the input port of the module, and the logic level is regarded as 0.

[0153] Out Figure 3 The output of the multiplexer tree is connected to the output port of the module. The number of levels depends on the maximum number of logic gates that the previous data passes through.

[0154] The calculation of the calculation level is as follows. The following shows the logical level that the input data passes through to each wire in this case:

[0155] wire name Logical Level wire name Logical Level wire name Logical Level a0 0 wa1 2 sa1 0 a1 0 wa2 4 sa2 0 a2 0 wa3 6 sa3 0 a3 0 wa4 8 sa4 0 a4 0 wb1 2 sb1 0 b0 0 wb2 4 sb2 0 b1 0 wb3 6 sb3 0 b2 0 wc1 10 sc0 0 b3 0 wc2 12 sc1 0 c1 0 wc3 14 sc2 0 c2 0 out 16 sc3 0 c3 0

[0156] It should be noted that when calculating the logic level of mux21 data, the logic level of the select end sel signal passing through the "not gate" inside mux21 can be ignored. Only the logic level added by d0 and d1 passing through the "AND gate" and "OR gate" needs to be calculated. Because sel is the selection signal of the current mux21 but does not participate in the data selection of mux21 downstream of the current mux21, it does not affect the subsequent algorithm and is also convenient for calculating the level in the subsequent steps.

[0157] For further understanding, refer to Figure 12-13 , respectively showing a calculation diagram of the wa1 logic level in a multiplexer tree provided by an embodiment of the present invention and a calculation diagram of the wc1 logic level in a multiplexer tree provided by an embodiment of the present invention.

[0158] According to the diagram and the definition of logic level calculation, the output wire logic level calculation formula of a mux21 can be obtained as follows:

[0159] logiclevel(out)=bigger(logiclevel(d0), logiclevel(d1))+2;

[0160] Before optimization, Figure 3 The gate-level resources of the multiplexer tree are shown in the following table:

[0161] Number of mux21 The number of gates used by sel Total number of gates 11 0 33

[0162] It should be noted that the data path refers to the path that the "0" and "1" end data of mux21 are passed back to out in sequence through mux21. The sel path refers to the path that the sel signal acts on mux21 after passing through the not and and gates and is far from out. The mux21 level refers to how many mux21s the data path passes through. The gate level refers to the number of logic gates calculated by not / and / or.

[0163] When the input of the multiplexer tree is limited to the input scenario, the logical level of the multiplexer tree depends on the deepest path in the longest tree, with Figure 3 Take the multiplexer tree as an example. The number of logical levels of the tree depends on the deepest path:

[0164] "mux0->mux1->mux2->mux3->mux4->mux8->mux9->mux10".

[0165] The number of logical levels is the number of mux21s in the deepest path multiplied by 2, that is, the calculation of its level is as shown in the following formula:

[0166] logiclevel(out)=8*2=16;

[0167]

[0168] Its data path is:

[0169] d0->mux11->out;

[0170] d1->mux11->out.

[0171] The sel path is:

[0172] sc0->not0->or0->or2->mux11->out;

[0173] sc1->not1->or0->or2->mux11->out;

[0174] sc2->not2->or1->or2->mux11->out;

[0175] sc3->not3->or1->or2->mux11->out;

[0176] The number of data path mux21 levels is: 1, because there is only one mux21.

[0177] The gate level of the sel path is: 5, reason: the gate level of not+or0(or or1)+or2+mux21.

[0178] In addition, when the select terminal sel signal passes through mux21, it can be considered as two gates, namely and+or. Therefore, the gate level is 5.

[0179] After an optimization, Figure 3 The multiplexer tree becomes Fig.10 The multiplexer tree.

[0180] After optimization, its Fig.10 The gate-level resources of the multiplexer tree are shown in the following table:

[0181] Number of mux21 The number of gates used by sel Total number of gates 12 7 43

[0182] The levels are shown in the following table:

[0183]

[0184] After completing one optimization, the operational parameters of the multiplexer tree can meet the parameter range requirements, and iterative optimization can continue.

[0185] Reference Fig.14 , shows a schematic diagram of the structure of a multiplexer tree provided by an embodiment of the present invention after several iterations of optimization. After several iterations of optimization, the gate-level resources of the optimized multiplexer tree are shown in the following table:

[0186] Number of mux21 The number of gates used by sel Total number of gates 14 19 47

[0187] The number of levels of the optimized multiplexer tree is shown in the following table:

[0188]

[0189]

[0190] contrast Figure 3 and Fig.14, the number of mux21 used is only increased by three, but the number of gates used by sel can be increased from 0 to 19, the total number of gates can be increased from 33 to 47, and the number of levels can be reduced from 16 to 12. A small amount of resources is used in exchange for a reduction in the number of levels of the mux21 tree, effectively reducing costs and improving computing efficiency.

[0191] In this embodiment, the embodiment of the present invention provides an optimization method for a multi-way selector tree, and its beneficial effect is that: after obtaining the multi-way selector tree to be optimized, the present invention can filter the selector path from the multi-way selector tree, and the selector path is the signal transmission path of the maximum level of the multi-way selector tree; according to the selector path, the multi-way selector tree is iteratively optimized until the operation parameters of the multi-way selector tree do not meet the parameter range, and the optimized selector tree is obtained. The whole process is not only fast and simple, but also the optimization only modifies the connection structure of the multi-way selector, uses a small amount of resources, greatly reduces the level of the multi-way selector tree, effectively reduces the cost and improves the computing efficiency.

[0192] The embodiment of the present invention also provides a multi-way selector tree optimization device, see Fig.15 , showing a schematic structural diagram of a multi-way selector tree optimization device provided by an embodiment of the present invention.

[0193] Wherein, as an example, the optimization device of the multiplexer tree may include:

[0194] The acquisition module 101 is used to filter a selector path from the multiplexer tree to be optimized after acquiring the multiplexer tree to be optimized, wherein the selector path is a signal transmission path of the maximum level of the multiplexer tree;

[0195] The optimization module 102 is used to iteratively optimize the multi-way selector tree according to the selector path until the operation parameters of the multi-way selector tree do not meet the parameter range, thereby obtaining an optimized selector tree, wherein the operation parameters include resource parameters and level parameters, and the iterative optimization is to repeatedly truncate and connect the multi-way selector tree.

[0196] Optionally, the acquisition module is further used to:

[0197] Determine a plurality of transmission level values ​​corresponding to the multiplexer tree, each of the transmission level values ​​being the number of multiplexers that a signal passes through after being input at a data end of the multiplexer tree;

[0198] Selecting the transmission level value with the largest value from the plurality of transmission level values ​​as the target base value;

[0199] According to the number of the target cardinality values, one of the paths where the multiplexers corresponding to the target cardinality values ​​are located is selected as a selector path.

[0200] Optionally, the acquisition module is further used to:

[0201] If the number of the target cardinality values ​​is equal to 1, the path where the multi-way selector corresponding to the target cardinality value is located is the selector path;

[0202] If the number of the target cardinality values ​​is greater than or equal to 2, a path that satisfies a selection port preset by the user is selected from the paths where the multiplexers corresponding to the target cardinality values ​​are located as the selector path.

[0203] Optionally, the optimization module is further used to:

[0204] After determining the midpoint of the selector path, truncating the multi-way selector tree at the midpoint to obtain a first tree to be optimized and a second tree to be optimized;

[0205] Connecting the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree;

[0206] If the operation parameters of the multi-way combination tree meet the parameter range, iterating repeatedly with the multi-way combination tree as the multi-way selector tree to be optimized;

[0207] If the operation parameters of the multi-way combination tree do not satisfy the parameter range, the multi-way selector tree to be optimized is used as the optimized selector tree.

[0208] Optionally, the optimization module is further used to:

[0209] If the number of multiplexers in the selector path is an odd number, then the average value of the number of multiplexers is rounded to an integer, and the output end of the multiplexer corresponding to the integer is taken as the midpoint;

[0210] If the number of multiplexers in the selector path is an even number, the output end of the multiplexer corresponding to the average value of the number of multiplexers is taken as the midpoint.

[0211] Optionally, the optimization module is further used to:

[0212] After the step of connecting the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree, a constant signal is input to the input end of the first tree to be optimized or the input end of the second tree to be optimized, wherein the input end of the first tree to be optimized or the input end of the second tree to be optimized is the port of the midpoint.

[0213] Optionally, the optimization module is further used to:

[0214] After the step of connecting the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree, a preset AND gate signal is input to a selection end of the preset selector.

[0215] Those skilled in the art can clearly understand that, for the sake of convenience and brevity of description, the specific working process of the device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0216] Furthermore, an embodiment of the present application also provides an electronic device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the optimization method of the multi-way selector tree as described in the above embodiment is implemented.

[0217] Furthermore, an embodiment of the present application also provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer-executable program, and the computer-executable program is used to enable a computer to execute the multi-way selector tree optimization method as described in the above embodiment.

[0218] It should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention. When an element such as a layer, region or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can also be an intermediate element. On the contrary, when an element is referred to as "directly on" or "above" another element, there is no intermediate element. It should also be understood that when an element is referred to as being "under" or "below" another element, it can be directly under or below the other element, or there can also be an intermediate element. On the contrary, when an element is referred to as being "directly under" or "below" another element, there is no intermediate element. Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0219] Those skilled in the art will appreciate that the embodiments of the present application may also provide computer program products. Therefore, the present application may adopt the form of complete hardware embodiments, complete software embodiments, or embodiments in combination with software and hardware. Moreover, the present application may adopt the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program codes.

[0220] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), apparatuses, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0221] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0222] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0223] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for optimizing a multiplexer tree, characterized in that: The method comprises: After obtaining the multiplexer tree to be optimized, screening a selector path from the multiplexer tree, the selector path being a signal transmission path of the maximum level of the multiplexer tree; The multi-way selector tree is iteratively optimized according to the selector path until the operation parameters of the multi-way selector tree do not meet the parameter range, thereby obtaining an optimized selector tree, wherein the operation parameters include resource parameters and level parameters, and the iterative optimization is to repeatedly truncate and connect the multi-way selector tree.

2. The method for optimizing a multiplexer tree according to claim 1, characterized in that: The filtering of the selector path from the multi-way selector tree comprises: Determine a plurality of transmission level values ​​corresponding to the multiplexer tree, each of the transmission level values ​​being the number of multiplexers that a signal passes through after being input at a data end of the multiplexer tree; Selecting the transmission level value with the largest value from the plurality of transmission level values ​​as the target base value; According to the number of the target cardinality values, one of the paths where the multiplexers corresponding to the target cardinality values ​​are located is selected as a selector path.

3. The method for optimizing a multiplexer tree according to claim 2, characterized in that: The selecting, according to the number of the target cardinality values, one of the paths where the multi-way selectors corresponding to the target cardinality values ​​are located as a selector path comprises: If the number of the target cardinality values ​​is equal to 1, the path where the multi-way selector corresponding to the target cardinality value is located is the selector path; If the number of the target cardinality values ​​is greater than or equal to 2, a path that satisfies a selection port preset by the user is selected from the paths where the multiplexers corresponding to the target cardinality values ​​are located as the selector path.

4. The method for optimizing a multiplexer tree according to claim 1, characterized in that: The iterative optimization of the multi-way selector tree according to the selector path until the operation parameters of the multi-way selector tree do not meet the parameter range to obtain the optimized selector tree includes: After determining the midpoint of the selector path, truncating the multi-way selector tree at the midpoint to obtain a first tree to be optimized and a second tree to be optimized; Connecting the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree; If the operation parameters of the multi-way combination tree meet the parameter range, iterating repeatedly with the multi-way combination tree as the multi-way selector tree to be optimized; If the operation parameters of the multi-way combination tree do not satisfy the parameter range, the multi-way selector tree to be optimized is used as the optimized selector tree.

5. The method for optimizing a multiplexer tree according to claim 4, characterized in that: Determining the midpoint of the selector path includes: If the number of multiplexers in the selector path is an odd number, the average value of the number of multiplexers is rounded to an integer, and the output end of the multiplexer corresponding to the integer is taken as the midpoint; If the number of multiplexers in the selector path is an even number, the output end of the multiplexer corresponding to the average value of the number of multiplexers is taken as the midpoint.

6. The method for optimizing a multiplexer tree according to claim 4, characterized in that: After the step of connecting the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree, the method further includes: A constant signal is input to an input end of the first tree to be optimized or an input end of the second tree to be optimized, wherein the input end of the first tree to be optimized or the input end of the second tree to be optimized is a port of the midpoint.

7. The method for optimizing a multiplexer tree according to claim 4, characterized in that: After the step of connecting the first tree to be optimized and the second tree to be optimized to a preset selector to obtain a multi-way combination tree, the method further includes: The preset AND gate signal is input to the selection end of the preset selector.

8. A multiplexer tree optimization device, characterized in that: The device comprises: An acquisition module, configured to, after acquiring a multiplexer tree to be optimized, filter a selector path from the multiplexer tree, wherein the selector path is a signal transmission path of a maximum level of the multiplexer tree; An optimization module is used to iteratively optimize the multi-way selector tree according to the selector path until the operation parameters of the multi-way selector tree do not meet the parameter range, thereby obtaining an optimized selector tree, wherein the operation parameters include resource parameters and level parameters, and the iterative optimization is to repeatedly truncate and connect the multi-way selector tree.

9. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method for optimizing a multi-way selector tree as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer-executable program, and the computer-executable program is used to enable a computer to execute the method for optimizing a multiplexer tree as described in any one of claims 1 to 7.

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