Global shutter pixel and image sensor

Abstract

The invention discloses a global shutter pixel and an image sensor, and relates to the technical field of image sensors, and the global shutter pixel comprises a photosensitive unit, a transmission unit, a reset unit, an amplification unit, a storage unit, an output unit and a port unit. The amplification unit comprises an amplification circuit and a filter circuit; the first end of the amplifying circuit serves as the output end of the amplifying unit, the first end of the filtering circuit is connected with the second end of the amplifying circuit, and the second end of the filtering circuit is connected with the port unit; and the storage unit is connected with the port unit. The voltage output by the amplification unit can be increased through the output level of the port unit, and when the pixel power supply voltage is reduced, the voltage output by the amplification unit can be kept unchanged or even increased. The voltage stored by the storage unit can be increased through the output level of the port unit, so that the output linearity of the pixel is increased. The filter circuit carries out filtering so that noise and ripple waves can be reduced, and finally a high-quality image is obtained.

Description

Technical Field

[0001] The present application relates to the technical field of image sensors, and in particular to a global shutter pixel and an image sensor. Background Art

[0002] like Figure 1 The global shutter pixel structure shown in the figure is an 8T (Transistors) structure. After the exposure is completed, the reset signal and the photoelectric signal captured during the exposure process first cause the floating diffusion node to have a corresponding voltage change, and then are converted into analog voltage domain signals through the first-stage source follower tube, stored through two capacitors, and then the second-stage source follower tube is used to transmit the two signals to the peripheral circuit. The source follower tubes of these two stages will multiply the previous stage signal by a coefficient less than 1 and output it to the next stage, so the final signal will be significantly smaller than the initial signal, resulting in a decrease in the image signal-to-noise ratio. For this reason, the pixel voltage is currently increased to increase the output value to improve the image signal-to-noise ratio. However, increasing the pixel voltage will lead to a significant increase in power consumption. In the face of the demand for low power consumption, the conventional method is to reduce the pixel power supply voltage, and reducing the pixel power supply voltage will lead to a decrease in the image signal-to-noise ratio. Therefore, how to reduce the pixel power supply voltage to achieve low power consumption while avoiding the decrease in image signal-to-noise ratio and ensuring image quality has become a technical problem that needs to be solved urgently by technicians in this field. Summary of the invention

[0003] The purpose of this application is to provide a global shutter pixel and image sensor, which can reduce the pixel power supply voltage to achieve low power consumption while avoiding the decrease of image signal-to-noise ratio and ensuring image quality.

[0004] In order to solve the above technical problems, the present application provides a global shutter pixel, comprising:

[0005] A photosensitive unit, a transmission unit, a reset unit, an amplifying unit, a storage unit, an output unit and a port unit; the amplifying unit includes an amplifying circuit and a filtering circuit; the first end of the amplifying circuit serves as the output end of the amplifying unit, the first end of the filtering circuit is connected to the second end of the amplifying circuit, and the second end of the filtering circuit is connected to the port unit; the storage unit is connected to the port unit;

[0006] The photosensitive unit is used to generate charges by sensing light;

[0007] The transmission unit is used to transmit the charge generated by the photosensitive unit to the floating diffusion node when the transmission unit is turned on; the input end of the amplification unit serves as the floating diffusion node;

[0008] The resetting unit is used to reset the pixel;

[0009] The amplifying unit is used to amplify the voltage at the floating diffusion node through the amplifying circuit and output it to the storage unit, and to filter it through the filtering circuit;

[0010] The storage unit is used to store the reset voltage and the signal voltage;

[0011] The output unit is used to output the signal voltage and the reset voltage;

[0012] The port unit is used to output a level signal to raise the voltage output by the amplifying unit in the storage reset voltage stage and the storage signal voltage stage, and to raise the voltage stored in the storage unit in the preset stage, the read reset voltage stage and the read signal voltage stage; the preset stage is located between the storage signal voltage stage and the read reset voltage stage.

[0013] In some embodiments, the port unit comprises:

[0014] A first port and a second port; the second end of the filter circuit is connected to the first port; the storage unit is connected to the second port;

[0015] The first port is used to output a first level signal in the reset voltage storage stage and the signal voltage storage stage to raise the voltage output by the amplifying unit;

[0016] The second port is used to output a first level signal in the preset stage, the read reset voltage stage and the read signal voltage stage to raise the voltage stored in the storage unit.

[0017] In some embodiments, the port unit comprises:

[0018] a third port; the second end of the filter circuit and the storage unit are both connected to the third port; the third port is used to output a first target level signal in the storage reset voltage stage and the storage signal voltage stage to raise the voltage output by the amplification unit; in the preset stage, the read reset voltage stage and the read signal voltage stage, output a second target level signal to raise the voltage stored in the storage unit; wherein the second target level signal output by the third port in the preset stage, the read reset voltage stage and the read signal voltage stage is higher than the first target level signal output in the storage reset voltage stage and the storage signal voltage stage.

[0019] In some embodiments, the storage unit includes:

[0020] A first storage unit and a second storage unit;

[0021] The first storage unit is used to store a signal voltage;

[0022] The second storage unit is used to store a reset voltage.

[0023] In some embodiments, the transmission unit is controlled by a first control signal, and when the first control signal is a first level signal, the transmission unit is turned on; the reset unit is controlled by a second control signal, and when the second control signal is a first level signal, the reset unit is turned on; the amplifier circuit is controlled by a third control signal, and when the third control signal is a first level signal, the first end of the amplifier circuit is connected to the second end of the amplifier circuit; the first storage unit is controlled by a fourth control signal, and when the fourth control signal is a first level signal, the capacitor in the first storage unit is connected to the output end of the amplifier unit; the second storage unit is controlled by a fifth control signal, and when the fifth control signal is a first level signal, the capacitor in the second storage unit is connected to the first storage unit; the output unit is controlled by a sixth control signal, and when the sixth control signal is a first level signal, the output unit outputs a voltage.

[0024] In some embodiments, in the reset stage, the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first level signals, and the sixth control signal, the signal output by the first port of the port unit, and the signal output by the second port of the port unit are second level signals; in the exposure stage, the first control signal, the sixth control signal, the signal output by the first port of the port unit, and the signal output by the second port of the port unit are second level signals; the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first level signals; in the reset voltage storage stage, the first control signal, the second control signal, the sixth control signal, and the signal output by the second port of the port unit are second level signals, and the third control signal, the fourth control signal, the fifth control signal, and the signal output by the first port of the port unit are first level signals; in the signal voltage storage stage , the first control signal, the second control signal, the fifth control signal, the sixth control signal and the signal output by the second port of the port unit are second level signals, and the third control signal, the fourth control signal and the signal output by the first port of the port unit are first level signals; in the preset stage, the first control signal to the sixth control signal and the signal output by the first port of the port unit are second level signals, and the signal output by the second port of the port unit is a first level signal; in the read reset voltage stage, the first control signal to the fifth control signal and the signal output by the first port of the port unit are second level signals, and the sixth control signal and the signal output by the second port of the port unit are first level signals; in the read signal voltage stage, the first control signal to the fifth control signal and the signal output by the first port of the port unit are second level signals, and the sixth control signal and the signal output by the second port of the port unit are first level signals.

[0025] In some embodiments, in the reset stage, the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first level signals, and the sixth control signal and the signal output by the third port of the port unit are second level signals; in the exposure stage, the first control signal, the sixth control signal, and the signal output by the third port of the port unit are second level signals; the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first level signals; in the reset voltage storage stage, the first control signal, the second control signal, and the sixth control signal are second level signals, the third control signal, the fourth control signal, and the fifth control signal are first level signals, and the signal output by the third port of the port unit is a first target level signal; in the signal voltage storage stage, the The first control signal, the second control signal, the fifth control signal, and the sixth control signal are second level signals, the third control signal and the fourth control signal are first level signals, and the signal output by the third port of the port unit is a first target level signal; in the preset stage, the first control signal to the sixth control signal are second level signals, and the signal output by the third port of the port unit is a second target level signal; in the read reset voltage stage, the first control signal to the fifth control signal are second level signals, the sixth control signal and the fifth control signal are first level signals, and the signal output by the third port of the port unit is a second target level signal; in the read signal voltage stage, the first control signal to the fifth control signal are second level signals, the sixth control signal and the fifth control signal are first level signals, and the signal output by the third port of the port unit is a second target level signal.

[0026] In some embodiments, the filtering circuit comprises:

[0027] A resistor and a first capacitor; the first capacitor is connected in parallel with the resistor, a first common end of the first capacitor and the resistor serves as a first end of the filter circuit, and a second common end of the first capacitor and the resistor serves as a second end of the filter circuit.

[0028] In some embodiments, the filtering circuit comprises:

[0029] A resistor and a first transistor; one end of the resistor is connected to the first end of the first transistor and serves as the first end of the filter circuit, and the other end of the resistor is connected to the second end of the first transistor and / or the third end of the first transistor and serves as the second end of the filter circuit.

[0030] In some embodiments, the photosensitive unit includes:

[0031] A photosensitive diode; an anode of the photosensitive diode is grounded, and a cathode of the photosensitive diode is connected to the transmission unit.

[0032] In some embodiments, the transmission unit includes:

[0033] A second transistor; a second end of the second transistor is connected to the photosensitive unit, a third end of the second transistor is connected to the input end of the amplifying unit, and the second transistor is controlled by the first control signal.

[0034] In some embodiments, the resetting unit comprises:

[0035] a third transistor; a second end of the third transistor is connected to the input end of the amplifying unit, a third end of the third transistor is connected to the pixel power supply, and the third transistor is controlled by the second control signal.

[0036] In some embodiments, the amplification circuit includes:

[0037] A fourth transistor and a fifth transistor; the first end of the fourth transistor serves as the input end of the amplifier circuit, the third end of the fourth transistor is connected to the pixel power supply, the second end of the fourth transistor is connected to the third end of the fifth transistor and serves as the first end of the amplifier circuit, the second end of the fifth transistor serves as the second end of the amplifier circuit, and the fifth transistor is controlled by the third control signal.

[0038] In some embodiments, the first storage unit includes:

[0039] A sixth transistor and a second capacitor; the second end of the sixth transistor is connected to the output end of the amplifying unit, the third end of the sixth transistor is connected to the first end of the second capacitor and the first end of the second storage unit, the sixth transistor is controlled by a fourth control signal, and the second end of the second capacitor is connected to the port unit.

[0040] In some embodiments, the second storage unit includes:

[0041] A seventh transistor and a third capacitor; the second end of the seventh transistor is connected to the first storage unit as the first end of the second storage unit, the third end of the seventh transistor is connected to the first end of the third capacitor and the input end of the output unit, the seventh transistor is controlled by a fifth control signal, and the second end of the third capacitor is connected to the port unit.

[0042] In some embodiments, the output unit includes:

[0043] An eighth transistor and a ninth transistor; the first end of the eighth transistor serves as the input end of the output unit, the third end of the eighth transistor is connected to the pixel power supply, the second end of the eighth transistor is connected to the third end of the ninth transistor, the second end of the ninth transistor serves as the output end of the output unit, and the ninth transistor is controlled by the sixth control signal.

[0044] In order to solve the above technical problem, the present application also provides an image sensor, including the global shutter pixel as described above.

[0045] The global shutter pixel provided in the present application includes: a photosensitive unit, a transmission unit, a reset unit, an amplifying unit, a storage unit, an output unit and a port unit; the amplifying unit includes an amplifying circuit and a filtering circuit; the first end of the amplifying circuit serves as the output end of the amplifying unit, the first end of the filtering circuit is connected to the second end of the amplifying circuit, and the second end of the filtering circuit is connected to the port unit; the storage unit is connected to the port unit; the photosensitive unit is used to generate charges by light; the transmission unit is used to transmit the charges generated by the photosensitive unit to a floating diffusion node when the transmission unit is turned on; the input end of the amplifying unit serves as the floating diffusion node; The reset unit is used to reset the pixel; the amplification unit is used to amplify the voltage at the floating diffusion node through the amplification circuit and output it to the storage unit, and filter it through the filtering circuit; the storage unit is used to store the reset voltage and the signal voltage; the output unit is used to output the signal voltage and the reset voltage; the port unit is used to output a level signal to raise the voltage output by the amplification unit in the reset voltage storage stage and the signal voltage storage stage, and to raise the voltage stored in the storage unit in the preset stage, the reset voltage reading stage and the signal voltage reading stage; the preset stage is located between the signal voltage storage stage and the reset voltage reading stage.

[0046] It can be seen that the global shutter pixel provided by the present application, the amplification unit includes an amplification circuit and a filtering circuit, the amplification circuit is connected to the filtering circuit, the filtering circuit is connected to the port unit, and the voltage output by the amplification unit can be raised through the output level of the port unit. When the pixel power supply voltage is reduced, the voltage output by the amplification unit can be kept unchanged or even increased. At the same time, the storage unit is connected to the port unit, and the voltage stored in the storage unit can be raised through the output level of the port unit, so that the pixel output can be linearly increased. In addition, filtering by the filtering circuit can reduce the noise and ripple generated by the level jump of the port unit output, and finally obtain a high-quality image.

[0047] The image sensor provided in this application also has the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the prior art and the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 A schematic diagram of a global shutter pixel with an 8T structure;

[0050] Figure 2 A schematic diagram of a global shutter pixel provided in an embodiment of the present application;

[0051] Figure 3 A schematic diagram of noise and ripple provided in an embodiment of the present application;

[0052] Figure 4 A schematic diagram of another noise and ripple provided in an embodiment of the present application;

[0053] Figure 5 A schematic diagram of a specific global shutter pixel provided in an embodiment of the present application;

[0054] Figure 6 A timing diagram provided in an embodiment of the present application;

[0055] Figure 7 A potential diagram provided by an embodiment of the present application;

[0056] Figure 8 Another timing diagram provided for an embodiment of the present application;

[0057] Fig. 9 A schematic diagram of another specific global shutter pixel provided in an embodiment of the present application;

[0058] Fig.10 A schematic diagram of another specific global shutter pixel provided in an embodiment of the present application;

[0059] Fig.11 A schematic diagram of another specific global shutter pixel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] The core of this application is to provide a global shutter pixel and image sensor, which can reduce the pixel power supply voltage to achieve low power consumption while avoiding the decrease of image signal-to-noise ratio and ensuring image quality.

[0061] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0062] Please refer to Figure 2 , Figure 2 A schematic diagram of a global shutter pixel provided in an embodiment of the present application, referring to Figure 2 As shown, the global shutter pixel includes:

[0063] A photosensitive unit 10, a transmission unit 20, a reset unit 30, an amplifying unit 40, a storage unit 50, an output unit 60 and a port unit 70; the amplifying unit 40 includes an amplifying circuit 401 and a filtering circuit 402; a first end of the amplifying circuit 401 serves as an output end of the amplifying unit 40, a first end of the filtering circuit 402 is connected to a second end of the amplifying circuit 401, and a second end of the filtering circuit 402 is connected to the port unit 70; the storage unit 50 is connected to the port unit 70;

[0064] The photosensitive unit 10 is used for generating charges by sensing light;

[0065] The transmission unit 20 is used to transmit the charge generated by the photosensitive unit 10 to the floating diffusion node when the transmission unit 20 is turned on; the input end of the amplification unit 40 serves as the floating diffusion node;

[0066] The resetting unit 30 is used to reset the pixel;

[0067] The amplifying unit 40 is used to amplify the voltage at the floating diffusion node through the amplifying circuit 401 and output it to the storage unit 50, and filter it through the filtering circuit 402;

[0068] The storage unit 50 is used to store the reset voltage and the signal voltage;

[0069] The output unit 60 is used to output the signal voltage and the reset voltage;

[0070] The port unit 70 is used to output a level signal to raise the voltage output by the amplifying unit 40 in the storage reset voltage stage and the storage signal voltage stage, and to raise the voltage stored in the storage unit 50 in the preset stage, the read reset voltage stage and the read signal voltage stage; the preset stage is located between the storage signal voltage stage and the read reset voltage stage.

[0071] The amplifying unit 40 includes an amplifying circuit 401 and a filtering circuit 402. The amplifying circuit 401 is used to amplify the voltage at the floating diffusion node and then output it to the storage unit 50. The filtering circuit 402 is used for filtering. One end of the filtering circuit 402 is connected to the amplifying circuit 401, and the other end of the filtering circuit 402 is connected to the port unit 70. When the pixel power supply voltage is reduced, the voltage output by the amplifying unit 40 will be reduced, the voltage stored in the storage unit 50 will be reduced, and the voltage output by the output unit 60 will be reduced, which will cause the signal-to-noise ratio of the overall image to decrease, affecting the quality of the image. In order to ensure the quality of the image, the filtering circuit 402 is connected to the port unit 70 in this embodiment, and the port unit 70 outputs a high level in the reset voltage storage stage and the signal voltage storage stage, so that the voltage of the second end of the amplifying circuit 401 can be raised in the reset voltage storage stage and the signal voltage storage stage, so that the voltage of the first end of the amplifying circuit 401 is increased, that is, the voltage of the output end of the amplifying unit 40 is increased. Therefore, when the pixel power supply voltage is reduced, the voltage of the output end of the amplifying unit 40 remains unchanged or even increases.

[0072] like Figure 3 As shown, noise and ripple will exist in the process of the level of the port unit 70 output changing from low to high. The main sources of noise are the switching noise itself and the noise caused by the switching current of the devices in the power supply. The noise may appear randomly in time, but it tends to be consistent with the clock in the system. The level output by the port unit 70 is obtained by rectifying, filtering, and stabilizing the external voltage. Due to unclean filtering, a noise signal containing periodic and random components will be attached to the level, thereby forming a ripple. The noise and ripple of the port unit 70 will be recorded at the output end of the amplification unit 40, resulting in an increase in the row and column noise of the pixel. To this end, in this embodiment, the amplification unit 40 is provided with a filter circuit 402, and the filter circuit 402 is used to reduce the noise and ripple caused by the voltage jump of the port unit 70, thereby achieving uniform control of the potential of the output end of the amplification unit 40. As shown Figure 4 As shown, the filtering circuit 402 can effectively reduce noise and ripple.

[0073] When the pixel power supply voltage is reduced, the voltage output by the amplification unit 40 will be reduced, the voltage stored by the storage unit 50 will be reduced, and the voltage output by the output unit 60 will be reduced, which will cause the signal-to-noise ratio of the overall image to decrease, affecting the quality of the image. In order to ensure the quality of the image, the storage unit 50 is connected to the port unit 70 in this embodiment. The port unit 70 outputs a high level in the preset stage, the read reset voltage stage, and the read signal voltage stage to raise the voltage stored in the storage unit 50 in the preset stage, the read reset voltage stage, and the read signal voltage stage. The preset stage is located between the storage signal voltage stage and the read reset voltage stage. In this way, when the pixel power supply voltage is reduced, the voltage stored in the storage unit 50 remains unchanged or even increases.

[0074] In some embodiments, the port unit 70 includes:

[0075] A first port and a second port; the second end of the filter circuit 402 is connected to the first port; the storage unit 50 is connected to the second port;

[0076] The first port is used to output a first level signal in the reset voltage storage stage and the signal voltage storage stage to raise the voltage output by the amplifying unit 40;

[0077] The second port is used to output a first level signal in the preset stage, the read reset voltage stage and the read signal voltage stage to raise the voltage stored in the storage unit 50 .

[0078] In this embodiment, the filter circuit 402 and the storage unit 50 are connected to different ports of the port unit 70. The first port outputs a first level signal in the storage reset voltage stage and the storage signal voltage stage to raise the voltage output by the amplifier unit 40. The second port outputs a first level signal in the preset stage, the read reset voltage stage and the read signal voltage stage to raise the voltage stored in the storage unit 50. The first level signal is a high level.

[0079] In some embodiments, the port unit 70 includes:

[0080] a third port; the second end of the filter circuit 402 and the storage unit 50 are both connected to the third port; the third port is used to output a first target level signal in the storage reset voltage stage and the storage signal voltage stage to raise the voltage output by the amplification unit 40; and output a second target level signal in the preset stage, the read reset voltage stage and the read signal voltage stage to raise the voltage stored in the storage unit 50; wherein the second target level signal output by the third port in the preset stage, the read reset voltage stage and the read signal voltage stage is higher than the first target level signal output in the storage reset voltage stage and the storage signal voltage stage.

[0081] In this embodiment, the filter circuit 402 and the storage unit 50 are connected to the same port of the port unit 70, which is called the third port. The third port outputs a first target level signal in the storage reset voltage stage and the storage signal voltage stage to raise the voltage output by the amplification unit 40; the third port outputs a second target level signal in the preset stage, the read reset voltage stage and the read signal voltage stage to raise the voltage stored in the storage unit 50. Among them, the first target level signal and the second target level signal are high levels. The second target level signal output by the third port in the preset stage, the read reset voltage stage and the read signal voltage stage is higher than the first target level signal output in the storage reset voltage stage and the storage signal voltage stage. The filter circuit 402 and the storage unit 50 are connected to the same port of the port unit 70, which can save the layout area of ​​the pixel and improve the integration.

[0082] refer to Figure 5 As shown, in some embodiments, the storage unit 50 includes:

[0083] A first storage unit 501 and a second storage unit 502;

[0084] The first storage unit 501 is used to store signal voltage;

[0085] The second storage unit 502 is used to store a reset voltage.

[0086] In this embodiment, the storage unit 50 includes a first storage unit 501 and a second storage unit 502 . The first storage unit 501 and the second storage unit 502 are used to store a signal voltage and a reset voltage respectively.

[0087] In some embodiments, the first storage unit 501 and the second storage unit 502 both include capacitors.

[0088] In some embodiments, the transmission unit 20 is controlled by a first control signal, and when the first control signal is a first level signal, the transmission unit 20 is turned on; the reset unit 30 is controlled by a second control signal, and when the second control signal is a first level signal, the reset unit 30 is turned on; the amplifier circuit 401 is controlled by a third control signal, and when the third control signal is a first level signal, the first end of the amplifier circuit 401 is connected to the second end of the amplifier circuit 401; the first storage unit 501 is controlled by a fourth control signal, and when the fourth control signal is a first level signal, the capacitor in the first storage unit 501 is connected to the output end of the amplifier unit 40; the second storage unit 502 is controlled by a fifth control signal, and when the fifth control signal is a first level signal, the capacitor in the second storage unit 502 is connected to the first storage unit 501; the output unit 60 is controlled by a sixth control signal, and when the sixth control signal is a first level signal, the output unit 60 outputs a voltage.

[0089] The first level signal is a high level, that is, when the first control signal is a high level, the transmission unit 20 is turned on; when the second control signal is a high level, the reset unit 30 is turned on; when the third control signal is a high level, the first end of the amplifier circuit 401 is connected to the second end of the amplifier circuit 401; when the fourth control signal is a high level, the capacitor in the first storage unit 501 is connected to the output end of the amplifier unit 40; when the fifth control signal is a high level, the capacitor in the second storage unit 502 is connected to the first storage unit 501; when the sixth control signal is a high level, the output unit 60 outputs a voltage.

[0090] In some embodiments, in the reset stage, the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first level signals, and the sixth control signal, the signal output by the first port of the port unit 70, and the signal output by the second port of the port unit 70 are second level signals; in the exposure stage, the first control signal, the sixth control signal, the signal output by the first port of the port unit 70, and the signal output by the second port of the port unit 70 are second level signals; the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first level signals; in the reset voltage storage stage, the first control signal, the second control signal, the sixth control signal, and the signal output by the second port of the port unit 70 are second level signals, and the third control signal, the fourth control signal, the fifth control signal, and the signal output by the first port of the port unit 70 are first level signals; in the signal voltage storage stage, The first control signal, the second control signal, the fifth control signal, the sixth control signal and the signal output by the second port of the port unit 70 are second level signals, and the third control signal, the fourth control signal and the signal output by the first port of the port unit 70 are first level signals; in the preset stage, the first control signal to the sixth control signal and the signal output by the first port of the port unit 70 are second level signals, and the signal output by the second port of the port unit 70 is a first level signal; in the read reset voltage stage, the first control signal to the fifth control signal and the signal output by the first port of the port unit 70 are second level signals, and the sixth control signal and the signal output by the second port of the port unit 70 are first level signals; in the read signal voltage stage, the first control signal to the fifth control signal and the signal output by the first port of the port unit 70 are second level signals, and the sixth control signal and the signal output by the second port of the port unit 70 are first level signals.

[0091] The first level signal is a high level, and the second level signal is a low level.

[0092] On the basis that the port unit 70 includes a first port and a second port, the second end of the filter circuit 402 is connected to the first port; and the storage unit 50 is connected to the second port, the timing of each control signal and the signals output from the first port and the second port can refer to Figure 6 As shown. Under this timing, the working principle of the global shutter pixel is as follows:

[0093] Figure 6In the figure, TG represents the first control signal, RST represents the second control signal, PC represents the third control signal, S1 represents the fourth control signal, S2 represents the fifth control signal, SEL represents the sixth control signal, PCB represents the signal output by the first port, and SDB represents the signal output by the second port.

[0094] From t0 to t1: the sixth control signal is at a low level (generally -1V to 0V), and the output unit 60 is turned off. The first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are at a high level (generally 2.5V to 3.5V), and the transmission unit 20, the reset unit 30, the amplification unit 40, the first storage unit 501, and the second storage unit 502 are turned on, clearing the original charge of the photosensitive unit 10, the floating diffusion node, the output end of the amplification unit 40, the first storage unit 501, and the second storage unit 502, and the voltage of the floating diffusion node is approximately equal to the pixel power supply PIXVDD. At the same time, from t0 to t1, the signals output by the first port and the second port are at a low level (generally -2V to 0V).

[0095] From t1 to t2: the first control signal is at a low level (e.g., -1V to 0V), the transmission unit 20 is turned off, and the photosensitive unit 10 begins to accumulate charges. The second control signal, the third control signal, the fourth control signal, and the fifth control signal are kept at a high level, and the reset unit 30, the amplification unit 40, the first storage unit 501, and the second storage unit 502 are kept turned on to remove the noise at the floating diffusion node, thereby improving the image quality.

[0096] From t2 to t3: the level of the output of the first port is pulled to a high level (generally 0.1V to 1.5V). The voltage of the floating diffusion node is amplified by the amplifier unit 40 and then transmitted to the storage unit 50. The transmitted voltage is approximately 70% to 90% of the voltage of the floating diffusion node. At this time, the fourth control signal and the fifth control signal are at a high level, the first storage unit 501 and the second storage unit 502 are in a conducting state, and the second storage unit 502 stores a reset voltage. At t3, the fifth control signal changes from a high level to a low level, thereby turning off the second storage unit 502.

[0097] Since a high level is output through the first port from time t2 to t3, the voltage at the output end of the amplifying unit 40 rises, and the voltage of the second storage unit 502 can be kept unchanged or even increased by pulling up the voltage of the first port while reducing the pixel power supply voltage PIXVDD. At the same time, the filtering circuit 402 can effectively reduce the noise and ripple caused by the voltage jump of the first port.

[0098] From t3 to t4: First, the first control signal becomes high, and the transmission unit 20 is turned on. Since the photosensitive unit 10 has a potential difference with the floating diffusion node, the charge is transmitted to the floating diffusion node through the transmission unit 20. Then the first control signal becomes low, thereby turning off the transmission unit 20, and the floating diffusion node enters a stable state. The voltage of the floating diffusion node is amplified by the amplifier unit 40 and then transmitted to the storage unit 50. The transmitted voltage is about 70% to 90% of the voltage of the floating diffusion node. At this time, the fourth control signal is high, the fifth control signal is low, the first storage unit 501 is turned on, the second storage unit 502 is turned off, and the first storage unit 501 stores the signal voltage. At t4, the fourth control signal changes from high to low, thereby turning off the first storage unit 501.

[0099] Similarly, since the output of the first port maintains a high level from time t3 to t4, the voltage stored in the first storage unit 501 can be kept unchanged or even increased by raising the level of the first port while reducing the pixel power supply voltage PIXVDD.

[0100] From t4 to t5: the level of the output of the second port is pulled up from a low level (generally 0.1V to 2V). Since the fourth control signal and the fifth control signal are at a low level from t4 to t5, the first storage unit 501 and the second storage unit 502 are turned off. Therefore, the first voltage domain storage node (one end of the first storage unit 501) and the second voltage domain storage node (one end of the second storage unit 502) are both in a floating state (the floating state means that there is no leakage channel in the storage node, and the storage charge of the storage node is conserved). The level raising value of the second port causes the first voltage domain storage node and the second voltage domain storage node to rise to the same voltage. Therefore Vout value remains unchanged (if attached Figure 7 As shown in FIG. 1 ), the reset voltage and the signal voltage actually read out are maintained or even increased when the pixel power supply PIXVDD decreases, so as to maintain the low noise and high linearity of the output of the output unit 60.

[0101] in, Vout = V1_SD-V2_SD. V1_SD represents the reset voltage, and V2_SD represents the signal voltage. SD stands for Storage Diode, which means voltage domain storage.

[0102] From t5 to t6: the sixth control signal is at a high level, thereby turning on the output unit 60, and the reset voltage is transmitted to the output terminal PIX_OUT of the pixel through the output unit 60, and its value is named V1_PIX_OUT.

[0103] From t6 to t7, the fifth control signal is at a high level, thereby turning on the second storage unit 502, and the voltage value after coupling the voltage stored in the first storage unit 501 and the second storage unit 502 is equal to (C2*V2_SD+ C3*V1_SD) / (C2+C3). C2 is the capacitor in the first storage unit 501, and C3 is the capacitor in the second storage unit 502.

[0104] From t7 to t8: the fifth control signal is at a low level, thereby turning off the second storage unit 502. At this time, the coupled voltage is transmitted to the output terminal PIX_OUT of the pixel through the output unit 60, and its value is named V2_PIX_OUT.

[0105] After t8: in reset standby state.

[0106] In some embodiments, in the reset stage, the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first level signals, and the sixth control signal and the signal output by the third port of the port unit 70 are second level signals; in the exposure stage, the first control signal, the sixth control signal, and the signal output by the third port of the port unit 70 are second level signals; the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first level signals; in the reset voltage storage stage, the first control signal, the second control signal, and the sixth control signal are second level signals, the third control signal, the fourth control signal, and the fifth control signal are first level signals, and the signal output by the third port of the port unit 70 is a first target level signal; in the signal voltage storage stage, the The first control signal, the second control signal, the fifth control signal, and the sixth control signal are second level signals, the third control signal and the fourth control signal are first level signals, and the signal output by the third port of the port unit 70 is a first target level signal; in the preset stage, the first control signal to the sixth control signal are second level signals, and the signal output by the third port of the port unit 70 is a second target level signal; in the read reset voltage stage, the first control signal to the fifth control signal are second level signals, the sixth control signal is a first level signal, and the signal output by the third port of the port unit 70 is a second target level signal; in the read signal voltage stage, the first control signal to the fifth control signal are second level signals, the sixth control signal is a first level signal, and the signal output by the third port of the port unit 70 is a second target level signal.

[0107] The first level signal, the first target level signal, and the second target level signal are high level, and the second level signal is low level, wherein the second target level signal is higher than the first target level signal.

[0108] On the basis that the port unit 70 includes a third port, the second end of the filter circuit 402 and the storage unit 50 are both connected to the third port, the timing of each control signal and the signal output from the third port can refer to Figure 8 As shown. Under this timing, the working principle of the global shutter pixel is as follows:

[0109] Figure 8 In the figure, TG represents the first control signal, RST represents the second control signal, PC represents the third control signal, S1 represents the fourth control signal, S2 represents the fifth control signal, SEL represents the sixth control signal, and SIG represents the signal output by the third port.

[0110] From t0 to t1: the sixth control signal is at a low level (generally -1V to 0V), and the output unit 60 is turned off. The first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are at a high level (generally 2.5V to 3.5V), and the transmission unit 20, the reset unit 30, the amplification unit 40, the first storage unit 501, and the second storage unit 502 are turned on, clearing the original charge of the photosensitive unit 10, the floating diffusion node, the output end of the amplification unit 40, the first storage unit 501, and the second storage unit 502, and the voltage of the floating diffusion node is approximately equal to the pixel power supply PIXVDD. At the same time, from t0 to t1, the signal output by the third port is at a low level (generally -2V to 0V).

[0111] From t1 to t2: the first control signal is at a low level (e.g., -1V to 0V), the transmission unit 20 is turned off, and the photosensitive unit 10 begins to accumulate charges. The second control signal, the third control signal, the fourth control signal, and the fifth control signal are kept at a high level, and the reset unit 30, the amplification unit 40, the first storage unit 501, and the second storage unit 502 are kept turned on to remove the noise at the floating diffusion node, thereby improving the image quality.

[0112] From t2 to t3: the level of the output of the third port is pulled to a high level (generally 0.1V to 1.5V). The voltage of the floating diffusion node is amplified by the amplifier unit 40 and then transmitted to the storage unit 50. The transmitted voltage is approximately 70% to 90% of the voltage of the floating diffusion node. At this time, the fourth control signal and the fifth control signal are at a high level, the first storage unit 501 and the second storage unit 502 are in a conducting state, and the second storage unit 502 stores a reset voltage. At t3, the fifth control signal changes from a high level to a low level, thereby turning off the second storage unit 502.

[0113] Since a high level is output through the third port from time t2 to t3, the voltage at the output end of the amplifying unit 40 rises, and the voltage of the second storage unit 502 can be kept unchanged or even increased by raising the voltage of the third port while reducing the pixel power supply voltage PIXVDD. At the same time, the filtering circuit 402 can effectively reduce the noise and ripple caused by the voltage jump of the first port.

[0114] From t3 to t4: First, the first control signal becomes high, and the transmission unit 20 is turned on. Since the photosensitive unit 10 has a potential difference with the floating diffusion node, the charge is transmitted to the floating diffusion node through the transmission unit 20. Then, the first control signal becomes low, so that the transmission unit 20 is turned off, and the floating diffusion node enters a stable state. The voltage of the floating diffusion node is amplified by the amplifier unit 40 and then transmitted to the storage unit 50. The transmitted voltage is about 70% to 90% of the voltage of the floating diffusion node. From t3 to t4, since the fourth control signal is high and the fifth control signal is low, the first storage unit 501 is turned on and the second storage unit 502 is turned off, so that the first storage unit 501 stores the signal voltage.

[0115] Similarly, since the output of the third port maintains a high level from time t3 to t4, the voltage stored in the first storage unit 501 can be kept unchanged or even increased by raising the level of the third port while reducing the pixel power supply voltage PIXVDD.

[0116] From t4 to t5: the level of the output of the third port continues to be pulled high (usually 0.1V to 2V). Since the fourth control signal and the fifth control signal are at low levels from t4 to t5, the first storage unit 501 and the second storage unit 502 are turned off, so the first voltage domain storage node (one end of the first storage unit 501) and the second voltage domain storage node (one end of the second storage unit 502) are both in a floating state, and the level raising value of the third port causes the first voltage domain storage node and the second voltage domain storage node to rise to the same voltage, so The Vout value remains unchanged, thereby maintaining or even increasing the reset voltage and signal voltage actually read out when the pixel power supply PIXVDD decreases, so as to maintain low noise and high linearity of the output of the output unit 60 .

[0117] From t5 to t6: the sixth control signal is at a high level, thereby turning on the output unit 60, and the reset voltage is transmitted to the output terminal PIX_OUT of the pixel through the output unit 60, and its value is named V1_PIX_OUT.

[0118] From t6 to t7, the fifth control signal is at a high level, thereby turning on the second storage unit 502, and the voltage value after coupling the voltage stored in the first storage unit 501 and the second storage unit 502 is equal to (C2*V2_SD+ C3*V1_SD) / (C2+C3). C2 is the capacitor in the first storage unit 501, and C3 is the capacitor in the second storage unit 502.

[0119] From t7 to t8: the fifth control signal is at a low level, thereby turning off the second storage unit 502. At this time, the coupled voltage is transmitted to the output terminal PIX_OUT of the pixel through the output unit 60, and its value is named V2_PIX_OUT.

[0120] After t8: in reset standby state.

[0121] refer to Figures 9 to 11 As shown in any embodiment, the photosensitive unit 10 includes: a photosensitive diode PD; the anode of the photosensitive diode PD is grounded, and the cathode of the photosensitive diode PD is connected to the transmission unit 20. The transmission unit 20 includes: a second transistor; the second end of the second transistor is connected to the photosensitive unit 10, the third end of the second transistor is connected to the input end of the amplification unit 40, and the second transistor is controlled by the first control signal. The reset unit 30 includes: a third transistor; the second end of the third transistor is connected to the input end of the amplification unit 40, the third end of the third transistor is connected to the pixel power supply, and the third transistor is controlled by the second control signal.

[0122] Fig. 9 and Fig.10 In the figure, PIXVDD represents the pixel power supply, and PIXVSS represents the pixel ground. The second transistor M2 and the third transistor M3 are turned on in the reset phase to clear the original charge of the photosensitive diode PD and the floating diffusion node FD. The photosensitive diode PD generates charge by light sensing in the exposure phase, and in the exposure phase, the second transistor M2 is continuously turned off, and the photosensitive diode PD accumulates charge. When the first control signal is a first level signal, the second transistor M2 is turned on. When the second control signal is a first level signal, the third transistor M3 is turned on. PCB represents the signal output by the first port, and SDB represents the signal output by the second port.

[0123] The first ends of the second transistor M2, the third transistor M3, and the fourth transistor M4 may be gates, the second ends of the second transistor M2, the third transistor M3, and the fourth transistor M4 may be sources, and the third ends of the second transistor M2, the third transistor M3, and the fourth transistor M4 may be drains.

[0124] refer to Figures 9 to 11As shown in any embodiment, in some embodiments, the amplification circuit 401 includes:

[0125] A fourth transistor M4 and a fifth transistor M5; a first end of the fourth transistor M4 serves as an input end of the amplifier circuit 401, a third end of the fourth transistor M4 is connected to a pixel power supply, a second end of the fourth transistor M4 is connected to a third end of the fifth transistor M5 and serves as a first end of the amplifier circuit 401, a second end of the fifth transistor M5 serves as a second end of the amplifier circuit 401, and the fifth transistor M5 is controlled by the third control signal.

[0126] The first terminals of the fourth transistor M4 and the fifth transistor M5 may be gates, the second terminals of the fourth transistor M4 and the fifth transistor M5 may be sources, and the third terminals of the fourth transistor M4 and the fifth transistor M5 may be drains.

[0127] The gate of the fourth transistor M4 is the input terminal of the amplifier circuit 401, and the source of the fourth transistor M4 is the output terminal of the amplifier circuit 401. The fourth transistor M4 serves as a first-stage source follower transistor. When the third control signal is at a high level, the fifth transistor M5 is turned on.

[0128] refer to Fig. 9 As shown, in some embodiments, the filtering circuit 402 includes:

[0129] Resistor R and a first capacitor C1; the first capacitor C1 is connected in parallel with the resistor R, a first common end of the first capacitor C1 and the resistor R serves as a first end of the filter circuit 402, and a second common end of the first capacitor C1 and the resistor R serves as a second end of the filter circuit 402.

[0130] In this embodiment, the filter circuit 402 includes a resistor R and a first capacitor C1, and the resistor R is connected in parallel with the first capacitor C1. The first capacitor C1 can be one or more combinations of metal wire-oxide-metal wire plate capacitor, metal plate-dielectric layer-metal plate capacitor, etc. The resistor R can be one or more combinations of gate silicon resistor, metal resistor, N / P type active silicon resistor.

[0131] refer to Fig.10 As shown, in some embodiments, the filtering circuit 402 includes:

[0132] Resistor R and the first transistor M1; one end of the resistor R is connected to the first end of the first transistor M1 and serves as the first end of the filter circuit 402, and the other end of the resistor R is connected to the second end of the first transistor M1 and / or the third end of the first transistor M1 and serves as the second end of the filter circuit 402.

[0133] The first terminal of the first transistor M1 may be a gate, the second terminal of the first transistor M1 may be a source, and the third terminal of the first transistor M1 may be a drain.

[0134] In this embodiment, the filter circuit 402 includes a resistor R and a first transistor M1. The first transistor M1 is used as a signal feedthrough compensation path. When noise and ripples cause a voltage difference between the two ends of the resistor R, the resistor R and the first transistor M1 form a filter loop, which can reduce or even eliminate noise and ripples in a short time.

[0135] refer to Figures 9 to 11 As shown in any example, in some embodiments, the first storage unit 501 includes:

[0136] The sixth transistor M6 and the second capacitor C2; the second end of the sixth transistor M6 is connected to the output end of the amplifying unit 40, the third end of the sixth transistor M6 is connected to the first end of the second capacitor C2 and the first end of the second storage unit 502, the sixth transistor M6 is controlled by a fourth control signal, and the second end of the second capacitor C2 is connected to the port unit 70.

[0137] The first terminal of the sixth transistor M6 may be a gate, the second terminal of the sixth transistor M6 may be a source, and the third terminal of the sixth transistor M6 may be a drain. When the fourth control signal is at a high level, the sixth transistor M6 is turned on.

[0138] refer to Figures 9 to 11 As shown in any example, in some embodiments, the second storage unit 502 includes:

[0139] The seventh transistor M7 and the third capacitor C3; the second end of the seventh transistor M7 is connected to the first storage unit 501 as the first end of the second storage unit 502, the third end of the seventh transistor M7 is connected to the first end of the third capacitor C3 and the input end of the output unit 60, the seventh transistor M7 is controlled by the fifth control signal, and the second end of the third capacitor C3 is connected to the port unit 70.

[0140] The first terminal of the seventh transistor M7 may be a gate, the second terminal of the seventh transistor M7 may be a source, and the third terminal of the seventh transistor M7 may be a drain. When the fifth control signal is at a high level, the seventh transistor M7 is turned on.

[0141] refer to Figures 9 to 11 As shown in any example, in some embodiments, the output unit 60 includes:

[0142] an eighth transistor M8 and a ninth transistor M9; a first end of the eighth transistor M8 serves as an input end of the output unit 60, a third end of the eighth transistor M8 is connected to a pixel power supply, a second end of the eighth transistor M8 is connected to a third end of the ninth transistor M9, a second end of the ninth transistor M9 serves as an output end of the output unit 60, and the ninth transistor M9 is controlled by a sixth control signal.

[0143] The first end of the eighth transistor M8 and the ninth transistor M9 may be a gate, the second end of the eighth transistor M8 and the ninth transistor M9 may be a source, and the third end of the eighth transistor M8 and the ninth transistor M9 may be a drain. When the sixth control signal is at a high level, the ninth transistor M9 is turned on. The eighth transistor M8 serves as a second-stage source follower.

[0144] Combination Figure 6 The timing diagram shown, Fig. 9 and Fig.10 The global shutter pixel shown works as follows:

[0145] The gate of the fourth transistor M4 is the floating diffusion node FD, the drain of the sixth transistor M6 is the first voltage domain storage node, and the drain of the seventh transistor M7 is the second voltage domain storage node. The time from t0 to t1 is the reset phase, the time from t1 to t2 is the exposure phase, and the time from t2 to t3 is the reset voltage storage phase (i.e. Figure 6 The storage V1 shown in FIG. 1 ) includes the storage signal voltage stage (i.e., the storage signal voltage stage) from t3 to t4. Figure 6 V2) and the charge transfer phase (i.e. Figure 6 The PD shown in FIG. 1 charges the FD and gradually changes to the voltage V2). The time from t4 to t5 is the preset stage described above (i.e. Figure 6 The lifting SD shown in FIG), t5 to t6 is the read reset voltage stage (i.e. Figure 6 The reading V1 shown in FIG), t6 to t7 is the voltage coupling stage (i.e. Figure 6 The C2 & C3 voltage coupling shown in FIG), t7 to t8 is the read signal voltage stage (i.e. Figure 6 Read V2 as shown in ).

[0146] From t0 to t1: the sixth control signal is at a low level (generally -1V to 0V), and the ninth transistor M9 is turned off. The first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are at a high level (generally 2.5V to 3.5V), and the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned on, clearing the original charge at the photosensitive diode PD, the floating diffusion node, the output end of the amplification unit 40, the first capacitor C1, the first voltage domain storage node, the second capacitor C2, and the second voltage domain storage node, and the voltage of the floating diffusion node is approximately equal to the pixel power supply PIXVDD. At the same time, from t0 to t1, the output levels of the first port and the second port are set to a low level (generally -2V to 0V).

[0147] From t1 to t2: the first control signal is at a low level (e.g., -1V to 0V), the second transistor M2 is turned off, and the photosensitive diode PD begins to accumulate charge. The second control signal, the third control signal, the fourth control signal, and the fifth control signal are kept at a high level, and the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are kept turned on to remove noise at the floating diffusion node, the first voltage domain storage node, and the second voltage domain storage node, thereby improving image quality.

[0148] From t2 to t3: pull the level of the output of the first port to a high level (generally 0.1V to 1.5V). The voltage of the floating diffusion node is transmitted to the first voltage domain storage node and the second voltage domain storage node through the fourth transistor M4. The transmitted voltage is approximately 70% to 90% of the voltage of the floating diffusion node. At this time, the seventh transistor M7 is in the on state, and the source and drain voltages of the seventh transistor M7 are equal. At t3, the fifth control signal changes from a high level to a low level, thereby turning off the seventh transistor M7. The third capacitor C3 can be a high-capacitance, low-leakage capacitor, and the third capacitor C3 is used to store the reset voltage.

[0149] Since a high level is output through the first port from time t2 to t3, the channel resistance R of the fifth transistor M5 becomes larger. Under the same channel current of the fourth transistor M4, the voltage at the output end of the amplification unit 40 rises. While reducing the pixel power supply voltage PIXVDD, the voltage stored in the third capacitor C3 can be kept unchanged or even increased by raising the voltage of the first port. At the same time, the noise and ripple caused by the voltage jump of the first port can be effectively reduced through the resistor R and the first capacitor C1.

[0150] From t3 to t4: First, the first control signal becomes high, and the second transistor M2 is turned on. Since the photodiode PD has a potential difference with the floating diffusion node, the charge is transferred to the floating diffusion node through the channel of the second transistor M2. Then the first control signal becomes low, thereby turning off the second transistor M2, and the floating diffusion node enters a stable state. The voltage of the floating diffusion node is transferred to the first voltage domain storage node through the fourth transistor M4. The transferred voltage is approximately 70% to 90% of the voltage of the floating diffusion node, and the second capacitor C2 stores the signal voltage. Similarly, since the output of the first port maintains a high level from t3 to t4, the voltage stored in the second capacitor C2 can be kept unchanged or even increased by raising the level of the first port while reducing the pixel power supply voltage PIXVDD.

[0151] From t4 to t5: the level of the output of the second port is pulled up from a low level (usually 0.1V to 2V). Since the sixth transistor M6 and the seventh transistor M7 are turned off from t4 to t5, the first voltage domain storage node and the second voltage domain storage node are both in a floating state, and the level raising value of the second port causes the first voltage domain storage node and the second voltage domain storage node to rise to the same voltage, so The Vout value remains unchanged, thereby maintaining or even increasing the reset voltage and signal voltage actually read out when the pixel power supply PIXVDD decreases, so as to maintain low noise and high linearity of the output of the output unit 60 .

[0152] in, Vout = V1_SD-V2_SD. V1_SD represents the reset voltage, and V2_SD represents the signal voltage. SD stands for Storage Diode, which means voltage domain storage.

[0153] From t5 to t6: the sixth control signal is at a high level, thereby turning on the ninth transistor M9, and the reset voltage is transmitted to the output terminal PIX_OUT of the pixel through the eighth transistor M8, and its value is named V1_PIX_OUT.

[0154] From t6 to t7, the fifth control signal is at a high level, thereby turning on the seventh transistor M7, and the voltage value of the second capacitor C2 and the third capacitor C3 after coupling is equal to (C2*V2_SD+ C3*V1_SD) / (C2+C3).

[0155] From t7 to t8: the fifth control signal is at a low level, thereby turning off the seventh transistor M7. At this time, the coupled voltage is transmitted to the output terminal PIX_OUT of the pixel through the eighth transistor M8, and its value is named V2_PIX_OUT.

[0156] After t8: in reset standby state.

[0157] Combination Figure 8 The timing diagram shown, Fig.11 The global shutter pixel shown works as follows:

[0158] The gate of the fourth transistor M4 is a floating diffusion node, the drain of the sixth transistor M6 is a first voltage domain storage node, and the drain of the seventh transistor M7 is a second voltage domain storage node. The time from t0 to t1 is the reset phase, the time from t1 to t2 is the exposure phase, and the time from t2 to t3 is the reset voltage storage phase (i.e. Figure 8 The storage V1 shown in FIG. 1 ) includes the storage signal voltage stage (i.e., the storage signal voltage stage) from t3 to t4. Figure 8 V2) and the charge transfer phase (i.e. Figure 8 The PD shown in FIG. 1 charges the FD and gradually changes to the voltage V2). The time from t4 to t5 is the preset stage described above (i.e. Figure 8 The lifting SD shown in FIG), t5 to t6 is the read reset voltage stage (i.e. Figure 8 The reading V1 shown in FIG), t6 to t7 is the voltage coupling stage (i.e. Figure 8 The C2 & C3 voltage coupling shown in FIG), t7 to t8 is the read signal voltage stage (i.e. Figure 8 Read V2 as shown in ).

[0159] From t0 to t1: the sixth control signal is at a low level (generally -1V to 0V), and the ninth transistor M9 is turned off. The first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are at a high level (generally 2.5V to 3.5V), and the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned on, clearing the original charge at the photosensitive diode PD, the floating diffusion node, the output end of the amplification unit 40, the first capacitor C1, the first voltage domain storage node, the second capacitor C2, and the second voltage domain storage node, and the voltage of the floating diffusion node is approximately equal to the pixel power supply PIXVDD. At the same time, from t0 to t1, the level of the output of the third port is set to a low level (generally -2V to 0V).

[0160] From t1 to t2: the first control signal is at a low level (e.g., -1V to 0V), the second transistor M2 is turned off, and the photosensitive diode PD begins to accumulate charge. The second control signal, the third control signal, the fourth control signal, and the fifth control signal are kept at a high level, and the third transistor M3, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are kept turned on to remove noise at the floating diffusion node, the first voltage domain storage node, and the second voltage domain storage node, thereby improving image quality.

[0161] From t2 to t3: the level of the output of the third port is pulled to a high level for the first time. The voltage of the floating diffusion node is transmitted to the first voltage domain storage node and the second voltage domain storage node through the fourth transistor M4, and the transmitted voltage is approximately 70% to 90% of the voltage of the floating diffusion node. At this time, the seventh transistor M7 is in an on state, and the source and drain voltages of the seventh transistor M7 are equal. At t3, the fifth control signal becomes a low level, thereby turning off the seventh transistor M7. The third capacitor C3 can be a high-capacitance low-leakage capacitor, and the third capacitor C3 is used to store the reset voltage.

[0162] Since a high level is output through the third port from time t2 to t3, the channel resistance R of the fifth transistor M5 becomes larger. Under the same channel current of the fourth transistor M4, the voltage at the output end of the amplification unit 40 rises. While reducing the pixel power supply voltage PIXVDD, the voltage stored in the third capacitor C3 can be kept unchanged or even increased by raising the voltage of the third port. At the same time, the noise and ripple caused by the voltage jump of the third port can be effectively reduced through the resistor R and the first capacitor C1.

[0163] From t3 to t4: First, the first control signal becomes high, the second transistor M2 is turned on, and since the photodiode PD has a potential difference with the floating diffusion node, the charge is transferred to the floating diffusion node through the channel of the second transistor M2. Then, the first control signal becomes low, thereby turning off the second transistor M2, and the floating diffusion node enters a stable state. The voltage of the floating diffusion node is transferred to the first voltage domain storage node through the fourth transistor M4, and the transferred voltage is approximately 70% to 90% of the voltage of the floating diffusion node. The second capacitor C2 stores the signal voltage. Similarly, since the output of the third port maintains a high level from t3 to t4, the voltage stored in the second capacitor C2 can be kept unchanged or even increased by raising the level of the third port while reducing the pixel power supply voltage PIXVDD.

[0164] From t4 to t5: the level of the output of the third port is pulled up for the second time based on the first pull-up. Since the fourth control signal and the fifth control signal are at low levels from t4 to t5, the sixth transistor M6 and the seventh transistor M7 are turned off, so the first voltage domain storage node and the second voltage domain storage node are both in a floating state, and the level-lifting value of the third port causes the first voltage domain storage node and the second voltage domain storage node to rise to the same voltage, so The Vout value remains unchanged, thereby maintaining or even increasing the reset voltage and signal voltage actually read out when the pixel power supply PIXVDD decreases, so as to maintain low noise and high linearity of the output of the output unit 60 .

[0165] in, Vout = V1_SD - V2_SD. V1_SD represents the reset voltage, and V2_SD represents the signal voltage.

[0166] From t5 to t6: the sixth control signal is at a high level, thereby turning on the ninth transistor M9, and the reset voltage is transmitted to the output terminal PIX_OUT of the pixel through the eighth transistor M8, and its value is named V1_PIX_OUT.

[0167] From t6 to t7, the fifth control signal is at a high level, thereby turning on the seventh transistor M7, and the voltage value of the second capacitor C2 and the third capacitor C3 after coupling is equal to (C2*V2_SD+ C3*V1_SD) / (C2+C3).

[0168] From t7 to t8: the fifth control signal is at a low level, thereby turning off the seventh transistor M7. At this time, the coupled voltage is transmitted to the output terminal PIX_OUT of the pixel through the eighth transistor M8, and its value is named V2_PIX_OUT.

[0169] After t8: in reset standby state.

[0170] In summary, the global shutter pixel provided in the present application, the amplification unit includes an amplification circuit and a filtering circuit, the amplification circuit is connected to the filtering circuit, the filtering circuit is connected to the port unit, and the voltage output by the amplification unit can be raised through the output level of the port unit, and the voltage output by the amplification unit can be kept unchanged or even increased when the pixel power supply voltage is reduced. At the same time, the storage unit is connected to the port unit, and the voltage stored in the storage unit can be raised through the output level of the port unit, so that the pixel output can be linearly increased. In addition, filtering by the filtering circuit can reduce the noise and ripple generated by the level jump of the port unit output, and finally obtain a high-quality image.

[0171] The present application also provides an image sensor, which includes the global shutter pixel as described in the above embodiment. For the introduction of the image sensor provided by the present application, reference can be made to the above embodiment of the global shutter pixel, which will not be repeated here.

[0172] Because the situation is complicated, it is impossible to list them one by one for explanation. Those skilled in the art should be able to realize that there may be multiple examples based on the basic principles of the embodiments provided in this application and combined with actual conditions, and they should all be within the scope of this application without paying enough creative work.

[0173] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0174] The global shutter pixel and image sensor provided by the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0175] It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

Claims

1. A global shutter pixel, characterized in that: include: A photosensitive unit, a transmission unit, a reset unit, an amplifying unit, a storage unit, an output unit and a port unit; the amplifying unit includes an amplifying circuit and a filtering circuit; the first end of the amplifying circuit serves as the output end of the amplifying unit, the first end of the filtering circuit is connected to the second end of the amplifying circuit, and the second end of the filtering circuit is connected to the port unit; the storage unit is connected to the port unit; The photosensitive unit is used to generate charges by sensing light; The transmission unit is used to transmit the charge generated by the photosensitive unit to the floating diffusion node when the transmission unit is turned on; the input end of the amplification unit serves as the floating diffusion node; The resetting unit is used to reset the pixel; The amplifying unit is used to amplify the voltage at the floating diffusion node through the amplifying circuit and output it to the storage unit, and to filter it through the filtering circuit; The storage unit is used to store the reset voltage and the signal voltage; The output unit is used to output the signal voltage and the reset voltage; The port unit is used to output a level signal to raise the voltage output by the amplifying unit in the storage reset voltage stage and the storage signal voltage stage, and to raise the voltage stored in the storage unit in the preset stage, the read reset voltage stage and the read signal voltage stage; the preset stage is located between the storage signal voltage stage and the read reset voltage stage.

2. The global shutter pixel according to claim 1, characterized in that: The port unit comprises: A first port and a second port; the second end of the filter circuit is connected to the first port; the storage unit is connected to the second port; The first port is used to output a first level signal in the reset voltage storage stage and the signal voltage storage stage to raise the voltage output by the amplifying unit; The second port is used to output a first level signal in the preset stage, the read reset voltage stage and the read signal voltage stage to raise the voltage stored in the storage unit.

3. The global shutter pixel according to claim 1, characterized in that: The port unit comprises: a third port; the second end of the filter circuit and the storage unit are both connected to the third port; the third port is used to output a first target level signal in the storage reset voltage stage and the storage signal voltage stage to raise the voltage output by the amplification unit; in the preset stage, the read reset voltage stage and the read signal voltage stage, output a second target level signal to raise the voltage stored in the storage unit; wherein the second target level signal output by the third port in the preset stage, the read reset voltage stage and the read signal voltage stage is higher than the first target level signal output in the storage reset voltage stage and the storage signal voltage stage.

4. The global shutter pixel according to claim 1, characterized in that: The storage unit comprises: A first storage unit and a second storage unit; The first storage unit is used to store a signal voltage; The second storage unit is used to store a reset voltage.

5. The global shutter pixel according to claim 4, characterized in that: The transmission unit is controlled by a first control signal, and when the first control signal is a first level signal, the transmission unit is turned on; the reset unit is controlled by a second control signal, and when the second control signal is a first level signal, the reset unit is turned on; the amplifier circuit is controlled by a third control signal, and when the third control signal is a first level signal, the first end of the amplifier circuit is connected to the second end of the amplifier circuit; the first storage unit is controlled by a fourth control signal, and when the fourth control signal is a first level signal, the capacitor in the first storage unit is connected to the output end of the amplifier unit; the second storage unit is controlled by a fifth control signal, and when the fifth control signal is a first level signal, the capacitor in the second storage unit is connected to the first storage unit; the output unit is controlled by a sixth control signal, and when the sixth control signal is a first level signal, the output unit outputs a voltage.

6. The global shutter pixel according to claim 5, characterized in that: In the reset stage, the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first level signals, and the sixth control signal, the signal output by the first port of the port unit, and the signal output by the second port of the port unit are second level signals; In the exposure stage, the first control signal, the sixth control signal, the signal output by the first port of the port unit, and the signal output by the second port of the port unit are second level signals; The second control signal, the third control signal, the fourth control signal, and the fifth control signal are first level signals; in the reset voltage storage stage, the first control signal, the second control signal, the sixth control signal, and the signal output by the second port of the port unit are second level signals, and the third control signal, the fourth control signal, the fifth control signal, and the signal output by the first port of the port unit are first level signals; in the signal voltage storage stage, the first control signal, the second control signal, the fifth control signal, the sixth control signal, and the signal output by the second port of the port unit are second level signals, and the third control signal, the fourth control signal, and the signal output by the first port of the port unit are first level signals; In the preset stage, the first control signal to the sixth control signal and the signal output by the first port of the port unit are second level signals, and the signal output by the second port of the port unit is a first level signal; In the reset voltage reading phase, the first control signal to the fifth control signal and the signal output by the first port of the port unit are second level signals, and the sixth control signal and the signal output by the second port of the port unit are first level signals; In the signal voltage reading phase, the first control signal to the fifth control signal and the signal output by the first port of the port unit are second level signals, and the sixth control signal and the signal output by the second port of the port unit are first level signals.

7. The global shutter pixel according to claim 5, characterized in that: In the reset stage, the first control signal, the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first level signals, and the sixth control signal and the signal output by the third port of the port unit are second level signals; In the exposure stage, the first control signal, the sixth control signal, and the signal output by the third port of the port unit are second level signals; the second control signal, the third control signal, the fourth control signal, and the fifth control signal are first level signals; In the reset voltage storage stage, the first control signal, the second control signal, and the sixth control signal are second level signals, the third control signal, the fourth control signal, and the fifth control signal are first level signals, and the signal output by the third port of the port unit is a first target level signal; in the signal voltage storage stage, the first control signal, the second control signal, the fifth control signal, and the sixth control signal are second level signals, the third control signal and the fourth control signal are first level signals, and the signal output by the third port of the port unit is a first target level signal; In the preset stage, the first control signal to the sixth control signal are second level signals, and the signal output by the third port of the port unit is a second target level signal; In the reset voltage reading phase, the first control signal to the fifth control signal are second level signals, the sixth control signal is a first level signal, and the signal output by the third port of the port unit is a second target level signal; In the signal voltage reading phase, the first control signal to the fifth control signal are second level signals, the sixth control signal is a first level signal, and the signal output by the third port of the port unit is a second target level signal.

8. The global shutter pixel according to any one of claims 1 to 7, characterized in that: The filtering circuit comprises: A resistor and a first capacitor; the first capacitor is connected in parallel with the resistor, a first common end of the first capacitor and the resistor serves as a first end of the filter circuit, and a second common end of the first capacitor and the resistor serves as a second end of the filter circuit.

9. The global shutter pixel according to any one of claims 1 to 7, characterized in that: The filtering circuit comprises: A resistor and a first transistor; one end of the resistor is connected to the first end of the first transistor and serves as the first end of the filter circuit, and the other end of the resistor is connected to the second end of the first transistor and / or the third end of the first transistor and serves as the second end of the filter circuit.

10. The global shutter pixel according to claim 1, characterized in that: The photosensitive unit comprises: A photosensitive diode; an anode of the photosensitive diode is grounded, and a cathode of the photosensitive diode is connected to the transmission unit.

11. The global shutter pixel according to claim 5, characterized in that: The transmission unit comprises: A second transistor; a second end of the second transistor is connected to the photosensitive unit, a third end of the second transistor is connected to the input end of the amplifying unit, and the second transistor is controlled by the first control signal.

12. The global shutter pixel according to claim 5, characterized in that: The reset unit comprises: a third transistor; a second end of the third transistor is connected to the input end of the amplifying unit, a third end of the third transistor is connected to the pixel power supply, and the third transistor is controlled by the second control signal.

13. The global shutter pixel according to claim 5, characterized in that: The amplifying circuit comprises: A fourth transistor and a fifth transistor; the first end of the fourth transistor serves as the input end of the amplifier circuit, the third end of the fourth transistor is connected to the pixel power supply, the second end of the fourth transistor is connected to the third end of the fifth transistor and serves as the first end of the amplifier circuit, the second end of the fifth transistor serves as the second end of the amplifier circuit, and the fifth transistor is controlled by the third control signal.

14. The global shutter pixel according to claim 5, characterized in that: The first storage unit comprises: A sixth transistor and a second capacitor; the second end of the sixth transistor is connected to the output end of the amplifying unit, the third end of the sixth transistor is connected to the first end of the second capacitor and the first end of the second storage unit, the sixth transistor is controlled by a fourth control signal, and the second end of the second capacitor is connected to the port unit.

15. The global shutter pixel according to claim 5, characterized in that: The second storage unit comprises: A seventh transistor and a third capacitor; the second end of the seventh transistor is connected to the first storage unit as the first end of the second storage unit, the third end of the seventh transistor is connected to the first end of the third capacitor and the input end of the output unit, the seventh transistor is controlled by a fifth control signal, and the second end of the third capacitor is connected to the port unit.

16. The global shutter pixel according to claim 5, characterized in that: The output unit comprises: An eighth transistor and a ninth transistor; the first end of the eighth transistor serves as the input end of the output unit, the third end of the eighth transistor is connected to the pixel power supply, the second end of the eighth transistor is connected to the third end of the ninth transistor, the second end of the ninth transistor serves as the output end of the output unit, and the ninth transistor is controlled by the sixth control signal.

17. An image sensor, characterized in that: Comprising a global shutter pixel as described in any one of claims 1 to 16.

Images