Preparation method of topcon cell and topcon cell

Abstract

This application provides a method for fabricating a TOPCon cell and the TOPCon cell itself. The method includes: providing a silicon substrate; forming a first tunneling oxide layer and an intrinsic amorphous silicon layer stacked on the surface of the silicon substrate; crystallizing the intrinsic amorphous silicon layer to obtain an intrinsic polycrystalline silicon layer; doping the intrinsic polycrystalline silicon layer with a boron source to obtain a pre-doped conductive layer and a pre-doped BSG layer, wherein the boron doping concentration of the pre-doped conductive layer is lower closer to the silicon substrate; and laser processing the pre-doped conductive layer and the pre-doped BSG layer to obtain a first doped conductive layer and a BSG layer, wherein the doping concentration of the first doped conductive layer is greater than that of the pre-doped conductive layer, and the doping concentration of the BSG layer is less than that of the pre-doped BSG layer. This application solves the problem in the prior art where the low boron doping concentration in the front emitter of the TOPCon cell leads to severe recombination of photogenerated carriers in the metal contact region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for preparing a TOPCon cell, the TOPCon cell, and a photovoltaic module. Background Technology

[0002] In N-type high-efficiency crystalline silicon solar cells, tunnel oxide passivated contact (TOPCon) technology has received continuous attention due to its excellent surface passivation effect, high theoretical efficiency, and good compatibility with traditional production lines. The most significant feature of TOPCon technology is its high-quality, ultra-thin silicon oxide and heavily doped polycrystalline silicon stacked structure, which allows one type of charge carrier to freely pass through the interface while blocking another, significantly suppressing interface recombination by creating a concentration difference between the two types of charge carriers at the interface. TOPCon technology utilizes the field effect and selective carrier transport to achieve efficient passivation across the entire surface, greatly reducing the metal contact recombination current and thus improving the cell's open-circuit voltage and short-circuit current. However, currently, N-type TOPCon high-efficiency cells only use an n+ polycrystalline silicon (polySi) passivated contact structure on the back side, while the emitter still uses a conventional boron diffusion structure. This results in severe recombination of photogenerated carriers in the metal contact region, leading to significant efficiency loss on the front side.

[0003] Traditional p+polySi fabrication methods typically employ intrinsic amorphous silicon + boron diffusion or in-situ doping + annealing. These methods place extremely high demands on the first tunneling oxide layer and also have limitations in doping concentration. They are prone to severe boron diffusion and have relatively low doping concentration in poly, resulting in limited passivation performance. Summary of the Invention

[0004] The main objective of this application is to provide a method for fabricating TOPCon cells, TOPCon cells, and photovoltaic modules, in order to solve the problem in the prior art where the low boron doping concentration in the front emitter of TOPCon cells leads to severe recombination of photogenerated carriers in the metal contact region.

[0005] To achieve the above objectives, according to one aspect of this application, a method for fabricating a TOPCon cell is provided, comprising: providing a silicon substrate; forming a first tunneling oxide layer and an intrinsic amorphous silicon layer stacked on the surface of the silicon substrate; performing a crystallization treatment on the intrinsic amorphous silicon layer to crystallize the intrinsic amorphous silicon layer to obtain an intrinsic polycrystalline silicon layer; doping the intrinsic polycrystalline silicon layer with a boron source, wherein the intrinsic polycrystalline silicon layer after doping with the boron source constitutes a pre-doped conductive layer and a pre-doped BSG layer, wherein the pre-doped BSG layer is located on the surface of the pre-doped conductive layer away from the silicon substrate, and in the pre-doped conductive layer, the boron doping concentration of the pre-doped conductive layer is lower the closer it is to the silicon substrate; performing laser treatment on the pre-doped conductive layer and the pre-doped BSG layer, wherein the laser-treated pre-doped conductive layer constitutes a first doped conductive layer, and the laser-treated pre-doped BSG layer constitutes a BSG layer, wherein the doping concentration of the first doped conductive layer is greater than the doping concentration of the pre-doped conductive layer, and the doping concentration of the BSG layer is less than the doping concentration of the pre-doped BSG layer; and removing the BSG layer.

[0006] Optionally, doping the intrinsic polycrystalline silicon layer with a boron source includes: using a tube diffusion furnace to dope the intrinsic polycrystalline silicon layer with the boron source in a temperature range of 700°C to 900°C.

[0007] Optionally, the intrinsic amorphous silicon layer is subjected to crystallization treatment, including annealing the intrinsic amorphous silicon layer in a temperature range of 900°C to 1050°C.

[0008] Optionally, the above-mentioned pre-doped conductive layer and the above-mentioned pre-doped BSG layer are subjected to laser processing, including: laser scanning of the above-mentioned pre-doped conductive layer and the above-mentioned pre-doped BSG layer, wherein the laser source includes an infrared nanosecond laser, the laser power is 100W to 300W, the laser scanning frequency is 300HZ to 1500HZ, and the scanning speed is 15000mm / s to 30000mm / s.

[0009] Optionally, forming a first tunneling oxide layer and an intrinsic amorphous silicon layer stacked on the surface of the silicon substrate includes: using a tubular LPCVD device to sequentially introduce oxygen and silane at a temperature of 500°C to 800°C to obtain the first tunneling oxide layer and the intrinsic amorphous silicon layer.

[0010] Optionally, the silicon substrate includes opposing first and second surfaces. A first tunneling oxide layer and an intrinsic amorphous silicon layer are stacked on the surface of the silicon substrate. The method includes: forming the first tunneling oxide layer and the intrinsic amorphous silicon layer on the first surface. The method further includes: forming a second tunneling oxide layer on the second surface; forming a second doped conductive layer on the surface of the second tunneling oxide layer away from the silicon substrate, wherein the doping type of the second doped conductive layer is different from the doping type of the first doped conductive layer; and forming a first antireflection layer on the surface of the second doped conductive layer away from the silicon substrate.

[0011] Optionally, after removing the BSG layer, the method further includes: forming a passivation layer on the surface of the first doped conductive layer away from the silicon substrate; and forming a second antireflection layer on the surface of the passivation layer away from the silicon substrate.

[0012] According to another aspect of this application, a TOPCon battery is provided, wherein the TOPCon battery is prepared using any of the above-described TOPCon battery preparation methods, and the TOPCon battery comprises: a silicon substrate; a first tunneling oxide layer located on the surface of the silicon substrate; and a first doped conductive layer located on the surface of the first tunneling oxide layer away from the silicon substrate, wherein the doping atoms of the first doped conductive layer include boron, and the doping concentration of the first doped conductive layer is 5E20cm⁻¹. -3 ~1E21cm -3 .

[0013] Optionally, the silicon substrate includes a first surface and a second surface opposite to each other, the first tunneling oxide layer is located on the first surface, and the TOPCon cell further includes: a second tunneling oxide layer located on the second surface; a second doped conductive layer located on the surface of the second tunneling oxide layer away from the silicon substrate, wherein the doping type of the second doped conductive layer is different from the doping type of the first doped conductive layer; and a first antireflection layer located on the surface of the second doped conductive layer away from the silicon substrate.

[0014] According to another aspect of this application, a photovoltaic module is provided, comprising a TOPCon cell prepared using any of the above-described methods for preparing TOPCon cells, or the above-described TOPCon cell.

[0015] Using the technical solution of this application, a first tunneling oxide layer and an intrinsic amorphous silicon layer are first formed on a silicon substrate. Then, the intrinsic amorphous silicon layer is crystallized to obtain an intrinsic polycrystalline silicon layer. Next, a boron source is doped into the intrinsic polycrystalline silicon layer to obtain a pre-doped conductive layer and a pre-doped BSG layer. Then, the pre-doped conductive layer and the pre-doped BSG layer are laser-treated to obtain a first doped conductive layer and a BSG layer. Finally, the BSG layer is removed. In the pre-doped conductive layer, the boron doping concentration is lower closer to the silicon substrate. The doping concentration of the first doped conductive layer is greater than that of the pre-doped conductive layer, and the doping concentration of the BSG layer is less than that of the pre-doped BSG layer. Compared to existing TOPCon batteries where low boron doping concentration in the front emitter leads to severe recombination of photogenerated carriers in the metal contact region, this application first forms a first tunneling oxide layer and an intrinsic amorphous silicon layer on a silicon substrate. The intrinsic amorphous silicon layer is then crystallized to obtain an intrinsic polycrystalline silicon layer. A boron source is then incorporated into the intrinsic polycrystalline silicon layer to form a high-surface-concentration, low-activation pre-doped conductive layer and a pre-BSG layer (the boron doping concentration is lower closer to the silicon substrate). This reduces the phenomenon of boron diffusion into the first tunneling oxide layer, significantly reducing the thermal diffusion motive force of boron atoms and thus reducing internal boron diffusion. Laser treatment of the pre-doped conductive layer and the pre-BSG layer, due to the instantaneous and localized heating of the laser, can quickly activate boron atoms to a high concentration without causing widespread boron diffusion. This ensures a high boron doping concentration in the first doped conductive layer. The high boron doping concentration can form a more efficient hole-selective transport interface, reducing the recombination current in the front metal contact region and improving battery efficiency. Attached Figure Description

[0016] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0017] Figure 1 A schematic flowchart of a method for fabricating a TOPCon battery according to an embodiment of this application is shown.

[0018] Figures 2 to 7 The diagrams show cross-sectional structural schematics of the TOPCon battery formed after each process step according to the embodiment of this application.

[0019] Figure 8 A schematic diagram comparing the doping curves of conventional front emitter fabrication methods with those of the front emitter fabrication method of this application is shown.

[0020] The above figures include the following reference numerals:

[0021] 10. Silicon substrate; 11. First tunneling oxide layer; 12. Intrinsic amorphous silicon layer; 13. Intrinsic polycrystalline silicon layer; 14. Pre-doped conductive layer; 15. Pre-doped BSG layer; 16. First doped conductive layer; 17. BSG layer; 101. First surface; 102. Second surface; 18. Second tunneling oxide layer; 19. Second doped conductive layer; 20. First antireflection layer; 21. Passivation layer; 22. Second antireflection layer; 23. First electrode; 24. Second electrode. Detailed Implementation

[0022] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0023] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0024] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0025] As described in the background section, the low boron doping concentration in the front emitter of the existing TOPCon cell leads to severe recombination of photogenerated carriers in the metal contact region. To address the above problem, embodiments of this application provide a method for preparing a TOPCon cell, a TOPCon cell, and a photovoltaic module.

[0026] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0027] Figure 1 This is a flowchart of a method for fabricating a TOPCon battery according to an embodiment of this application. Figure 1 As shown, the method includes the following steps:

[0028] Step S101, as follows Figure 2 As shown, a silicon substrate 10 is provided;

[0029] Specifically, the doping type of the silicon substrate mentioned above is N-type.

[0030] Step S102, as follows Figure 3 As shown, a first tunneling oxide layer 11 and an intrinsic amorphous silicon layer 12 are stacked on the surface of the silicon substrate 10.

[0031] Specifically, the aforementioned intrinsic amorphous silicon layer is i-poly.

[0032] Step S103, as follows Figure 3 and Figure 4 As shown, the intrinsic amorphous silicon layer 12 is subjected to crystallization treatment to crystallize the intrinsic amorphous silicon layer 12, thereby obtaining an intrinsic polycrystalline silicon layer 13.

[0033] Step S104, as follows Figure 4 and Figure 5 As shown, a boron source is incorporated into the intrinsic polysilicon layer 13. The intrinsic polysilicon layer 13 after incorporating the boron source constitutes a pre-doped conductive layer 14 and a pre-doped BSG layer 15. The pre-doped BSG layer 15 is located on the surface of the pre-doped conductive layer 14 that is away from the silicon substrate 10. In the pre-doped conductive layer 14, the boron doping concentration is lower the closer it is to the silicon substrate 10.

[0034] Specifically, the boron doping concentration is lower in the pre-doped conductive layer that is closer to the silicon substrate.

[0035] Step S105, as follows Figure 5 and Figure 6 As shown, the pre-doped conductive layer 14 and the pre-doped BSG layer 15 are subjected to laser processing. The laser-processed pre-doped conductive layer 14 constitutes the first doped conductive layer 16, and the laser-processed pre-doped BSG layer 15 constitutes the BSG layer 17. The doping concentration of the first doped conductive layer 16 is greater than the doping concentration of the pre-doped conductive layer 14, and the doping concentration of the BSG layer 17 is less than the doping concentration of the pre-doped BSG layer 15.

[0036] Specifically, the BSG layer is boron-doped silicon dioxide, and the first doped conductive layer is P-type doped.

[0037] Step S106, as follows Figure 6 and Figure 7 As shown, remove the BSG layer 17 mentioned above.

[0038] In this embodiment, a first tunneling oxide layer and an intrinsic amorphous silicon layer are first formed on a silicon substrate. Then, the intrinsic amorphous silicon layer is crystallized to obtain an intrinsic polycrystalline silicon layer. Next, a boron source is doped into the intrinsic polycrystalline silicon layer to obtain a pre-doped conductive layer and a pre-doped BSG layer. Then, the pre-doped conductive layer and the pre-doped BSG layer are laser-treated to obtain a first doped conductive layer and a BSG layer. Finally, the BSG layer is removed. In the pre-doped conductive layer, the boron doping concentration is lower closer to the silicon substrate. The doping concentration of the first doped conductive layer is greater than that of the pre-doped conductive layer, and the doping concentration of the BSG layer is less than that of the pre-doped BSG layer. Compared to existing TOPCon batteries where low boron doping concentration in the front emitter leads to severe recombination of photogenerated carriers in the metal contact region, this application first forms a first tunneling oxide layer and an intrinsic amorphous silicon layer on a silicon substrate. The intrinsic amorphous silicon layer is then crystallized to obtain an intrinsic polycrystalline silicon layer. A boron source is then incorporated into the intrinsic polycrystalline silicon layer to form a high-surface-concentration, low-activation pre-doped conductive layer and a pre-BSG layer (the boron doping concentration is lower closer to the silicon substrate). This reduces the phenomenon of boron diffusion into the first tunneling oxide layer, significantly reducing the thermal diffusion motive force of boron atoms and thus reducing internal boron diffusion. Laser treatment of the pre-doped conductive layer and the pre-BSG layer, due to the instantaneous and localized heating of the laser, can quickly activate boron atoms to a high concentration without causing widespread boron diffusion. This ensures a high boron doping concentration in the first doped conductive layer. The high boron doping concentration can form a more efficient hole-selective transport interface, reducing the recombination current in the front metal contact region and improving battery efficiency.

[0039] In addition, compared with traditional thermal diffusion or annealing, laser doping can more precisely control the doping depth. This means that the doped boron atoms can be more effectively confined within the intrinsic polycrystalline silicon layer, avoiding excessive diffusion into the silicon substrate, reducing recombination at the tunnel oxide layer, and maintaining its passivation performance.

[0040] Specifically, the first tunneling oxide layer and the first doped conductive layer constitute a passivated contact structure. The material of the first tunneling oxide layer can be a dielectric material, such as silicon oxide.

[0041] Specifically, the silicon substrate is used to receive incident light and generate photogenerated carriers. The material of the silicon substrate can include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. The silicon substrate is an N-type semiconductor substrate, that is, the N-type silicon substrate is doped with N-type dopant ions, which can be any one of phosphorus ions, arsenic ions, or antimony ions.

[0042] In one alternative embodiment, doping the intrinsic polycrystalline silicon layer with a boron source includes: using a tube diffusion furnace to dope the intrinsic polycrystalline silicon layer with the boron source at a temperature range of 700°C to 900°C. In this embodiment, doping the intrinsic polycrystalline silicon layer with a boron source at a low temperature range of 700°C to 900°C further ensures a low thermal diffusion kinetics for boron atoms, further reduces the phenomenon of boron penetrating into the first tunneling oxide layer, and thus further ensures a high boron doping concentration in the subsequently obtained first doped conductive layer.

[0043] Specifically, in a tubular boron diffusion furnace at 700℃~900℃, a boron source is introduced at a low temperature to form a low-activation p+poly (i.e., a pre-doped conductive layer) with high surface concentration and a pre-doped BSG layer.

[0044] According to some exemplary embodiments of this application, the intrinsic amorphous silicon layer is subjected to crystallization treatment, including annealing the intrinsic amorphous silicon layer in a temperature range of 900°C to 1050°C. In this embodiment, annealing in a temperature range of 900°C to 1050°C can effectively transform the amorphous silicon layer into a polycrystalline silicon layer. The crystallization process causes the amorphous silicon atoms to recombine and form a crystalline structure, thereby improving the electrical properties and carrier mobility of the material.

[0045] Specifically, nitrogen gas is introduced into a tube annealing furnace at a temperature of 900℃~1050℃ to anneal and form a crystallized i-poly (i.e., intrinsic polycrystalline silicon layer).

[0046] In other embodiments, the pre-doped conductive layer and the pre-doped BSG layer are subjected to laser processing, including: laser scanning of the pre-doped conductive layer and the pre-doped BSG layer, wherein the laser source includes an infrared nanosecond laser with a laser power of 100W to 300W, a laser scanning frequency of 300Hz to 1500Hz, and a scanning speed of 15000mm / s to 30000mm / s. In this embodiment, the infrared nanosecond laser has high energy density and short pulse characteristics, which can precisely control local heating, further enabling the rapid diffusion and activation of the boron source, further forming a high-concentration first doped conductive layer, further achieving more efficient carrier transport and collection, and further reducing the recombination current in the metal contact area.

[0047] Specifically, a highly doped p++poly layer (i.e., the first doped conductive layer) and a BSG layer are formed by laser doping.

[0048] According to some other exemplary embodiments of this application, forming a stacked first tunneling oxide layer and an intrinsic amorphous silicon layer on the surface of the aforementioned silicon substrate includes: using a tubular LPCVD apparatus, sequentially introducing oxygen and silane at a temperature of 500°C to 800°C to obtain the aforementioned first tunneling oxide layer and the aforementioned intrinsic amorphous silicon layer. In this embodiment, within a lower temperature range (500°C to 800°C), introducing oxygen can promote the formation of a high-quality first tunneling oxide layer, and subsequently introducing silane can deposit an intrinsic amorphous silicon layer on the tunneling oxide layer.

[0049] Specifically, in a tubular LPCVD system, oxygen and silane are sequentially introduced at temperatures ranging from 500°C to 800°C to form a first tunneling oxide layer and an intrinsic amorphous silicon layer. The oxygen flow rate typically ranges from 100 sccm to 1000 sccm, and the specific value can be adjusted according to the equipment characteristics and the required thickness of the first tunneling oxide layer. The silane flow rate generally ranges from 10 sccm to 500 sccm, but this needs to be considered in conjunction with the oxygen flow rate and deposition temperature. The gas pressure in the LPCVD process needs to be maintained at a low level (between 100 mTorr and 1000 mTorr) to ensure uniform distribution of gas molecules and effective reaction within the reaction chamber. The thickness of the first tunneling oxide layer is typically between 1 nm and 10 nm, and the thickness of the intrinsic amorphous silicon layer is typically between 100 nm and 500 nm.

[0050] In some other alternatives to this application, such as Figure 7 As shown, the silicon substrate 10 includes a first surface 101 and a second surface 102 opposite to each other. A first tunneling oxide layer 11 and an intrinsic amorphous silicon layer 12 are stacked on the surface of the silicon substrate 10. The method includes: forming the first tunneling oxide layer 11 and the intrinsic amorphous silicon layer 12 on the first surface 101. The method further includes: forming a second tunneling oxide layer 18 on the second surface 102; forming a second doped conductive layer 19 on the surface of the second tunneling oxide layer 18 away from the silicon substrate 10, wherein the doping type of the second doped conductive layer 19 is different from the doping type of the first doped conductive layer 16; and forming a first antireflection layer 20 on the surface of the second doped conductive layer 19 away from the silicon substrate 10. In this embodiment, a first tunneling oxide layer and an intrinsic amorphous silicon layer are stacked on the first surface of the silicon substrate, and a second tunneling oxide layer and a second doped conductive layer are formed on the second surface. This constructs a double-sided passivated contact structure, which can further significantly improve the photoelectric conversion efficiency of the battery. The first antireflection layer can significantly reduce light reflection loss and increase light absorption and utilization, thereby further improving the performance of the battery.

[0051] Specifically, the doping type of the second doped conductive layer is N-type, the material of the first antireflection layer includes one of silicon oxide, silicon nitride, or silicon oxynitride, and the material of the second tunneling oxide layer can be a dielectric material, such as silicon oxide.

[0052] Specifically, the first tunneling oxide layer and the second tunneling oxide layer can be prepared simultaneously or at different times.

[0053] Specifically, the tunneling layer is used to achieve interface passivation on the silicon substrate surface, achieving a chemical passivation effect. The tunneling layer can be formed using a deposition process, such as chemical vapor deposition. In other embodiments, when the material of the tunneling layer is silicon oxide, the tunneling layer can also be formed using an in-situ growth process, such as thermal oxidation and nitric acid passivation, to generate the tunneling layer in situ on the silicon substrate surface.

[0054] In some alternative embodiments of this application, after removing the aforementioned BSG layer, the method further includes: Figure 7 As shown, a passivation layer 21 is formed on the surface of the first doped conductive layer 16 away from the silicon substrate 10; a second antireflection layer 22 is formed on the surface of the passivation layer 21 away from the silicon substrate 10. In this embodiment, the formed passivation layer can further improve the surface passivation effect of the battery and reduce the recombination loss of charge carriers on the surface; the addition of the second antireflection layer can further reduce the reflection of light on the battery surface and further increase the absorption of light, thereby further improving the performance of the battery.

[0055] Specifically, the passivation layer can be made of one or more of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, or silicon carbonitride; the second antireflection layer can be made of one of silicon oxide, silicon nitride, or silicon oxynitride. The passivation layer and antireflection layer can be a single-layer or multi-layer structure. For multi-layer structures, the materials of different layers can be different from each other, or some layers can have the same material, but different from the materials of other layers. In some embodiments, the passivation layer can be formed using a PECVD method.

[0056] In other embodiments, the above method further includes: Figure 7 As shown, a plurality of first electrodes 23 are formed on the surface of the second antireflection layer 22 away from the silicon substrate 10, and the predetermined direction is perpendicular to the thickness of the silicon substrate 10; a plurality of second electrodes 24 are formed on the surface of the first antireflection layer 20 away from the silicon substrate 10, and the predetermined direction is also present.

[0057] Specifically, the first electrode is in direct contact with the first doped conductive layer on or through the second antireflection layer and the passivation layer, and the second electrode is in direct contact with the second doped conductive layer on or through the first antireflection layer, for establishing an electrical connection to the external circuit.

[0058] In other embodiments, providing a silicon substrate includes: providing a preliminary silicon substrate; and cleaning the preliminary silicon substrate with an alkaline solution to obtain the silicon substrate. In this embodiment, cleaning the preliminary silicon substrate with an alkaline solution can remove the damaged layer, paving the way for subsequent processes.

[0059] Specifically, the original silicon wafer (i.e., the prepared silicon substrate) is treated in an alkaline solution to remove the damaged layer and form a polished morphology.

[0060] It should be noted that there are generally two commonly used p+polySi fabrication techniques. One method involves first depositing a tunneling oxide layer, then crystallizing the intrinsic amorphous silicon layer at high temperature, and then forming a p+polySi layer through tubular boron diffusion. The other method involves depositing a tunneling oxide layer and an in-situ p+polySi layer through PECVD, and then activating the p+polySi layer with boron through annealing. The disadvantages of these methods are that they require a high-quality tunneling oxide layer, are prone to severe internal boron diffusion, and have a low doping concentration in the poly, resulting in limited passivation performance.

[0061] In summary, this application employs an intrinsic amorphous silicon + boron deposition + laser doping method to significantly increase the boron doping concentration in amorphous silicon and reduce metal recombination and contact (i.e., first depositing a first tunneling oxide layer and intrinsic amorphous silicon on the treated silicon wafer, then crystallizing at high temperature, then depositing boron at low temperature, and finally doping by laser).

[0062] Figure 8 A schematic diagram comparing the doping curves of conventional front emitter fabrication methods with those of the front emitter fabrication method of this application is shown. Figure 8 In the diagram, the orange curve represents the conventional method for fabricating the front emitter, and the gray curve represents the method for fabricating the front emitter of this application. The horizontal axis represents the depth of the passivation contact structure in μm, and the vertical axis represents the boron doping concentration in the passivation contact structure in cm. -3 The passivation contact structure consists of a stacked tunneling oxide layer and a front emitter. The front emitter is a P-type doped conductive layer. The shallower regions (e.g., 0–0.4 μm) correspond to the location of the front emitter, while the deeper regions (e.g., 0.4 μm–0.7 μm) correspond to the location of the tunneling oxide layer. Figure 8As can be seen from the above, this application effectively reduces the severe phenomenon of boron internal diffusion compared with the prior art, while greatly increasing the boron doping concentration in the front emitter.

[0063] Specifically, Table 1 shows a comparison of the performance parameters of the front emitter prepared using the TOPCon battery preparation method of this application with those prepared using conventional front emitter preparation methods.

[0064] Table 1

[0065]

[0066] Specifically, in Table 1, Lifetime represents carrier lifetime, Jo represents dark current density, Voc represents fill factor, FF represents [missing information], and Res represents resistivity.

[0067] To enable those skilled in the art to better understand the technical solution of this application, the implementation process of the TOPCon battery preparation method of this application will be described in detail below with reference to specific embodiments.

[0068] This embodiment relates to a specific method for preparing a TOPCon battery, including the following steps:

[0069] Step S1: Provide a pre-prepared silicon substrate, and clean the pre-prepared silicon substrate using an alkaline solution to obtain a silicon substrate;

[0070] Step S2: Using a tubular LPCVD equipment, oxygen and silane are successively introduced at 500℃~800℃ to form the first tunneling oxide layer and the intrinsic amorphous silicon layer;

[0071] Step S3: Annealing is performed in a tube annealing furnace at a temperature of 900℃~1050℃ by introducing nitrogen gas to form an intrinsic polycrystalline silicon layer;

[0072] Step S4: In a tube-type boron diffusion furnace at 700℃~900℃, a boron source is doped into the intrinsic polycrystalline silicon layer to obtain a pre-doped conductive layer and a pre-doped BSG layer. The pre-doped BSG layer is located on the surface of the pre-doped conductive layer away from the silicon substrate. In the pre-doped conductive layer, the boron doping concentration is lower the closer the pre-doped conductive layer is to the silicon substrate.

[0073] Step S5: Perform laser treatment on the pre-doped conductive layer and the pre-doped BSG layer. The laser-treated pre-doped conductive layer constitutes the first doped conductive layer, and the laser-treated pre-doped BSG layer constitutes the BSG layer. The doping concentration of the first doped conductive layer is greater than that of the pre-doped conductive layer, and the doping concentration of the BSG layer is less than that of the pre-doped BSG layer.

[0074] Step S6: Remove the BSG layer.

[0075] This application also provides a TOPCon battery, which is prepared using any of the above-described TOPCon battery preparation methods. The TOPCon battery includes: a silicon substrate; a first tunneling oxide layer located on the surface of the silicon substrate; and a first doped conductive layer located on the surface of the first tunneling oxide layer away from the silicon substrate. The doping atoms of the first doped conductive layer include boron, and the doping concentration of the first doped conductive layer is 5E20cm⁻¹. -3 ~1E21cm -3 .

[0076] In the above embodiments, the TOPCon cell includes a stacked silicon substrate, a first tunneling oxide layer, and a first doped conductive layer, wherein the doping atoms of the first doped conductive layer include boron, and the doping concentration of the first doped conductive layer is 5E20cm⁻¹. -3 ~1E21cm -3 Compared to the problem in existing TOPCon batteries where the low boron doping concentration in the front emitter leads to severe recombination of photogenerated carriers in the metal contact region, the first doped conductive layer in this application has a doping concentration of 5E20cm⁻¹. -3 ~1E21cm -3 This ensures a high boron doping concentration in the first doped conductive layer. High boron doping can form a more effective hole-selective transport interface, reduce the recombination current in the front metal contact area, and improve battery efficiency.

[0077] In one alternative embodiment, the silicon substrate includes a first surface and a second surface opposite to each other, the first tunneling oxide layer is located on the first surface, and the TOPCon cell further includes: a second tunneling oxide layer located on the second surface; a second doped conductive layer located on the surface of the second tunneling oxide layer away from the silicon substrate, wherein the doping type of the second doped conductive layer is different from the doping type of the first doped conductive layer; and a first antireflection layer located on the surface of the second doped conductive layer away from the silicon substrate.

[0078] In other embodiments, the TOPCon battery further includes: a passivation layer located on the surface of the first doped conductive layer away from the silicon substrate; a second antireflection layer located on the surface of the passivation layer away from the silicon substrate; a plurality of first electrodes spaced apart in a predetermined direction located on a portion of the surface of the second antireflection layer away from the silicon substrate, wherein the predetermined direction is perpendicular to the thickness of the silicon substrate; and a plurality of second electrodes spaced apart in the predetermined direction located on a portion of the surface of the first antireflection layer away from the silicon substrate.

[0079] This application also provides a photovoltaic module, including a TOPCon cell prepared by any of the above-described methods for preparing TOPCon cells, or the above-described TOPCon cell.

[0080] In the above embodiments, the photovoltaic module includes a TOPCon cell prepared using the TOPCon cell preparation method, or a TOPCon cell. In the TOPCon cell preparation method, a first tunneling oxide layer and an intrinsic amorphous silicon layer are first formed on a silicon substrate. Then, the intrinsic amorphous silicon layer is crystallized to obtain an intrinsic polycrystalline silicon layer. Next, a boron source is doped into the intrinsic polycrystalline silicon layer to obtain a pre-doped conductive layer and a pre-doped BSG layer. Then, the pre-doped conductive layer and the pre-doped BSG layer are laser-treated to obtain a first doped conductive layer and a BSG layer. Finally, the BSG layer is removed. In the pre-doped conductive layer, the boron doping concentration is lower closer to the silicon substrate. The doping concentration of the first doped conductive layer is greater than that of the pre-doped conductive layer, and the doping concentration of the BSG layer is less than that of the pre-doped BSG layer. Compared to existing TOPCon batteries where low boron doping concentration in the front emitter leads to severe recombination of photogenerated carriers in the metal contact region, this application first forms a first tunneling oxide layer and an intrinsic amorphous silicon layer on a silicon substrate. The intrinsic amorphous silicon layer is then crystallized to obtain an intrinsic polycrystalline silicon layer. A boron source is then incorporated into the intrinsic polycrystalline silicon layer to form a high-surface-concentration, low-activation pre-doped conductive layer and a pre-BSG layer (the boron doping concentration is lower closer to the silicon substrate). This reduces the phenomenon of boron diffusion into the first tunneling oxide layer, significantly reducing the thermal diffusion motive force of boron atoms and thus reducing internal boron diffusion. Laser treatment of the pre-doped conductive layer and the pre-BSG layer, due to the instantaneous and localized heating of the laser, can quickly activate boron atoms to a high concentration without causing widespread boron diffusion. This ensures a high boron doping concentration in the first doped conductive layer. The high boron doping concentration can form a more efficient hole-selective transport interface, reducing the recombination current in the front metal contact region and improving battery efficiency.

[0081] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0082] In the TOPCon cell fabrication method of this application, a first tunneling oxide layer and an intrinsic amorphous silicon layer are first stacked on a silicon substrate. Then, the intrinsic amorphous silicon layer is crystallized to obtain an intrinsic polycrystalline silicon layer. Next, a boron source is doped into the intrinsic polycrystalline silicon layer to obtain a pre-doped conductive layer and a pre-doped BSG layer. Then, the pre-doped conductive layer and the pre-doped BSG layer are laser-treated to obtain a first doped conductive layer and a BSG layer. Finally, the BSG layer is removed. In the pre-doped conductive layer, the boron doping concentration is lower closer to the silicon substrate. The doping concentration of the first doped conductive layer is greater than that of the pre-doped conductive layer, and the doping concentration of the BSG layer is less than that of the pre-doped BSG layer. Compared to existing TOPCon batteries where low boron doping concentration in the front emitter leads to severe recombination of photogenerated carriers in the metal contact region, this application first forms a first tunneling oxide layer and an intrinsic amorphous silicon layer on a silicon substrate. The intrinsic amorphous silicon layer is then crystallized to obtain an intrinsic polycrystalline silicon layer. A boron source is then incorporated into the intrinsic polycrystalline silicon layer to form a high-surface-concentration, low-activation pre-doped conductive layer and a pre-BSG layer (the boron doping concentration is lower closer to the silicon substrate). This reduces the phenomenon of boron diffusion into the first tunneling oxide layer, significantly reducing the thermal diffusion motive force of boron atoms and thus reducing internal boron diffusion. Laser treatment of the pre-doped conductive layer and the pre-BSG layer, due to the instantaneous and localized heating of the laser, can quickly activate boron atoms to a high concentration without causing widespread boron diffusion. This ensures a high boron doping concentration in the first doped conductive layer. The high boron doping concentration can form a more efficient hole-selective transport interface, reducing the recombination current in the front metal contact region and improving battery efficiency.

[0083] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for preparing a TOPCon battery, characterized in that, include: Provide silicon substrate; A first tunneling oxide layer and an intrinsic amorphous silicon layer are stacked on the surface of the silicon substrate; The intrinsic amorphous silicon layer is subjected to crystallization treatment, which is annealing with nitrogen gas at a temperature of 900℃~1050℃ to obtain an intrinsic polycrystalline silicon layer. A boron source is diffused into the intrinsic polycrystalline silicon layer at 700℃ to 900℃. The intrinsic polycrystalline silicon layer after the boron source is incorporated forms a pre-doped conductive layer and a pre-doped BSG layer. The pre-doped BSG layer is located on the surface of the pre-doped conductive layer away from the silicon substrate. In the pre-doped conductive layer, the boron doping concentration is lower the closer it is to the silicon substrate. The pre-doped conductive layer and the pre-doped BSG layer are subjected to laser processing and laser scanning. The laser source is an infrared nanosecond laser with a power of 100W~300W, a scanning frequency of 300Hz~1500Hz, and a scanning speed of 15000mm / s~30000mm / s. The laser-processed pre-doped conductive layer constitutes the first doped conductive layer, and the laser-processed pre-doped BSG layer constitutes the BSG layer. The doping concentration of the first doped conductive layer is greater than that of the pre-doped conductive layer, and the doping concentration of the BSG layer is less than that of the pre-doped BSG layer. The doping concentration of the first doped conductive layer is 5E20cm⁻¹. -3 ~1E21cm -3 ; Remove the BSG layer.

2. The method for preparing a TOPCon battery according to claim 1, characterized in that, The boron source is incorporated into the intrinsic polycrystalline silicon layer, including: The boron source is doped into the intrinsic polycrystalline silicon layer using a tubular diffusion furnace within a temperature range of 700℃ to 900℃.

3. The method for preparing a TOPCon battery according to claim 1, characterized in that, A first tunneling oxide layer and an intrinsic amorphous silicon layer are stacked on the surface of the silicon substrate, comprising: Using a tubular LPCVD equipment, oxygen and silane are introduced sequentially at a temperature of 500℃~800℃ to obtain the first tunneling oxide layer and the intrinsic amorphous silicon layer.

4. The method for preparing a TOPCon battery according to claim 1, characterized in that, The silicon substrate includes opposing first and second surfaces. Forming a first tunneling oxide layer and an intrinsic amorphous silicon layer stacked on the surface of the silicon substrate includes: forming the first tunneling oxide layer and the intrinsic amorphous silicon layer on the first surface. The method further includes: forming a second tunneling oxide layer on the second surface; forming a second doped conductive layer on the surface of the second tunneling oxide layer away from the silicon substrate, wherein the doping type of the second doped conductive layer is different from the doping type of the first doped conductive layer; and forming a first antireflection layer on the surface of the second doped conductive layer away from the silicon substrate.

5. The method for preparing a TOPCon battery according to claim 1, characterized in that, After removing the BSG layer, the method further includes: A passivation layer is formed on the surface of the first doped conductive layer away from the silicon substrate; a second antireflection layer is formed on the surface of the passivation layer away from the silicon substrate.

6. A TOPCon battery, characterized in that, The TOPCon battery is prepared using the method for preparing a TOPCon battery according to any one of claims 1 to 5, and the TOPCon battery comprises: Silicon substrate; A first tunneling oxide layer is located on the surface of the silicon substrate; A first doped conductive layer is located on the surface of the first tunneling oxide layer away from the silicon substrate. The doping atoms of the first doped conductive layer include boron, and the doping concentration of the first doped conductive layer is 5E20cm⁻¹. -3 ~1E21cm -3 .

7. The TOPCon battery according to claim 6, characterized in that, The silicon substrate includes opposing first and second surfaces, with the first tunneling oxide layer located on the first surface. The TOPCon cell further includes: A second tunneling oxide layer is located on the second surface; The second doped conductive layer is located on the surface of the second tunneling oxide layer away from the silicon substrate, and the doping type of the second doped conductive layer is different from that of the first doped conductive layer. The first antireflective layer is located on the surface of the second doped conductive layer away from the silicon substrate.

8. A photovoltaic module, characterized in that, This includes TOPCon batteries prepared using the method for preparing TOPCon batteries according to any one of claims 1 to 5, or TOPCon batteries according to claim 6 or 7.

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