Integrated energy management circuit for a charging integrated system

Abstract

The present invention belongs to the technical field of charging management, and particularly relates to a comprehensive energy management circuit for a charging integrated system; the present invention provides a hardware basis for the comprehensive energy management circuit of a charging integrated system. The present invention includes a charging power supply and communication part, an electric vehicle communication part, a communication ID setting part, a full-bridge drive part, an input voltage detection part, a power supply part, a relay drive part, an ADC conversion part, and a main control FPGA part, characterized in that the information transmission ports of the main control FPGA part are respectively connected to the information transmission ports of the charging power supply and communication part, the information transmission ports of the electric vehicle communication part, the information transmission ports of the communication ID setting part, and the information transmission ports of the full-bridge drive part; the present invention solves the problem in the prior art that only by increasing the number of charging piles can the tight use situation of charging piles be satisfied by jointly controlling each charging pile and flexibly allocating power.

Description

Technical Field

[0001] The present invention belongs to the technical field of charging management, and particularly relates to a comprehensive energy management circuit for an integrated charging system. Background Art

[0002] During the peak charging period of electric vehicles, the usage of charging piles is tense. If only the number of charging piles is simply increased, both the cost and the floor area will increase significantly, and at the same time, the requirement for the incoming power of the substation will increase significantly. In addition, in existing electric vehicle charging stations, there is no function for charging piles to work together with each other, so the flexibility of use still needs to be further improved.

[0003] In the prior art, for example, the Chinese invention patent with the publication number CN114784837A discloses a charging station energy management system and its management method. The energy management system includes an AC-DC module, a DC bus, a DC-DC module, and a controller connected in sequence. The output end of the DC-DC module is connected to a charging vehicle, and also includes an energy storage device. The controller controls whether the energy storage device charges the charging vehicle according to the output power requirement of the DC-DC module and the power distribution of the AC-DC module. This patent can reduce the infrastructure of the DC bus of the charging station, greatly reduce the construction cost of the charging station, realize rapid ultra-fast charging of electric vehicles, rationally utilize the peak-valley electricity price, and avoid resource waste caused by excessive power design margin of the charging station. The utility model with the publication number CN220457128U discloses a power management controller for an electric vehicle charging pile, including a main control board, a civilian power end, an industrial power end, a charging output end, a tram power supply end, a power consumption output end, and intelligent switches controlled by the main control board. Among them, the intelligent switch has three control positions, namely the first control position, the second control position, and the third control position. The civilian power end connected to the civilian power grid and the power consumption output end form a first line through the first control position via a wire, and the power consumption output end is connected to the local power grid outside to supply power to the local power grid.

[0004] The following situations will occur when there is no function for charging piles to work together with each other:

[0005] The utilization rate of the charging power supply is low. The charging of electric vehicles is not continuously charged at the maximum power. Some electric vehicles require 20KW of charging, some require 60WK of charging, etc. The charging power is also related to the temperature. The lower the temperature, the lower the maximum power. Therefore, the maximum power of the charging pile cannot be utilized 100%.

[0006] Table 1 is an example of the power and time percentages used in each stage during the process of charging an electric vehicle battery from 0% to 100%:

[0007] Charging Stage Battery Level Range Power Ratio (%) Time Ratio (%) 0%-20% 0%-20% 70% 10% 20%-50% 20%-50% 50% 20% 50%-80% 50%-80% 30% 30% 80%-100% 80%-100% 20% 40%

[0008] Table 1

[0009] 0%-20% stage: At the initial stage of charging, the battery receives a relatively high power (70%) because the battery can be charged quickly. This stage takes 10% of the total charging time.

[0010] 20%-50% stage: The charging power is reduced to 50%, and this stage takes 20% of the time.

[0011] 50%-80% stage: The charging power is further reduced to 30%, and this stage takes 30% of the time.

[0012] 80%-100% stage: The final charging stage, the power is as low as 20%, and this stage takes 40% of the time.

[0013] The above charging power and total charging time are for the ideal case of a temperature of 25 degrees Celsius. In a low-temperature situation, the lower the temperature, the smaller the maximum power value and the longer the charging time. This causes a great waste of efficiency for conventional charging piles because the power of a conventional charging power supply unit is 120KW or 60KW, and the power cannot be maximized when the charging power is low. Summary of the Invention

[0014] The present invention aims at the above problems and provides a hardware basis for the integrated energy management circuit of a charging integrated system.

[0015] To achieve the above object, the present invention adopts the following technical solutions. The present invention includes a charging power supply and communication part, an electric vehicle communication part, a communication ID setting part, a full-bridge drive part, an input voltage detection part, a power supply part, a relay drive part, an ADC conversion part, and a main control FPGA part. It is characterized in that the information transmission ports of the main control FPGA part are respectively connected to the information transmission ports of the charging power supply and communication part, the information transmission ports of the electric vehicle communication part, the information transmission ports of the communication ID setting part, the information transmission ports of the full-bridge drive part, the information transmission ports of the input voltage detection part, the information transmission ports of the relay drive part, and the information transmission ports of the ADC conversion part;

[0016] The power output ports of the power supply part are respectively connected to the power ports of the charging power supply and communication part, the power ports of the electric vehicle communication part, the power ports of the communication ID setting part, the power ports of the full-bridge drive part, the power ports of the input voltage detection part, the power ports of the relay drive part, the power ports of the ADC conversion part, and the power ports of the main control FPGA part;

[0017] The drive signal output port of the full-bridge drive part is connected to the drive signal input port of the charging power supply and communication part;

[0018] The detection signal input port of the input voltage detection part is connected to the detection signal output port of the charging power supply and the communication part;

[0019] The drive signal output port of the relay drive part is connected to the relay drive signal input port of the charging power supply and the communication part;

[0020] The signal input port of the ADC conversion part is connected to the output voltage and current acquisition signal output port and the switching tube working current acquisition signal output port of the charging power supply and the communication part.

[0021] As a preferred solution, the charging power supply and communication part of the present invention includes the YK818C relay K100. The control terminals of K100 are respectively connected to U2-OB and U2-OA. The 1st, 3rd, 4th, and 6th pins of the SH8023 chip U2 are respectively connected to U2-OB, P30, U2-OA, and P28 correspondingly;

[0022] VIN+1 is connected to the 1st pin of the common mode inductor U4, VIN-1 is connected to the 3rd pin of U4. The 2nd pin of U4 is respectively connected to one end of the controlled switch of K100 and one end of the resistor R9. The other end of R9 is respectively connected to the other end of the controlled switch of K100 and VBUS. The 4th pin of U4 is respectively connected to GND-P and the 1st pin of the HSTS08L module U46;

[0023] The gate of the IXFN50N120SiC tube Q1 is connected to A-PWM through the resistor R11. The drain of Q1 is connected to VBUS, and the source of Q1 is connected to the first end of the primary side of the transformer T1;

[0024] The gate of the IXFN50N120SiC tube Q2 is connected to A-PWM through the resistor R12. The drain of Q2 is connected to VBUS, and the source of Q2 is connected to the first end of the primary side of the transformer T1;

[0025] The gate of the IXFN50N120SiC tube Q5 is connected to B-PWM through the resistor R22. The drain of Q5 is connected to the first end of the primary side of the transformer T1, and the source of Q5 is connected to the 2nd pin of U46;

[0026] The gate of the IXFN50N120SiC tube Q6 is connected to B-PWM through the resistor R23. The drain of Q6 is connected to the first end of the primary side of the transformer T1, and the source of Q6 is connected to the 2nd pin of U46;

[0027] The gate of the IXFN50N120SiC tube Q3 is connected to C-PWM through the resistor R13. The drain of Q3 is connected to VBUS, and the source of Q3 is connected to the second end of the primary side of the transformer T1;

[0028] The gate of the IXFN50N120SiC tube Q4 is connected to C-PWM through the resistor R14. The drain of Q4 is connected to VBUS, and the source of Q4 is connected to the second end of the primary side of the transformer T1;

[0029] The gate of the IXFN50N120 SiC transistor Q7 is connected to D-PWM through the resistor R24. The drain of Q7 is connected to the second end of the primary side of the transformer T1, and the source of Q7 is connected to pin 2 of U46;

[0030] The gate of the IXFN50N120 SiC transistor Q8 is connected to D-PWM through the resistor R25. The drain of Q8 is connected to the second end of the primary side of the transformer T1, and the source of Q8 is connected to pin 2 of U46;

[0031] The sources of Q1 to Q8 are respectively connected to A-S, A-S, C-S, C-S, B-S, B-S, D-S, D-S correspondingly;

[0032] The OUT port of U46 is connected to pin 3 of the LMP7731MF chip U6 through the inductor L1, inductor L2, resistor R35, and resistor R36 in sequence. Pins 1 and 4 of U6 are connected to AD-0;

[0033] One end of the first secondary side T1B of T1 is connected to VOUT and the controlled switches of the relays K101 to K106 through the diode BD1 and the inductor L15 respectively. The other end of T1B is connected to pin 1 of the HSTS08L module U45;

[0034] One end of the second secondary side T1C of T1 is connected to the inductor L15 through the diode BD2. The other end of T1C is connected to pin 1 of U45;

[0035] The OUT port of U45 is connected to pin 3 of the LMP7731MF chip U5 through the resistor R32 and resistor R33 in sequence. Pins 1 and 4 of U5 are connected to AD-1;

[0036] Pin 1 of the HBV-A3.3 module VP1 is connected to VOUT through the resistor R34. Pin 2 of VP1 is connected to GOUT through the resistor R37. Pin 4 of VP1 is connected to pin 3 of the LMP7731MF chip U7 through the resistor R38. Pins 1 and 4 of U7 are connected to AD-2;

[0037] Pins 1 and 4 of the CAN / TJA1050T / CM chip U8 are respectively connected to P10 and P7 correspondingly. Pin 7 of U8 is connected to pin 2 of the connector CH1 through the inductor L3. Pin 6 of U8 is connected to pin 1 of CH1 through the inductor L4.

[0038] As another preferred solution, the communication part of the electric vehicle of the present invention includes a CAN / TJA1050T / CM chip U10. The 1st and 4th pins of U10 are respectively connected to TXD and RXD correspondingly. The 7th pin of U10 is connected to the 3rd pin of the ACT45B-510-2P-TL003 common mode filter L7. The 2nd pin of L7 is respectively connected to the 2nd pin of the connector P1 and one end of the inductor L5 through the fuse F1. The other end of L5 is connected to the 2nd pin of the connector CH3.

[0039] The 6th pin of U10 is connected to the 4th pin of L7. The 1st pin of L7 is respectively connected to one end of the resistor R43 and one end of the inductor L8 through the fuse F2. The other end of L8 is connected to the 2nd pin of the connector CH3. The other end of R43 is connected to the 1st pin of P1.

[0040] The 1st to 4th pins of the B0505S-1W module U11 are respectively connected to GND, +5V, +5V2, and GND2 correspondingly.

[0041] The 2nd, 3rd, 6th, and 7th pins of the ADUM1201CRZ chip U12 are respectively connected to P85, P86, RXD, and TXD correspondingly.

[0042] As another preferred solution, the communication ID setting part of the present invention uses a DIP switch U9. The 5th to 8th pins of U9 are respectively connected to P72, P71, P69, and P11 correspondingly. The 1st to 4th pins of U9 are respectively connected to one end of the resistors R39 to R42 correspondingly. The other ends of R39 to R42 are connected to +3.3V.

[0043] As another preferred solution, the full-bridge drive part of the present invention uses a BTD3011 chip U40. The IN+ port of U40 is sequentially connected to CHA1 through R45 and R44. The OUTL port of U40 is connected to A-PWM. The VISO port of U40 is connected to VCCA. The OUTH port of U40 is connected to A-PWM. The VEE port of U40 is connected to A-S.

[0044] As another preferred solution, the input voltage detection part of the present invention includes an LM224D chip U20. The 5th pin of U20 is respectively connected to one end of the resistor R71 and one end of the resistor R78. The other end of R71 is connected to VBUS. The other end of R78 is connected to GND-P. The 6th pin of U20 is respectively connected to one end of the resistor R70 and the cathode of the zener diode D31. The anode of D31 is connected to GND-P. The other end of R70 is connected to VBUS.

[0045] The 7th pin of U20 is connected to the anode of the input end of the EL357 chip OP1. The cathode of the input end of OP1 is sequentially connected to GND-P through the resistor R80 and the light-emitting diode E1. The emitter of the output end of OP1 is connected to P110.

[0046] As another preferred solution, the power supply part of the present invention includes an LM1085-3.3 module U24. The pin 3 of U24 is connected to +5V, and the pin 2 of U24 is connected to +3.3V;

[0047] The Vout port of the AMS1117-1.2 module U28 is connected to +3.3V, and the Vin port of U28 is connected to +1.2V;

[0048] The pin 1 of the LM2576-5.0 module U18 is connected to +24V, and the pin 2 of U18 is connected to the pin 4 of U18 and +5V respectively through an inductor L6;

[0049] The pin 1 of the UC1844 module U19 is connected to FB, the pin 4 of U19 is connected to RT / CT, the pin 5 of U19 is connected to the gate of the 12N170K5 transistor Q1 through a resistor R75. The source of Q1 is connected to GND-P through a resistor R81, and the drain of Q1 is connected to one end of the primary side of the transformer T2. The other end of the primary side of T2 is connected to VBUS; The pin 7 of U19 is sequentially connected to one end of the secondary side T2B of T2 through a resistor R66 and a diode D27. The other end of T2B is connected to GND-P;

[0050] One end of the secondary side T2C of T2 is sequentially connected to +24V through a diode D23 and an inductor L10, and the other end of T2C is connected to GND;

[0051] One end of the secondary side T2D of T2 is sequentially connected to the pin 1 of the K7815M-1000R3 module U15 through a diode D25 and an inductor L11. The pin 3 of U15 is connected to +15VP, and the other end of T2D is connected to GND-P;

[0052] One end of the secondary side T2E of T2 is sequentially connected to VCCA through a diode D28 and an inductor L12, and the other end of T2E is connected to GNDA;

[0053] One end of the secondary side T2F of T2 is sequentially connected to VCCB through a diode D30 and an inductor L13, and the other end of T2F is connected to GNDB;

[0054] One end of the secondary side T2G of T2 is sequentially connected to VCCC through a diode D32 and an inductor L14, and the other end of T2G is connected to GNDC;

[0055] One end of the secondary side T2H of T2 is sequentially connected to VCCD through a diode D33 and an inductor L16, and the other end of T2H is connected to GNDD;

[0056] The pin 4 of the PC817 chip U33 is connected to FB, the pin 3 of U33 is connected to GND-P, the pin 1 of U33 is connected to VCCD through a resistor R89, the pin 2 of U33 is connected to the pin 2 of the TL431 chip U35. The pin 3 of U35 is connected to GNDD, the pin 1 of U35 is connected to one end of a resistor R93 and one end of a resistor R95 respectively. The other end of R95 is connected to GNDD, and the other end of R93 is connected to VCCD through a resistor R90.

[0057] As another preferred solution, the relay driving part of the present invention uses the SH8023 chip U13. The 1st, 3rd, 4th, and 6th pins of U13 are respectively connected to U13-OB, P32, U13-OA, and P31 correspondingly. The control terminal of the YK818C relay K101 is connected to U13-OB and U13-OA.

[0058] Secondly, the ADC conversion part of the present invention uses the AD7788 chip U22. The 1st, 2nd, 3rd, 9th, and 10th pins of U22 are respectively connected to P119, P113, AD-2, P121, and P120 correspondingly.

[0059] The 4th pin of the LT1790 module U32 is sequentially connected to +3.3V through the resistor R94 and the bead L9, and the 6th pin of U32 is connected to +2.5V2.

[0060] In addition, the main control FPGA part of the present invention uses the EP4CE15E22I7 chip U1. The 28th, 30th, 31st, 32nd, and 33rd pins of U1 are respectively connected to P28, P30, P31, P32, and P33 correspondingly.

[0061] The 1st, 2nd, 5th, and 6th pins of the EPCS4SI8N chip U3 are respectively connected to FPGA-nCSO, FPGA-DATA0, FPGA-ASDO, and FPGA-DCLK correspondingly.

[0062] The 58th to 61st, 64th to 69th, 71st, and 72nd pins of U1 are respectively connected to P58 to P61, P64 to P69, P71, and P72 correspondingly.

[0063] The 13th pin of U1 is connected to FPGA-DATA0 through the resistor R31. The 11th, 10th, 8th, 7th, and 6th pins of U1 are respectively connected to P11, P10, FPGA-nCSO, P7, and FPGA-ASDO correspondingly.

[0064] The 76th, 77th, 80th, 83rd, 85th, and 86th pins of U1 are respectively connected to CHA1, CHA4, P85, and P86 correspondingly.

[0065] The 110th to 115th, 119th to 121st pins of U1 are respectively connected to P110 to P115, P119 to P121 correspondingly.

[0066] The beneficial effects of the present invention: The charging power supply and communication part of the present invention can conduct communication between various DC-DC high-power charging piles (i.e., charging stations). It can jointly control each charging station and flexibly allocate power.

[0067] The switching tube control signal of the main control FPGA part of the present invention controls the switching tubes of the charging power supply and the communication part after passing through the full-bridge drive part.

[0068] The main control FPGA part of the present invention communicates with the electric vehicle controller of the electric vehicle to be charged through the electric vehicle communication part to obtain the charging information of the electric vehicle.

[0069] The communication ID setting part of the present invention sets the IDs of each charging pile to distinguish each charging pile.

[0070] The input voltage detection part of the present invention is used to detect the input voltage values of the charging power supply and the communication part.

[0071] The power supply part of the present invention provides appropriate power supply voltages for each part of the system.

[0072] The main control FPGA part of the present invention controls the state of the electric energy output of the charging power supply and the communication part through the relay drive part.

[0073] The ADC conversion part of the present invention converts the detected analog detection value into a digital quantity and sends it to the main control FPGA part.

[0074] As can be seen from the above, the present invention flexibly distributes power by jointly controlling each charging pile, solves the problem in the prior art that only by increasing the number of charging piles can meet the tense use situation of charging piles, and the problems of no mutual cooperation, poor flexibility and low utilization rate of the charging power supply among each charging pile. Brief Description of the Drawings

[0075] The following further describes the present invention in conjunction with the drawings and specific embodiments. The protection scope of the present invention is not limited to the description of the following content.

[0076] Figures 1 to 4 is the circuit schematic diagram of the charging power supply and communication part of the present invention.

[0077] Figure 5 is the circuit schematic diagram of the electric vehicle communication part of the present invention.

[0078] Figure 6 is the circuit schematic diagram of the communication ID setting part of the present invention.

[0079] Figure 7 is the circuit schematic diagram of the full-bridge drive part of the present invention.

[0080] Figure 8 is the circuit schematic diagram of the input voltage detection part of the present invention.

[0081] Figures 9 to 12 is the circuit schematic diagram of the power supply part of the present invention.

[0082] Figure 13This is the circuit schematic diagram of the relay drive part of the present invention.

[0083] Figure 14 This is the circuit schematic diagram of the ADC conversion part of the present invention.

[0084] Figures 15 to 17 This is the circuit schematic diagram of the main control FPGA part of the present invention.

[0085] Figure 18 This is the connection diagram of multiple charging piles of the present invention. Specific embodiments

[0086] The present invention includes a charging power supply and communication part, an electric vehicle communication part, a communication ID setting part, a full-bridge drive part, an input voltage detection part, a power supply part, a relay drive part, an ADC conversion part, and a main control FPGA part. The information transmission ports of the main control FPGA part are respectively connected to the information transmission ports of the charging power supply and communication part, the electric vehicle communication part, the communication ID setting part, the full-bridge drive part, the input voltage detection part, the relay drive part, and the ADC conversion part;

[0087] The power output ports of the power supply part are respectively connected to the power ports of the charging power supply and communication part, the electric vehicle communication part, the communication ID setting part, the full-bridge drive part, the input voltage detection part, the relay drive part, the ADC conversion part, and the main control FPGA part;

[0088] The drive signal output port of the full-bridge drive part is connected to the drive signal input port of the charging power supply and communication part;

[0089] The detection signal input port of the input voltage detection part is connected to the detection signal output port of the charging power supply and communication part;

[0090] The drive signal output port of the relay drive part is connected to the relay drive signal input port of the charging power supply and communication part;

[0091] The signal input port of the ADC conversion part is connected to the output voltage and current acquisition signal output port and the switching tube working current acquisition signal output port of the charging power supply and communication part.

[0092] The charging power supply and communication part includes the YK818C relay K100. The control ends of K100 are respectively connected to U2-OB and U2-OA. The 1st, 3rd, 4th, and 6th pins of the SH8023 chip U2 are respectively connected to U2-OB, P30, U2-OA, and P28 correspondingly;

[0093] The VIN+1 is connected to pin 1 of the common mode inductor U4, the VIN-1 is connected to pin 3 of U4, pin 2 of U4 is respectively connected to one end of the K100 controlled switch and one end of the resistor R9, the other end of R9 is respectively connected to the other end of the K100 controlled switch and VBUS, and pin 4 of U4 is respectively connected to GND-P and pin 1 of the HSTS08L module U46;

[0094] The gate of the IXFN50N120SiC transistor Q1 is connected to A-PWM through the resistor R11, the drain of Q1 is connected to VBUS, and the source of Q1 is connected to the first end of the primary side of the transformer T1;

[0095] The gate of the IXFN50N120SiC transistor Q2 is connected to A-PWM through the resistor R12, the drain of Q2 is connected to VBUS, and the source of Q2 is connected to the first end of the primary side of the transformer T1;

[0096] The gate of the IXFN50N120SiC transistor Q5 is connected to B-PWM through the resistor R22, the drain of Q5 is connected to the first end of the primary side of the transformer T1, and the source of Q5 is connected to pin 2 of U46;

[0097] The gate of the IXFN50N120SiC transistor Q6 is connected to B-PWM through the resistor R23, the drain of Q6 is connected to the first end of the primary side of the transformer T1, and the source of Q6 is connected to pin 2 of U46;

[0098] The gate of the IXFN50N120SiC transistor Q3 is connected to C-PWM through the resistor R13, the drain of Q3 is connected to VBUS, and the source of Q3 is connected to the second end of the primary side of the transformer T1;

[0099] The gate of the IXFN50N120SiC transistor Q4 is connected to C-PWM through the resistor R14, the drain of Q4 is connected to VBUS, and the source of Q4 is connected to the second end of the primary side of the transformer T1;

[0100] The gate of the IXFN50N120SiC transistor Q7 is connected to D-PWM through the resistor R24, the drain of Q7 is connected to the second end of the primary side of the transformer T1, and the source of Q7 is connected to pin 2 of U46;

[0101] The gate of the IXFN50N120SiC transistor Q8 is connected to D-PWM through the resistor R25, the drain of Q8 is connected to the second end of the primary side of the transformer T1, and the source of Q8 is connected to pin 2 of U46;

[0102] The sources of Q1 to Q8 are respectively connected to A-S, A-S, C-S, C-S, B-S, B-S, D-S, D-S correspondingly;

[0103] The OUT port of U46 is successively connected to pin 3 of the LMP7731MF chip U6 through the inductor L1, the inductor L2, the resistor R35, and the resistor R36, and pins 1 and 4 of U6 are connected to AD-0;

[0104] One end of the first secondary side T1B of T1 is successively connected to VOUT and the controlled switches of relays K101 - K106 through diode BD1 and inductor L15 respectively, and the other end of T1B is connected to pin 1 of HSTS08L module U45;

[0105] One end of the second secondary side T1C of T1 is connected to inductor L15 through diode BD2, and the other end of T1C is connected to pin 1 of U45;

[0106] The OUT port of U45 is successively connected to pin 3 of LMP7731MF chip U5 through resistor R32 and resistor R33, and pins 1 and 4 of U5 are connected to AD - 1;

[0107] Pin 1 of HBV - A3.3 module VP1 is connected to VOUT through resistor R34, pin 2 of VP1 is connected to GOUT through resistor R37, pin 4 of VP1 is connected to pin 3 of LMP7731MF chip U7 through resistor R38, and pins 1 and 4 of U7 are connected to AD - 2;

[0108] Pins 1 and 4 of CAN / TJA1050T / CM chip U8 are respectively connected to P10 and P7 correspondingly, pin 7 of U8 is connected to pin 2 of connector CH1 through inductor L3, and pin 6 of U8 is connected to pin 1 of CH1 through inductor L4.

[0109] As Figure 3 shown, R38 and C46 form a low - pass filter at the Hz level. R38 uses 27R and C46 uses 0.1uF 50V, which greatly improves the suppression of high - frequency interference.

[0110] Figures 1 to 17 This is just a circuit diagram of a DC - DC high - power charging pile (charging station). CH1 is used to communicate with other charging piles, query the idle information on the CAN bus, which charging pile is in the idle state, and request to be connected in parallel with this charging pile to charge the electric vehicle together. When the charging power of this charging pile is sufficient, disconnect other charging piles connected in parallel with this charging pile.

[0111] VIN+ is connected to 750VDC.

[0112] Q1 - Q8 form an H - bridge topology structure. Two switching tubes are connected in parallel (for example, Q1 and Q2 are in parallel, and A - PWM controls Q1 and Q2 simultaneously) to increase the current and avoid the situation where the rated current of a single switching tube is insufficient.

[0113] Q1 - Q8 use IXFN50N120SiC tubes. The IXFN50N120SiC tube is a silicon carbide MOS, with low heat generation and high efficiency.

[0114] Q1 and Q2 conduct and turn off simultaneously; Q7 and Q8 conduct and turn off simultaneously; Q5 and Q6 conduct and turn off simultaneously; Q3 and Q4 conduct and turn off simultaneously; they form a full-bridge topology. When Q1, Q2, Q7, and Q8 conduct, the current in the primary side T1A of the transformer flows forward. When Q5, Q6, Q3, and Q4 conduct, the current flows reversely through T1A, forming an alternating magnetic flux in T1A. The secondary sides T1B and T1C of the transformer generate secondary power supplies due to the induced electromotive force, providing electrical energy for the secondary load.

[0115] R9 and the controlled switch K100 (K100A) form a surge protection circuit. When the voltage between VBUS and GND-P is lower than 500V (the voltage between VBUS and GND-P is detected by the circuit composed of R84, R83, R86, D34, U20, and OP2), K100A disconnects; when the circuit voltage is higher than 500V, K100A closes, reducing the current impact on the front end during the charging of the backend energy storage capacitor.

[0116] As Figure 2 shown, there are large-capacity filter capacitors C11, C12, C20, and C21 at the input end of the circuit. At the moment when the circuit is connected to the power supply line (750V), due to the characteristics of the capacitor, the capacitor voltage rises rapidly from 0V to the power supply voltage of 750V. The initial internal resistance of the capacitor is approximately 0, and at this moment, the charging current is approximately infinite, similar to a transient short circuit of the power grid, which will instantaneously pull down the power grid voltage and cause interference to other devices on the power grid. To reduce this interference, R9 is connected in series with the capacitor in the circuit to limit the charging current and reduce the impact on the power grid. When the capacitor charging voltage rises to 600V, control K100 to conduct and short-circuit R9 to avoid energy loss on R9.

[0117] U46 is used for detecting the current of the switching tube. U6 collects the detected current of the switching tube for overcurrent protection. To prevent magnetic bias and avoid the problem of unilateral saturation of the transformer T1 during operation, resulting in the burning of the switching tube due to the imbalance between the positive and negative half axes.

[0118] As Figure 2As shown in the figure, the main transformer T1 of the H-bridge topology operates on the positive and negative half axes of the hysteresis loop. When Q1, Q2, Q7, and Q8 are conducting, it operates in the positive half cycle; when Q3, Q4, Q5, and Q6 are conducting, it operates in the negative half cycle. The normal operating condition without deviation is that after each cycle of operation, it returns to the 0 point position of the hysteresis loop. When magnetic bias occurs, the hysteresis loop does not return to the 0 point position but is above or below the 0 point, which results in the current flowing through Q1, Q2, Q7, and Q8 being greater than or less than that through Q3, Q4, Q5, and Q6 at the same power. Since the currents of the two sets of switching tubes are different, after multiple accumulations, it will cause one set of tubes to be overcurrent and burned out. In the present invention, when each set of switching tubes is operating, the maximum current of this set of switching tubes is detected. When it reaches 50% of the rated current, this set of switching tubes is forced to turn off and the other set of switching tubes is turned on, thus avoiding the occurrence of magnetic bias and protecting the switching tubes from being burned out due to magnetic bias overcurrent.

[0119] As Figure 2 shown, L1, L2, C41~C43 form a 58KHz low-pass filter circuit. L1 and L2 use 0.45mH inductors, C41 uses a 16nF 25V capacitor, C42 uses a 54nF 25V capacitor, and C43 uses a 17nF 25V capacitor; a two-stage low-pass filter structure is adopted, which has a better filtering effect and ensures that the source signal is not lost. The operating frequency of the full-bridge circuit selected in the present invention is 40KHz. To ensure the integrity of current acquisition, the acquisition frequency is greater than the operating frequency and as low as possible.

[0120] Used for DEBUG1 debugging.

[0121] The communication part of the electric vehicle includes the CAN / TJA1050T / CM chip U10. The 1st and 4th pins of U10 are respectively connected to TXD and RXD correspondingly. The 7th pin of U10 is connected to the 3rd pin of the ACT45B-510-2P-TL003 common-mode filter L7. The 2nd pin of L7 is respectively connected to the 2nd pin of the connector P1 and one end of the inductor L5 through the fuse F1. The other end of L5 is connected to the 2nd pin of the connector CH3;

[0122] The 6th pin of U10 is connected to the 4th pin of L7. The 1st pin of L7 is respectively connected to one end of the resistor R43 and one end of the inductor L8 through the fuse F2. The other end of L8 is connected to the 2nd pin of the connector CH3. The other end of R43 is connected to the 1st pin of P1;

[0123] The 1st~4th pins of the B0505S-1W module U11 are respectively connected to GND, +5V, +5V2, and GND2 correspondingly;

[0124] The 2nd, 3rd, 6th, and 7th pins of the ADUM1201CRZ chip U12 are respectively connected to P85, P86, RXD, and TXD correspondingly.

[0125] U12 isolates U1 from U10. Its function is that this CAN interface is connected to the charging gun (CH3 is connected to the charging gun, and conventional charging guns all have a CAN bus for communicating with the electric vehicle). The charging gun is connected to the outside. When there is damage or interference from the outside that gets onto the CAN bus, the U1 circuit will not be damaged.

[0126] When the charging gun is inserted into the electric vehicle for charging, the electric vehicle controller communicates with U10 to obtain the electric vehicle charging information. U1 adjusts the duty cycle according to the information to charge the electric vehicle. When the electric vehicle charging dock is connected to the charging gun, the electric vehicle controller and the charging pile communicate through the CAN bus, sending data such as the current battery information, charging voltage, charging current, and temperature of the electric vehicle to the charging pile. The charging pile charges the electric vehicle according to this information, which is a conventional technology.

[0127] When the required power increases (the power judgment is obtained through communication with the electric vehicle. For example, the electric vehicle will send the required charging voltage and charging current to the charging pile), U1 sends it to the bus through the internal CAN to request other charging piles to be connected in parallel with it.

[0128] Charge the electric vehicle battery and send the charging information to the request receiver. As the battery is fully charged (by receiving the information from the electric vehicle controller through CH3 to know the charging status of the battery), the required charging power decreases. U1 requests to disconnect the requested power supply through the internal CAN to break the parallel connection. Through the above power supply cooperation, optimal charging is achieved.

[0129] As Figure 3 shown, among Channel-1 to Channel-6, one port is connected to the charging gun, and the other five ports are used for parallel control with other charging piles.

[0130] One DC-DC high-power charging stack of the present invention can charge multiple electric vehicles, improving the utilization rate of a single DC-DC high-power charging stack. At the same time, it communicates with other DC-DC high-power charging stacks through U8. When it is necessary to increase the output power of a certain DC-DC high-power charging stack, it can be controlled to be connected in parallel with other DC-DC high-power charging stacks.

[0131] The output power of a single DC-DC high-power charging stack can be designed to be 10KW. An array is composed of six DC-DC high-power charging stacks. Each DC-DC high-power charging stack can be freely connected in parallel. The maximum charging power is 60KW. Through the parallel control of the power supply, the power can be flexibly distributed. Multiple cars can be charged simultaneously, or the remaining power for each car's charging can be switched out and distributed to other charging cars for use.

[0132] As Figure 5As shown, P1 is used to quickly select whether to connect a 120-ohm resistor to the communication bus through a pin. The 120-ohm resistor is used to filter out interference on the communication. Under normal circumstances, a 120-ohm resistor is connected at the beginning and the farthest position of the communication bus, and the bus resistance is 60 ohms. The entire system includes multiple charging piles. Before the equipment is put into use, it is impossible to determine which device is the head, which device is the tail, and which device is the intermediate device (the intermediate device does not need to connect a 120-ohm resistor). Therefore, P1 is used to select whether to connect a 120-ohm resistor.

[0133] U11 is used to isolate the +5V input power supply from the +5V2 output power supply. The primary side of U11 is connected to +5V, and the secondary side of U11 is connected to +5V2. This avoids mutual interference between the primary and secondary circuits and improves the voltage withstand performance of the circuit.

[0134] The communication ID setting part uses a DIP switch U9. The 5th to 8th pins of U9 are respectively connected to P72, P71, P69, and P11 correspondingly. The 1st to 4th pins of U9 are respectively connected to one end of resistors R39 to R42 correspondingly, and the other ends of R39 to R42 are connected to +3.3V.

[0135] The full-bridge drive part uses a BTD3011 chip U40. The IN+ port of U40 is connected to CHA1 through R45 and R44 in sequence. The OUTL port of U40 is connected to A-PWM. The VISO port of U40 is connected to VCCA. The OUTH port of U40 is connected to A-PWM. The VEE port of U40 is connected to A-S.

[0136] As Figure 2 shown, A-S is a special pin of the IXFN50N120SiC silicon carbide MOSFET. This pin is used to drive the MOS, which is the same as the source electrode of a traditional MOS. The advantage is that this pin does not directly participate in the power part and is not affected by large currents on the control electrode.

[0137] As Figure 7 shown, R44, R45, D17, D18, and C80 form an anti-interference circuit, which clamps the interference level on CHA1 to 3.3V and will not exceed 3.3V (exceeding 3.3V will damage U1).

[0138] Both OUTL and OUTH are connected to A-PWM. OUTH is used to turn on the high level, and OUTL is pulled down to the low level.

[0139] The input voltage detection part includes an LM224D chip U20. The 5th pin of U20 is respectively connected to one end of resistor R71 and one end of resistor R78. The other end of R71 is connected to VBUS, and the other end of R78 is connected to GND-P. The 6th pin of U20 is respectively connected to one end of resistor R70 and the cathode of zener diode D31. The anode of D31 is connected to GND-P, and the other end of R70 is connected to VBUS;

[0140] Pin 7 of U20 is connected to the anode of the input terminal OP1 of the EL357 chip. The cathode of the input terminal OP1 is sequentially connected to GND-P through the resistor R80 and the light-emitting diode E1. The emitter of the output terminal of OP1 is connected to P110.

[0141] As Figure 8 shown, it is designed in the form of a voltage comparator using LM224D (U20). Pin 6 of U20 is clamped to 12V. When the voltage at pin 5 of U20 exceeds 12V, the output of pin 7 of U20 is at a high level. When the voltage at pin 5 of U20 is lower than 12V, there is no output at pin 7 of U20. Using the resistor voltage division of R71 and R78, when the voltage reaches 600V, the voltage at pin 5 of U20 is 12.6V. At this moment, the output of pin 7 of U20 is at a high level, OP1 conducts, P110 is at a high level, and U1 detects that the input voltage exceeds 600V.

[0142] U20A is used to detect that the VBUS voltage exceeds 600V (turn off the surge protection K100), U20C is used to detect that the VBUS voltage is lower than 500V (undervoltage), and U20D is used to detect that the VBUS voltage exceeds 900V (overvoltage). In case of undervoltage or overvoltage, U1 controls the turn-off of the switching tube through the full-bridge drive part. Overvoltage will damage the switching tube. In case of undervoltage, under the same power condition, the current flowing through the switching tube is large, which will damage the switching tube.

[0143] The power supply part includes the LM1085-3.3 module U24. Pin 3 of U24 is connected to +5V, and pin 2 of U24 is connected to +3.3V;

[0144] The Vout port of the AMS1117-1.2 module U28 is connected to +3.3V, and the Vin port of U28 is connected to +1.2V;

[0145] Pin 1 of the LM2576-5.0 module U18 is connected to +24V. Pin 2 of U18 is connected to pin 4 of U18 and +5V respectively through the inductor L6;

[0146] Pin 1 of the UC1844 module U19 is connected to FB. Pin 4 of U19 is connected to RT / CT. Pin 5 of U19 is connected to the gate of the 12N170K5 tube Q1 through the resistor R75. The source of Q1 is connected to GND-P through the resistor R81. The drain of Q1 is connected to one end of the primary side of the transformer T2. The other end of the primary side of T2 is connected to VBUS. Pin 7 of U19 is sequentially connected to one end of the secondary side T2B of T2 through the resistor R66 and the diode D27. The other end of T2B is connected to GND-P;

[0147] One end of the secondary side T2C of T2 is sequentially connected to +24V through the diode D23 and the inductor L10. The other end of T2C is connected to GND;

[0148] One end of the secondary side T2D of T2 is connected to pin 1 of module U15 of K7815M-1000R3 through diode D25 and inductor L11 in sequence. Pin 3 of U15 is connected to +15VP. The other end of T2D is connected to GND-P;

[0149] One end of the secondary side T2E of T2 is connected to VCCA through diode D28 and inductor L12 in sequence. The other end of T2E is connected to GNDA;

[0150] One end of the secondary side T2F of T2 is connected to VCCB through diode D30 and inductor L13 in sequence. The other end of T2F is connected to GNDB;

[0151] One end of the secondary side T2G of T2 is connected to VCCC through diode D32 and inductor L14 in sequence. The other end of T2G is connected to GNDC;

[0152] One end of the secondary side T2H of T2 is connected to VCCD through diode D33 and inductor L16 in sequence. The other end of T2H is connected to GNDD;

[0153] Pin 4 of PC817 chip U33 is connected to FB. Pin 3 of U33 is connected to GND-P. Pin 1 of U33 is connected to VCCD through resistor R89. Pin 2 of U33 is connected to pin 2 of TL431 chip U35. Pin 3 of U35 is connected to GNDD. Pin 1 of U35 is connected to one end of resistor R93 and one end of resistor R95 respectively. The other end of R95 is connected to GNDD. The other end of R93 is connected to VCCD through resistor R90.

[0154] T2 and the primary and secondary connection circuits of T2 form an auxiliary power supply circuit.

[0155] Pin 7 of U19 charges capacitor C119 through R64 and R65. When the charge reaches about 16V, U19 starts, and magnetic flux is generated in the core of T2 transformer. The induced electromotive force of T2B has current to continue to supply power to pin 7 of U19.

[0156] Pin 3 of U19 is the overcurrent detection pin for the switching current. When the current passing through Q1 is too large, the voltage across resistor R81 increases, and the voltage at pin 3 of U19 increases. After reaching its turn-off threshold, pin 6 of U19 becomes low level, turning off Q1 to protect Q1 from overcurrent.

[0157] Pin 4 of U19 is the switching frequency setting pin of U19, which is determined by R68 and C122.

[0158] Pin 6 of U19 is the switching transistor drive pin.

[0159] Pin 8 of U19 is the chip reference voltage output.

[0160] Pin 1 of U19 is the feedback acquisition pin.

[0161] T2H, U33, and U35 form a feedback sampling circuit that samples the voltage from the output terminal T2H to compare with the reference voltage. When the voltage is lower than the reference voltage, U19 increases the duty cycle; when it is higher than the reference voltage, U19 decreases the duty cycle.

[0162] U35 is a reference source. A change in the voltage at pin 1 of U35 will change the current value from pin 2 to pin 3 of U35, thereby changing the brightness of the light-emitting diode on the primary side of U33, and then changing the conduction state of the photosensitive triode on the secondary side of U33. The secondary side of U33 is connected to the feedback pin FB of U19. Thus, U19 uses the feedback signal to adjust the duty cycle and control the stability of the voltage on the secondary side of T2.

[0163] The relay drive part uses the SH8023 chip U13. Pins 1, 3, 4, and 6 of U13 are respectively connected to U13-OB, P32, U13-OA, and P31 correspondingly. The control terminals of the YK818C relay K101 are connected to U13-OB and U13-OA.

[0164] The main control FPGA part controls which of Channel-1 to Channel-6 outputs electrical energy through U13, U14, U16, U17, U23, and U25 according to the request of each channel (through CH3 communication).

[0165] The working principle of the circuit of the present invention is as follows: Figure 18 As shown, assume there are six charging piles, and each charging pile has an electric vehicle connected. Each charging pile charges the electric vehicle connected to it. When an electric vehicle connected to a certain charging pile requires more power (judged by the main control FPGA part of this charging pile), this charging pile sends a request on the bus through CH1. The charging piles that are idle or have not fully released their power respond, and the response priority can be confirmed according to the ID (from low to high). After this charging pile connects to a charging pile and still fails to meet the demand, this charging pile can send a request again to connect other idle or not fully released power charging piles again. By controlling the KA to KF switches (taking KA as an example for illustration. Figure 18 In which KA1 to KA6 are equivalent to Figure 3 In which K101B to K106B), select which charging pile or charging piles to connect. When the power demand of this charging pile decreases and it no longer needs to connect to other charging piles, it sends a disconnection request, and the priority level is from high to low.

[0166] YK818C is a magnetic latching relay, which is power-saving, has stable performance, small size, and large load capacity.

[0167] The SH8023 chip is a magnetic latching relay drive chip.

[0168] The ADC conversion part uses the AD7788 chip U22. The pins 1, 2, 3, 9, and 10 of U22 are respectively connected to P119, P113, AD-2, P121, and P120 correspondingly.

[0169] The pin 4 of the LT1790 module U32 is successively connected to +3.3V through the resistor R94 and the bead L9, and the pin 6 of U32 is connected to +2.5V2.

[0170] As Figure 14 shown, three AD7788 chips are set, corresponding to the output voltage acquisition signal (AD-2), the output current acquisition signal (AD-1), and the switching tube working current acquisition signal (AD-0) of the charging power supply and the communication part respectively.

[0171] AD-0: Used to detect the current signal of Q1~Q8 for overcurrent / short-circuit / bias magnetic protection.

[0172] AD-1: Used to detect the magnitude and direction of the output current. The main control FPGA part controls the magnitude of the output current through the full-bridge drive part to make the magnitude of the current meet the requirements of the charging electric vehicle.

[0173] AD-2: Used to detect the output voltage. The main control FPGA part controls the level of the output voltage through the full-bridge drive part to make the voltage meet the requirements of the charging electric vehicle.

[0174] The level of the output voltage and the magnitude of the current are used to adjust the duty cycle of the tubes Q1~Q8 after detection to control the output voltage and current to meet the requirements of the charging electric vehicle.

[0175] The main control FPGA part uses the EP4CE15E22I7 chip U1. The pins 28, 30, 31, 32, and 33 of U1 are respectively connected to P28, P30, P31, P32, and P33 correspondingly.

[0176] The pins 1, 2, 5, and 6 of the EPCS4SI8N chip U3 are respectively connected to FPGA-nCSO, FPGA-DATA0, FPGA-ASDO, and FPGA-DCLK correspondingly.

[0177] The pins 58~61, 64~69, 71, and 72 of U1 are respectively connected to P58~P61, P64~P69, P71, and P72 correspondingly.

[0178] The pin 13 of U1 is connected to FPGA-DATA0 through the resistor R31. The pins 11, 10, 8, 7, and 6 of U1 are respectively connected to P11, P10, FPGA-nCSO, P7, and FPGA-ASDO correspondingly.

[0179] The pins 76, 77, 80, 83, 85, and 86 of U1 are respectively and correspondingly connected to CHA1, CHA4, P85, and P86.

[0180] The pins 110 to 115, 119 to 121 of U1 are respectively and correspondingly connected to P110 to P115, P119 to P121.

[0181] It can be understood that the above specific description of the present invention is only for explaining the present invention and is not limited to the technical solutions described in the embodiments of the present invention. Those of ordinary skill in the art should understand that the present invention can still be modified or equivalently replaced to achieve the same technical effects; as long as the usage requirements are met, they are all within the protection scope of the present invention.

Claims

1. A comprehensive energy management circuit for an integrated charging system, comprising a charging power supply and communication part, an electric vehicle communication part, a communication ID setting part, a full-bridge driving part, an input voltage detection part, a power supply part, a relay driving part, an ADC conversion part and a main control FPGA part, characterized in that The information transmission port of the main control FPGA part is respectively connected with the information transmission port of the charging power supply and communication part, the information transmission port of the electric vehicle communication part, the information transmission port of the communication ID setting part, the information transmission port of the full-bridge driving part, the information transmission port of the input voltage detection part, the information transmission port of the relay driving part, and the information transmission port of the ADC conversion part; The power output port of the power supply part is respectively connected to the power port of the charging power supply and communication part, the power port of the electric vehicle communication part, the power port of the communication ID setting part, the power port of the full-bridge drive part, the power port of the input voltage detection part, the power port of the relay drive part, the power port of the ADC conversion part, and the power port of the main control FPGA part; The driving signal output port of the full-bridge driving part is connected to the driving signal input port of the charging power supply and the communication part; The detection signal input port of the input voltage detection part is connected to the detection signal output port of the charging power supply and the communication part; The driving signal output port of the relay driving part is connected to the relay driving signal input port of the charging power supply and the communication part; The signal input port of the ADC conversion part is connected to the output voltage and current acquisition signal output port of the charging power supply and communication part and the switch tube working current acquisition signal output port; The charging power supply and communication part includes a YK818C relay K100, the control end of K100 is connected to U2-OB and U2-OA respectively, and the 1st, 3rd, 4th and 6th pins of the SH8023 chip U2 are connected to U2-OB, P30, U2-OA and P28 respectively; VIN+1 is connected to the 1st pin of the common mode inductor U4, VIN-1 is connected to the 3rd pin of U4, the 2nd pin of U4 is connected to one end of the K100 controlled switch and one end of the resistor R9 respectively, the other end of R9 is connected to the other end of the K100 controlled switch and VBUS respectively, the 4th pin of U4 is connected to GND-P and the 1st pin of the HSTS08L module U46 respectively; The gate of IXFN50N120SiC tube Q1 is connected to A-PWM through resistor R11, the drain of Q1 is connected to VBUS, and the source of Q1 is connected to the first terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q2 is connected to A-PWM through resistor R12, the drain of Q2 is connected to VBUS, and the source of Q2 is connected to the first terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q5 is connected to B-PWM through resistor R22, the drain of Q5 is connected to the first terminal of the primary side of transformer T1, and the source of Q5 is connected to pin 2 of U46; The gate of IXFN50N120SiC tube Q6 is connected to B-PWM through resistor R23, the drain of Q6 is connected to the first terminal of the primary side of transformer T1, and the source of Q6 is connected to pin 2 of U46; The gate of IXFN50N120SiC tube Q3 is connected to C-PWM through resistor R13, the drain of Q3 is connected to VBUS, and the source of Q3 is connected to the second terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q4 is connected to C-PWM through resistor R14, the drain of Q4 is connected to VBUS, and the source of Q4 is connected to the second terminal of the primary side of transformer T1; The gate of IXFN50N120SiC tube Q7 is connected to D-PWM through resistor R24, the drain of Q7 is connected to the second terminal of the primary side of transformer T1, and the source of Q7 is connected to pin 2 of U46; The gate of IXFN50N120SiC tube Q8 is connected to D-PWM through resistor R25, the drain of Q8 is connected to the second terminal of the primary side of transformer T1, and the source of Q8 is connected to pin 2 of U46; The sources of Q1 to Q8 are connected to AS, AS, CS, CS, BS, BS, DS, and DS respectively; The OUT port of U46 is connected to the 3rd pin of LMP7731MF chip U6 through inductor L1, inductor L2, resistor R35 and resistor R36 in sequence, and the 1st and 4th pins of U6 are connected to AD-0; One end of the first secondary side T1B of T1 is connected to VOUT and the controlled switches of relays K101 to K106 respectively through diode BD1 and inductor L15, and the other end of T1B is connected to pin 1 of HSTS08L module U45; One end of the second secondary side T1C of T1 is connected to the inductor L15 through the diode BD2, and the other end of T1C is connected to the pin 1 of U45; The OUT port of U45 is connected to the 3rd pin of LMP7731MF chip U5 through resistors R32 and R33, and the 1st and 4th pins of U5 are connected to AD-1; Pin 1 of HBV-A3.3 module VP1 is connected to VOUT through resistor R34, pin 2 of VP1 is connected to GOUT through resistor R37, pin 4 of VP1 is connected to pin 3 of LMP7731MF chip U7 through resistor R38, and pins 1 and 4 of U7 are connected to AD-2; Pins 1 and 4 of the CAN / TJA1050T / CM chip U8 are connected to P10 and P7 respectively, pin 7 of U8 is connected to pin 2 of the connector CH1 through inductor L3, and pin 6 of U8 is connected to pin 1 of CH1 through inductor L4.

2. According to claim 1, the integrated energy management circuit of the charging integrated system is characterized in that The electric vehicle communication part includes a CAN / TJA1050T / CM chip U10, wherein the 1st and 4th pins of U10 are respectively connected to TXD and RXD, and the 7th pin of U10 is connected to the 3rd pin of the ACT45B-510-2P-TL003 common mode filter L7, and the 2nd pin of L7 is respectively connected to the 2nd pin of the connector P1 and one end of the inductor L5 through the fuse F1, and the other end of L5 is connected to the 2nd pin of the connector CH3; Pin 6 of U10 is connected to pin 4 of L7, and pin 1 of L7 is connected to one end of resistor R43 and one end of inductor L8 through fuse F2. The other end of L8 is connected to pin 2 of connector CH3, and the other end of R43 is connected to pin 1 of P1. The 1~4 pins of the B0505S-1W module U11 are connected to GND, +5V, +5V2, and GND2 respectively; The 2, 3, 6, and 7 pins of the ADUM1201CRZ chip U12 are connected to P85, P86, RXD, and TXD respectively.

3. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The communication ID setting part adopts the dip switch U9, and the 5th to 8th pins of U9 are respectively connected to P72, P71, P69, and P11, and the 1st to 4th pins of U9 are respectively connected to one end of the resistors R39 to R42, and the other end of R39 to R42 is connected to +3.3V.

4. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The full-bridge driving part adopts BTD3011 chip U40, the IN+ port of U40 is connected to CHA1 through R45 and R44 in sequence, the OUTL port of U40 is connected to A-PWM, the VISO port of U40 is connected to VCCA, the OUTH port of U40 is connected to A-PWM, and the VEE port of U40 is connected to AS.

5. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The input voltage detection part includes an LM224D chip U20, wherein the 5th pin of U20 is respectively connected to one end of a resistor R71 and one end of a resistor R78, the other end of R71 is connected to VBUS, the other end of R78 is connected to GND-P, the 6th pin of U20 is respectively connected to one end of the resistor R70 and the cathode of the voltage regulator D31, the anode of D31 is connected to GND-P, and the other end of R70 is connected to VBUS; Pin 7 of U20 is connected to the anode of the OP1 input terminal of the EL357 chip, and the cathode of the OP1 input terminal is connected to GND-P through resistor R80 and light-emitting diode E1 in sequence; the emitter of the OP1 output terminal is connected to P110.

6. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The power supply part includes an LM1085-3.3 module U24, pin 3 of U24 is connected to +5V, and pin 2 of U24 is connected to +3.3V; The Vout port of the AMS1117-1.2 module U28 is connected to +3.3V, and the Vin port of U28 is connected to +1.2V; Pin 1 of LM2576-5.0 module U18 is connected to +24V, and pin 2 of U18 is connected to pin 4 of U18 and +5V respectively through inductor L6; Pin 1 of UC1844 module U19 is connected to FB, pin 4 of U19 is connected to RT / CT, pin 5 of U19 is connected to the gate of 12N170K5 tube Q1 through resistor R75, source of Q1 is connected to GND-P through resistor R81, drain of Q1 is connected to one end of the primary side of transformer T2, and the other end of the primary side of T2 is connected to VBUS; pin 7 of U19 is connected to one end of the secondary side T2B of T2 through resistor R66 and diode D27 in sequence, and the other end of T2B is connected to GND-P; One end of the secondary side T2C of T2 is connected to +24V through diode D23 and inductor L10, and the other end of T2C is connected to GND; One end of the secondary side T2D of T2 is connected to the 1st pin of the K7815M-1000R3 module U15 through the diode D25 and the inductor L11, the 3rd pin of U15 is connected to +15VP, and the other end of T2D is connected to GND-P; One end of the secondary side T2E of T2 is connected to VCCA through diode D28 and inductor L12, and the other end of T2E is connected to GNDA; One end of the secondary side T2F of T2 is connected to VCCB through diode D30 and inductor L13, and the other end of T2F is connected to GNDB; One end of the secondary side T2G of T2 is connected to VCCC through diode D32 and inductor L14, and the other end of T2G is connected to GNDC; One end of the secondary side T2H of T2 is connected to VCCD through diode D33 and inductor L16 in sequence, and the other end of T2H is connected to GNDD; Pin 4 of PC817 chip U33 is connected to FB, pin 3 of U33 is connected to GND-P, pin 1 of U33 is connected to VCCD through resistor R89, pin 2 of U33 is connected to pin 2 of TL431 chip U35, pin 3 of U35 is connected to GNDD, pin 1 of U35 is respectively connected to one end of resistor R93 and one end of resistor R95, the other end of R95 is connected to GNDD, and the other end of R93 is connected to VCCD through resistor R90.

7. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The relay driving part adopts SH8023 chip U13, and the 1st, 3rd, 4th and 6th pins of U13 are respectively connected to U13-OB, P32, U13-OA and P31, and the control terminal of YK818C relay K101 is connected to U13-OB and U13-OA.

8. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The ADC conversion part adopts AD7788 chip U22, and pins 1, 2, 3, 9, and 10 of U22 are respectively connected to P119, P113, AD-2, P121, and P120; Pin 4 of the LT1790 module U32 is connected to +3.3V through resistor R94 and magnetic bead L9, and pin 6 of U32 is connected to +2.5V2.

9. The integrated energy management circuit of the charging integrated system according to claim 1, characterized in that The main control FPGA part adopts EP4CE15E22I7 chip U1, and pins 28, 30, 31, 32, and 33 of U1 are respectively connected to P28, P30, P31, P32, and P33; Pins 1, 2, 5, and 6 of the EPCS4SI8N chip U3 are connected to FPGA-nCSO, FPGA-DATA0, FPGA-ASDO, and FPGA-DCLK respectively; Pins 58-61, 64-69, 71, and 72 of U1 are connected to P58-P61, P64-P69, P71, and P72 respectively; Pin 13 of U1 is connected to FPGA-DATA0 through resistor R31, and pins 11, 10, 8, 7, and 6 of U1 are connected to P11, P10, FPGA-nCSO, P7, and FPGA-ASDO respectively; Pins 76, 77, 80, 83, 85, and 86 of U1 are connected to CHA1, CHA4, P85, and P86 respectively; Pins 110~115 and 119~121 of U1 are connected to P110~P115 and P119~P121 respectively.

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