Test vector generation method and device and computing equipment

Abstract

The embodiment of the invention discloses a test vector generation method and device and computing equipment, and the method comprises the steps: obtaining conversion information, the conversion information comprises pin information, at least one piece of test service information and a conversion rule, each piece of test service information comprises fixed test data and configurable test data, performing parameter value configuration on each piece of first target configurable test data to obtain each piece of first configuration test data, determining first target test service information corresponding to each piece of first configuration test data in the conversion information, converting each piece of first configuration test data by using a conversion rule to obtain a first target test vector, and sending the first target test vector to a server; and executing the first target test vector to test and obtain a first test result. Therefore, when the test vector is generated, only the configurable test data needs to be set, and all test information required by testing does not need to be edited in the test vector template, so that a large amount of manpower is saved, and the accuracy and efficiency of the test vector are improved.

Description

Technical Field

[0001] The present application relates to chip testing technology, and in particular to a test vector generation method, apparatus and computing device. Background Art

[0002] Chip testing is the detection of chip or wafer parameters, functions and performance through chip testing equipment. The workflow of chip testing usually includes generating test patterns, loading the test patterns into the test system, and then running the test patterns in the test system to test the chip.

[0003] In the process of implementing the present application, it was found through research that in the related art, when generating a test vector, it is usually necessary to manually edit all the test information required for the test in a test vector template, and then convert the edited test vector template into a chip authentication program (CAP) file, and then manually convert the CAP into a test vector. However, in actual applications, a large number of functional test scenarios are included in the chip test, and there are usually multiple similar test sub-scenarios in these functional test scenarios, and each functional test sub-scenario needs to correspond to a test vector, which requires manual generation of a large number of test vectors, which not only wastes a lot of manpower, but also easily leads to low-level errors when generating test vectors, resulting in poor accuracy of the test vectors. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a test vector generation method, apparatus and computing device.

[0005] One aspect of an embodiment of the present application provides a test vector generation method, which is applied to a chip testing device, including: obtaining conversion information, the conversion information including: pin information, at least one test business information and conversion rules, each test business information in the at least one test business information respectively including fixed test data and configurable test data; when generating a test vector in a first preset mode, configuring parameter values ​​for each first target configurable test data in at least one first target configurable test data to obtain first configuration test data corresponding to each first target configurable test data; determining the first target test business information corresponding to each first configuration test data in the conversion information; in response to receiving a first test instruction, converting each first configuration test data using the conversion rule to obtain a first target test vector; executing the first target test vector and obtaining a first test result.

[0006] Another aspect of an embodiment of the present application provides a test vector generation device, which is applied to a chip testing device, including: a first acquisition module, used to obtain conversion information, the conversion information including: pin information, at least one test business information and conversion rules, each test business information in the at least one test business information respectively including fixed test data and configurable test data; a first configuration module, used to configure parameter values ​​for each first target configurable test data in at least one first target configurable test data when generating a test vector in a first preset mode, so as to obtain first configuration test data corresponding to each first target configurable test data; a first association module, used to determine the first target test business information corresponding to each first configuration test data in the conversion information; a first conversion module, used to convert each first configuration test data using the conversion rule in response to receiving a first test instruction, so as to obtain a first target test vector; a first test module, used to execute the first target test vector and obtain a first test result.

[0007] Another aspect of an embodiment of the present application provides an electronic device, comprising: a memory for storing a computer program; a processor for executing the computer program stored in the memory, and when the computer program is executed, the above-mentioned test vector generation method is implemented.

[0008] According to another aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned test vector generation method is implemented.

[0009] According to another aspect of an embodiment of the present application, a computer program product is provided, comprising computer program instructions, wherein the computer program instructions implement the above-mentioned test vector generation method when executed by a processor.

[0010] The test vector generation method, device and computing device in the embodiment of the present application, the test vector generation method includes: obtaining conversion information, the conversion information includes: pin information, at least one test business information and conversion rules, each test business information in the at least one test business information includes fixed test data and configurable test data respectively, when generating a test vector in the first preset mode, configuring the parameter value of each first target configurable test data to obtain each first configuration test data, and then determining the first target test business information corresponding to each first configuration test data in the conversion information, when receiving the first test instruction, using the conversion rule, converting each first configuration test data to obtain the first target test vector, executing the first target test vector and obtaining the first test result. In the embodiment of the present application, the conversion information provides pin information, configurable test parameters and fixed test parameters, so that when generating a test vector, the user only needs to set the configurable test data, and no longer needs to edit all the test information required for the test in the test vector template, thereby not only saving a lot of manpower, but also improving the accuracy and efficiency of the test vector. At the same time, in the embodiment of the present application, when the first test instruction is executed, the corresponding first target test vector can be automatically converted and generated through the conversion file, without the need for manual conversion, which further improves the efficiency of test vector generation.

[0011] In addition, in an embodiment of the present application, the test vector template is abandoned, and the first target configurable test data provided by the conversion information is used, so that the length of the generated first target test vector can be flexibly set according to needs, avoiding the situation where the set vector length is fixed and cannot meet the test requirements when the test vector template is used to generate the test vector.

[0012] The technical solution of the present application is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0014] The present application can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0015] Figure 1 It is a flowchart of a test vector generation method provided by an exemplary embodiment of the present application.

[0016] Figure 2 It is a flowchart of a test vector generation method provided by another exemplary embodiment of the present application.

[0017] Figure 3 It is a flowchart of step S140 provided by an exemplary embodiment of the present application.

[0018] Figure 4 It is a flowchart of a test vector generation method provided by another exemplary embodiment of the present application.

[0019] Figure 5 It is a flowchart of a test vector generation method provided by another exemplary embodiment of the present application.

[0020] Figure 6 It is a structural block diagram of a test vector generating device provided by an exemplary embodiment of the present disclosure.

[0021] Figure 7 This is a schematic diagram of the structure of an application embodiment of the electronic device of the present application. DETAILED DESCRIPTION

[0022] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present application.

[0023] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present application are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0024] It should also be understood that in the embodiments of the present application, "plurality" may refer to two or more than two, and "at least one" may refer to one, two or more than two.

[0025] It should also be understood that any component, data or structure mentioned in the embodiments of the present application can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0026] In addition, the term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the associated objects before and after are in an "or" relationship.

[0027] It should also be understood that the description of the various embodiments in this application focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0028] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0029] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present application, its application, or uses.

[0030] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0031] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0032] The embodiments of the present application can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above systems, etc.

[0033] Electronic devices such as terminal devices, computer systems, servers, etc. can be described in the general context of computer system executable instructions (such as program modules) executed by computer systems. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0034] In the process of implementing the present application, it is found through research that when performing chip testing, there are often a large number of test sub-scenarios with similar functions in a test scenario, and each test sub-scenario needs to be tested based on the corresponding test vector. For example, in some functional test scenarios of the system-on-chip (SoC), it is necessary to configure the action of the register, and a group of registers needs to correspond to a test vector. There are tens of thousands of groups of registers in the system-on-chip, and the difference between these registers is relatively small, usually only a few bits. At the same time, the configuration of the test vectors of these registers is also relatively fixed (16 or 32-bit vector value). According to the test vector generation method in the prior art, it is necessary to generate tens of thousands of CAP files first, and then convert these CAP files into corresponding test vectors for use. This not only wastes a lot of manpower, but also easily causes low-level errors when generating test vectors, resulting in poor accuracy of the test vectors.

[0035] Figure 1 FIG. 1 is a flow chart of a test vector generation method provided by an exemplary embodiment of the present application. This embodiment can be applied to chip test equipment, such as Figure 1 As shown, the test vector generation method may include the following steps:

[0036] Step S110, obtaining conversion information.

[0037] The chip test equipment is used to test the function and / or performance of the device under test such as the chip. Exemplarily, the chip test equipment may be an integrated circuit automatic tester (Automatic Test Equipment, ATE). The upload interface of the chip test equipment may be used to add the conversion information to the chip test equipment.

[0038] The conversion information can be used to represent the basic rules and information for generating test vectors. For example, the conversion information can include the basic rules for binary conversion. The file format of the conversion information can be, for example, a PAF (Personal Ancestral File) file, and the conversion information supports operations such as writing (Write), reading (Read), and waiting (Idle) on the device under test.

[0039] In one embodiment, the conversion information includes: pin information, at least one test service information and a conversion rule, and each test service information in the at least one test service information includes fixed test data and configurable test data.

[0040] The pin information (Pins) may include the identification of multiple pins, etc. The test service information (Frames) is used to represent the relevant information of the test service of a functional test of a device under test such as a chip or an integrated circuit. Each test service information may include total test data (Datas), and the total test data includes fixed test data and configurable test data (Fields). Fixed test data is used to represent test data that is fixed and cannot be configured in the test service, and configurable test data is used to represent test data that can be configured according to test requirements. Exemplarily, fixed test data and configurable test data can be set according to test requirements, and fixed test data may include, for example, file version and true value waveform, etc., and configurable test data may include, for example, input excitation signal value, etc. Assume that the total test data in the test service information includes 100 rows, 1-5 rows are test data corresponding to the input excitation signal, that is, 1-5 rows are configurable test data, and the remaining rows correspond to the fixed test data of the test service. The conversion rules may include binary conversion rules for fixed test data and configurable test data.

[0041] In one embodiment, a test project of the device under test may be obtained from a chip testing device, and conversion information may be created according to test parameters in the test project, wherein the test project includes an overall test plan for implementing the test of the device under test.

[0042] Step S120, when generating a test vector in the first preset mode, configuring parameter values ​​for each first target configurable test data in at least one first target configurable test data to obtain first configuration test data corresponding to each first target configurable test data.

[0043] Among them, the test vector (Pattern) is used to describe the input / expected vector value of different pins in each cycle. The test vector may include the test information required to test the device under test, which is stored in the test vector in the form of binary code. For example, the test vector may include the input timing waveform and the expected timing waveform in the form of binary code. The chip test equipment will send a series of timing stimuli to the input pins of the device under test according to the input timing waveform. At this time, the output pins of the device under test will output a series of actual timing waveforms. These actual timing waveforms are compared with the expected timing waveforms. If they are the same, the device under test meets its function, otherwise there is a problem with the device under test.

[0044] The configurable test data that needs to be configured in the first preset mode may be referred to as first target configurable test data. The first target configurable test data after parameter value configuration may be determined as first configuration test data corresponding to the first target configurable test data.

[0045] In one embodiment, the configurable test data to be configured can be selected from the conversion information as the first target configurable test data. Before configuring the parameter value of the first target configurable test data, the legality of the conversion information can be verified. Exemplarily, it can be verified whether the pin information and timing information (fixed test data) in the conversion information comply with the regulations in the test project. If they comply, it can be determined that the conversion information is legal, and after determining that the conversion information is legal, the first target configurable test data is configured.

[0046] Step S130: determining the first target test service information corresponding to each first configuration test data in the conversion information.

[0047] The test service information corresponding to the first configuration test data in the conversion information may be referred to as first target test service information.

[0048] In one embodiment, the first target test service information corresponding to each first configuration test data in the conversion information can be customized and determined according to the test requirements. A mapping relationship between each first configuration test data and the corresponding first target test service information can be established.

[0049] After determining the first target test business information corresponding to each first configuration test data in the conversion information, the test order of each first configuration test data can also be adjusted to make the test order of each first configuration test data consistent with the test order of the corresponding first target test business information in the conversion file.

[0050] Step S140 , in response to receiving the first test instruction, convert each first configuration test data using a conversion rule to obtain a first target test vector.

[0051] The first target test vector may include binary codes corresponding to each first configuration test data.

[0052] In one embodiment, when the chip testing device receives the first test instruction, it uses the conversion rules in the conversion information to perform binary conversion on each first configuration test data to obtain the binary code corresponding to each first configuration test data, and the binary code corresponding to each first configuration test data constitutes the first target test vector.

[0053] Step S150, executing a first target test vector and obtaining a first test result.

[0054] The chip testing device may execute a first target test vector for testing to obtain a first test result.

[0055] In an embodiment of the present application, the conversion information provides pin information, configurable test parameters and fixed test parameters, so that when generating a test vector, the user only needs to set the configurable test data, and no longer needs to edit the test information required for all tests in the test vector template, thereby not only saving a lot of manpower, but also improving the accuracy and efficiency of the test vector. At the same time, in an embodiment of the present application, when executing the first test instruction, the corresponding first target test vector can be automatically converted and generated through the conversion file, and no manual operation is required for conversion, which further improves the generation efficiency of the test vector. In addition, in an embodiment of the present application, the test vector template is abandoned, and the first target configurable test data provided by the conversion information is used, so that the length of the generated first target test vector can be flexibly set according to the demand, avoiding the situation where the fixed vector length cannot meet the test requirements when the test vector template is used to generate the test vector.

[0056] Figure 2 FIG. 1 is a flow chart of a test vector generation method provided by another exemplary embodiment of the present application. In some optional implementations, such as Figure 2 As shown, after step S150, the following steps are also included:

[0057] Step S210: for each first configuration test data, using preset code interface mapping information, calling the preset code interface corresponding to the first configuration test data to perform code conversion on the first configuration test data to obtain the test code corresponding to the first configuration test data.

[0058] The test code is used to represent the operation code (Operation Code) executed by the chip test equipment to test the device under test.

[0059] In one embodiment, a plurality of preset code interfaces may be pre-set, and the preset code interfaces are used to convert test data into operation codes. The corresponding preset code interface may be determined according to the type information (Frame Type) of the first target test business information corresponding to the first configuration test data, and the editing information of the data in the first configuration test data. Among them, the type information of the first target test business information may include Write, Read and Idle, etc., wherein Idle indicates the length of time required to wait after each execution of a cycle. The editing information of the data in the first configuration test data includes the value (Value) unit information of the data in the first configuration test data, the chip test mode, the form and the state. The chip test mode includes a multi-chip test mode and a single chip test mode. The form includes a character string and a numerical value. The state includes the completion of the first configuration test data and the start of the next first configuration test data.

[0060] The legality of the first configuration test data may also be verified before code conversion. For example, it may be verified whether the parameter value configuration of the first configuration test data is complete, and whether the name of the first configuration test data is the same as the name of the configurable test data in the first target test service information corresponding to the first configuration test data in the conversion information.

[0061] Exemplarily, each first configuration test data may be converted into code in the following manner:

[0062] Step 1. Identify whether the type corresponding to the first target configurable test data corresponding to the first configuration test data is Idle, and if it is Idle, execute step 2; if it is not Idle, execute step 3;

[0063] Step 2. Identify whether the value in the first configuration test data has a time unit. When the value has a time unit, call the preset code interface Set Wait Time (Value) and add the value to Value. When the value does not have a time unit, call the preset code interface Set Wait Cycle (Value) and add the value to Value, and then execute step 9, wherein Set Wait Time (Value) represents a code interface for setting the waiting time, and Set Wait Cycle (Value) represents a code interface for setting the number of cycles.

[0064] Step 3. Call the preset code interface Field(field name) to add the name of the first target configurable test data to the field name, where Field(field name) represents a code interface for setting the name of the first target configurable test data;

[0065] Step 4. Identify whether the chip test mode of the first configuration test data is a multi-chip test mode (MultiSite), if it is determined to be, execute step 5, if it is determined not to be, execute step 6;

[0066] Step 5. Traverse the values ​​corresponding to the test positions in the first configuration test data, and call Set Value (to Site Bit Sequence (site, value)), and add the test position and its corresponding value to (site, value). SetValue (to Site Bit Sequence) represents a code interface for setting the data of the test position to be executed. The test position includes the pin, and then execute step 7;

[0067] Step 6. Identify whether the value in the first configuration test data is a string. If it is a string, call the preset code interface Set Value (to Site Bit Sequence (site, value)). If not, call the preset code interface Set Value (Value), where Set Value (Value) is a code interface for setting the data of the test location to be executed;

[0068] Step 7. When the mask function (Mask) is enabled in the conversion information and the mask function is also enabled in the first configuration test data, step 8 is executed, otherwise step 9 is executed, wherein the mask function indicates that the value in the first configuration test data needs to be masked (not executed);

[0069] Step 8. When the value in the first configuration test data is a string, the preset code interface Mask (to Bit Sequence Value) is called; when the value in the first configuration test data is not a string, the preset code interface Mask (Value) is called, where Mask (to Bit Sequence Value) and Mask (Value) are both code interfaces for masking values;

[0070] Step 9. Determine whether the state of the first configuration test data is Apply. If yes, call the preset code interface Apply() and then execute step 10. If not, directly execute step 10. When the state of the first configuration test data is Apply, it indicates that the first configuration test data is completed and the next first configuration test data can be started. Apply() indicates a code interface for configuring the state of the first configuration test data.

[0071] Step 10. Perform code conversion based on the above preset code interface to generate User API code (test code corresponding to the first configuration test data).

[0072] Step S220 , updating the test code corresponding to each first configuration test data into the test code corresponding to the test project, so as to update each first configuration test data into the test project.

[0073] Among them, the operation of step S210 is performed on each first configuration test data to obtain the test code corresponding to each first configuration test data, and then the test code corresponding to each first configuration test data is used to replace the corresponding test code in the test project to update each first configuration test data to the test project, so that each first configuration test data can be executed when executing the test project.

[0074] In an embodiment of the present application, a preset code interface is utilized to implement fast and efficient code conversion of first configuration test data, and the test code corresponding to the first configuration test data is updated to the test code corresponding to the test project, so that each first configuration test data can be executed when the test project is executed, thereby avoiding the need to adjust the test project as a whole when debugging the test parameters in the test project, thereby improving the debugging efficiency of the chip test.

[0075] Figure 3 is a flow chart of step S140 provided by an exemplary embodiment of the present application. In some optional implementations, such as Figure 3 As shown, step S140 may include:

[0076] Step S141, use the conversion rules to perform binary conversion on the pin information to obtain the test vector corresponding to the pin information, and for each first configuration test data, use the conversion rules to perform binary conversion on the first configuration test data and the fixed test data in the first target test business information corresponding to the first configuration test data to obtain the test vector corresponding to the first configuration test data.

[0077] In one embodiment, for each first configuration test data, the first configuration test data is binary converted using the conversion rule to obtain a first binary code, and the fixed test data in the first target test business information corresponding to the first configuration test data is binary converted using the conversion rule to obtain a second binary code, and the first binary code and the second binary code of the first configuration test data constitute a test vector corresponding to the first configuration test data.

[0078] Exemplarily, a test vector engine (Pattern Gen) module can also be set in the chip testing device. The test vector engine module can be generated by encapsulating an independent dynamic link library (Dynamic Link Library, DLL). The test vector engine module can be used to call conversion rules to perform binary conversion on the pin information, the first configuration test data and the fixed test data in the first target test business information.

[0079] Step S142: determining a first target test vector based on the test vectors corresponding to each first configuration test data and the test vectors corresponding to the pin information.

[0080] The first target test vector may include a test vector corresponding to each first configuration test data and a test vector corresponding to the pin information.

[0081] In the embodiment of the present application, conversion rules are used to automatically convert the first configuration test data, the fixed test data in the first target test service information, and the binary of the pin information, eliminating the need for manual conversion, thereby improving the efficiency of test vector generation.

[0082] In some optional implementations, step S120 in the embodiment of the present application may further include: determining output pin information corresponding to each first configuration test data.

[0083] The output pin information may include an identifier of a pin for outputting a test result. The output pin information for outputting a first test result of each first configuration test data may be set.

[0084] Correspondingly, step S150 in the embodiment of the present application may further include: obtaining a first test result based on output pin information corresponding to each first configuration test data.

[0085] Exemplarily, the test vector may be generated in the first preset mode in the following manner:

[0086] 1. It can verify the legitimacy of the conversion information and generate a test task when the conversion information is determined to be legal;

[0087] 2. Add each first target configurable test data in the test task;

[0088] 3. Perform vector value completion (corresponding parameter value configuration, SetValue) on each first target configurable test data to obtain corresponding first configuration test data;

[0089] 4. Perform Set Apply setting on each first configuration test data, that is, determine the first target test service information corresponding to each first configuration test data in the conversion information, and perform Set Capture Pin setting, that is, determine the output pin information corresponding to each first configuration test data;

[0090] 5. When executing the test task (receiving the first test instruction), generate the first target test vector based on the conversion information, execute the first target test vector, capture the first test result through the output pin information corresponding to each first configuration test data, and display it.

[0091] In the embodiment of the present application, by setting the output pin information corresponding to each first configuration test data, the first test result can be obtained quickly and efficiently.

[0092] Figure 4 FIG. 1 is a flow chart of a test vector generation method provided by another exemplary embodiment of the present application. In some optional implementations, such as Figure 4As shown, the test vector generation method also includes the following steps:

[0093] Step S310 , when generating a test vector in the second preset mode, loading conversion information into the chip test system.

[0094] Among them, the chip testing equipment includes a chip testing system, the chip testing system includes a testing project, and the chip testing system can run the testing project to perform chip testing on the device under test.

[0095] In one implementation, the conversion information may be loaded into the chip testing system through a user interface (User API Interface) of the chip testing system.

[0096] Step S320 , performing parameter value configuration on each second target configurable test data in the at least one second target configurable test data to obtain second configuration test data corresponding to each second target configurable test data.

[0097] The configurable test data that needs to be configured in the second preset mode may be referred to as second target configurable test data. The second target configurable test data after parameter value configuration may be determined as second configuration test data corresponding to the second target configurable test data.

[0098] In one embodiment, the configurable test data to be configured may be selected from the conversion information as the second target configurable test data. Before configuring the parameter value of the second target configurable test data, the legality of the conversion information may be verified first.

[0099] Step S330: determine the second target test service information corresponding to each second configuration test data in the conversion information.

[0100] The test service information corresponding to the second configuration test data in the conversion information may be referred to as second target test service information.

[0101] In one embodiment, the second target test service information corresponding to each second configuration test data in the conversion information can be customized and determined according to the test requirements. A mapping relationship between each second configuration test data and the corresponding second target test service information can be established.

[0102] Step S340, in response to receiving the second test instruction, based on each second configuration test data corresponding to the second target test business information, each second configuration test data is converted using the conversion information to obtain a second target test vector, and each second configuration test data is updated into the test project.

[0103] The second target test vector may include binary codes corresponding to each second configuration test data.

[0104] In one embodiment, when the chip test system receives an instruction to execute the second test, for each second configuration test data, the second configuration test data is binary converted using a conversion rule to obtain a binary code corresponding to the second configuration test data, and the fixed test data in the second target test business information corresponding to the second configuration test data is binary converted using a conversion rule to obtain a binary code corresponding to the fixed test data, and the binary code corresponding to the second configuration test data and the binary code corresponding to the fixed test data constitute a test vector corresponding to the second configuration test data, and the second target test vector is determined by the test vectors corresponding to each second configuration test data and the test vector corresponding to the pin information. The second target test vector can be updated to the test project through the user interface of the chip test system so that it can be executed when the test project is executed.

[0105] Exemplarily, the test vector engine module may be called through a user interface of the chip test system, and then the conversion rule may be called through the test vector engine module to perform binary conversion on the second configuration test data.

[0106] Step S350, execute the second target test vector and obtain a second test result.

[0107] The chip testing system may execute the second target test vector for testing to obtain a second test result.

[0108] In one embodiment, after configuring the parameter values ​​of each second target configurable test data, the result output identifier corresponding to each second configuration test data can also be determined, and then the output identifier is used as the identifier of the obtained second test result, and the second test result can be read based on the output identifier.

[0109] Exemplarily, the test vector may be generated in the second preset mode in the following manner:

[0110] 1. Load the conversion information into the chip test system through the user interface of the chip test system;

[0111] 2. Verify the legality of the conversion information, and when the conversion information is determined to be legal, add configurable test data for each second target;

[0112] 3. Complete the vector value (corresponding parameter value configuration, SetValue) for each second target configurable test data to obtain the corresponding second configuration test data;

[0113] 4. Perform Set Apply setting for each second configuration test data, i.e., determine the second target test service information corresponding to each second configuration test data in the conversion information, and perform Set Read ID (output identifier) ​​setting, i.e., determine the result output identifier corresponding to each second configuration test data;

[0114] 5. When the second test instruction is received, a second target test vector is generated based on the conversion information, and the second target test vector is executed. The second test result stored in the register is read through Set Read ID (output identifier), and the test ends.

[0115] In an embodiment of the present application, by configuring parameters of the second target configurable test data and converting it using the conversion rules in the conversion information, a corresponding second target test vector is obtained, and the second target test vector is updated to the test project, thereby achieving efficient debugging of the test project.

[0116] Figure 5 FIG. 1 is a flow chart of a test vector generation method provided by another exemplary embodiment of the present application. In some optional implementations, such as Figure 5 As shown, the test vector generation method also includes the following steps:

[0117] Step S410 , in response to monitoring that new test data is added to the test project, a new test vector sequence corresponding to the new test data is obtained.

[0118] Among them, the test vector sequence (Pattern Burst) can include multiple test vectors, and the test vector sequence is the smallest unit of the test business corresponding to the underlying execution test vector. The test vector sequence can be stored in a *.pbl project file, and multiple test vector sequences can be stored in one *.pbl file.

[0119] The new test vector sequence includes test vectors corresponding to the new test data, and the new test data includes each first configuration test data or each second configuration test data. That is, the new test vector sequence includes test vectors corresponding to each first configuration test data or each second configuration test data.

[0120] Exemplarily, new test data may be run to generate a new test vector sequence corresponding to the new test data based on the conversion information.

[0121] Step S420, obtaining each current test vector sequence and each historical test vector sequence corresponding to the test project.

[0122] Among them, each current test vector sequence includes at least one current test vector corresponding to the test project, and each historical test vector sequence includes at least one historical test vector corresponding to the test project.

[0123] In one implementation, a test project may include multiple test services, each test service may correspond to at least one test vector sequence, and the test vector sequences corresponding to the test services constitute the test vector sequence corresponding to the test project.

[0124] The test vector sequence corresponding to the most recently executed test project is called the current test vector sequence, and the test vector sequence corresponding to the test project run by the historical debugging test project is called the historical test vector sequence.

[0125] Step S430 , in response to the fact that there is no test vector sequence identical to the new test vector sequence in each current test vector sequence and each historical test vector sequence, the new test vector sequence is added to each current test vector sequence.

[0126] In one embodiment, the new test vector sequence can be compared with each current test vector sequence and each historical test vector sequence respectively to determine whether there is a test vector sequence that is identical to the new test vector sequence in each current test vector sequence and each historical test vector sequence. When there is no test vector sequence that is identical to the new test vector sequence in either the current test vector sequence or the historical test vector sequence, the new test vector sequence is added to each current test vector sequence.

[0127] In some optional implementations, the test vector sequence corresponds to a unique vector identifier, the vector identifier includes prefix information and information summary, the prefix information includes the business function corresponding to the test vector sequence, and the information summary is generated by encrypting the configurable test data corresponding to the test vector sequence.

[0128] The service function corresponding to each test vector sequence is the service function corresponding to the test service corresponding to the test vector sequence, the service function indicates the function of the device under test to be tested by the test service, and the configurable test data corresponding to the test vector sequence is the configurable test data in the test service corresponding to the test vector sequence. The configurable test parameters can be encrypted using an encryption algorithm such as Message Digest Algorithm 5 (MD5) to obtain an MD5 value, and the MD5 is used as the information digest.

[0129] Correspondingly, in an embodiment of the present application, in response to the fact that the vector identifiers of each current test vector sequence and the vector identifiers of each historical test vector sequence are different from the vector identifier of the new test vector sequence, it is determined that there is no test vector sequence that is identical to the new test vector sequence in either the current test vector sequence or the historical test vector sequence.

[0130] In one embodiment, when each current test vector sequence has a test vector sequence that is identical to a new test vector sequence, the new test vector sequence is updated to a historical test vector sequence.

[0131] Step S440, in response to the fact that there is no test vector sequence identical to the new test vector sequence in each current test vector sequence, and there is a test vector sequence identical to the new test vector sequence in each historical test vector sequence, updating the historical test vector sequence identical to the new test vector sequence into each current test vector sequence.

[0132] Among them, when the vector identifiers of each current test vector sequence are different from the vector identifier of the new test vector sequence, and there is a vector identifier among the vector identifiers of each historical test vector sequence that is the same as the vector identifier of the new test vector sequence, the historical test vector sequence corresponding to the same vector identifier is updated to each current test vector sequence.

[0133] It should be noted that in the embodiment of the present application, there is no execution order between step S430 and step S440.

[0134] In an embodiment of the present application, by determining whether the current test vector sequence includes a test vector sequence that is identical to a new test vector sequence, it is avoided that the new test vector sequence is directly added to the test vector sequence of the test project, resulting in a large number of repeated test vector sequences in the test vector sequence of the test project, thereby facilitating technical personnel to debug the test project.

[0135] In some optional embodiments, the test vector generation method in the embodiment of the present application also includes: in response to the presence of a test vector sequence with the same business function as that corresponding to the new test vector sequence in each current test vector sequence, updating the current test vector sequence corresponding to the same business function as the new test vector sequence to a historical test vector sequence, and updating the new test vector sequence to each current test vector sequence.

[0136] The service function corresponding to each current test vector sequence may be compared with the service function corresponding to the new test vector sequence to determine whether there is a current test vector sequence in each current test vector sequence with the same service function as that corresponding to the new test vector sequence.

[0137] In some optional embodiments, in response to the prefix information of the vector identifier of any current test vector sequence being the same as the prefix information of the vector identifier of a new test vector sequence, and the information digest in the vector identifier of any current test vector sequence being different from the information digest in the vector identifier of the new test vector sequence, it is determined that the business function corresponding to any current test vector sequence is the same as the business function corresponding to the new test vector sequence.

[0138] Exemplarily, each current test vector sequence may be stored in a Pa.pbl file, and each historical test vector sequence may be stored in a Paback.pbl file.

[0139] Check whether there is a test vector sequence with the same vector identifier as the new test vector sequence in the Pa.pbl file. If yes, terminate the operation. If no, check whether there is a test vector sequence with the same vector identifier as the new test vector sequence in the Paback.pbl file. If yes, add the historical test vector sequence with the same vector identifier as the new test vector sequence in the Paback.pbl file to the Pa.pbl file.

[0140] Check whether there is a current test vector sequence in the Pa.pbl file whose only prefix information is the same as the prefix information of the new test vector sequence. If so, update the same current test vector sequence to a historical test vector sequence and add it to the Paback.pbl file, and then add the new test vector sequence to the Pa.pbl file; if not, add the new test vector sequence to the Pa.pbl file.

[0141] In an embodiment of the present application, a new test vector sequence replaces a current test vector sequence with the same service function in the current test vector sequence, thereby avoiding the existence of a large number of test vector sequences with repeated service functions in the current test vector sequence.

[0142] Figure 6 is a structural block diagram of a test vector generation device provided by an exemplary embodiment of the present disclosure. The test vector generation device is applied to a chip test device, such as Figure 6 As shown, the test vector generating device comprises:

[0143] A first acquisition module 510 is used to acquire conversion information, where the conversion information includes: pin information, at least one test service information and a conversion rule, where each test service information in the at least one test service information includes fixed test data and configurable test data;

[0144] A first configuration module 520 is used to configure parameter values ​​for each first target configurable test data in at least one first target configurable test data when generating a test vector in the first preset mode, so as to obtain first configuration test data corresponding to each first target configurable test data;

[0145] A first association module 530 is used to determine the first target test service information corresponding to each first configuration test data in the conversion information;

[0146] A first conversion module 540 is used for converting each first configuration test data using the conversion rule in response to receiving the first test instruction to obtain a first target test vector;

[0147] The first test module 550 is used to execute the first target test vector and obtain a first test result.

[0148] In some optional implementations, the test vector generating device further includes:

[0149] A code conversion module, configured to, for each of the first configuration test data, use preset code interface mapping information to call a preset code interface corresponding to the first configuration test data to perform code conversion on the first configuration test data, so as to obtain a test code corresponding to the first configuration test data;

[0150] The code updating module is used to update the test code corresponding to each of the first configuration test data into the test code corresponding to the test project, so as to update each of the first configuration test data into the test project.

[0151] In some optional embodiments, the first conversion module 540 is specifically used to perform binary conversion on the pin information using the conversion rule to obtain a test vector corresponding to the pin information, and for each of the first configuration test data, perform binary conversion on the first configuration test data and the fixed test data in the first target test business information corresponding to the first configuration test data using the conversion rule to obtain a test vector corresponding to the first configuration test data; determine the first target test vector based on the test vectors corresponding to the each of the first configuration test data and the test vector corresponding to the pin information.

[0152] In some optional implementations, the test vector generating device further includes:

[0153] An output information setting module, used to determine the output pin information corresponding to each first configuration test data;

[0154] The obtaining of the first test result is further used to: obtain the first test result based on the output pin information corresponding to each of the first configuration test data.

[0155] In some optional implementations, the chip testing device includes a chip testing system, and the test vector generating device further includes:

[0156] A loading module, used for loading the conversion information into the chip testing system when generating a test vector in a second preset mode;

[0157] A second configuration module, configured to configure parameter values ​​for each second target configurable test data in at least one second target configurable test data, to obtain second configuration test data corresponding to each second target configurable test data;

[0158] A second association module, used to determine the second target test service information corresponding to each second configuration test data in the conversion information;

[0159] A second conversion module is used for, in response to receiving a second test instruction, based on the second target test service information corresponding to each of the second configuration test data, converting each of the second configuration test data using the conversion information to obtain a second target test vector, and updating each of the second configuration test data into the test project;

[0160] The second test module is used to execute the second target test vector and obtain a second test result.

[0161] In some optional implementations, the test vector generating device further includes:

[0162] A second acquisition module, configured to acquire, in response to monitoring that new test data is added to the test project, a new test vector sequence corresponding to the new test data, wherein the new test vector sequence includes a test vector corresponding to the new test data, and the new test data includes each of the first configuration test data or each of the second configuration test data;

[0163] A third acquisition module is used to acquire each current test vector sequence and each historical test vector sequence corresponding to the test project, each current test vector sequence includes at least one current test vector corresponding to the test project, and each historical test vector sequence includes at least one historical test vector corresponding to the test project;

[0164] A first judgment module, configured to add the new test vector sequence to each of the current test vector sequences in response to the fact that there is no test vector sequence identical to the new test vector sequence in each of the current test vector sequences and each of the historical test vector sequences;

[0165] A second judgment module is used to update the historical test vector sequence that is identical to the new test vector sequence into each of the current test vector sequences in response to the presence of a test vector sequence that is identical to the new test vector sequence in each of the historical test vector sequences.

[0166] In some optional implementations, the test vector generating device further includes:

[0167] A third judgment module is used to update the current test vector sequence corresponding to the same business function as the new test vector sequence into the historical test vector sequence in response to the presence of a test vector sequence with the same business function as the new test vector sequence in each current test vector sequence, and to update the new test vector sequence to each current test vector sequence.

[0168] In some optional implementations, the test vector sequence corresponds to a unique vector identifier, the vector identifier includes prefix information and an information digest, the prefix information includes a service function corresponding to the test vector sequence, and the information digest is generated by encrypting configurable test data corresponding to the test vector sequence;

[0169] The test vector generating device also includes:

[0170] A fourth judgment module is used to determine that there is no test vector sequence identical to the new test vector sequence in either the current test vector sequence or the historical test vector sequence in response to the vector identifiers of the current test vector sequences and the vector identifiers of the historical test vector sequences being different from the vector identifier of the new test vector sequence;

[0171] A fourth judgment module is used to determine that the business function corresponding to any current test vector sequence is the same as the business function corresponding to the new test vector sequence in response to the prefix information of the vector identifier of any current test vector sequence being the same as the prefix information of the vector identifier of the new test vector sequence, and the information summary in the vector identifier of any current test vector sequence is different from the information summary in the vector identifier of the new test vector sequence.

[0172] The test vector generation device of the embodiment of the present disclosure corresponds to the embodiment of the test vector generation method of the present disclosure, and the relevant contents can be referenced to each other and will not be repeated here.

[0173] The beneficial technical effects corresponding to the exemplary embodiments of the test vector generation device of the disclosed embodiments can be found in the corresponding beneficial technical effects of the above-mentioned corresponding exemplary method part, which will not be repeated here.

[0174] In addition, an embodiment of the present disclosure further provides an electronic device, including:

[0175] Memory for storing computer programs;

[0176] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the test vector generation method described in any of the above embodiments of the present disclosure is implemented.

[0177] Figure 7This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. Figure 7 The electronic device according to the embodiment of the present disclosure is described. The electronic device may be any one or both of the first device and the second device, or a stand-alone device independent of them, and the stand-alone device may communicate with the first device and the second device to receive the collected input signals from them.

[0178] like Figure 7 As shown, the electronic device includes one or more processors and memory.

[0179] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0180] The memory may include one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may execute the program instructions to implement the test vector generation method of the various embodiments of the present disclosure described above and / or other desired functions.

[0181] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0182] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0183] The output device can output various information to the outside, including the determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0184] Of course, to simplify, Figure 7 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0185] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps in the test vector generation method according to various embodiments of the present disclosure described in the above part of this specification.

[0186] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0187] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium on which computer program instructions are stored. When the computer program instructions are executed by a processor, the processor executes the steps of the test vector generation method according to various embodiments of the present disclosure described in the above part of this specification.

[0188] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0189] A person of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, etc., various media that can store program codes.

[0190] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0191] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0192] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0193] The method and apparatus of the present disclosure may be implemented in many ways. For example, the method and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0194] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0195] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0196] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A test vector generation method, applied to a chip test device, characterized in that: include: Acquire conversion information, the conversion information including: pin information, at least one test service information and conversion rules, each test service information in the at least one test service information including fixed test data and configurable test data; When generating a test vector in the first preset mode, configuring a parameter value for each first target configurable test data in at least one first target configurable test data to obtain first configuration test data corresponding to each first target configurable test data; Determine the first target test service information corresponding to each first configuration test data in the conversion information; In response to receiving the first test instruction, convert each first configuration test data using the conversion rule to obtain a first target test vector; Execute the first target test vector and obtain a first test result.

2. The method according to claim 1, characterized in that After obtaining the first test result, the method further includes: For each of the first configuration test data, using the preset code interface mapping information, calling the preset code interface corresponding to the first configuration test data to perform code conversion on the first configuration test data, and obtaining the test code corresponding to the first configuration test data; The test codes corresponding to the first configuration test data are updated into the test codes corresponding to the test project, so as to update the first configuration test data into the test project.

3. The method according to claim 1 or 2, characterized in that: The converting each first configuration test data by using the conversion rule to obtain a first target test vector includes: Using the conversion rule to perform binary conversion on the pin information to obtain a test vector corresponding to the pin information, and for each of the first configuration test data, using the conversion rule to perform binary conversion on the first configuration test data and fixed test data in the first target test service information corresponding to the first configuration test data to obtain a test vector corresponding to the first configuration test data; The first target test vector is determined by the test vectors corresponding to the first configuration test data and the test vectors corresponding to the pin information.

4. The method according to any one of claims 1 to 3, characterized in that: After configuring the parameter value of each first target configurable test data in the at least one first target configurable test data, the method further includes: Determine the output pin information corresponding to each first configuration test data; The obtaining of the first test result comprises: The first test result is obtained based on the output pin information corresponding to each first configuration test data.

5. The method according to any one of claims 1 to 4, characterized in that: The chip testing device includes a chip testing system, and the method further includes: When generating a test vector in a second preset mode, loading the conversion information into the chip testing system; Perform parameter value configuration on each second target configurable test data in the at least one second target configurable test data to obtain second configuration test data corresponding to each second target configurable test data; Determine the second target test service information corresponding to each second configuration test data in the conversion information; In response to receiving the second test instruction, based on the second target test service information corresponding to each of the second configuration test data, each of the second configuration test data is converted using the conversion information to obtain a second target test vector, and each of the second configuration test data is updated into the test project; Execute the second target test vector and obtain a second test result.

6. The method according to claim 5, characterized in that Also includes: In response to monitoring that new test data is added to the test project, a new test vector sequence corresponding to the new test data is acquired, the new test vector sequence includes a test vector corresponding to the new test data, and the new test data includes each of the first configuration test data or each of the second configuration test data; Acquire each current test vector sequence and each historical test vector sequence corresponding to the test project, wherein each current test vector sequence includes at least one current test vector corresponding to the test project, and each historical test vector sequence includes at least one historical test vector corresponding to the test project; In response to the fact that there is no test vector sequence identical to the new test vector sequence in either the current test vector sequences or the historical test vector sequences, adding the new test vector sequence to the current test vector sequences; In response to the fact that there does not exist a test vector sequence identical to the new test vector sequence in the current test vector sequences, and there exists a test vector sequence identical to the new test vector sequence in the historical test vector sequences, the historical test vector sequence identical to the new test vector sequence is updated to the current test vector sequences.

7. The method according to claim 6, characterized in that Also includes: In response to the presence of a test vector sequence with the same business function as that corresponding to the new test vector sequence in each of the current test vector sequences, the current test vector sequence corresponding to the same business function as the new test vector sequence is updated into the historical test vector sequence, and the new test vector sequence is updated into each of the current test vector sequences.

8. The method according to claim 7, characterized in that The test vector sequence corresponds to a unique vector identifier, the vector identifier includes prefix information and information summary, the prefix information includes the service function corresponding to the test vector sequence, and the information summary is generated by encrypting the configurable test data corresponding to the test vector sequence; The method further comprises: In response to the vector identifiers of the current test vector sequences and the vector identifiers of the historical test vector sequences being different from the vector identifier of the new test vector sequence, determining that there is no test vector sequence identical to the new test vector sequence in either the current test vector sequences or the historical test vector sequences; In response to the fact that the prefix information of the vector identifier of any current test vector sequence is the same as the prefix information of the vector identifier of the new test vector sequence, and the information summary in the vector identifier of any current test vector sequence is different from the information summary in the vector identifier of the new test vector sequence, it is determined that the business function corresponding to any current test vector sequence is the same as the business function corresponding to the new test vector sequence.

9. A test vector generation device, applied to a chip test device, characterized in that: include: A first acquisition module is used to acquire conversion information, wherein the conversion information includes: pin information, at least one test service information and a conversion rule, wherein each test service information in the at least one test service information includes fixed test data and configurable test data; A first configuration module is used to configure parameter values ​​for each first target configurable test data in at least one first target configurable test data when generating a test vector in a first preset mode, so as to obtain first configuration test data respectively corresponding to each first target configurable test data; A first association module, used to determine the first target test service information corresponding to each first configuration test data in the conversion information; A first conversion module, configured to convert each first configuration test data using the conversion rule in response to receiving a first test instruction to obtain a first target test vector; The first test module is used to execute the first target test vector and obtain a first test result.

10. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is used to execute a computer program stored in the memory, and when the computer program is executed, the test vector generation method described in any one of claims 1 to 8 is implemented.

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