Reset circuit, control method and electronic equipment thereof

Abstract

The invention discloses a reset circuit, a control method and electronic equipment thereof, the reset circuit comprises a controller and a logic gate circuit combination, and the controller comprises a timer circuit, a first processor, a second processor and a chip. And the logic gate circuit combination is used for generating reset signals through combinational logic control according to the received timer circuit, the first processor, the second processor and external control signals, and outputting the reset signals to the first processor and the second processor respectively. The external control signals comprise a ZLRST1 # signal and a ZLFRSTEN # signal, so that reset control among the timer circuit, the first processor and the second processor is achieved, and the first processor and the second processor can be reset independently or simultaneously. The circuit is simple in design, can flexibly solve the problem of asynchronous reset or poor reliability among core devices, reduces the power consumption, improves the reliability, and can meet the use requirements of medium and long-term power-up and high-performance spaceborne computers.

Description

Technical Field

[0001] The present application relates to the field of satellite-borne computer systems, and in particular to a reset circuit, a control method and electronic equipment thereof. Background Art

[0002] In the on-board controller (OBC) system, core components such as processors, field-programmable gate arrays (FPGAs) and memories are easily affected by high-energy particles in the space environment, causing changes in storage content, which in turn leads to serious consequences such as software anomalies, program out of control and system disorder. To solve this problem, the existing design uses a "watchdog" and reset circuit for monitoring and correction.

[0003] However, the existing design processors have independent power-on / watchdog reset circuits, and the FPGA has a separate power-on reset circuit. The resets of the core components are not synchronized or have poor reliability. In particular, when a single-particle flip occurs in the FPGA on orbit, it needs to be powered on again to resolve the problem, resulting in frequent power on and off of the equipment, increased power consumption and heat dissipation, and failure to meet the needs of medium- and long-term power supply and high-performance onboard computers.

[0004] Therefore, a new reset circuit design is urgently needed to improve the stability and reliability of the onboard computer. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a reset circuit, a control method and an electronic device thereof, which are used to solve the problem mentioned in the background technology that the reset between the core components is not synchronized or the reliability is poor, and when a single particle flip occurs on the FPGA in orbit, it needs to be powered on again, resulting in frequent power on and off of the equipment, increasing power consumption and heat consumption, and failing to meet the needs of medium- and long-term power supply and high-performance onboard computers.

[0006] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution: In a first aspect, a reset circuit is provided, comprising a controller and a logic gate circuit combination; The controller includes a timer circuit, a first processor, a second processor and a chip; The PFI pin of the timer circuit is used to receive an external control signal, the WDI pin of the timer circuit is connected to the GPIO1 output terminal of the first processor, and the RST pin of the timer circuit is connected to the RST# pin of the first processor, and is used to output a power-on reset signal RST# according to the input GPIO1 signal; The GPI02 pin of the first processor is connected to the logic gate circuit combination to output a GPI02 signal; The output end of the second processor is respectively connected to the first processor and the logic gate circuit combination for outputting a STATUS signal; The chip is connected to the second processor, and the input end of the chip is connected to the logic gate circuit combination; The logic gate circuit combination is used to generate a reset signal through combinational logic control according to receiving the timer circuit, the first processor, the second processor and the external control signal, and output it to the first processor and the second processor respectively; The external control signal includes a ZL_RST# signal and a ZL_FRST_EN# signal to implement reset control among the timer circuit, the first processor, and the second processor, so that the first processor and the second processor can be reset individually or simultaneously.

[0007] In combination with the first aspect, in a possible implementation manner, the logic gate circuit combination includes a first OR gate, a second OR gate, a first AND gate, and a second AND gate; The two input ends of the first OR gate are respectively connected to the RST pin of the timer circuit and the ZL_FRST_EN# signal end, and are used to output the RS_RST# signal according to the input RST# signal and the ZL_FRST_EN# signal, and input the RS_RST# signal to the chip to trigger the refresh configuration of the chip; The two input ends of the first AND gate are respectively connected to the output end of the STATUS signal of the second processor and the output end of the first OR gate, and are used to output a FRST_EN1 signal according to the input STATUS signal and the RS_RST# signal; The two input terminals of the second OR gate are respectively connected to the GPIO2 output terminal and the ZL_FRST_EN# signal terminal of the first processor, and are used to output the FRST_EN2 signal according to the GPIO2 signal output by the first processor and the ZL_FRST_EN# signal; The two input ends of the second AND gate are respectively connected to the output end of the first AND gate and the output end of the second OR gate, and are used to output the F_RST# signal according to the output FRST_EN1 signal and the FRST_EN2 signal, and transmit the F_RST# signal to the second processor.

[0008] In combination with the first aspect, in a possible implementation, when the input ZL_RST# signal and the ZL_FRST_EN# signal are both at a low level, the reset circuit is in a reset state and enters a low power consumption mode; When the input ZL_RST# signal is at a low level and the ZL_FRST_EN# signal is at a high level, the first processor is in a reset state, the second processor is in a normal working mode, and the reset circuit enters a local low power consumption mode; When the input ZL_RST# signal is a low pulse signal and the ZL_FRST_EN# signal is at a high level, the first processor is reset and the second processor maintains a normal working mode; When the input ZL_RST# signal is a high level signal and the ZL_FRST_EN# signal is a low level signal, the second processor is reset, and the first processor maintains normal operation or the initialization state after reset; When the input ZL_RST# signal is a low pulse signal and the ZL_FRST_EN# signal is also at a low level, the entire system is reset and the reset circuit is reinitialized.

[0009] In combination with the first aspect, in a possible implementation manner, the logic gate circuit combination further includes a third OR gate and a third AND gate; The input end of the third OR gate is connected to the WDO pin of the timer circuit, and is used to disable the timer circuit according to the input DOG_DISABLE signal; The two input ends of the third AND gate are respectively connected to the output end of the third OR gate and the PFO pin of the timer circuit, and the output end of the third AND gate is connected to the MR pin of the timer circuit.

[0010] In combination with the first aspect, in a possible implementation, the first processor is configured to periodically output a high-low varying GPIO1 signal to a WDI pin of the timer circuit within a time interval not exceeding 800 milliseconds.

[0011] In a second aspect, a control method of the reset circuit as described above is provided, comprising the following steps: S1: After power-on, the timer circuit is controlled to output a power-on reset signal RST#; S2: The first processor starts to run after the power-on reset is completed, and periodically outputs a high-low changing GPI01 signal to the WDI pin of the timer circuit within a preset time to maintain the normal operation of the timer circuit; S3: the logic gate circuit combination generates a reset signal through combinational logic control according to the RST# signal of the first processor, the STATUS signal of the second processor, the ZL_RST# signal and the ZL_FRST_EN# signal; S4: outputting the generated reset signal to the first processor and the second processor respectively, so as to achieve individual or simultaneous resetting of the first processor and the second processor; S5: According to different combinations of the ZL_RST# signal and the ZL_FRST_EN# signal, the reset circuit is controlled to enter a low power consumption mode, a partial low power consumption mode, the first processor is reset, the second processor is reset, or the entire reset circuit is reset.

[0012] In conjunction with the second aspect, in a possible implementation, the method further includes: The program loading status of the second processor is detected, and when the loading of the second processor is completed, a control signal is generated by combining the logic gate circuits to complete the resetting of the second processor.

[0013] In combination with the second aspect, in a possible implementation manner, reset control of the first processor or the second processor is implemented by changing the level states of the input ZL_RST# signal and the ZL_FRST_EN# signal.

[0014] In combination with the second aspect, in a possible implementation, the disabling and enabling of the timer circuit is controlled according to the DOG_DISABLE signal, and the reset operation of the timer circuit is implemented through the MR pin of the timer circuit, thereby enhancing the stability and reliability of the reset circuit.

[0015] According to a third aspect, an electronic device is provided, comprising the aforementioned reset circuit, wherein the electronic device is a space embedded computer.

[0016] Compared with the prior art, this application has the following beneficial effects: A reset circuit provided by the present application realizes flexible reset control of a first processor and a second processor through a combinational logic operation of an external control signal and a logic gate circuit. The first processor or the second processor can be reset individually, or the first processor and the second processor can be reset simultaneously. The timer circuit can monitor the operating status of the first processor. If the first processor becomes abnormal or stops working, the timer circuit can trigger a reset operation to ensure the reliability of the reset circuit. The design is simple, and the problem of reset asynchronism between core components can be flexibly solved, thereby reducing power consumption, improving reliability, and meeting the requirements of medium- and long-term power-on and high-performance onboard computers.

[0017] In a possible implementation, multiple controls on chip refresh configuration are implemented through a combination of logic gate circuits, which improves the stability of the reset circuit and avoids the instability caused by a single signal abnormality; at the same time, the flexibility of the reset circuit is enhanced, and the refresh can be flexibly triggered according to the processor state and external signals; compared with traditional complex circuits, the present invention simplifies the design and reduces the cost. In addition, by introducing the ZL_FRST_EN# signal, the reset circuit's ability to respond quickly to faults is improved, ensuring that the refresh operation will not cause faults.

[0018] In one possible implementation, by introducing two control signals, ZL_RST# and ZL_FRST_EN#, fine control of the reset circuit working state and power consumption mode is achieved, thereby improving the flexibility, energy efficiency, stability and reliability of the system, while simplifying the design and maintenance of the circuit.

[0019] In a possible implementation, by introducing the DOG_DISABLE signal and a corresponding logic gate circuit combination, fine control of the reset circuit is achieved, the flexibility, reliability and energy efficiency of the reset circuit are improved, and the design and maintenance of the circuit are simplified.

[0020] In a possible implementation, the first processor periodically outputs a high-low varying GPIO1 signal to the WDI pin of the timer circuit, thereby realizing an efficient and reliable reset circuit design solution. This solution not only improves the stability and reliability of the reset circuit, but also simplifies the circuit design and reduces the cost.

[0021] The present application provides a reset circuit control method, which realizes stable, reliable and flexible operation of the reset circuit through an efficient reset circuit control method. The method not only improves the stability and flexibility of the reset circuit, but also reduces power consumption and reset circuit design cost.

[0022] In a possible implementation, by adding detection of the second processor program loading state and reset control, the stability and reliability of the reset circuit are further improved. This step not only simplifies the debugging and maintenance process of the reset circuit, but also improves the startup efficiency of the reset circuit.

[0023] In one possible implementation, by inputting and changing the level states of the ZL_RST# signal and the ZL_FRST_EN# signal, the first processor and the second processor can be reset simultaneously or individually, and the reset blocking of non-task devices can be achieved, thereby enabling the reset circuit to autonomously switch to a low-power mode, reducing resource overhead and improving the reliability of the reset circuit.

[0024] In one possible implementation, by controlling the disabling and enabling of the timer circuit according to the DOG_DISABLE signal and implementing the reset operation through the MR pin of the timer circuit, the stability and reliability of the reset circuit are further enhanced, the control logic of the reset circuit is simplified, and the flexibility of the reset circuit is improved.

[0025] It can be understood that any of the control methods and electronic devices provided above for the reset circuit all include technical features corresponding to the reset circuit. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the reset circuit provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the overall structure of a reset circuit provided in an embodiment of the present application.

[0027] Reference numerals in the figure: 1, controller; 11, timer circuit; 12, first processor; 13, second processor; 14, chip; 2, logic gate circuit combination; 21, first OR gate; 22, second OR gate; 23, first AND gate; 24, second AND gate; 25, third OR gate; 26, third AND gate. DETAILED DESCRIPTION

[0028] The specific implementation of the embodiment of the present application is further described in detail below with reference to the accompanying drawings.

[0029] like Figure 1 An embodiment of the present application provides a reset circuit, which may include a controller 1 and a logic gate circuit combination 2.

[0030] The controller 1 may further include a timer circuit 11 , a first processor 12 , a second processor 13 , and a chip 14 external control signal.

[0031] External Control Signal The PFI pin of the timer circuit 11 is used to receive an external control signal.

[0032] The external control signal may include a ZL_RST# signal and a ZL_FRST_EN# signal.

[0033] Specifically, the timer circuit 11 is used to receive a ZL_RST# signal.

[0034] The ZL_RST# signal is used to trigger the reset operation of the entire reset circuit, and the ZL_FRST_EN# signal is used to control whether the first processor 12 is allowed to be reset.

[0035] The WDI pin of the timer circuit 11 is connected to the GPI01 output terminal of the first processor 12, and is used to receive the GPI01 signal output by the first processor 12. The RST pin of the timer circuit 11 is connected to the RST# pin of the first processor 12, and is used to output a power-on reset signal RST#.

[0036] Optionally, the timer circuit 11 may be a watchdog circuit.

[0037] The GPI02 pin of the first processor 12 is connected to the logic gate circuit combination 2, and is used to output the GPI02 signal to the logic gate circuit combination 2. The RST# pin of the first processor 12 is connected to the RST pin of the timer circuit 11, and is used to receive the power-on reset signal RST# output by the timer circuit 11. After the upper reset is completed, the first processor 12 starts running the program and changes the GPI02 signal between high and low.

[0038] Optionally, the first processor 12 may be a processor.

[0039] The output end of the second processor 13 is respectively connected to the first processor 12 and the logic gate circuit combination 2 for outputting a STATUS signal. The first processor 12 and the second processor 13 are connected via EMIF and SRIO.

[0040] Optionally, the second processor 13 may be an FPGA.

[0041] The chip 14 is connected to the second processor 13 via a SELECTMAP port, and an input end of the chip 14 is connected to the logic gate circuit combination 2 for refreshing the configuration chip 14 .

[0042] The logic gate circuit combination 2 receives signals from the timer circuit 11, the first processor 12, the second processor 13 and the external control signal. A reset signal is generated through combinational logic control and output to the first processor 12 and the second processor 13 respectively. When the ZL_RST# signal in the external control signal is triggered, the logic gate circuit combination 2 generates a global reset signal and resets the first processor 12 and the second processor 13 at the same time.

[0043] When the ZL_FRST_EN# signal in the external control signal is activated, the logic gate circuit combination 2 can selectively reset the first processor 12 according to the state of the first processor 12 or the second processor 13 .

[0044] The logic gate circuit combination 2 can also monitor the operating state of the first processor 12 according to the timer circuit 11 and trigger a reset operation when necessary.

[0045] In the embodiment of the present application, flexible reset control of the first processor 12 and the second processor 13 is achieved through the combinational logic operation of the external control signal and the logic gate circuit combination 2. The first processor 12 or the second processor 13 can be reset individually, or the first processor 12 and the second processor 13 can be reset simultaneously.

[0046] At the same time, the operating state of the first processor 12 can be monitored by the timer circuit 11. If the first processor 12 becomes abnormal or stops working, the timer circuit 11 can initiate a reset operation to ensure the reliability of the reset circuit.

[0047] In addition, the system design is simple and can flexibly solve the problem of reset asynchrony among core components, reduce the long-term power consumption of the reset circuit, improve reliability, and meet the needs of medium- and long-term power supply and high-performance onboard computers.

[0048] In a possible embodiment, the logic gate circuit combination 2 may include a first OR gate 21 , a second OR gate 22 , a first AND gate 23 , and a second AND gate 24 .

[0049] The two input terminals of the first OR gate 21 are respectively connected to the RST pin and the ZL_FRST_EN# signal terminal of the timer circuit 11, and are used to output the RS_RST# signal according to the input RST# signal and the ZL_FRST_EN# signal, and input the RS_RST# signal to the chip 14 to trigger the refresh configuration of the chip 14.

[0050] Specifically, when either the RST signal or the ZL_FRST_EN# signal is at a high level, the first OR gate 21 will output the RS_RST# signal, which is then input to the chip 14 to trigger the refresh configuration process of the chip 14 .

[0051] The two input terminals of the first AND gate 23 are respectively connected to the STATUS signal output terminal of the second processor 13 and the output terminal of the first OR gate 21, and are used to output the FRST_EN1 signal according to the input STATUS signal and the RS_RST# signal.

[0052] Specifically, when the STATUS signal and the RS_RST# signal are both at high level, the first AND gate 23 will output the FRST_EN1 signal. This design ensures that the refresh enable signal is enabled only under certain conditions.

[0053] The two input terminals of the second OR gate 22 are respectively connected to the GPIO2 output terminal of the first processor 12 and the ZL_FRST_EN# signal terminal, and are used to output the FRST_EN2 signal according to the GPIO2 signal and the ZL_FRST_EN# signal output by the first processor 12.

[0054] Specifically, when either the GPIO2 signal or the ZL_FRST_EN# signal is at a high level, the second OR gate 22 will output the FRST_EN2 signal.

[0055] The two input ends of the second AND gate 24 are respectively connected to the output end of the first AND gate 23 and the output end of the second OR gate 22 , and are used to output the F_RST# signal according to the output FRST_EN1 signal and the FRST_EN2 signal, and transmit the F_RST# signal to the second processor 13 .

[0056] Specifically, only when the FRST_EN1 signal and the FRST_EN2 signal are both at high level, the second AND gate 24 will output the F_RST# signal. The F_RST# signal is then transmitted to the second processor 13 to trigger the second processor 13 to perform a reset operation.

[0057] In the embodiment of the present application, through the logic gate circuit combination 2, multiple controls on the refresh configuration of the chip 14 are realized, the stability of the reset circuit is improved, and the instability problem caused by a single signal abnormality is avoided; at the same time, the flexibility of the reset circuit is enhanced, and the refresh can be flexibly triggered according to the processor state and external signals; compared with the traditional complex circuit, the present invention simplifies the design and reduces the cost. In addition, by introducing the ZL_FRST_EN# signal, the ability to respond quickly to faults is improved to ensure that the refresh operation will not cause faults.

[0058] In a possible embodiment, when the input ZL_RST# signal and ZL_FRST_EN# signal are both at low level, the entire reset circuit is in a reset state and enters a low power consumption mode. At this time, both processors stop working and the reset circuit enters a low power consumption mode to save energy.

[0059] When the input ZL_RST# signal is at a low level and the ZL_FRST_EN# signal is at a high level, the first processor 12 is in a reset state, the second processor 13 is in a normal working mode, and the reset circuit enters a local low power consumption mode.

[0060] If only the ZL_RST# signal is at a low level and the ZL_FRST_EN# signal is at a high level, the first processor 12 enters a reset state and stops working, while the second processor 13 maintains a normal working mode.

[0061] This mode is suitable for the scenario where the first processor 12 needs to be restarted or reset, while the second processor 13 still needs to continue to execute tasks. The overall power consumption of the reset circuit is lower than that of a full reset.

[0062] When the input ZL_RST# signal is a low pulse signal and the ZL_FRST_EN# signal is at a high level, the first processor 12 is reset and the second processor 13 maintains a normal working mode.

[0063] When the ZL_RST# signal is a low pulse signal and the ZL_FRST_EN# signal remains at a high level, only the first processor 12 is reset, while the second processor 13 is not affected and continues to work normally.

[0064] When the input ZL_RST# signal is a high level signal and the ZL_FRST_EN# signal is a low level signal, the second processor 13 is reset, and the first processor 12 maintains a normal working state or an initialization state after reset.

[0065] If the ZL_RST# signal is high and the ZL_FRST_EN# signal is low, the second processor 13 enters the reset state, while the first processor 12 may be in a normal working state or has recovered from a previous reset and is in an initialization state. This mode allows the reset circuit to restart or reset the second processor 13 without interfering with the first processor 12.

[0066] When the input ZL_RST# signal is a low pulse signal and the ZL_FRST_EN# signal is also at a low level, the entire system is reset, both processors stop working, and the reset circuit is reinitialized.

[0067] In the embodiments of the present application, by combining different input signal states, the system can flexibly enter different operating modes, including low power consumption mode, local low power consumption mode and reset operations for different processors, providing a high degree of controllability and flexibility; at the same time, in low power consumption mode and local low power consumption mode, the reset circuit can reduce the power consumption of the processor as needed, thereby effectively extending the battery life of the device or reducing overall energy consumption; therefore, by providing a variety of reset mechanisms, the reset circuit can quickly recover when an abnormal situation occurs, thereby improving the stability and reliability of the system reset circuit.

[0068] In a possible embodiment, the logic gate circuit combination 2 may further include a third OR gate 25 and a third AND gate 26 .

[0069] The input end of the third OR gate 25 is connected to the WDO pin of the timer circuit 11 , and is used to disable the timer circuit 11 according to the input DOG_DISABLE signal.

[0070] Two input terminals of the third AND gate 26 are respectively connected to the output terminal of the third OR gate 25 and the PFO pin of the timer circuit 11 , and the output terminal of the third AND gate 26 is connected to the MR pin of the timer circuit 11 .

[0071] When the DOG_DISABLE signal is high, the third OR gate 25 will output a high level regardless of the state of the WDO pin of the timer circuit 11. This will cause the output of the third AND gate 26 to be low, thereby disabling the reset operation of the timer circuit 11.

[0072] When the DOG_DISABLE signal is at a low level, the output of the third OR gate 25 will depend on the state of the WDO pin of the timer circuit 11. If the WDO pin outputs a high level, indicating that a system abnormality is detected, the third OR gate 25 outputs a high level, and then the MR pin is activated through the third AND gate 26, thereby resetting the timer circuit 11.

[0073] The state of the PFO pin of the timer circuit 11 is usually used to indicate a power failure. If a power failure occurs, the PFO pin of the timer circuit 11 may become high, which will prevent the third AND gate 26 from outputting a high level, even if the WDO pin of the timer circuit 11 is also high. However, in this embodiment, the DOG_DISABLE signal has a higher priority because it can directly control the disabling of the reset operation.

[0074] In the embodiment of the present application, by introducing the DOG_DISABLE signal and the corresponding logic gate circuit combination 2, fine control of the reset circuit is achieved, the flexibility, reliability and energy efficiency of the reset circuit are improved, and the design and maintenance of the reset circuit are simplified.

[0075] In a possible embodiment, the first processor 12 is configured to periodically output a high-low varying GPIO1 signal to the WDI pin of the timer circuit 11 within a time interval not exceeding 800 milliseconds.

[0076] In the embodiment of the present application, an efficient and reliable reset circuit design scheme is implemented by the first processor 12 periodically outputting a high-low changing GPIO1 signal to the WDI pin of the timer circuit 11. This scheme not only improves the stability and reliability of the system, but also simplifies the system design and reduces the cost.

[0077] In a possible embodiment, the following steps are included: S1: After power-on, the power-on reset signal RST# is output by controlling the timer circuit 11; Optionally, the power-on reset signal RST# can be any one of a low level, a low pulse signal or a high level signal. Specifically, after the system is powered on, the timer circuit 11 is first activated and outputs a power-on reset signal RST#. This signal is used to initialize the system, including the first processor 12 and the second processor 13.

[0078] S2: The first processor 12 starts to run after the power-on reset is completed, and periodically outputs a GPI01 signal with high and low changes to the WDI pin of the timer circuit 11 within a preset time to maintain the normal operation of the timer circuit 11.

[0079] After the power-on reset is completed, the first processor 12 starts to run. In order to maintain the normal operation of the timer circuit 11 and prevent it from triggering unnecessary reset operations, the first processor 12 periodically outputs a high-low changing GPIO1 signal to the WDI pin of the timer circuit 11 within a preset time, for example, every 800 milliseconds.

[0080] S3: The logic gate circuit combination 2 generates a reset signal through combinational logic control according to the RST# signal of the first processor 12, the STATUS signal of the second processor 13, the ZL_RST# signal and the ZL_FRST_EN# signal.

[0081] The logic gate circuit combination 2 receives the RST# signal from the first processor 12, the STATUS signal, the ZL_RST# signal and the ZL_FRST_EN# signal from the second processor 13. These signals are processed by the combinational logic to generate an appropriate reset signal.

[0082] Optionally, the ZL_FRST_EN# signal can be either a high level or a low level.

[0083] S4: Outputting the generated reset signal to the first processor 12 and the second processor 13 respectively, so as to achieve individual or simultaneous resetting of the first processor 12 and the second processor 13 .

[0084] The reset signal generated by the logic gate circuit combination 2 is output to the first processor 12 and the second processor 13 respectively. According to the specific type of the reset signal, the first processor 12 and the second processor 13 will perform corresponding reset operations, specifically, the first processor 12 and the second processor 13 are reset at the same time, the first processor 12 is reset alone, or the second processor 13 is reset alone.

[0085] S5: According to different combinations of the ZL_RST# signal and the ZL_FRST_EN# signal, the reset circuit is controlled to enter a low power consumption mode, a partial low power consumption mode, the first processor 12 is reset, the second processor 13 is reset, or the entire reset circuit is reset.

[0086] By changing the combined state of the ZL_RST# signal and the ZL_FRST_EN# signal, the reset circuit can be flexibly controlled to enter different working modes.

[0087] For example, when ZL_RST# is at a high level and ZL_FRST_EN# is at a low level, the reset circuit may enter a low power consumption mode, and when ZL_RST# is at a high level and ZL_FRST_EN# is also at a high level, a reset operation on the first processor 12 may be triggered.

[0088] In the embodiment of the present application, a highly efficient reset circuit control method is used to achieve stable, reliable and flexible operation of the reset circuit. The method not only improves the stability and flexibility of the reset circuit, but also reduces power consumption and circuit design cost.

[0089] In a possible embodiment, the method further includes: detecting a program loading state of the second processor 13 , and when the loading of the second processor 13 is completed, generating a control signal through the logic gate circuit combination 2 to complete resetting the second processor 13 .

[0090] In the embodiment of the present application, the stability and reliability of the reset circuit are further improved by adding detection and reset control of the program loading state of the second processor 13. This step not only simplifies the debugging and maintenance process of the reset circuit, but also improves the startup efficiency of the reset circuit.

[0091] In a possible embodiment, reset control of the first processor 12 or the second processor 13 is implemented by changing the level states of the input ZL_RST# signal and the ZL_FRST_EN# signal.

[0092] In the embodiment of the present application, by inputting and changing the level state of the ZL_RST# signal and the ZL_FRST_EN# signal, the first processor 12 and the second processor 13 can be reset simultaneously or individually, and the reset blocking of non-task devices can be achieved, thereby enabling the reset circuit to autonomously switch to a low power consumption mode, reducing resource overhead and improving the reliability of the reset circuit.

[0093] In a possible embodiment, the disabling and enabling of the timer circuit 11 are controlled according to the DOG_DISABLE signal, and the reset operation of the timer circuit 11 is implemented through the MR pin of the timer circuit 11, thereby enhancing the stability and reliability of the reset circuit.

[0094] The timer circuit 11 is used to monitor the operating state of the first processor 12. When the first processor 12 does not send any signal within a specified time, the timer circuit 11 will trigger a reset operation.

[0095] In an embodiment of the present application, by controlling the disabling and enabling of the timer circuit 11 according to the DOG_DISABLE signal and implementing the reset operation through the MR pin of the timer circuit 11, the stability and reliability of the reset circuit are enhanced, the reset circuit control logic is simplified, and the flexibility of the reset circuit is improved.

[0096] Based on this, an embodiment of the present application further provides an electronic device, which includes any one of the reset circuits provided above. Optionally, the electronic device can be a space embedded computer.

[0097] In the embodiment of the present application, the electronic device can improve the flexibility and reliability of the computer and reduce the long-term power consumption.

[0098] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that modifying the technical solutions described in the aforementioned embodiments, or replacing some or all of the technical features therein by equivalents, does not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the application.

Claims

1. A reset circuit, characterized in that: It comprises a controller (1) and a logic gate circuit combination (2); The controller (1) comprises a timer circuit (11), a first processor (12), a second processor (13) and a chip (14); The PFI pin of the timer circuit (11) is used to receive an external control signal, the WDI pin of the timer circuit (11) is connected to the GPIO1 output end of the first processor (12), and the RST pin of the timer circuit (11) is connected to the RST# pin of the first processor (12), and is used to output a power-on reset signal RST# according to an input GPIO1 signal; The GPI02 pin of the first processor (12) is connected to the logic gate circuit combination (2) for outputting a GPI02 signal; The output end of the second processor (13) is connected to the first processor (12) and the logic gate circuit combination (2) respectively, and is used to output a STATUS signal; The chip (14) is connected to the second processor (13), and an input end of the chip (14) is connected to the logic gate circuit combination (2); The logic gate circuit combination (2) is used to generate a reset signal through combinational logic control according to the received timer circuit (11), the first processor (12), the second processor (13) and the external control signal, and output the reset signal to the first processor (12) and the second processor (13) respectively; The external control signal includes a ZL_RST# signal and a ZL_FRST_EN# signal to implement reset control between the timer circuit (11), the first processor (12), and the second processor (13), so that the first processor (12) and the second processor (13) can be reset individually or simultaneously.

2. The reset circuit according to claim 1, characterized in that: The logic gate circuit combination (2) comprises a first OR gate (21), a second OR gate (22), a first AND gate (23) and a second AND gate (24); The two input ends of the first OR gate (21) are respectively connected to the RST pin of the timer circuit (11) and the ZL_FRST_EN# signal end, and are used to output a RS_RST# signal according to the input RST# signal and the ZL_FRST_EN# signal, and input the RS_RST# signal to the chip (14) to trigger the refresh configuration of the chip (14); The two input ends of the first AND gate (23) are respectively connected to the output end of the STATUS signal of the second processor (13) and the output end of the first OR gate (21), and are used to output a FRST_EN1 signal according to the input STATUS signal and the RS_RST# signal; The two input ends of the second OR gate (22) are respectively connected to the GPIO2 output end and the ZL_FRST_EN# signal end of the first processor (12), and are used to output a FRST_EN2 signal according to the GPIO2 signal output by the first processor (12) and the ZL_FRST_EN# signal; The two input ends of the second AND gate (24) are respectively connected to the output end of the first AND gate (23) and the output end of the second OR gate (22), and are used to output the F_RST# signal according to the output FRST_EN1 signal and the FRST_EN2 signal, and transmit the F_RST# signal to the second processor (13).

3. The reset circuit according to claim 1, characterized in that: When the input ZL_RST# signal and ZL_FRST_EN# signal are both low level, the reset circuit is in reset state and enters low power mode; When the input ZL_RST# signal is at a low level and the ZL_FRST_EN# signal is at a high level, the first processor (12) is in a reset state, the second processor (13) is in a normal working mode, and the reset circuit enters a local low power consumption mode; When the input ZL_RST# signal is a low pulse signal and the ZL_FRST_EN# signal is at a high level, the first processor (12) is reset and the second processor (13) maintains a normal working mode; When the input ZL_RST# signal is a high level signal and the ZL_FRST_EN# signal is a low level signal, the second processor (13) is reset, and the first processor (12) maintains normal operation or an initialization state after reset; When the input ZL_RST# signal is a low pulse signal and the ZL_FRST_EN# signal is also at a low level, the entire system is reset and the reset circuit is reinitialized.

4. The reset circuit according to claim 1, characterized in that: The logic gate circuit combination (2) further includes a third OR gate (25) and a third AND gate (26); The input end of the third OR gate (25) is connected to the WDO pin of the timer circuit (11), and is used to disable the timer circuit (11) according to the input DOG_DISABLE signal; The two input ends of the third AND gate (26) are respectively connected to the output end of the third OR gate (25) and the PFO pin of the timer circuit (11), and the output end of the third AND gate (26) is connected to the MR pin of the timer circuit (11).

5. The reset circuit according to claim 1, characterized in that: The first processor (12) is configured to periodically output a high-low varying GPIO1 signal to the WDI pin of the timer circuit (11) within a time interval not exceeding 800 milliseconds.

6. A control method for a reset circuit as claimed in any one of claims 1 to 5, characterized in that: The steps include: S1: After power-on, the timer circuit (11) is controlled to output a power-on reset signal RST#; S2: the first processor (12) starts running after power-on reset is completed, and periodically outputs a GPI01 signal with high and low changes to the WDI pin of the timer circuit (11) within a preset time, so as to maintain the normal operation of the timer circuit (11); S3: the logic gate circuit combination (2) generates a reset signal through combinational logic control according to the RST# signal of the first processor (12), the STATUS signal of the second processor (13), the ZL_RST# signal and the ZL_FRST_EN# signal; S4: outputting the generated reset signal to the first processor (12) and the second processor (13) respectively, so as to achieve individual or simultaneous reset of the first processor (12) and the second processor (13); S5: According to different combinations of the ZL_RST# signal and the ZL_FRST_EN# signal, the reset circuit is controlled to enter a low power consumption mode, a partial low power consumption mode, the first processor (12) is reset, the second processor (13) is reset, or the entire reset circuit is reset.

7. The control method according to claim 6, characterized in that: Also includes: The program loading state of the second processor (13) is detected, and when the loading of the second processor (13) is completed, a control signal is generated through the logic gate circuit combination (2) to complete the resetting of the second processor (13).

8. The control method according to claim 6, characterized in that: By changing the level states of the input ZL_RST# signal and the ZL_FRST_EN# signal, reset control of the first processor (12) or the second processor (13) is achieved.

9. The control method according to claim 6, characterized in that: The disabling and enabling of the timer circuit (11) are controlled according to the DOG_DISABLE signal, and a reset operation of the timer circuit (11) is implemented through the MR pin of the timer circuit (11), thereby enhancing the stability and reliability of the reset circuit.

10. An electronic device, comprising the reset circuit according to any one of claims 1 to 5, characterized in that: The electronic device is a space embedded computer.

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