Performance evaluation method and equipment of flash memory and storage medium

Abstract

The invention discloses a flash memory performance evaluation method and device and a storage medium, and relates to the technical field of data processing.The method comprises the steps that firstly, event parameters of at least one event corresponding to all channels in a flash memory are determined, and then a simulation model is constructed according to the event parameters and basic parameters in a technical document; the method comprises the following steps: firstly, generating a simulation model, then running the simulation model based on a simulation environment in a simulation module to obtain an output result of the simulation model, generating a time sequence simulation diagram according to the output result, finally determining performance evaluation information of the flash memory according to the time sequence simulation diagram, and displaying the performance evaluation information in a result interface. According to the method, the flash memory processing process is simulated through the simulation model, so that the interaction amount of the data is recorded through the simulation model, the flash memory is evaluated through the result under the simulation condition output by the simulation model to obtain the performance evaluation information, and the accuracy of performance evaluation of the flash memory is improved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a flash memory performance evaluation method, device and storage medium. Background Art

[0002] With the continuous advancement of flash memory technology, its read and write speeds are increasing, bringing significant performance improvements to data storage and processing. In the data interaction scenario within the flash memory, in order to test the overall performance of the flash memory, the overall performance of the flash memory is generally evaluated by recording the amount of data interaction during the actual operation of the flash memory. However, due to the fast data interaction speed, data may be missed during the actual recording process, which affects the subsequent evaluation process, resulting in low accuracy of the performance evaluation of the flash memory by the relevant scheme.

[0003] The above contents are only used to assist in understanding the technical solution of the present application and do not constitute an admission that the above contents are prior art. Summary of the invention

[0004] The present application provides a flash memory performance evaluation method, device and storage medium, aiming to solve the problem of low accuracy of flash memory performance evaluation in related solutions.

[0005] To achieve the above object, the present application provides a flash memory performance evaluation method, the flash memory performance evaluation method comprising the following steps:

[0006] Determine an event parameter of at least one event corresponding to each channel in the flash memory;

[0007] Building a simulation model according to the event parameters and basic parameters in the technical documentation;

[0008] Running the simulation model based on the simulation environment in the simulation module to obtain an output result of the simulation model, and generating a timing simulation diagram according to the output result;

[0009] The performance evaluation information of the flash memory is determined according to the timing simulation diagram, and the performance evaluation information is displayed in a result interface.

[0010] In one embodiment, the step of determining the event parameter of at least one event corresponding to each channel in the flash memory includes:

[0011] Determining each channel in the flash memory;

[0012] When detecting that a target event in each of the channels is triggered, obtaining a triggering time point of the target event;

[0013] The corresponding concurrency is determined according to the target event, and the concurrency and the trigger time point are determined as the event parameters.

[0014] In one embodiment, after the step of constructing a simulation model according to the event parameters and basic parameters in the technical document, the method further includes:

[0015] Use a logic analyzer to capture the timing parameters corresponding to the target events in the flash memory at low speeds;

[0016] Training the simulation model based on the timing parameters, and updating the model parameters of the simulation model according to the training results output by the simulation model;

[0017] Calculate the corresponding error value according to the training result, and when the error value is lower than a preset threshold, determine the updated simulation model;

[0018] The updated simulation model is deployed in the simulation module so that the simulation module runs the simulation model based on the simulation environment.

[0019] In one embodiment, the step of determining and outputting the performance evaluation information of the flash memory according to the timing simulation diagram includes:

[0020] Determine the amount of data to be operated and the corresponding operation duration according to the timing simulation diagram;

[0021] Determine the throughput according to the data volume and the operation duration;

[0022] The throughput is determined as the performance evaluation information, and the throughput is displayed in the result interface.

[0023] In one embodiment, after the step of determining the throughput as the performance evaluation information and displaying the throughput in the result interface, the method further includes:

[0024] Determine the operation time interval of each event of the target channel according to the timing simulation diagram;

[0025] When the operation time interval is less than a preset time length, it is determined that an abnormality exists in the target channel;

[0026] The identifier of the target channel and the corresponding target event are output in association.

[0027] In one embodiment, after the step of determining the operation time interval of each event of the target channel according to the timing simulation diagram, the method further includes:

[0028] When the operation time interval is greater than a preset time length, determining an idle point according to the operation time interval;

[0029] An optimization report is generated according to the idle points and the optimization report is sent to an operation and maintenance end.

[0030] In one embodiment, after the step of running the simulation model based on the simulation environment in the simulation module to obtain the output result of the simulation model and generating a timing simulation diagram according to the output result, the step further includes:

[0031] Acquire pre-stored identification information, where the identification information is associated with a target channel that needs to be controlled;

[0032] Determine, in the timing simulation diagram according to the identification information, a state interval of a target signal associated with the identification information;

[0033] When the state interval is within a preset interval, the target channel corresponding to the target signal is controlled to change the channel state, so that the target channel prevents events from entering the target channel within a time interval corresponding to the state interval.

[0034] In one embodiment, after the step of determining the performance evaluation information of the flash memory according to the timing simulation diagram and displaying the performance evaluation information in a result interface, the method further includes:

[0035] Obtaining output performance evaluation information, and generating optimization suggestions based on the performance evaluation information;

[0036] The timing parameters and the optimized code are adjusted based on the optimization suggestion, and the adjusted timing parameters and the optimized code are applied to the flash memory.

[0037] In addition, to achieve the above-mentioned purpose, the present application also provides a flash memory performance evaluation device, which includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the computer program is configured to implement the steps of the flash memory performance evaluation method as described above.

[0038] In addition, to achieve the above-mentioned purpose, the present application also provides a storage medium, which is a computer-readable storage medium, and a computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, the steps of the flash memory performance evaluation method as described above are implemented.

[0039] The present application provides a performance evaluation method for a flash memory, a performance evaluation device for a flash memory, and a storage medium. The method determines the event parameters of at least one event corresponding to each channel in the flash memory, and then constructs a simulation model based on the event parameters and basic parameters in a technical document. The simulation model is then run based on a simulation environment in a simulation module to obtain an output result of the simulation model, and a timing simulation diagram is generated based on the output result. Finally, performance evaluation information of the flash memory is determined based on the timing simulation diagram, and the performance evaluation information is displayed in a result interface, thereby recording the interaction amount of data through the simulation model, and then evaluating the flash memory through the results of the simulation output by the simulation model to obtain performance evaluation information, so as to improve the accuracy of the performance evaluation of the flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0042] Figure 1 A schematic diagram of a flow chart of a first embodiment of a flash memory performance evaluation method of the present application;

[0043] Figure 2 A schematic diagram of a flow chart of a second embodiment of a flash memory performance evaluation method of the present application;

[0044] Figure 3 A schematic flow chart of a third embodiment of a flash memory performance evaluation method of the present application;

[0045] Figure 4 This is a flow chart of a fourth embodiment of the flash memory performance evaluation method of the present application;

[0046] Figure 5 This is a flow chart of a seventh embodiment of the flash memory performance evaluation method of the present application;

[0047] Figure 6 This is a flow chart of an eighth embodiment of the flash memory performance evaluation method of the present application;

[0048] Figure 7 A schematic diagram of the architecture of the hardware operating environment of the flash memory performance evaluation device involved in the embodiment of the present application.

[0049] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0050] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0051] In order to better understand the above technical solution, exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0052] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0053] The main solution of the present application is: determine the event parameters of at least one event corresponding to each channel in the flash memory; build a simulation model based on the event parameters and the basic parameters in the technical documentation; run the simulation model based on the simulation environment in the simulation module to obtain the output results of the simulation model, and generate a timing simulation diagram based on the output results; determine the performance evaluation information of the flash memory based on the timing simulation diagram, and display the performance evaluation information in the result interface.

[0054] With the continuous advancement of flash memory technology, its read and write speeds are increasing, bringing significant performance improvements to data storage and processing. In the data interaction scenario within the flash memory, in order to test the overall performance of the flash memory, the overall performance of the flash memory is generally evaluated by recording the amount of data interaction during the actual operation of the flash memory. However, due to the fast data interaction speed, data may be missed during the actual recording process, which affects the subsequent evaluation process, resulting in low accuracy of the performance evaluation of the flash memory by the relevant scheme.

[0055] The present application determines the event parameters of at least one event corresponding to each channel in the flash memory, and then builds a simulation model based on the event parameters and the basic parameters in the technical documentation, and then runs the simulation model based on the simulation environment in the simulation module to obtain the output result of the simulation model, and generates a timing simulation diagram based on the output result, and finally determines the performance evaluation information of the flash memory based on the timing simulation diagram, and displays the performance evaluation information in the result interface, thereby realizing the recording of the interaction amount of data through the simulation model, and then evaluating the flash memory through the results of the simulation situation output by the simulation model to obtain performance evaluation information, so as to improve the accuracy of the performance evaluation of the flash memory.

[0056] Embodiment 1

[0057] Please refer to Figure 1 , in the first embodiment, Figure 1 In the first embodiment of the flash memory performance evaluation method of the present application, the solid state drive performance evaluation method comprises the following steps:

[0058] Step S10: determining event parameters of at least one event corresponding to each channel in the flash memory.

[0059] In this embodiment, the processing action is performed by the performance evaluation system, and the flash memory is a medium used for storage in a solid-state hard disk. There are usually multiple channels inside a flash memory chip, each channel contains multiple storage cells for parallel reading and writing data, and these storage cells are connected together through complex circuits. Each storage cell usually contains a floating gate transistor for storing charge to represent data. Events include reading, writing, and erasing, and each event has its corresponding time parameter.

[0060] Specifically, NAND flash memory is used in this embodiment, and different types of flash memory have different structures and operation modes. In flash memory operation, the event type of the parameter needs to be determined. For each event type, there is a series of event parameters associated with it, where these parameters include but are not limited to address, data, timestamp, error code, etc. For example, in a write event, the parameters include the data to be written, the target address, the write time, etc.

[0061] It should be noted that Flash Memory is an erasable programmable read-only memory (EPROM) that is written in macroblocks and stores data by changing the charge state in the storage cell. When a high voltage is applied to a Flash memory cell, electrons are injected into the floating gate of the storage cell, thereby changing its threshold voltage. The change in threshold voltage determines the conduction state of the storage cell when reading, thereby representing different data values.

[0062] When obtaining event parameters, you can obtain event information related to flash memory operations by accessing the flash memory controller. The flash memory controller is the core component responsible for managing and controlling flash memory operations. The flash memory controller usually maintains an event log to record various events during flash memory operations. By reading the event log, you can obtain parameter information related to a specific event.

[0063] After obtaining the event parameters, that is, the parameter information obtained from the event log, which is the original binary data or encoded data, it is necessary to parse this data to obtain the specific parameter value. The specific parsing process includes operations such as decoding, verification and conversion of data. When parsing the parameter information, it is necessary to determine the information related to the channel, including the channel number, channel status, channel error, etc. By associating the channel information, it is possible to determine on which channel each event occurred.

[0064] Step S20: constructing a simulation model according to the event parameters and basic parameters in the technical document.

[0065] In this embodiment, the technical document is the technical document corresponding to the flash memory model, and the technical document can be obtained through the interface provided by the manufacturer associated with the flash memory. After obtaining the technical document, the basic parameters in the technical document are parsed and extracted according to the preset keyword matching algorithm. Finally, a simulation model is constructed according to the event parameters and the basic parameters, and the simulation model is used to simulate the processing process of the event in the channel.

[0066] Specifically, before building a simulation model, determine the purpose of the simulation model, such as evaluating the performance of flash memory. According to the purpose of the simulation model, determine the parameters that need to be paid attention to. Then formulate keywords corresponding to the parameters and extract the corresponding basic parameters in the technical documentation. In addition, select a suitable simulation tool, such as MATLAB, Simulink, ModelSim, etc. to ensure that the selected tool supports simulation functions.

[0067] In the construction of the simulation model, the flash memory chip and its channels, storage units, etc. are defined as system entities. Each entity is assigned a unique identifier and attributes, such as address, capacity, status, etc. According to the technical documentation and actual needs, set the event parameters related to the flash memory operation, such as read and write time, delay, error rate, etc. Ensure the accuracy and rationality of the event parameters to reflect the actual performance of the flash memory. Configure the basic parameters of the flash memory chip, such as clock frequency, voltage range, power consumption, etc. These parameters will affect the accuracy and reliability of the simulation model. According to the working principle and event parameters of the flash memory, construct the event logic in the simulation model. Including the trigger conditions, execution order and results of the event. Use the selected simulation tool to build a simulation model based on the system entities, event parameters and basic parameters.

[0068] After the simulation model is established, the model is verified and debugged. The correctness of the simulation model is verified by comparing it with known data, which is the behavior of the flash memory at low speed captured by the logic analyzer. Then use the debugging functions provided by the simulation tool, such as breakpoints, single-step execution, variable monitoring, etc. to debug the simulation model to ensure that it can run properly and produce accurate results. According to the simulation results and actual needs, the model is optimized to improve the simulation speed and accuracy, such as by adjusting event parameters, optimizing algorithms, and improving data structures.

[0069] Optionally, you can also set appropriate simulation conditions, such as initial state, input data, simulation time, etc., according to the simulation goal. Make sure that the simulation conditions can reflect the actual operation of the flash memory. Use the simulation tool to run the simulation model and collect the simulation results. And monitor the key indicators and parameters in the simulation process to ensure the stability and accuracy of the simulation process. In addition, you can use charts, statistical methods, and data analysis tools to display and analyze the simulation results. And write a detailed simulation report based on the simulation results and analysis, in which the report includes the simulation goal, model building process, simulation conditions, simulation results, and analysis conclusions.

[0070] Step S30: running the simulation model based on the simulation environment in the simulation module to obtain an output result of the simulation model, and generating a timing simulation diagram according to the output result.

[0071] In this embodiment, the simulation module is deployed in the performance evaluation system, and a simulation environment is provided in the simulation module, and the simulation environment is an operating environment for simulating flash memory. The simulation model is run through the simulation environment, so that the output result of the simulation model can be obtained, and the output result is the operating parameters corresponding to each module in the simulation model when the simulation model is run under the simulation environment. Then, the timing simulation diagram is generated according to the operating parameters.

[0072] Specifically, after the simulation module is deployed in the performance evaluation system, check and ensure that the simulation environment has been configured, including checking the required software licenses and hardware resources to see if they meet the requirements. Then open the simulation software and load the previously built simulation model, check that the model file is not damaged and that all dependent libraries and files are correctly linked. Then, set the simulation parameters such as simulation time, time step, input signal, etc. according to the simulation requirements. In the simulation module, click the "Run" component to start the simulation environment.

[0073] After the simulation environment is started, the simulation module will perform simulation operations according to the set parameters and the logic in the model. During the operation of the simulation model, the progress and status of the simulation can be monitored through the interface of the simulation software or the command line window. After the simulation model is completed, the data generated in the simulation model is collected, and the collected data is drawn into a timing simulation diagram using the third-party drawing software provided by the simulation software. In addition, the scale, color, label and other attributes of the graph can be adjusted to improve readability. Then analyze the timing simulation diagram and record the analysis results in a document or report, including the description of the timing simulation diagram, the measured values ​​of key parameters, the analysis conclusions, etc.

[0074] As an optional implementation, the timing simulation diagram is generated based on the operating parameters by first setting corresponding identifiers for each module in the simulation model, and then using the identifiers of the simulation modules as ordinates. Then, the corresponding operating parameters in the output result are obtained, and the operating parameters are used as abscissas and highlighted in corresponding colors, thereby generating the timing simulation diagram.

[0075] Step S40: determining the performance evaluation information of the flash memory according to the timing simulation diagram, and displaying the performance evaluation information in a result interface.

[0076] In this embodiment, after obtaining the timing simulation diagram through the simulation model, a report associated with the timing simulation diagram is also obtained. The report records various operating indicators and parameters detected when the simulation model is running in the simulation environment. The operating indicators and parameters are obtained through the report and the timing simulation diagram, and the performance evaluation information of the flash memory is calculated through the operating indicators and parameters, and the performance evaluation information is displayed in the result interface.

[0077] Specifically, the operation indicators and parameters are determined by the timing simulation diagram, which can be to identify key signals related to the performance of the flash memory in the timing simulation diagram, such as read and write signals, address signals, data signals, clock signals, etc., and determine the timing relationship between the signals in the timing simulation diagram, such as the start and end time of the read and write operations, the delay time of data transmission, etc.

[0078] Then, use the measurement tools provided by the simulation software to measure key parameters in the timing simulation diagram, such as read and write speed, delay time, throughput, etc. According to the waveform and timing relationship of the read and write signals obtained in the timing simulation diagram, the read and write speed of the flash memory is evaluated. Among them, the read and write speed is usually measured by the amount of data transmitted per second or the number of read and write operations per second. Finally, the read and write speed is used as the performance evaluation information of the flash memory and output.

[0079] As an optional implementation, the performance evaluation information of the flash memory can also be evaluated by measuring the delay time of data transmission in the timing simulation diagram, including the start-up delay of the read and write operations, the delay of data transmission, etc. Among them, the shorter the delay time, the faster the response speed of the flash memory and the better the performance.

[0080] Finally, the performance evaluation information of the flash memory obtained through measurement and analysis is organized into a table for clear display and comparison. A flash memory performance evaluation report can also be generated based on the organized data. The report includes a description of the simulation model, an interpretation of the timing simulation diagram, the measurement results of key parameters, conclusions and suggestions of the performance evaluation, etc. The flash memory performance evaluation report is then output in an appropriate format (such as PDF, Word, etc.) and fed back to the operation and maintenance end so that the management personnel of the operation and maintenance end can optimize the parameters of the flash memory according to the performance evaluation report.

[0081] In the technical solution provided in this embodiment, the event parameters of at least one event corresponding to each channel in the flash memory are first determined, and then a simulation model is constructed based on the event parameters and the basic parameters in the technical document. Then, the simulation model is run based on the simulation environment in the simulation module to obtain the output result of the simulation model, and a timing simulation diagram is generated based on the output result. Finally, the performance evaluation information of the flash memory is determined based on the timing simulation diagram, and the performance evaluation information is displayed in the result interface. The solution of this embodiment simulates the flash memory processing process through the simulation model, thereby outputting the performance evaluation information of the flash memory under the simulation condition, thereby improving the accuracy of the performance evaluation of the flash memory.

[0082] Embodiment 2

[0083] Please refer to Figure 2 , Figure 2 This is the second embodiment of the flash memory performance evaluation method of the present application, based on the first embodiment, step S10 includes:

[0084] Step S11: Determine each channel in the flash memory.

[0085] Step S12: when it is detected that a target event in each of the channels is triggered, the triggering time point of the target event is obtained.

[0086] Step S13: determining the corresponding concurrency according to the target event, and determining the concurrency and the triggering time point as the event parameters.

[0087] In this embodiment, the number of channels in the flash memory can be determined by searching each channel in the flash memory through the main controller, or by determining the number of flash memory channel controllers. After determining the number of channels, a unique identifier is assigned to each channel. A detection module is provided in the channel to detect the target event entering the channel in real time. When the target event is detected to be triggered, the triggering here is the target event entering the channel. At this time, the detection module immediately records the current time point as the trigger time point.

[0088] Specifically, concurrency refers to the number of events processed simultaneously in the flash memory within the same time period. After the target event is detected, the concurrency at the current moment is calculated according to the preset concurrency calculation method. Finally, the calculated concurrency and the recorded trigger time point are used as event parameters.

[0089] In the technical solution provided in this embodiment, by acquiring the trigger time point and concurrency of the target event in the channel and using the trigger time point and concurrency as event parameters, the accuracy of subsequent simulation model construction can be improved.

[0090] Embodiment 3

[0091] Please refer to Figure 3 , Figure 3 The third embodiment of the flash memory performance evaluation method of the present application is based on the first embodiment, and after step S20, further includes:

[0092] Step S21: Capture the timing parameters corresponding to the target event in the flash memory under low speed conditions through a logic analyzer.

[0093] Step S22: training the simulation model based on the timing parameters, and updating the model parameters of the simulation model according to the training results output by the simulation model.

[0094] Step S23: Calculate a corresponding error value according to the training result, and when the error value is lower than a preset threshold, determine the updated simulation model.

[0095] Step S24: deploying the updated simulation model in the simulation module, so that the simulation module runs the simulation model based on the simulation environment.

[0096] In this embodiment, the sampling rate, trigger conditions, channel settings and other parameters of the logic analyzer are first configured according to the characteristics of the target event to ensure that the logic analyzer can accurately capture the timing parameters of the target event. Then, the target event in the flash memory under the low-speed condition that needs to be captured is determined, and the target event can be a read-write operation and a data transmission. Then, the probe of the logic analyzer is connected to the corresponding interface of the flash memory and the logic analyzer is started to capture the timing parameters under the low-speed condition. During the capture process, the interface of the logic analyzer is continuously detected to ensure that the timing waveform and data of the target event are correctly captured, and finally the captured timing parameters are recorded to obtain the timing parameters.

[0097] It should be noted that the logic analyzer is a high-performance data domain test instrument, which is mainly used to analyze the logical relationship of the digital system. Its working principle is to use the clock to collect and display digital signals from the test equipment. It usually only displays two voltage levels (logic 1 and 0). Therefore, after setting the reference voltage, the measured signal is judged by the comparator. Those higher than the reference voltage are High (logic 1), and those lower than the reference voltage are Low (logic 0), thereby forming a digital waveform.

[0098] After capturing the timing parameters, the timing parameters need to be preprocessed, including data cleaning and format conversion. Then, the captured timing data is divided into a training set and a test set according to the simulation model, and the training set in the preprocessed timing parameters is used as input data to train the simulation model. During the training process, the parameters and structure of the model are adjusted according to the results output by each training set, and iterative training is performed to reduce the value of the error function. When the value of the error function is lower than a preset threshold, it is determined that the model has been trained. Finally, the trained simulation model is saved and deployed in the simulation module, so that when the simulation module is triggered to load, the deployed simulation model is called, and then the simulation model is run based on the simulation environment in the simulation module.

[0099] In the technical solution provided in this embodiment, the timing parameters of the flash memory under low-speed conditions are captured and used to train the simulation model, thereby improving the accuracy of the simulation model in evaluating the performance of the flash memory.

[0100] Embodiment 4

[0101] Please refer to Figure 4 , Figure 4 This is the fourth embodiment of the flash memory performance evaluation method of the present application, based on the first embodiment, step S40 includes:

[0102] Step S41: Determine the amount of data to be operated and the corresponding operation duration according to the timing simulation diagram.

[0103] Step S42: Determine the throughput according to the data volume and operation duration.

[0104] Step S43: determining the throughput as the performance evaluation information, and displaying the throughput in the result interface.

[0105] In this embodiment, the start and end time points of each operation are identified in the timing simulation diagram. Then, the interval of each operation is marked according to the start and end time points, and the duration of each operation interval is measured using a measuring tool, and the duration of each operation is recorded. Then, the amount of data transmitted by each operation is determined based on the data transmission waveform or data mark in the timing simulation diagram. Among them, the amount of data can be recorded in bits, bytes or data blocks.

[0106] In the process of determining throughput, throughput is usually defined as the amount of data successfully transmitted per unit time. It is calculated using the formula "throughput = data volume / operation duration". Substitute the data volume and operation duration of each operation into the throughput calculation formula to calculate the throughput of each operation and record it. In addition, the average throughput can also be calculated, that is, the average value of the throughput of all operations is calculated. Finally, the throughput or the average value of the throughput is used as performance evaluation information, and the throughput is displayed in the result interface.

[0107] In the technical solution provided in this embodiment, the throughput of operations in the flash memory is calculated through a timing simulation diagram, and the throughput is displayed in a result interface as performance evaluation information of the flash memory, thereby completing the performance evaluation of the flash memory.

[0108] In the fifth embodiment, based on the fourth embodiment, after step S43, the method further includes:

[0109] Step S431: Determine the operation time interval of each event of the target channel according to the timing simulation diagram.

[0110] Step S432: When the operation time interval is less than a preset time length, it is determined that an abnormality exists in the target channel.

[0111] Step S433: associate and output the identifier of the target channel and the corresponding target event.

[0112] In this embodiment, by reading the timing simulation diagram, that is, using a simulation tool to open the timing simulation diagram containing the timing information of the target channel, the position of each target event is marked in the timing simulation diagram, and then the time interval between adjacent operations in the target event is calculated using a measurement tool, and the specific value of each operation time interval is recorded.

[0113] Specifically, the preset duration is set according to the demand. A reasonable preset duration can be set according to the working characteristics of the flash memory and the normal operation specifications of the target channel. The preset duration can reflect the minimum time interval of the target channel under normal operation. Then, each operation time interval measured is compared with the preset duration. If a certain operation time interval is less than the preset duration, it is preliminarily determined that the operation may be abnormal. Combined with the historical data, system log and other information of the target channel, the abnormal operation preliminarily determined is further comprehensively judged. If multiple operation time intervals are less than the preset duration, it means that abnormal operations occur frequently, indicating that the target channel is abnormal. For operations determined to be abnormal, the time of occurrence, the identification of the target channel, the specific type of abnormal operation and other information are recorded. The recorded abnormal information is associated with the corresponding target event. Finally, a detailed abnormal report is generated based on the recorded abnormal information and the associated target event, and the abnormal report is fed back to the operation and maintenance end.

[0114] In the technical solution provided in this embodiment, whether there is an abnormality is determined by the interval duration of the operations in the timing simulation diagram, and the abnormal target channel is associated with the event output to identify the abnormal channel in the flash memory, and then adjust the timing of the flash memory and the event.

[0115] In the sixth embodiment, based on the fifth embodiment, after step S431, the method further includes:

[0116] Step S4311: when the operation time interval is greater than a preset time length, determining an idle point according to the operation time interval;

[0117] Step S4312: Generate an optimization report based on the idle points and send the optimization report to the operation and maintenance end.

[0118] In this embodiment, after reading the operation time interval data of each event of the target channel from the timing simulation diagram, it is determined whether the operation time interval is greater than a preset duration. The preset duration here is set according to demand to determine whether the operation time interval is too long, thereby determining whether there is an idle point.

[0119] Specifically, each operation time interval is compared with a preset duration threshold. If a certain operation time interval is greater than the preset duration threshold, it is preliminarily judged that the point is an idle point. Combined with system logs, application status and other information, the preliminarily judged idle point is verified. Ensure that the judgment of the idle point is accurate and avoid misjudgment. Then collect detailed information related to the idle point, including the time, location, duration, etc. of the idle point. At the same time, collect the configuration information and performance indicators of the system or application, and analyze the cause of the idle point based on the collected information. Among them, the cause includes insufficient system resources, application logic errors, network delays, etc. Determine matching optimization suggestions for the cause of the idle point. An optimization suggestion library is pre-stored in the system, and matching optimization suggestions can be queried through keywords in the cause. Finally, the optimization suggestions are sent to the operation and maintenance end so that technical support personnel can take corresponding optimization measures.

[0120] In the technical solution provided in this embodiment, by determining idle points and generating optimization reports according to the idle points, the flash memory is optimized to improve the operating efficiency of the flash memory.

[0121] Embodiment 7

[0122] Please refer to Figure 5 , Figure 5 The seventh embodiment of the flash memory performance evaluation method of the present application is based on the first embodiment, and after step S30, further includes:

[0123] Step S31: obtaining pre-stored identification information, wherein the identification information is associated with a target channel that needs to be controlled.

[0124] Step S32: determining, in the timing simulation diagram according to the identification information, a state interval of a target signal associated with the identification information.

[0125] Step S33: When the state interval is within a preset interval, controlling the target channel corresponding to the target signal to change the channel state, so that the target channel prevents events from entering the target channel within a time interval corresponding to the state interval.

[0126] In this embodiment, the identification information is associated with a target channel that needs to be controlled, which is stored in a database, and the identification information can be queried in the database through a preset keyword. Then, according to the queried identification information, the state interval of the target signal associated with the identification information is extracted in the timing simulation diagram, wherein the state interval represents the time interval during which the target signal lasts in a state. Through the timing simulation diagram, the state corresponding to each signal can be determined, and the target signal is used to represent the state of a preset signal. Through the identification of the target signal, the target signal corresponding to the identification can be determined in the timing simulation diagram, and then all the corresponding intervals can be queried, that is, the state interval, wherein the state interval corresponds to a section of undulating intervals. When the state interval falls within the preset interval, the channel corresponding to the target signal is controlled to change the channel state so that the channel prevents the event from entering the channel during the time interval corresponding to the state interval. In addition, to determine whether the target interval is in the preset interval, a comparator can be used to compare the value of the state interval with the value of the preset interval.

[0127] Optionally, preset actions are set according to actual needs. These actions can be closing a channel, changing the channel state, sending an alarm, etc. In a multi-channel control system, these preset actions can be implemented by programming. For example, microinstructions are written on a digital board, or trigger conditions are set on a power board. If the target interval is within the preset interval, the execution of the preset action is triggered. In the time interval corresponding to the target interval, the event is prevented from entering the channel by controlling the switch or state of the channel. This can be achieved by setting a logic gate or switch circuit at the entrance of the channel. When the target interval is in the preset interval, the logic gate or switch circuit will be in a closed state, thereby preventing the event from entering the channel.

[0128] In the technical solution provided in this embodiment, the state interval is determined by simulating a timing diagram, and when the state interval is within a preset interval, the event is prevented from entering the channel, thereby improving the accuracy of the simulated flash memory operation.

[0129] Embodiment 8

[0130] Please refer to Figure 6 , Figure 6 This is the eighth embodiment of the flash memory performance evaluation method of the present application, based on the first embodiment, after step S40, further comprising:

[0131] Step S50: Acquire the performance evaluation information, and generate optimization suggestions according to the performance evaluation information.

[0132] Step S60: adjusting timing parameters and optimizing codes based on the optimization suggestion, and applying the adjusted timing parameters and codes to the flash memory.

[0133] In this embodiment, after the simulation model outputs performance evaluation information, the output performance evaluation information is obtained, and the performance evaluation information includes throughput, read and write speed, and delay time. Then, the problem of the flash memory is determined based on the performance evaluation information, such as whether it is caused by low code efficiency, improper resource allocation, or other factors. In response to the problem of low code efficiency, suggestions such as optimizing algorithms, reducing unnecessary calculations, and using more efficient data structures are proposed. In response to the problem of improper resource allocation, suggestions such as adjusting memory space, optimizing garbage collection algorithms, and reasonably allocating thread pools are proposed. The above suggestions are then determined as optimization suggestions. After determining the optimization suggestions, the timing parameters are adjusted according to the optimization suggestions, and the code is compiled to ensure that there are no problems with the code. Finally, the compiled code and the adjusted timing parameters are deployed to the flash memory.

[0134] In the technical solution provided in this embodiment, optimization suggestions are generated through performance evaluation information, and then timing parameters and optimization codes are adjusted based on the optimization suggestions, thereby completing the optimization of the flash memory and improving the optimization efficiency of the flash memory.

[0135] Since the system introduced in the embodiment of the present application is a system used to implement the method of the embodiment of the present application, based on the method introduced in the embodiment of the present application, the person skilled in the art can understand the specific structure and deformation of the system, so it is not repeated here. All systems used in the method of the embodiment of the present application belong to the scope of protection of this application.

[0136] The present application provides a flash memory performance evaluation device, which includes: at least one processor; and a memory that is communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the flash memory performance evaluation method in the above-mentioned embodiment 1.

[0137] Reference below Figure 7 , which shows a schematic diagram of the structure of a flash memory performance evaluation device suitable for implementing the embodiment of the present application. The flash memory performance evaluation device in the embodiment of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 7 The flash memory performance evaluation device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0138] like Figure 7 As shown, the performance evaluation device of the flash memory may include a processing device 1001 (e.g., a core processor, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM: Read Only Memory) 1002 or a program loaded from a storage device 1003 to a random access memory (RAM: Random Access Memory) 1004. In RAM1004, various programs and data required for the operation of the performance evaluation device of the flash memory are also stored. The processing device 1001, ROM1002, and RAM1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems can be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the performance evaluation device of the flash memory to communicate wirelessly or wired with other devices to exchange data. Although the performance evaluation device of the flash memory with various systems is shown in the figure, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or provided alternatively.

[0139] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0140] The flash memory performance evaluation device provided by the present application adopts the flash memory performance evaluation method in the above embodiment, which can solve the technical problem that the performance evaluation of the flash memory in the related solution is of low accuracy. Compared with the prior art, the beneficial effects of the flash memory performance evaluation device provided by the present application are the same as the beneficial effects of the flash memory performance evaluation method provided by the above embodiment, and the other technical features in the flash memory performance evaluation device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0141] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0142] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0143] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the flash memory performance evaluation method in the above-mentioned embodiment.

[0144] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0145] The computer-readable storage medium may be included in the performance evaluation device of the flash memory; or may exist independently without being assembled into the performance evaluation device of the flash memory.

[0146] The above-mentioned computer-readable storage medium carries one or more programs. When the above-mentioned one or more programs are executed by the performance evaluation device of the flash memory, the performance evaluation device of the flash memory: determines the event parameters of at least one event corresponding to each channel in the flash memory; builds a simulation model according to the event parameters and the basic parameters in the technical document; runs the simulation model based on the simulation environment in the simulation module to obtain the output result of the simulation model, and generates a timing simulation diagram according to the output result; determines the performance evaluation information of the flash memory according to the timing simulation diagram, and displays the performance evaluation information in the result interface.

[0147] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0148] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0149] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0150] The readable storage medium provided by the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned flash memory performance evaluation method, and can solve the technical problem that the relevant scheme has low accuracy in performance evaluation of flash memory. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the flash memory performance evaluation method provided by the above-mentioned embodiment, and will not be elaborated here.

[0151] An embodiment of the present application provides a computer program product, including a computer program, which implements the steps of the flash memory performance evaluation method as described above when the computer program is executed by a processor.

[0152] The computer program product provided by the present application can solve the technical problem that the relevant solutions have low accuracy in evaluating the performance of flash memory. Compared with the prior art, the beneficial effects of the computer program product provided by the embodiment of the present application are the same as the beneficial effects of the performance evaluation method of the flash memory provided by the above embodiment, which will not be described in detail here.

[0153] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent processing scope of the present application.

Claims

1. A flash memory performance evaluation method, characterized in that: The flash memory performance evaluation method comprises the following steps: Determine an event parameter of at least one event corresponding to each channel in the flash memory; Building a simulation model according to the event parameters and basic parameters in the technical documentation; Running the simulation model based on the simulation environment in the simulation module to obtain an output result of the simulation model, and generating a timing simulation diagram according to the output result; The performance evaluation information of the flash memory is determined according to the timing simulation diagram, and the performance evaluation information is displayed in a result interface.

2. The method according to claim 1, characterized in that The step of determining the event parameter of at least one event corresponding to each channel in the flash memory comprises: Determining each channel in the flash memory; When detecting that a target event in each of the channels is triggered, obtaining a triggering time point of the target event; The corresponding concurrency is determined according to the target event, and the concurrency and the trigger time point are determined as the event parameters.

3. The method according to claim 1, characterized in that After the step of constructing a simulation model according to the event parameters and the basic parameters in the technical document, the method further includes: Use a logic analyzer to capture the timing parameters corresponding to the target events in the flash memory at low speeds; Training the simulation model based on the timing parameters, and updating the model parameters of the simulation model according to the training results output by the simulation model; Calculate the corresponding error value according to the training result, and when the error value is lower than a preset threshold, determine the updated simulation model; The updated simulation model is deployed in the simulation module so that the simulation module runs the simulation model based on the simulation environment.

4. The method according to claim 1, characterized in that The step of determining the performance evaluation information of the flash memory according to the timing simulation diagram and displaying the performance evaluation information in a result interface comprises: Determine the amount of data to be operated and the corresponding operation duration according to the timing simulation diagram; Determine the throughput according to the data volume and the operation duration; The throughput is determined as the performance evaluation information, and the throughput is displayed in the result interface.

5. The method according to claim 4, characterized in that After the step of determining the throughput as the performance evaluation information and displaying the throughput in the result interface, the method further includes: Determine the operation time interval of each event of the target channel according to the timing simulation diagram; When the operation time interval is less than a preset time length, it is determined that an abnormality exists in the target channel; The identifier of the target channel and the corresponding target event are output in association.

6. The method according to claim 5, characterized in that After the step of determining the operation time interval of each event of the target channel according to the timing simulation diagram, the method further includes: When the operation time interval is greater than a preset time length, determining an idle point according to the operation time interval; An optimization report is generated according to the idle points and the optimization report is sent to an operation and maintenance end.

7. The method according to claim 1, characterized in that After the step of running the simulation model based on the simulation environment in the simulation module to obtain the output result of the simulation model and generating a timing simulation diagram according to the output result, the method further includes: Acquire pre-stored identification information, where the identification information is associated with a target channel that needs to be controlled; Determine, in the timing simulation diagram according to the identification information, a state interval of a target signal associated with the identification information; When the state interval is within a preset interval, the target channel corresponding to the target signal is controlled to change the channel state, so that the target channel prevents events from entering the target channel within a time interval corresponding to the state interval.

8. The method according to claim 1, characterized in that After the step of determining the performance evaluation information of the flash memory according to the timing simulation diagram and displaying the performance evaluation information in a result interface, the method further includes: Obtaining the performance evaluation information, and generating optimization suggestions based on the performance evaluation information; The timing parameters and the optimized code are adjusted based on the optimization suggestion, and the adjusted timing parameters and the optimized code are applied to the flash memory.

9. A flash memory performance evaluation device, characterized in that: The flash memory performance evaluation device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the flash memory performance evaluation method according to any one of claims 1 to 8.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the flash memory performance evaluation method according to any one of claims 1 to 8 are implemented.

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