Bus control method, chip, bus architecture, electronic equipment and readable medium

Abstract

The invention provides a bus control method, a chip, a bus architecture, electronic equipment and a readable medium. The chip comprises a processor and an interface. The processor is used for receiving a first instruction through the interface, controlling the chip to access the SPMI bus based on the first instruction and monitoring data transmitted by the SPMI bus after the chip accesses the SPMI bus, and the SPMI bus is connected with a first node and a second node and is used for transmitting communication data between the first node and the second node; and the processor is also used for establishing connection between the control chip and the first node and the second node through the SPMI bus, disconnecting the connection between the first node and the second node, obtaining second data based on the first data, and sending the second data to the second node when monitoring that the data transmitted by the SPMI bus comprises the first data. Data in the master-slave system based on the SPMI bus is controlled through external equipment such as a chip.

Description

Technical Field

[0001] The present application relates to the field of bus communication technology, and in particular to a bus control method, a chip, a bus architecture, an electronic device, a computer program product, and a computer-readable storage medium. Background Art

[0002] Electronic devices such as mobile phones use a system power management interface (SPMI) bus to connect multiple hosts and multiple slaves of the electronic devices, and the multiple hosts and multiple slaves exchange data through the SPMI bus.

[0003] However, data in the master-slave system based on the SPMI bus must be controlled by the host, and the data in the master-slave system cannot be controlled by external devices. Summary of the invention

[0004] The present application provides a bus control method, a chip, a bus architecture, an electronic device, a computer program product and a computer-readable storage medium, which can realize the control of data in a master-slave system based on an SPMI bus through an external device.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] In a first aspect, the present application provides a chip, comprising a processor and an interface; the processor is used to receive a first instruction through the interface, and based on the first instruction, control the chip to access the system power management interface SPMI bus, and after the chip accesses the SPMI bus, monitor the data transmitted by the SPMI bus, the SPMI bus connects a first node and a second node, and is used to transmit communication data between the first node and the second node; the processor is also used to control the chip to establish a connection with the first node and the second node through the SPMI bus when it monitors that the data transmitted by the SPMI bus includes first data, disconnect the connection between the first node and the second node, obtain second data based on the first data, and send the second data to the second node; the first data is the data written by the first node to the second node.

[0007] It can be seen from the above scheme that after the chip receives the first instruction, it can access the SPMI bus based on the first instruction and monitor the data transmitted by the bus. After monitoring the data that the first node writes the second data, the connection between the first node and the second node connected on the SPMI bus is disconnected. The chip also establishes connections with the first node and the second node through the SPMI bus respectively, and obtains the second data based on the first data, and then sends the second data to the second node, thereby realizing the control of data in the master-slave system based on the SPMI bus through an external device such as a chip.

[0008] It should be noted that the chip is connected to the SPMI bus only after receiving the first instruction, that is, before receiving the first instruction, the chip has no connection with the SPMI bus, which can also avoid the impact of the chip failure on the SPMI bus.

[0009] In one possible implementation, the processor is further used to: when it is monitored that the data transmitted by the SPMI bus includes the first data, simulate the second node to perform bus arbitration on the first node, so as to avoid the first node sending data to the SPMI bus to interfere with the data writing operation during the process of the chip writing the second data to the second node.

[0010] In one possible implementation, the processor is further used to: when it is monitored that the data transmitted by the SPMI bus includes the first data, simulate the first node to perform bus arbitration on the second node, thereby preventing the second node from sending data to the SPMI bus to interfere with the data writing operation during the process of the chip writing the second data to the second node.

[0011] In a possible implementation, the processor control chip sends the second data to the second node, including: when the first node preempts the SPMI bus with the highest priority, the processor control chip sends the second data to the second node.

[0012] In one possible implementation, after simulating bus arbitration on the first node with the second node, the processor is also used for: when the SPMI bus instruction cycle for bus arbitration on the second node reaches the stage where the second node preempts the SPMI bus with the highest priority, the control chip sends a first preset address to the first node to inform the first node that the SPMI bus is preempted, so as to prevent the first node from preempting the bus.

[0013] In one possible implementation, after the processor control chip sends the first preset address to the first node, the processor is also used to: when the SPMI bus instruction cycle for bus arbitration at the second node reaches the frame sequence stage, the control chip writes third data to the third node, and the third node has a second preset address.

[0014] In a possible implementation manner, the second preset address is different from the address of the first node so as not to interfere with the first node connected to the SPMI bus.

[0015] In a possible implementation manner, the first preset address is different from the address of the second node so as not to interfere with the second node connected to the SPMI bus.

[0016] In the second aspect, the present application provides a bus architecture, including: a first node, a second node, a switch module and a chip; the first node and the second node are connected to the SPMI bus and the chip through the switch module; the chip is used to receive a first instruction, and based on the first instruction, access the SPMI bus through the switch module, and after accessing the SPMI bus, monitor the data transmitted by the SPMI bus; when the data transmitted by the SPMI bus is monitored to include the first data, a connection is established with the first node and the second node through the SPMI bus through the switch module, and the connection between the first node and the second node is disconnected; the chip is also used to obtain second data based on the first data, and send the second data to the second node; the first data is the data written by the first node to the second node.

[0017] In a possible implementation manner, the chip is further connected to a processor, and the first instruction is sent by the processor to the chip.

[0018] In a possible implementation, the chip and the processor are connected via an SPI interface or an I2C interface.

[0019] In one possible embodiment, the switch module includes: a first switch and a second switch; the first switch connects the first node and the chip through the SPMI bus, and the first switch is used to control the connection or disconnection of the first node and the chip; the second switch connects the first node, the second node and the chip through the SPMI bus, and the second switch is used to control the direct connection between the first node and the second node, or to control the connection between the second node and the chip.

[0020] In one possible embodiment, the switch module includes: a first switch and a second switch; the first switch connects the first node, the second node and the chip through the SPMI bus, and the first switch is used to control the first node and the second node to be directly connected, or to control the first node to be connected to the chip; the second switch connects the second node and the chip through the SPMI bus, and the second switch is used to control the second node to be connected or disconnected from the chip.

[0021] In a third aspect, the present application provides an electronic device comprising: a processor, and a bus architecture as described in any one of the second aspect and its possible implementations; the processor is used to generate a first instruction and send the first instruction to a chip of the bus architecture.

[0022] In a fourth aspect, the present application provides a bus control method applied to a chip, comprising: receiving a first instruction; based on the first instruction, accessing a system power management interface SPMI bus, and after accessing the SPMI bus, monitoring data transmitted by the SPMI bus; the SPMI bus connects a first node and a second node, and is used to transmit communication data between the first node and the second node; when it is monitored that the data transmitted by the SPMI bus includes first data, establishing a connection with the first node and the second node through the SPMI bus, disconnecting the connection between the first node and the second node, and based on the first data, obtaining second data, and then sending the second data to the second node, the first data being data written by the first node to the second node.

[0023] In a possible implementation, the method further includes: when it is monitored that the data transmitted by the SPMI bus includes the first data, simulating the second node to perform bus arbitration on the first node.

[0024] In a possible implementation, the method further includes: when it is monitored that the data transmitted by the SPMI bus includes the first data, simulating the first node to perform bus arbitration on the second node.

[0025] In a possible implementation manner, sending the second data to the second node includes: sending the second data to the second node when the first node preempts the SPMI bus with the highest priority.

[0026] In one possible implementation, after simulating bus arbitration on the first node with the second node, the method further includes: sending a first preset address to the first node when the SPMI bus instruction cycle for bus arbitration at the second node reaches the stage where the second node preempts the SPMI bus with the highest priority.

[0027] In one possible implementation, after sending the first preset address to the first node, the method further includes: when the SPMI bus instruction cycle for bus arbitration at the second node reaches the frame sequence stage, writing third data to a third node, the third node having a second preset address.

[0028] In a fifth aspect, the present application further provides a computer-readable storage medium for storing a computer program, which, when executed, is specifically used to implement a bus control method as described in any one of the fourth aspect and its possible implementations.

[0029] In a sixth aspect, the present application provides a computer program product, which, when executed on a computer, enables the computer to execute a bus control method as described in any one of the fourth aspect and possible implementations thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1It is a schematic diagram of the SPMI bus architecture in the related art;

[0031] Figure 2 Schematic diagram of the instruction cycle of the SPMI bus in the embodiment of the present application;

[0032] Figure 3 A schematic diagram of the SPMI bus architecture provided in an embodiment of the present application;

[0033] Figure 4 Another schematic diagram of the architecture of the SPMI bus provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of the integrated circuit IC provided in an embodiment of the present application being in a listening mode, the integrated circuit IC being connected to a host and a slave;

[0035] Figure 6 A schematic diagram of the integrated circuit IC provided in an embodiment of the present application being in a data resending mode, the integrated circuit IC being connected to a host and a slave;

[0036] Figure 7 A flowchart of a method for an integrated circuit IC to simulate a host and write data to a slave provided by an embodiment of the present application;

[0037] Figure 8 A hardware structure diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. The terms used in the following embodiments are only for the purpose of describing specific embodiments and are not intended to be used as limitations on the present application. As used in the specification and the appended claims of the present application, the singular expressions "one", "a kind", "said", "above", "the" and "this" are intended to also include expressions such as "one or more", unless there is a clear contrary indication in the context. It should also be understood that in the embodiments of the present application, "one or more" refers to one, two or more; "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist; for example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship.

[0039] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0040] The multiple involved in the embodiments of the present application means greater than or equal to two. It should be noted that in the description of the embodiments of the present application, the words "first", "second", etc. are only used for the purpose of distinguishing the description, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0041] The System Power Management Interface (SPMI) bus is an asynchronous bus that can connect multiple hosts (Master) and multiple slaves (Slave). Multiple hosts and multiple slaves exchange data through the SPMI bus. For example, Figure 1 The SPMI bus is shown to connect 4 masters and 4 slaves. Both the master and the slave can be understood as nodes on the SPMI bus.

[0042] In the related art, the data interaction between the host and the slave on the SPMI bus is controlled by the host and cannot be controlled by an external device. In order to solve the problem that the data interaction between the host and the slave on the SPMI bus cannot be controlled by an external device, an embodiment of the present application provides an SPMI bus architecture.

[0043] Before introducing the SPMI bus architecture provided in the embodiment of the present application, the relevant knowledge of the SPMI bus is first explained through the following content.

[0044] Generally, the SPMI bus may include a clock signal line and a data signal line, wherein the clock signal line is used to transmit a clock signal SCLK (Serial Clock), and the data signal line is used to transmit a data signal SDATA (Serial Data).

[0045] In some embodiments, the SPMI bus can support simultaneous connection of 4 hosts and access to 16 slaves.

[0046] In an application scenario, the SPMI bus can be connected to one or more processing units on a system-on-a-Chip (SoC) and one or more processing units on a power management chip (PMIC). Among them, one or more processing units on the SoC act as the host, and one or more processing units on the PMIC act as slaves. The host and the slave can exchange data through the SPMI bus.

[0047] The SPMI bus operates according to the SPMI bus instruction cycle, such as Figure 2 As shown, the SPMI bus command cycle includes the following stages: bus arbitration, sequence start, frame sequence, and bus stop cycle.

[0048] In the bus arbitration phase, when the data signal line of the SPMI bus is pulled high, the host currently occupying the SPMI bus releases the clock signal SCLK through the clock signal line. The host or slave connected to the SPMI bus pulls up the data signal line under the corresponding clock signal SCLK to declare its priority. If there is a device with a higher priority requesting to occupy the SPMI bus, the host currently occupying the SPMI bus releases the bus to the device with a higher priority according to the priority. After the host or slave seizes the SPMI bus and becomes the owner of the SPMI bus, it obtains control of the clock signal SCLK of the SPMI bus and provides the clock signal SCLK of the SPMI bus.

[0049] After completing bus arbitration, the SPMI bus enters the sequence start phase. The sequence start phase can be a bus buffer phase. In the sequence start phase, the device that wins the bus will pull down the clock signal SCLK, and at the same time control the data signal line to first pull up the data signal SDATA, and then pull down the data signal SDATA, generating a start timing (sequence start condition, SSC). After the slave on the SPMI bus, such as the power management chip, detects the start timing, it is ready to receive the subsequent frame sequence.

[0050] In some embodiments, the frame sequence is used to execute a data transmission instruction. The data transmission instruction includes information such as a transmission command, a transmission address, and transmission data. In some embodiments, the types of transmission commands include but are not limited to: the host reads the register of the slave, the host writes the register of the slave, and the slave writes the register of the host.

[0051] The bus stop cycle phase is a process of bus stop, at which the SPMI bus is in an idle state. When the SPMI bus is in the bus stop cycle phase, the clock signal SCLK and the transmission data signal SDATA of the SPMI bus are both pulled low.

[0052] Figure 3 An SPMI bus architecture provided by an embodiment of the present application is demonstrated.

[0053] For example, Figure 3 As shown, in the SPMI bus architecture provided in the embodiment of the present application, the SPMI bus connects 4 hosts and 4 slaves. However, the number of hosts and slaves connected by the SPMI bus is not limited to Figure 3 shown.

[0054] The four hosts are connected to the first switch K1 through the SPMI bus, and the integrated circuit (IC) is connected through the first switch K1. The IC is also connected to the second switch K2, and the four slaves are connected through the second switch K2. The first switch K1 can be used to control the connection or disconnection between the host and the IC.

[0055] The four hosts are also connected to the second switch K2 via the SPMI bus, and the four slaves are connected via the second switch K2 via the SPMI bus, that is, the four hosts and the four slaves are connected via the second switch K2. The second switch K2 connects the host, the slave and the IC respectively, so the second switch K2 can be used to control the host and the slave to be directly connected, or to control the slave to be connected to the IC.

[0056] The IC may also be connected to the CPU, and the IC and the CPU are not connected in a manner of an SPMI bus. In some embodiments, the IC may be connected to the CPU via an SPI interface or an I2C interface.

[0057] In some embodiments, the IC is used to control the connection mode of the first switch K1 and the second switch K2 to achieve direct connection between the host and the slave, or to achieve connection between the host and the slave through the IC. In addition, when the host is connected to the slave through the IC, the IC is also used to simulate the host to perform bus arbitration, resend data to the slave, and other operations, thereby achieving external control of data interaction between the host and the slave on the SPMI bus.

[0058] In some embodiments, the IC can also receive instructions sent by the CPU, and control the connection mode of the first switch K1 and the second switch K2 based on the instructions, that is, connecting or disconnecting the host and the IC through the first switch K1, and connecting the host and the slave, or connecting the slave and the IC through the second switch K2.

[0059] In some embodiments, the first switch K1 and the second switch K2 may be single-pole double-throw switches. The moving ends of the first switch K1 and the second switch K2 may be movable between the two ports ① and ②. Figure 3 As shown, the moving end of the first switch K1 is located at port ①, and the moving end of the second switch is located at port ①.

[0060] The moving end of the first switch K1 is located at port ②, the moving end of the second switch K2 is located at port ②, the IC is connected to the SPMI bus, and the host and the slave are connected through the SPMI bus. The moving end of the first switch K1 is located at port ①, the moving end of the second switch is located at port ①, the IC is disconnected from the SPMI bus, the host is directly connected to the slave through the SPMI bus, and the host and the slave exchange data through the SPMI bus.

[0061] It should be noted that the moving end of the first switch K1 is located at port ②, which can be understood as the first switch K1 is located in the first channel, and the moving end of the first switch K1 is located at port ①, which can be understood as the first switch K1 is located in the second channel; the moving end of the second switch K2 is located at port ②, which can be understood as the second switch K2 is located in the first channel, and the moving end of the second switch K2 is located at port ①, which can be understood as the second switch K2 is located in the second channel.

[0062] It can be seen that the moving end of the first switch K1 is located at port ①, and the moving end of the second switch is located at port ①. The IC can be completely disconnected from the SPMI bus and has no connection with the host and slave on the SPMI bus. In this way, when the IC fails, the IC can be disconnected from the SPMI bus to avoid the IC from affecting the host and slave on the PMI bus due to the failure.

[0063] It should be noted that the moving end of the first switch K1 is located at port ①, and the moving end of the second switch is located at port ②, or the moving end of the first switch K1 is located at port ②, and the moving end of the second switch is located at port ①. Although the connection between the IC and the SPMI bus is disconnected, the IC is not completely cut off from the SPMI bus. If the IC fails, the failure will also affect the host and slave on the PMI bus. For example, if the IC has a grounding fault, the host or slave on the bus will also be grounded.

[0064] Depend on Figure 3 The SPMI bus architecture shown can be seen:

[0065] The first switch K1 and the first switch K2 form a switch module; multiple hosts, multiple slaves, and the integrated circuit IC are connected to the switch module through the SPMI bus. The integrated circuit IC can control the switch module to switch between the first channel, the second channel, and the third channel. If the switch module is switched to the first channel, the host and the slave are connected to the integrated circuit IC through the SPMI bus. If the switch module is switched to the second channel, the host is directly connected to the slave through the SPMI bus, and the integrated circuit IC cuts out the SPMI bus. If the switch module is switched to the third channel, the host is directly connected to the slave through the SPMI bus, and the integrated circuit IC is connected to the SPMI bus.

[0066] It should be noted that the connection method between the switch module and multiple hosts, multiple slaves, and integrated circuits is not limited to Figure 3 The following combination Figure 4 , another SPMI bus architecture provided in an embodiment of the present application is introduced.

[0067] In this embodiment, in the SPMI bus architecture, the SPMI bus also connects 4 hosts and 4 slaves. Of course, the number of hosts and slaves connected by the SPMI bus is not limited to 4.

[0068] like Figure 4 As shown, four hosts are connected to the first switch K1 through the SPMI bus, and the slave and the integrated circuit IC are connected through the first switch K1, and the IC is connected to the four slaves through the second switch K2. The first switch K1 can be used to control the host and the slave to be directly connected, or to control the host to be connected to the IC. The second switch K2 is used to control the slave to be connected or disconnected with the IC.

[0069] The IC may also be connected to the CPU, and the IC and the CPU are not connected in a manner of an SPMI bus. In some embodiments, the IC may be connected to the CPU via an SPI interface or an I2C interface.

[0070] In some embodiments, the IC is used to control the connection mode of the first switch K1 and the second switch K2 to achieve direct connection between the host and the slave, or to achieve connection between the host and the slave through the IC. In addition, when the host is connected to the slave through the IC, the IC is also used to simulate the host to perform bus arbitration, resend data to the slave, and other operations, thereby achieving external control of data interaction between the host and the slave on the SPMI bus.

[0071] In some embodiments, the IC can also receive instructions sent by the CPU, and control the connection mode of the first switch K1 and the second switch K2 based on the instructions, that is, connecting or disconnecting the host and the IC through the first switch K1, and connecting the host and the slave, or connecting the slave and the IC through the second switch K2.

[0072] In some embodiments, the first switch K1 and the second switch K2 may be single-pole double-throw switches. The movable ends of the first switch K1 and the second switch K2 may be movable between ports ① and ②. The movable end of the first switch K1 is located at port ②, and the movable end of the second switch K2 is located at port ②. The IC is connected to the SPMI bus, and the host and the slave are connected through the SPMI bus. The movable end of the first switch K1 is located at port ①, and the movable end of the second switch is located at port ①. The IC is disconnected from the SPMI bus, and the host is directly connected to the slave through the SPMI bus, and the host and the slave exchange data through the SPMI bus.

[0073] In the related art, the CPU cannot adjust the voltage of the power management chip through the SPMI bus. In particular, when the CPU is in a high power consumption operation state, the voltage of the power management chip needs to be reduced.

[0074] Based on this, in an application scenario, the host 1 can be understood as a processing unit in the CPU for sending voltage values, and the slave 1 can be understood as a processing unit in the power management chip.

[0075] The following uses this application scenario as an example. Figure 5 and Figure 6 , introduces the process of CPU adjusting the voltage of the power management chip according to business needs. Figure 5 and Figure 6 In the SPMI bus architecture shown, the switch module and the host 1, slave 1 and IC adopt Figure 3 The connection method shown. Of course, this does not limit the connection method between the switch module and the host, slave and IC.

[0076] The IC can be divided into monitoring mode and data retransmission mode. Figure 5 The IC is in listening mode, and the connection between the first switch K1 and the second switch K2 in the SPMI bus architecture is shown. Figure 6 It shows the connection method of the first switch K1 and the second switch K2 in the SPMI bus architecture when the IC is in data retransmission mode.

[0077] like Figure 5 As shown, the IC is in monitoring mode, the first switch K1 is located at the first channel, the second switch K2 is located at the second channel, the IC is connected to the host 1 through the first switch K1, the host 1 and the slave 1 are connected and can communicate, and the IC monitors the communication data between the host 1 and the slave 1.

[0078] like Figure 6 As shown, the IC is in data retransmission mode, the first switch K1 is located in the first channel, the second switch K2 is also located in the first channel, the connection between the host 1 and the slave 1 is disconnected, the host 1 is connected to the slave 1 through the IC, and the IC can simulate the host 1 and send communication data to the slave 1.

[0079] The IC receives an instruction to control the IC to enter the data retransmission mode, and based on the instruction, disconnects the connection between the host 1 and the slave 1 through the first switch K1 and the second switch K2, and realizes the connection between the host 1 and the slave 1 through the IC. In addition, the IC simulates the host 1 to perform the operation of the host 1, and the IC can also adjust the voltage of the slave 1 to reduce power consumption, so that the voltage of the power management chip is adjusted through the IC.

[0080] In some embodiments, Figure 5 and Figure 6As shown, the IC may include: a switch control module, a bus monitoring module and a data resending module.

[0081] The switch control module is connected to the first switch K1 and the second switch K2, and is used to control the first switch K1 and the second switch K2 to switch between the first channel and the second channel. In some embodiments, the switch control module can receive instructions sent by the CPU, and control the first switch K1 to switch between the first channel and the second channel based on the instructions. In other embodiments, the switch control module controls the first switch K1 to be located in the first channel, that is, the IC is connected to the host (such as Figure 5 After the host 1), the switch control module can also control the second switch K2 to switch between the first channel and the second channel based on the instruction sent by the host.

[0082] The bus monitoring module is connected to the first channel of the first switch K1 and is used to monitor the host (such as Figure 5 The host 1), slave (such as Figure 5 The bus monitoring module monitors the communication data between the slave 1 and the slave 1 in the bus monitoring module, and determines the channel of the second switch K2 according to the monitored communication data. In some embodiments, the bus monitoring module can control the second switch K2 to switch between the first channel and the second channel through the switch control module based on the monitored communication data.

[0083] The data retransmission module is connected to the first channel of the first switch K1 and the first channel of the second switch K2 respectively. The data retransmission module is also connected to the bus monitoring module. The bus monitoring module can send a data retransmission notification message to the data retransmission module based on the monitored communication data. The data retransmission module determines the retransmission data according to the data retransmission notification message, and simulates the host to send the retransmission data to the slave.

[0084] In some embodiments, during the process of the data resending module simulating the host sending data to the slave, the bus monitoring module also continues to monitor the host side bus and performs bus arbitration on the host simulating the slave to ensure that the bus preemption of the data resending module is completed smoothly and prevent the host on the bus from sending data during the data resending module sending data, thereby affecting the normal operation of the bus.

[0085] Figure 7 Shows the host (such as Figure 5 The host 1 in the example sends a signal to the slave (such as Figure 5 During the process of slave 1) writing data, the IC monitors the data of the SPMI bus and simulates the flowchart of the host writing data to the slave.

[0086] like Figure 7 As shown, the method in which the IC monitors the data of the SPMI bus and simulates the host writing data to the slave includes:

[0087] S701. The CPU issues an instruction to control the IC to enter a data resending mode.

[0088] In an application scenario, the CPU can generate and send instructions to the IC to control the IC to enter the data resending mode based on business needs. For example, the CPU monitors that it is currently in a high-power consumption scenario such as gaming or video playback. In order to reduce power consumption, the CPU can generate and send instructions to the IC to control the IC to enter the data resending mode.

[0089] S702, the IC controls itself to connect to the host.

[0090] In some embodiments, a switch control module of the IC controls the IC to connect to the host.

[0091] The instruction generated by the CPU to control the IC to enter the data retransmission mode can be transmitted to the switch control module of the IC through the IC interface. The switch control module controls the first switch K1 based on the instruction to control the IC to enter the data retransmission mode. Figure 5 As shown, the switch is moved to port ②, that is, the first switch K1 is located in the first path, and the IC can be connected to the host via the SPMI bus.

[0092] S703: The IC monitors the communication data on the SPMI bus, and determines whether the communication data includes the first data.

[0093] After the IC is connected to the host via the SPMI bus, the IC can monitor the communication data on the SPMI bus. In some embodiments, the bus monitoring module of the IC monitors the communication data on the SPMI bus.

[0094] The first data may refer to data written by the host to the slave. When the IC monitors that data written by the host to the slave is transmitted on the SPMI bus, it determines that the communication data on the SPMI bus includes the first data.

[0095] In some embodiments, the CPU may configure a monitoring data table in the IC, and the monitoring data table may record the first data and the adjustment value corresponding to the first data, and the adjustment value is used to obtain the second data from the first data. The second data is the content of step S707 below, which is the data sent by the IC to the slave. The IC may determine whether the communication data includes the first data based on the monitoring data table. In some embodiments, the CPU may update the monitoring data table configured by the IC.

[0096] In the aforementioned application scenario, the first data recorded in the monitoring data table refers to the voltage value written by the host to the slave. Figure 5 and Figure 6 As shown, the IC monitors the communication data written by the host 1 to the slave 1 through the SPMI bus, and determines that the communication data includes a voltage value.

[0097] If the IC determines that the communication data includes the first data, then the following steps S704 to S706 are executed. If the IC determines that the communication data does not include the first data, step S703 may be continuously executed.

[0098] S704, the IC disconnects the connection between the host and the slave.

[0099] In some embodiments, if the bus monitoring module determines that the communication data includes the first data, the connection between the host and the slave may be disconnected through the switch control module.

[0100] In some other embodiments, the switch control module controls the second switch K2 as follows: Figure 6 As shown, the switch moves to port ②, that is, the second switch K2 is located in the first path, the connection line between the host and the slave is disconnected, and the IC is still connected to the slave.

[0101] S705, the IC performs bus arbitration on the host simulating the slave.

[0102] As can be seen from step S702 and step S704, the original connection lines between the host and the slave are disconnected, and the IC is connected to the host and the slave respectively. The IC can simulate and replace the host to write data to the slave. In some embodiments, the IC is connected to the host and the slave, which can be understood as: the upper port of the IC is connected to the host through the SPMI bus, and the lower port of the IC is connected to the slave through the SPMI bus.

[0103] In order to prevent the host from sending data to the bus to interfere with the IC's data writing operation when the IC writes data to the slave instead of the host, the IC performs a bus arbitration operation on the slave to the host.

[0104] In some embodiments, as described above, Figure 2 The data retransmission module of the IC performs bus arbitration on the host simulating the slave by pulling up the data signal line of the SPMI bus connected to the upper port. Pulling up the data signal line of the SPMI bus connected to the upper port may refer to setting the data signal line of the SPMI bus connected to the upper port to a high potential, such as a potential above 1.5V.

[0105] S706. The IC determines second data based on the first data.

[0106] The bus monitoring module determines that the communication data includes the first data through step S703, and can send a data resending notification message to the data resending module of the IC. The data resending module receives the data resending notification message, determines that data resending is required, and determines the second data based on the first data.

[0107] In some embodiments, as in step S703, the IC is configured with a monitoring data table, which can record the first data and the adjustment value corresponding to the first data. The IC accumulates the adjustment value corresponding to the first data on the first data to obtain the second data. It can be understood that the adjustment value can be positive or negative.

[0108] In the aforementioned application scenario, in order to achieve power reduction, the IC can reduce the voltage value written by the host to the slave. The adjustment value is a negative value. The IC accumulates the adjustment value based on the first data, which means that the IC subtracts the absolute value of the adjustment value from the voltage value to obtain the voltage value after the value is reduced.

[0109] After the IC executes step S706 and obtains the second data, it can execute steps S711 to S713 to implement the IC simulating the host to write the second data to the slave. In the above application scenario, the second data is the adjusted voltage value, and the IC simulates the host to write the second data to the slave, thereby implementing the voltage adjustment of the power management chip through the IC.

[0110] S707, the IC determines whether the SPMI bus instruction cycle in which the slave performs bus arbitration has reached the stage where the slave seizes the SPMI bus with the highest priority.

[0111] In some embodiments, as described above, Figure 2 The bus arbitration in the SPMI bus instruction cycle includes a stage in which the master or slave on the SPMI bus declares its own priority.

[0112] When the SPMI bus instruction cycle for bus arbitration of the slave reaches the stage where the slave preempts the SPMI bus with the highest priority, execute step S708. When the SPMI bus instruction cycle for bus arbitration of the slave does not reach the stage where the slave preempts the SPMI bus with the highest priority, repeat step S707.

[0113] S708. The IC sends the first slave address to the host.

[0114] The first slave address is a false slave address, and is not the address of any slave connected to the SPMI bus.

[0115] When the slave seizes the SPMI bus with the highest priority, the IC sends the first slave address to the host, which can be understood as informing the host that the SPMI bus is seized by a slave to prevent the host from seizing the bus. Moreover, since the slave address is a false address, it will not affect the data communication process of the real slave connected to the SPMI bus.

[0116] In some embodiments, the data resending module sends the first slave address to the host.

[0117] S709, the IC determines whether the SPMI bus instruction cycle of the slave performing bus arbitration has reached the frame sequence stage.

[0118] In some embodiments, as described above, Figure 2 The SPMI bus instruction cycle includes a frame sequence phase.

[0119] If the SPMI bus instruction cycle for bus arbitration of the slave reaches the frame sequence stage, step S710 is executed; if the SPMI bus instruction cycle for bus arbitration of the slave does not reach the frame sequence stage, step S709 is repeated.

[0120] S710 . The IC writes third data to the host.

[0121] In some embodiments, the host into which the IC writes the third data is different from all hosts connected to the SPMI bus, and it can be understood that its address is also a false address.

[0122] In some other embodiments, the data resending module writes the third data into the register of the host through the master write instruction. The third data can be any data, such as 00.

[0123] The frame sequence stage of the SPMI bus instruction cycle in which the slave performs bus arbitration is the stage in which the slave writes data to the host. Therefore, the IC needs to simulate the slave writing data to the host, and in order not to interfere with the host connected to the SPMI bus, the IC writes third data to the host with the false address.

[0124] S711, IC arbitrates the slave simulating the master.

[0125] In order to prevent the IC from sending data to the bus and interfering with the IC's data writing operation when the IC is writing data to the slave instead of the master, the IC performs the bus arbitration operation of the master on the slave.

[0126] In some embodiments, the data retransmission module performs bus arbitration on the slave simulating the host by pulling up the data signal line of the SPMI bus connected to the lower port. Pulling up the data signal line of the SPMI bus connected to the lower port may refer to setting the data signal line of the SPMI bus connected to the lower port to a high potential, such as a potential above 1.5V.

[0127] In some embodiments, step S711 and step S706 may be performed in parallel, and are not limited to Figure 7 The order in which the displays are executed.

[0128] S712, the IC determines whether the SPMI bus instruction cycle in which the host performs bus arbitration has reached the stage where the host seizes the SPMI bus with the highest priority.

[0129] If the SPMI bus instruction cycle in which the host performs bus arbitration reaches the stage where the host preempts the SPMI bus with the highest priority, execute step S713; if the SPMI bus instruction cycle in which the host performs bus arbitration does not reach the stage where the host preempts the SPMI bus with the highest priority, repeat step S712.

[0130] S713: The IC sends the second data to the slave device.

[0131] In some embodiments, the data retransmission module sends the second data to a slave connected to the SPMI bus. The data retransmission module writes the second data value into the slave through an external register write instruction.

[0132] In the aforementioned application scenarios, combined with Figure 5 and Figure 6 , the IC writes the second data, ie, the adjusted voltage value, into Slave1.

[0133] In some embodiments, after the IC writes the second data into the slave, the switch control module controls the first switch and the second switch to switch from the first channel to the second channel, so that the host re-establishes a connection line with the slave, and the host and the slave can directly communicate data. In addition, the IC is completely cut out of the SPMI bus and can enter a dormant stage, waiting for the CPU to send instructions.

[0134] Figure 7 The figure shows the process of IC simulating the host writing data to the slave. In actual application, when the IC receives the instruction to control the IC to enter the data retransmission mode, the IC disconnects the connection between the host and the slave through the first switch K1 and the second switch K2, and after the host and the slave are connected, the IC can also simulate the slave writing data to the host.

[0135] The process of IC simulating the slave writing data to the host may include:

[0136] After the IC receives the instruction to control the IC to enter the data retransmission mode, the IC controls itself to connect to the slave and monitor the communication data on the bus. After determining that the communication data includes the first data, the IC disconnects the connection between the host and the slave and connects to the host. The first data refers to the data written by the slave to the host.

[0137] IC reads the first data from the slave and obtains the second data based on the first data. The second data refers to the data written by IC to the host. The way IC obtains the second data based on the first data can be found in Figure 7 The content of step S706 in .

[0138] After reading the first data, the IC arbitrates the slave simulating the host. The IC determines the SPMI bus instruction cycle of the host performing bus arbitration, and when it reaches the stage where the host seizes the SPMI bus with the highest priority, it sends the first host address to the slave; the first host address is also a false address. In addition, the IC determines the SPMI bus instruction cycle of the host performing bus arbitration, and when it reaches the frame sequence stage, the IC writes the third data to the false slave. The third data can be any data.

[0139] The IC also arbitrates the host simulating the slave. The IC determines the SPMI bus instruction cycle of the slave performing bus arbitration, and when the slave seizes the SPMI bus with the highest priority, it sends the second data to the host, thus realizing the IC simulating the slave and writing data to the host.

[0140] The SPMI bus architecture provided in the embodiment of the present application can be applicable to mobile phones, tablet computers, desktops, laptops, notebook computers, ultra-mobile personal computers (UMPC), handheld computers, netbooks, personal digital assistants (PDA), wearable electronic devices, smart watches and other electronic devices.

[0141] Take mobile phones as an example. Figure 8 This is an example of the composition of an electronic device provided in an embodiment of the present application. Figure 8 As shown, the electronic device 800 may include a processor 810, an internal memory 820, a USB interface 830, a charging management module 840, a power management module 841, and a battery 842, etc.

[0142] It is to be understood that the structure illustrated in this embodiment does not constitute a specific limitation on the electronic device 800. In other embodiments, the electronic device 800 may include more or fewer components than shown in the figure, or combine some components, or separate some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0143] The processor 810 can be understood as the system-on-chip SoC proposed in the foregoing content, and can include one or more processing units, for example: the processor 810 can include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, a smart sensor hub (sensor hub) and / or a neural-network processing unit (neural-network processing unit, NPU), etc. Among them, different processing units can be independent devices or integrated in one or more processors.

[0144] In some embodiments, an application processor (AP) may serve as a central processing unit (CPU) of an electronic device.

[0145] In some embodiments, the processor 810 may also include an integrated circuit (IC), and the working process of the IC can be found in the above content, which will not be repeated here. In other embodiments, the functions of the integrated circuit IC can also be implemented by other devices, such as a field programmable gate array (FPGA), a microcontroller unit (MCU), an active device circuit, and an application specific integrated circuit (ASIC). IC, FPGA, MCU, active device circuit and ASIC can all be understood as chips, and the chip can be understood as including a processor and an interface. The chip can communicate with external components through the interface, and the processor can drive the chip to execute the bus control method proposed in the above content.

[0146] The processor 810 may also be provided with a memory for storing instructions and data. In some embodiments, the memory in the processor 810 is a cache memory. The memory may store instructions or data that the processor 810 has just used or cyclically used. If the processor 810 needs to use the instruction or data again, it may be directly called from the memory. This avoids repeated access, reduces the waiting time of the processor 810, and thus improves the efficiency of the system.

[0147] The internal memory 820 can be used to store computer executable program codes, and the executable program codes include instructions. The processor 810 executes various functional applications and data processing of the electronic device 800 by running the instructions stored in the internal memory 820. The internal memory 820 may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc. The data storage area may store data created during the use of the electronic device 800 (such as audio data, a phone book, etc.), etc. In addition, the internal memory 820 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor 810 executes various functional applications and data processing of the electronic device 800 by running the instructions stored in the internal memory 820, and / or the instructions stored in the memory provided in the processor.

[0148] The charging management module 840 is used to receive charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 840 may receive charging input from a wired charger through the USB interface 830. In some wireless charging embodiments, the charging management module 840 may receive wireless charging input through a wireless charging coil of the electronic device 800. While the charging management module 840 is charging the battery 842, it may also power the electronic device 800 through the power management module 841.

[0149] The power management module 841 is used to connect the battery 842, the charging management module 840 and the processor 810. The power management module 841 receives input from the battery 842 and / or the charging management module 840 to power the processor 810, the internal memory 820, etc. The power management module 841 can also be used to monitor parameters such as battery capacity, battery cycle number, battery health status (leakage, impedance), etc. In some embodiments, the power management module 841 can also be set in the processor 810. In other embodiments, the power management module 841 and the charging management module 840 can also be set in the same device.

[0150] In some embodiments, the power management module 841 may include a power management chip.

[0151] Another embodiment of the present application further provides a computer-readable storage medium, which stores instructions, and when the computer-readable storage medium is executed on a computer or a processor, the computer or the processor executes one or more steps in any of the above methods.

[0152] The computer-readable storage medium may be a non-temporary computer-readable storage medium, for example, the non-temporary computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0153] Another embodiment of the present application further provides a computer program product including instructions. When the computer program product is run on a computer or a processor, the computer or the processor executes one or more steps in any of the above methods.

Claims

1. A chip, characterized in that: Including processor and interface; The processor is used to receive a first instruction through the interface; based on the first instruction, control the chip to access the system power management interface SPMI bus, and after the chip accesses the SPMI bus, monitor the data transmitted by the SPMI bus, the SPMI bus connects the first node and the second node, and is used to transmit communication data between the first node and the second node; The processor is further configured to control the chip to establish a connection with the first node and the second node through the SPMI bus, disconnect the connection between the first node and the second node, obtain second data based on the first data, and send the second data to the second node when monitoring that the data transmitted by the SPMI bus includes the first data; The first data is data written by the first node to the second node.

2. The chip according to claim 1, characterized in that: The processor is further configured to: when monitoring that the data transmitted by the SPMI bus includes the first data, simulate the second node to perform bus arbitration on the first node.

3. The chip according to claim 1 or 2, characterized in that: The processor is further configured to: when monitoring that the data transmitted by the SPMI bus includes the first data, simulate the first node to perform bus arbitration on the second node.

4. The chip according to any one of claims 1 to 3, characterized in that: The processor controls the chip to send the second data to the second node, including: When the first node preempts the SPMI bus with the highest priority, the processor controls the chip to send the second data to the second node.

5. The chip according to claim 2, characterized in that: After simulating the second node to perform bus arbitration on the first node, the processor is further used to: when the SPMI bus instruction cycle of the second node performing bus arbitration reaches the stage where the second node preempts the SPMI bus with the highest priority, control the chip to send a first preset address to the first node.

6. The chip according to claim 5, characterized in that: After the processor controls the chip to send the first preset address to the first node, the processor is also used to: when the SPMI bus instruction cycle for bus arbitration at the second node reaches the frame sequence stage, control the chip to write third data to a third node, and the third node has a second preset address.

7. The chip according to claim 6, characterized in that: The second preset address is different from the address of the first node.

8. The chip according to claim 5, characterized in that: The first preset address is different from the address of the second node.

9. A bus architecture, characterized in that: include: A first node, a second node, a switch module and a chip; The first node and the second node are connected to the SPMI bus and the chip through the switch module; The chip is used to receive a first instruction, access the SPMI bus through the switch module based on the first instruction, and after accessing the SPMI bus, monitor the data transmitted by the SPMI bus; When it is monitored that the data transmitted by the SPMI bus includes the first data, the switch module is used to establish a connection with the first node and the second node through the SPMI bus, and disconnect the connection between the first node and the second node; further configured to obtain second data based on the first data, and send the second data to the second node; The first data is data written by the first node to the second node.

10. The bus architecture according to claim 9, characterized in that: The chip is also connected to a processor, and the first instruction is sent to the chip by the processor.

11. The bus architecture according to claim 10, characterized in that: The chip and the processor are connected via an SPI interface or an I2C interface.

12. The bus architecture according to any one of claims 9 to 11, characterized in that: The switch module comprises: a first switch and a second switch; The first switch connects the first node and the chip through the SPMI bus, and the first switch is used to control the first node to be connected or disconnected from the chip; The second switch connects the first node, the second node and the chip through the SPMI bus, and the second switch is used to control the first node and the second node to be directly connected, or to control the second node to be connected to the chip.

13. The bus architecture according to any one of claims 9 to 11, characterized in that: The switch module comprises: a first switch and a second switch; The first switch connects the first node, the second node, and the chip through the SPMI bus, and the first switch is used to control the first node and the second node to be directly connected, or to control the first node to be connected to the chip; The second switch connects the second node and the chip via the SPMI bus, and the second switch is used to control the second node to be connected or disconnected from the chip.

14. An electronic device, characterized in that: include: A processor and a bus architecture as claimed in any one of claims 9 to 13; The processor is used to generate a first instruction and send the first instruction to the chip of the bus architecture.

15. A bus control method, characterized in that: Applied to a chip, the method comprises: receiving a first instruction; Based on the first instruction, access the system power management interface SPMI bus, and after accessing the SPMI bus, monitor the data transmitted by the SPMI bus; the SPMI bus connects the first node and the second node, and is used to transmit communication data between the first node and the second node; When monitoring that the data transmitted by the SPMI bus includes first data, establishing a connection with the first node and the second node through the SPMI bus, disconnecting the connection between the first node and the second node, and obtaining second data based on the first data; the first data is the data written by the first node to the second node; The second data is sent to the second node.

16. The bus control method according to claim 15, characterized in that: Also includes: When it is monitored that the data transmitted by the SPMI bus includes the first data, bus arbitration is performed on the first node by simulating the second node.

17. The bus control method according to claim 15 or 16, characterized in that: Also includes: When it is monitored that the data transmitted by the SPMI bus includes the first data, bus arbitration is performed on the second node simulating the first node.

18. The bus control method according to any one of claims 15 to 17, characterized in that: The sending the second data to the second node comprises: When the first node preempts the SPMI bus with the highest priority, the second data is sent to the second node.

19. The bus control method according to claim 16, characterized in that: After simulating the second node to perform bus arbitration on the first node, the method further includes: When the SPMI bus instruction cycle in which the second node performs bus arbitration reaches the stage where the second node seizes the SPMI bus with the highest priority, a first preset address is sent to the first node.

20. The bus control method according to claim 19, characterized in that: After sending the first preset address to the first node, the method further includes: When the SPMI bus instruction cycle for bus arbitration at the second node reaches the frame sequence stage, third data is written to the third node, and the third node has a second preset address.

21. A computer-readable storage medium, characterized in that: Used to store a computer program, which, when executed, is specifically used to implement the bus control method as described in any one of claims 15 to 20.

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