Integrated circuit, method, medium, device and chip for data transmission

Abstract

The embodiment of the invention discloses an integrated circuit, a method, a medium, equipment and a chip for data transmission, the integrated circuit comprises at least two processing elements, the first processing element of any one of the at least two processing elements comprises a first buffer and a first memory; the first processing element is configured to determine the data transmission priority of the first memory and a second processing element cascaded in front of the first processing element according to the current cache state of the first cache; acquiring data to be transmitted according to the data transmission priority; and caching the to-be-transmitted data to the first buffer, so that the to-be-transmitted data can be read by a later cascade circuit of the first processing element. According to the embodiment of the invention, the condition that all the buffers on the data transmission path are fully stored can be avoided, and the deadlock problem of the annular interconnection network is effectively solved.

Description

Technical Field

[0001] The present disclosure relates to integrated circuit technology, and more particularly to an integrated circuit, method, medium, device and chip for data transmission. Background Art

[0002] In on-chip interconnection networks, ring interconnection networks are a common topology. Data transmission in a ring interconnection network forms a data loop. When all buffers (such as first-in-first-out queues) on the data loop are full, a ring-shaped data dependency is formed on the data loop, and all data (or transmission load) cannot be transmitted forward. Therefore, it is easy to cause deadlock, which in turn affects data transmission efficiency. Summary of the invention

[0003] Embodiments of the present disclosure provide an integrated circuit, method, medium, device, and chip for data transmission to avoid deadlock in a data loop and ensure data transmission efficiency.

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided an integrated circuit for data transmission, comprising: at least two processing elements, wherein a first processing element of any one of the at least two processing elements comprises a first buffer and a first memory; the first processing element is configured to: determine, according to a current cache state of the first buffer, a data transmission priority between the first memory and a second processing element cascaded previously to the first processing element; obtain data to be transmitted according to the data transmission priority; and cache the data to be transmitted to the first buffer so that the data to be transmitted can be read by a subsequent cascade circuit of the first processing element.

[0005] A second aspect of an embodiment of the present disclosure provides a data transmission method, comprising: determining, based on a current cache state of a first cache in a first processing element, a data transmission priority between a first memory in the first processing element and a second processing element cascaded previously to the first processing element; acquiring data to be transmitted according to the data transmission priority; and caching the data to be transmitted in the first cache so that the data to be transmitted can be read by a subsequent cascade circuit of the first processing element.

[0006] According to a third aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is used to execute the data transmission method described in any of the above embodiments of the present disclosure.

[0007] According to a fourth aspect of an embodiment of the present disclosure, an electronic device is provided, comprising: a processor; a second memory for storing executable instructions of the processor; and the processor is configured to read the executable instructions from the second memory and execute the instructions to implement the data transmission method described in any of the above embodiments of the present disclosure.

[0008] A fifth aspect of the embodiments of the present disclosure provides a computer program product. When instructions in the computer program product are executed by a processor, the data transmission method provided by any of the above embodiments of the present disclosure is executed.

[0009] According to a sixth aspect of the embodiments of the present disclosure, a chip is provided, wherein the chip includes: an integrated circuit for data transmission provided by any of the above embodiments of the present disclosure.

[0010] Based on the integrated circuit, method, medium, device and chip for data transmission provided by the above-mentioned embodiments of the present disclosure, for any processing element (referred to as the first processing element) on the data transmission path, the data transmission priority of two data sources (i.e., the first memory and the second processing element) can be determined according to the current cache state of the first cache inside the first processing element for caching the data to be transmitted, and then the data to be transmitted is obtained according to the data transmission priority, and the data to be transmitted is cached in the first cache. In this way, when the remaining storage space in the first cache is small, the data to be transmitted can be obtained from the data source with a higher data transmission priority, for example, the data to be transmitted can be obtained from the second processing element first. In this way, the cache of the second processing element can release part of the cache space, so that at any time there is at least one cache that is not full on the data transmission path, thereby avoiding the situation where all the caches on the data transmission path are full, and thus effectively solving the deadlock problem of the ring interconnection network. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is an exemplary application scenario of the integrated circuit for data transmission provided by the present disclosure;

[0012] Figure 2 is a schematic diagram of the structure of an integrated circuit for data transmission provided by an exemplary embodiment of the present disclosure;

[0013] Figure 3 is a schematic structural diagram of an integrated circuit for data transmission provided by another exemplary embodiment of the present disclosure;

[0014] Figure 4 is a schematic diagram of the structure of a processing element provided by an exemplary embodiment of the present disclosure;

[0015] Figure 5is a schematic structural diagram of an integrated circuit for data transmission provided by yet another exemplary embodiment of the present disclosure;

[0016] Figure 6 is a flowchart of a data transmission method provided by an exemplary embodiment of the present disclosure;

[0017] Figure 7 is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure;

[0018] Figure 8 is a flowchart of a data transmission method provided by yet another exemplary embodiment of the present disclosure;

[0019] Fig. 9 is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure;

[0020] Fig.10 is a flowchart of a data transmission method provided by yet another exemplary embodiment of the present disclosure;

[0021] Fig.11 is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure;

[0022] Fig.12 It is a structural diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0024] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0025] SUMMARY OF THE DISCLOSURE

[0026] In the process of implementing the present disclosure, the inventors discovered that in the on-chip ring interconnection network topology of the chip, the data transmission of the ring interconnection network forms a data loop. When all buffers (such as first-in-first-out queues) on the data loop are full, a ring data dependency is formed on the data loop, and all data (or transmission load) cannot be transmitted forward. Therefore, it is easy to cause a deadlock state of the ring interconnection network, thereby affecting the data transmission efficiency.

[0027] Exemplary Overview

[0028] Figure 1This is an exemplary application scenario of the integrated circuit for data transmission provided by the present disclosure. Figure 1 As shown, the application scenario takes the on-chip ring interconnection network as an example. The ring interconnection network may include at least two processing elements, and at least two processing elements are interconnected to form a ring interconnection network. As shown in the figure, the ring interconnection network includes processing element 11, processing element 12, ..., processing element 1n, a total of n processing elements, n is an integer greater than 1, each processing element 1i (i = 1, 2, ..., n) may include a buffer 1i1, during data transmission, each processing element 1i can cache the data to be transmitted through the buffer 1i1, for any processing element 1i, the processing element 1i cascaded later (if i is less than n, then j = i + 1, if i = n, then j = 1) reads the data to be transmitted from the buffer 1i1 of the processing element 1i, thereby realizing data transmission. The data sources of the data to be transmitted in the processing element 1i include two, namely, the processing element 1k cascaded before the processing element 1i (if i is greater than 1, then k=i-1, if i=1, then k=n) and the memory inside the processing element 1i, that is, the processing element 1i can cache the data from the processing element 1k cascaded before into the buffer 1i1, and can also cache the data in the internal memory of the processing element 1i into the buffer 1i1, so that the processing element 1j cascaded after can read the data to be transmitted from the buffer 1i1. The data of the processing element 1k cascaded before comes from the buffer 1k1 in the processing element 1k. In the integrated circuit for data transmission disclosed in the present invention, for any processing element (referred to as the first processing element, also referred to as the first processing unit) 1i among the processing elements, the first processing element 1i includes a buffer (referred to as the first buffer) 1i1 and a memory (referred to as the first memory). The first processing element 1i is configured to: determine the data transmission priority of the first memory and the second processing element 1k cascaded in front of the first processing element 1i according to the current cache state of the cache 1i1; obtain the data to be transmitted according to the data transmission priority; cache the data to be transmitted to the first cache 1i1 so that the data to be transmitted can be read by the subsequent cascade circuit of the first processing element 1i (for example, the subsequent cascade processing element 1j) to realize data transmission. In this way, when the remaining storage space of the first cache 1i1 is small, the data to be transmitted can be obtained from the data source with a higher data transmission priority, for example, the data to be transmitted can be obtained from the second processing element 1k in priority, so that the cache 1k1 of the second processing element 1k can release part of the cache space to ensure that there is at least one cache on the data transmission path that is not full of data at any time, so as to avoid the situation where all the caches on the data transmission path are full of data, and effectively solve the deadlock problem of the ring interconnection network.

[0029] In practical applications, the integrated circuit for data transmission according to the embodiment of the present disclosure is not limited to being applied to a ring interconnection network, but can also be applied to other non-ring topology structures, which are not specifically limited.

[0030] Exemplary Devices

[0031] Figure 2 is a schematic diagram of the structure of an integrated circuit for data transmission provided by an exemplary embodiment of the present disclosure. This embodiment can be applied in chips, such as chips in terminal devices such as vehicle-mounted computing platforms, mobile phones, and tablets, for example. Figure 2 As shown, the integrated circuit for data transmission (referred to as integrated circuit) of the embodiment of the present disclosure may include: at least two processing elements, in which n processing elements are taken as an example, namely, processing element 11, processing element 12, ..., processing element 1n, where n is an integer greater than 1. A first processing element 1i (i=1, 2, ..., n) of any of the at least two processing elements includes a buffer (referred to as a first buffer) 1i1 and a memory (referred to as a first memory) 1i2.

[0032] The first processing element 1i is configured to:

[0033] According to the current cache state of the first buffer 1i1, the data transmission priority (or simply the priority) of the first memory 1i2 and the second processing element 1k (if i is greater than 1, then k=i-1) cascaded before the first processing element 1i is determined; according to the data transmission priority, the data to be transmitted is obtained; the data to be transmitted is cached in the first buffer 1i1 so that the data to be transmitted can be read by the subsequent cascade circuit of the first processing element 1i.

[0034] The number of processing elements included in the integrated circuit can be determined according to the requirements of the actual application scenario, and is not limited in the embodiments of the present disclosure. For example, the number n of processing elements can be 2, 3, 4, ...

[0035] In some optional embodiments, the processing element 1i can be any device that has data interaction requirements with other devices. For example, in the fields involving computer vision such as intelligent driving and security monitoring, there is a need for data transmission between processing devices such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural network Processing Unit), DPU (Data Processing Unit), TPU (Tensor Processing Unit), ISP (Image Signal Processing) units, etc. These processing devices can be respectively used as processing elements in the embodiments of the present disclosure.

[0036] In some optional embodiments, at least two processing elements are interconnected to form a ring interconnection topology. Figure 2 , for processing element 11, if processing element 11 is interconnected with processing element 1n, a ring interconnection topology is formed, and the preceding cascade circuit of processing element 11 is processing element 1n, and the following cascade circuit of processing element 1n is processing element 11. For example, in an intelligent driving scenario, there is a need for data interaction between processing elements for perception processing, processing elements for positioning processing, and processing elements for planning control, which can be respectively used as processing elements in the embodiments of the present disclosure. Perception processing is a processing process of perceiving the surrounding environment of the vehicle based on sensor data and obtaining perception results. The perception results may include perceived obstacles and road elements around the vehicle. Positioning processing is a processing process of real-time positioning of the vehicle based on the perception results. Planning control is a process of performing path planning based on the perception results and positioning results, and controlling the driving state of the vehicle according to the planned path. The driving state of the vehicle also needs to be provided to the perception processing element for continuing the perception processing, so that the processing elements are interconnected to form a ring interconnection topology. It can be understood that the above-mentioned processing elements for perception processing, processing elements for positioning processing, and processing elements for planning control are only an exemplary description and are not a limitation of the embodiments of the present application. In practical applications, the processing of perception, positioning, planning and control is not limited to corresponding to one processing element respectively. For example, at least one processing element can also be used to collaboratively realize intelligent driving functions such as perception, positioning, planning and control. Each processing element in the at least one processing element can be used as a processing element in the embodiment of the present disclosure. In addition, the processing element of the embodiment of the present disclosure is not limited to the processing element in the intelligent driving scenario. As long as there is a data transmission demand between multiple processing elements, data transmission can be realized through the integrated circuit for data transmission of the embodiment of the present disclosure.

[0037] In some optional embodiments, the buffer li1 may be any memory with a buffering function. For example, the buffer li1 may be a FIFO (First Input First Output) buffer or other types of buffers.

[0038] In some optional embodiments, the memory 1i2 may be any memory with data storage function. For example, the memory 1i2 may include DRAM (Dynamic Random Access Memory), such as DDR (Double Data Rate Synchronous Dynamic Random-Access Memory), LPDDR (Low Power Double Data Rate Synchronous Dynamic Random-Access Memory), etc., without specific limitation.

[0039] In some optional embodiments, the current cache state of the first buffer 1i1 is a state indicating the degree of occupancy of the first buffer 1i1. The current cache state may include multiple preset states, for example, multiple preset states of different degrees may be included according to the degree of occupancy of the first buffer 1i1, and each preset state may include, for example, multiple preset states such as an empty state, an almost empty state, an intermediate state, an almost full state, and a full state. Among them, the empty state can be expressed as the ratio of the occupied cache space to the overall cache space (which can be referred to as the occupied ratio) being less than the first threshold, the almost empty state (which can also be called the almost empty state) can be expressed as the ratio of the occupied cache space to the overall cache space being greater than (or equal to) the first threshold and less than the second threshold, the intermediate state can be expressed as the ratio of the occupied cache space to the overall cache space being greater than (or equal to) the second threshold and less than the third threshold, the almost full state (which can also be called the almost full state) can be expressed as the ratio of the occupied cache space to the overall cache space being greater than (or equal to) the third threshold and less than the fourth threshold, and the full state (which can also be called the full state) can be expressed as the ratio of the occupied cache space to the overall cache space being greater than or equal to the fourth threshold. The first threshold, the second threshold, the third threshold and the fourth threshold can be set according to actual needs. For example, the third threshold and the fourth threshold are determined according to the bandwidth of each data transmission, so that when the occupied ratio is greater than the fourth threshold, the remaining free cache space cannot support caching the data transmitted once, that is, the remaining free cache space is smaller than the size of the data to be transmitted. When the occupied ratio is greater than the third threshold and less than the fourth threshold, the remaining free cache space can support caching the data transmitted at least once. The specific values ​​of each threshold are not limited in the embodiments of the present disclosure. For another example, each preset state may include a first preset state (i.e., a full state, an occupied ratio greater than or equal to the fourth threshold), a second preset state (a state that is about to be full but not full, an occupied ratio less than the fourth threshold and greater than or equal to the third threshold), and other preset states (an occupied ratio less than the third threshold). The other preset states cover the above-mentioned empty state, almost empty state and intermediate state. The division of specific cache states is not limited.

[0040] In some optional embodiments, the second processing element 1k cascaded in front of the first processing element 1i refers to the previous processing element on which the input data of the first processing element 1i depends, such as Figure 2, the second processing element cascaded before the processing element 12 is the processing element 11, and the second processing element cascaded before the processing element 13 is the processing element 12. The data transmission priority between the first memory 1i2 and the second processing element 1k may include the following two situations: the data transmission priority of the second processing element 1k is higher than that of the first memory 1i2, and the data transmission priority of the second processing element 1k is the same as that of the first memory 1i2.

[0041] In some optional embodiments, the correspondence between the various cache states of the first cache 1i1 and the data transmission priorities can be preset, and the data transmission priorities between the first memory 1i2 and the second processing element 1k can be determined according to the current cache state of the first cache 1i1 and the correspondence between the various pre-configured cache states and the data transmission priorities. For example, the data transmission priorities corresponding to the empty state, the almost empty state, and the intermediate state are all the same as the data transmission priorities between the first memory 1i2 and the second processing element 1k, and the data transmission priority corresponding to the almost full state is that the data transmission priority of the second processing element 1k is higher than the data transmission priority of the first memory 1i2. The specific correspondence between the various cache states and the data transmission priorities can be set according to actual needs, and is not limited to the relationship in the above example.

[0042] In some optional embodiments, the data transmission priority between the first memory 1i2 and the second processing element 1k may also include a priority type for indicating the need to pause the acquisition of the data to be transmitted from the first memory 1i2 and the second processing element 1k. For example, the data transmission priority may include three types: priority, same, and pause. Priority indicates that the data transmission priority of the second processing element 1k is higher than that of the first memory 1i2, same indicates that the data transmission priority of the second processing element 1k is the same as that of the first memory 1i2, and pause indicates that the acquisition of the data to be transmitted needs to be paused. For example, when the current cache state of the first buffer 1i1 is full, the data transmission priority between the second processing element 1k and the first memory 1i2 is determined to be paused.

[0043] In some optional embodiments, the data transmission priorities of the first memory 1i2 and the second processing element 1k can be represented by priority numbers, for example, the priority of the second processing element 1k is 1, and the priority of the first memory 1i2 is 2, which means that the priority of the second processing element 1k is level 1, and the priority of the first memory 1i2 is level 2, and level 1 is higher than level 2. In practical applications, the data transmission priority can also be represented in other ways, as long as the data transmission priority of the first memory 1i2 and the second processing element 1k can be determined.

[0044] In some optional embodiments, the data to be transmitted is data that needs to be transmitted by the first processing element 1i to the subsequent cascade circuit. Possible data sources of the data to be transmitted include the second processing element 1k and the first memory 1i2. The data transmission priority of the first memory 1i2 and the second processing element 1k determines the data source of the current data to be transmitted. The data to be transmitted is obtained preferentially from the data source with a higher priority. If the data transmission priority of the first memory 1i2 and the second processing element 1k is the same, the first memory 1i2 and the second processing element 1k can both be used as data sources, and the data of the first memory 1i2 and the second processing element 1k can both be used as data sources, and the data of the first memory 1i2 and the second processing element 1k can both be used as data sources. If the data transmission priority of the second processing element 1k is higher than the priority of the first memory 1i2, the data to be transmitted is obtained from the second processing element 1k in priority, that is, the data from the second processing element 1k (which can be called the first data) is taken as the data to be transmitted, and the data to be transmitted is cached in the first buffer 1i1. For the data in the first memory 1i2 (which can be called the second data), if the first buffer 1i1 can still store the second data, the second data can be cached in the first buffer 1i1. If the first buffer 1i1 cannot cache the second data, the acquisition of the second data from the first memory 1i2 can be suspended, and the cache space of the first buffer 1i1 can be released before the second data is obtained from the first memory 1i2, and the second data is taken as the data to be transmitted, and the data to be transmitted is cached in the first buffer 1i1. The data cached in the first buffer 1i1 is the data that needs to be transmitted to the subsequent cascade circuit. The subsequent cascade circuit can read the data from the first buffer 1i1 to realize the transmission of data from the first processing element 1i to the subsequent cascade circuit. Each processing element can realize data transmission according to the above process, thereby realizing data transmission between the processing elements in the previous and next cascades.

[0045] In some optional embodiments, the subsequent cascade circuit of the first processing element 1i can be determined according to the position of the first processing element 1i in each processing element. For example, for processing element 1n, if buffer 1n1 is connected to processing element 11, the subsequent cascade circuit of processing element 1n is processing element 11. If buffer 1n of processing element 1n is connected to an output interface or pin of an integrated circuit, the subsequent cascade circuit of buffer 1n1 is an external circuit of the integrated circuit. For other processing elements 1i (i is not equal to n), the subsequent cascade circuit of processing element 1i is 1j (j=i+1).

[0046] In some optional embodiments, the number of the processing elements 1j cascaded after the first processing element 1i may be one or more, and is not specifically limited. For example, the processing elements cascaded after the perception processing element may include a positioning processing element and a planning control element, that is, the perception result of the perception processing element may be transmitted to the positioning processing element and the planning control element respectively, the positioning processing element locates the vehicle based on the perception result, the positioning result is transmitted to the planning control element, and the planning control element performs planning control based on the perception result and the positioning result.

[0047] The integrated circuit for data transmission provided in this embodiment can determine the data transmission priority of two data sources (i.e., the first memory and the second processing element) according to the current cache state of the first cache inside the first processing element for caching the data to be transmitted, for any processing element on the data transmission path (referred to as the first processing element), and then obtain the data to be transmitted according to the data transmission priority, and cache the data to be transmitted in the first cache. In this way, when the remaining storage space in the first cache is small, the data to be transmitted can be obtained from the data source with a higher data transmission priority in priority, for example, the data to be transmitted can be obtained from the second processing element in priority, so that the cache of the second processing element can release part of the cache space, so that at any time there is at least one cache that is not full on the data transmission path, thereby avoiding the situation where all the caches on the data transmission path are full, and effectively solving the deadlock problem of the ring interconnection network.

[0048] Figure 3 is a schematic structural diagram of an integrated circuit for data transmission provided by another exemplary embodiment of the present disclosure.

[0049] In some optional embodiments, based on any of the above embodiments, Figure 3 As shown, the first processing element 1i also includes: an interface (referred to as a first interface) 1i3 and an arbitrator (referred to as a first arbitrator) 1i4.

[0050] The first interface 1i3 is used to receive the first data from the second processing element 1k.

[0051] The first arbiter 1i4 is configured to: determine the data transmission priority between the first memory 1i2 and the second processing element 1k according to the current cache status of the first cache 1i1; determine at least one of the first data received by the first interface 1i3 and the second data in the first memory 1i2 as data to be transmitted according to the data transmission priority, and cache the data to be transmitted to the first cache 1i1.

[0052] The first interface 1i4 may be an interface between processing elements that meets a corresponding communication protocol. The first processing element 1i may read data from the buffer 1k1 of the second processing element 1k through the first interface 1i4 and use the read data as the first data.

[0053] In some optional embodiments, the first interface 1i4 is connected to the second processing element 1k and the first arbiter 1i4 respectively. The first arbiter 1i4 is connected to the first memory 1i2 and the first buffer 1i1 respectively.

[0054] In some optional embodiments, the first arbitrator 1i4 can be any logic device, controller, processor, etc. with corresponding arbitration functions. The first arbitrator li4 can be implemented based on hardware, software, or a combination of hardware and software, and is not specifically limited. The first arbitrator 1i4 is configured to: determine the data transmission priority between the first memory 1i2 and the second processing element 1k according to the current cache state of the first buffer 1i1; if the priority of the second processing element 1k is higher than the priority of the first memory 1i2, the first data received by the first interface 1i3 is determined as the data to be transmitted, and the data to be transmitted is cached in the first buffer 1i1. If the priority of the second processing element 1k is the same as the priority of the first memory 1i2, the first data and the second data in the first memory 1i2 are respectively used as the data to be transmitted, and the first data and the second data are cached in the first buffer 1i1.

[0055] In an embodiment of the present disclosure, a first processing element communicates with a second processing element through a first interface, receives first data from the second processing element, and then arbitrates the first data and second data of a first memory according to a current cache state of the first cache through a first arbitrator, determines data to be transmitted, and caches the data to be transmitted in the first cache, thereby realizing effective control of data transmission, so that when the first cache is about to be full, the data to be transmitted is obtained from the second processing element on a priority basis, so that the cache of the second processing element can release part of the cache space, thereby ensuring that there is always at least one cache in a not full state on the data transmission path, thereby avoiding the problem of deadlock.

[0056] In some optional embodiments, the first arbitrator 1i4 is further configured to:

[0057] According to the state signal output by the first buffer 1i1, the current buffer state of the first buffer 1i1 is determined.

[0058] The state signal output by the first buffer li1 is a signal representing the current occupancy degree of the first buffer 1i1.

[0059] In some optional embodiments, the status signal output by the first buffer 1i1 can be obtained by monitoring the occupancy of the cache space by the first buffer. For example, the current storage capacity of the first buffer 1i1 can be determined by counting the difference between the number of writes and reads, and the status signal that the first buffer 1i1 should output can be determined based on the current storage capacity and the total storage capacity of the first buffer. For another example, the read pointer and the write pointer point to the read address and the write address of the cache space respectively, and the status signal that the first buffer 1i1 should output is determined based on the relationship between the read address and the write address and the address range of the cache space of the first buffer 1i1. The specific method for determining the status signal output by the first buffer 1i1 is determined by the specific function of the first buffer 1i1, and is not limited by the embodiments of the present disclosure.

[0060] In some optional embodiments, the integrated circuit of the embodiment of the present disclosure may further include a control unit, which is configured to determine the current cache state of the first buffer 1i1 according to the state signal output by the first buffer 1i1. The control unit is connected to the first buffer 1i1 and the first arbiter 1i4 respectively, and transmits the current cache state to the first arbiter 1i4. The first arbiter 1i4 determines the data transmission priority between the first memory 1i2 and the second processing element 1k according to the current cache state, and obtains the data to be transmitted according to the data transmission priority, and caches the data to be transmitted to the first buffer 1i1.

[0061] In some optional embodiments, the state signal can represent different cache states of the first buffer 1i1 through different signal values. For example, if the state signal is a first signal value, it indicates that the first buffer 1i1 is in a first preset state (e.g., a full state); if the state signal value is a second signal value, it indicates that the first buffer 1i1 is in a second preset state (e.g., a state that is almost full but not full); if the state signal value is a third signal value, it indicates that the first buffer 1i1 is in a third preset state (e.g., a state that is not almost full), and so on.

[0062] In some optional embodiments, the state signal may include multiple state signals, for example, the state signal may include a first state signal (e.g., a full signal indicating whether it is full), a second state signal (e.g., an almost full signal indicating whether it is almost full), a third state signal (e.g., an almost empty signal indicating whether it is almost empty), and a fourth state signal (e.g., an empty signal indicating whether it is empty). Furthermore, the current cache state of the first buffer 1i1 may be comprehensively determined based on the current signal values ​​of the multiple state signals. The specific state signal may be determined according to the output function of the first buffer 1i1. For example, the FIFO buffer may output a full signal, an almost full signal, an almost empty signal, and an empty signal, each of which may include two preset values, such as 1 and 0. For the full signal, 1 indicates full, and 0 indicates not full. For the almost full signal, 1 indicates almost full, and 0 indicates not almost full. For the almost empty signal, 1 indicates almost empty, and 0 indicates not almost empty. For the empty signal, 1 indicates empty, and 0 indicates not empty. Since "not full" includes multiple situations such as "almost full" and "not nearly full", and "not nearly full" includes multiple situations such as "not nearly empty", "almost empty", and "empty", the current cache state of the first buffer 1i1 can be determined by combining the specific signal values ​​of multiple state signals. For example, if the first state signal is a first preset value (e.g., 1), it can be determined that the current cache state of the first buffer 1i1 is a full state (i.e., the first preset state). If the first state signal is a second preset value (e.g., 0), the value of the second state signal can be further determined. If the second state signal is the first preset value, it can be determined that the current cache state of the first buffer 1i1 is a nearly full but not full state (i.e., the second preset state), and so on.

[0063] In the embodiment of the present disclosure, the current cache state of the first cache is determined according to the state signal output by the first cache. Since the state signal output by the first cache represents the current occupancy degree of the first cache, the real-time and accuracy of the current cache state can be ensured.

[0064] In some optional embodiments, the state signal includes a first state signal, a second state signal and a third state signal.

[0065] The first state signal may be expressed as a full signal, indicating whether the first buffer 1i1 is currently full. The second state signal may be expressed as an almost full signal, indicating whether the first buffer 1i1 is currently almost full. The third state signal may be expressed as an almost empty signal, indicating whether the first buffer 1i1 is currently almost empty. Optionally, the state signal may further include a fourth state signal, which may be expressed as an empty signal, indicating whether the first buffer 1i1 is currently empty.

[0066] The first arbiter 1i4 is configured as:

[0067] In response to the first state signal being the first preset value, the current cache state is determined to be the first preset state; or, in response to the first state signal being the second preset value and the second state signal being the first preset value, the current cache state is determined to be the second preset state; or, in response to the second state signal being the second preset value, the current cache state is determined to be the third preset state; or, in response to the third state signal being the first preset value, the current cache state is determined to be the fourth preset state.

[0068] The first preset value and the second preset value may be any two different preset values, used to represent different semantics. For example, the first preset value is 1, and the second preset value is 0; or, the first preset value is 0, and the second preset value is 1, and the specific values ​​of the first preset value and the second preset value are not limited. The embodiment of the present disclosure is described by taking the first preset value as 1 and the second preset value as 0 as an example.

[0069] In some optional embodiments, the first state signal is a first preset value (e.g., 1), indicating that the current cache state is a full state (i.e., the first preset state), that is, the first cache 1i1 is currently in a full state. If the first state signal is a second preset value (e.g., 0), it indicates that the first cache 1i1 is not currently full, and the current cache state of the first cache 1i1 is further determined based on the second state signal. If the second state signal is a first preset value (e.g., 1), it indicates that the first cache 1i1 is currently in a state of being almost full but not full (referred to as being almost full but not full) (i.e., the second preset state), that is, the first cache 1i1 is close to being full, and a small amount of available cache space remains. If the second state signal is a second preset value (e.g., 0), it indicates that the first cache 1i1 is currently in a state of not being almost full (i.e., the third preset state), that is, the current storage capacity of the first cache 1i1 has not yet met the condition of being almost full (e.g., the occupied ratio is less than the third threshold). If the third state signal is the first preset value (eg 1), it indicates that the first buffer 1i1 is currently in an almost empty state (ie the fourth preset state), that is, the current storage capacity of the first buffer 1i1 is very small and close to being empty.

[0070] In the embodiment of the present disclosure, three status signals are used to determine the current cache state of the first cache, thereby providing an accurate and effective reference for determining the data transmission priority between the first memory and the second processing element.

[0071] In some optional embodiments, the first arbiter 1i4 is configured as:

[0072] In response to the current cache state being the second preset state, the data transmission priority is determined to preferentially obtain the data to be transmitted from the second processing element 1k; or, in response to the current cache state being the third preset state or the fourth preset state, the data transmission priority is determined to be the same as the priority of the second processing element 1k and the first memory 1i2.

[0073] Among them, the current cache state is the second preset state, indicating that the first cache 1i1 is currently in a state of being almost full but not full, and the remaining free cache space is small. In order to avoid that all the caches on the data transmission path are full, it is determined that the priority of the second processing element 1k is higher than the priority of the first memory 1i2, so as to preferentially obtain the data to be transmitted from the cache 1k1 of the second processing element 1k, so that the cache of the second processing element 1k releases part of the cache space, and ensures that there is at least one cache on the data transmission path that is not full, thereby avoiding the deadlock problem. When the current cache state is the third preset state or the fourth preset state, it means that the first cache 1i1 is currently in a state of not being almost full, and has sufficient free cache space, and can support obtaining the data to be transmitted from both the second processing element 1k and the first memory 1i2. Therefore, the data transmission priority is determined to be the same as that of the second processing element 1k and the first memory 1i2. If there are both first data from the second processing element 1k and second data from the first memory 1i2, the first data and the second data can be cached in the first cache 1i1 as data to be transmitted. It can be understood that when the data transmission priority is the same as that of the second processing element 1k and the first memory 1i2, if only the first data from the second processing element 1k exists at the current moment, the first data will be used as the data to be transmitted; if only the second data from the first memory 1i2 exists at the current moment, the second data will be used as the data to be transmitted.

[0074] In an embodiment of the present disclosure, when the current cache state of the first cache is almost full but not full, since the remaining free cache space is small, the cache of the second processing element can release part of the cache space by preferentially obtaining the data to be transmitted from the second processing element, thereby ensuring that there is always at least one cache in the data transmission path that is not full, effectively avoiding the deadlock problem.

[0075] In some optional embodiments, the first arbiter 1i4 is configured as:

[0076] In response to the current cache state being the second preset state, the data transmission priority is determined to obtain the first data only from the second processing element 1k as the data to be transmitted, and the acquisition of data from the first memory 1i2 is suspended.

[0077] Among them, when the current cache state is the second preset state, it means that the first cache 1i1 is currently in a state of being almost full but not full, and the remaining free cache space is small. In this case, the data transmission priority is determined to obtain the data to be transmitted only from the second processing element 1k, and suspend the acquisition of data from the first memory 1i2, that is, only the first data from the second processing element is cached in the first cache 1i1 as the data to be transmitted, and the second data is not temporarily obtained from the first memory 1i2.

[0078] In an embodiment of the present disclosure, when the first buffer is almost full but not full, only supports obtaining the data to be transmitted from the second processing element, and suspends obtaining data from the first memory, thereby ensuring that there is always at least one buffer on the data transmission path that is not full, effectively avoiding the deadlock problem.

[0079] In some optional embodiments, the first arbitrator is further configured to: after pausing the acquisition of data from the first memory 1i2, in response to the current cache state changing to a third preset state or a fourth preset state, restart the acquisition of the data to be transmitted from the first memory 1i2, and cache the data to be transmitted to the first cache 1i1.

[0080] Among them, after pausing to obtain data from the first memory 1i2, as the data continues to flow and the processing elements continue to work, the cache state of the first buffer 1i1 can change in real time. If the current cache state changes from the second preset state to the third preset state or the fourth preset state, it means that the current cache state of the first buffer 1i1 changes to a state that is not almost full or almost empty, and has sufficient cache space to support caching data from the second processing element 1k and data from the first memory 1i2 at the same time. Therefore, it is possible to restart obtaining the data to be transmitted from the first memory 1i2 and cache the data to be transmitted to the first buffer 1i1.

[0081] In an embodiment of the present disclosure, when the first buffer is almost full but not full, the acquisition of the data to be transmitted from the first memory is suspended to avoid a deadlock problem, until the current cache state of the first buffer can support the simultaneous caching of the data to be transmitted of the first memory and the second processing element, and then the acquisition of the data to be transmitted from the first memory is restarted, and the data to be transmitted is cached to the first buffer, thereby maintaining data transmission efficiency while ensuring that no deadlock problem occurs.

[0082] In some optional embodiments, based on any of the above embodiments, the first processing element 1i is configured as:

[0083] In response to the data transmission priority of the second processing element 1k being higher than the data transmission priority of the first memory 1i2, the data to be transmitted is obtained from the second processing element 1k; or, in response to the data transmission priority of the second processing element 1k being the same as that of the first memory 1i2, the data to be transmitted is obtained from the second processing element 1k and the first memory 1i2.

[0084] In the case where the data transmission priority of the second processing element 1k is higher than the data transmission priority of the first memory 1i2, the data to be transmitted is obtained from the second processing element 1k in priority, so that the second processing element 1k can release part of the cache space to avoid the situation where all the caches on the data transmission path are full. After the data to be transmitted is obtained from the second processing element 1k in priority and cached in the first cache 1i1, if the first cache 1i1 can still store the data of the first memory 1i2, the data to be transmitted can continue to be obtained from the first memory 1i2 and cached in the first cache 1i1.

[0085] It should be noted that in the embodiment of the present disclosure, for any processing element 1i, the data to be transmitted is a general term for the data that needs to be transmitted at the current moment and changes in real time, and does not refer to a specific data, that is, the data to be transmitted acquired at any moment is called the data to be transmitted, the data acquired from the second processing element 1k can be called the data to be transmitted, and the data acquired from the first memory 1i2 can also be called the data to be transmitted. At the same moment, if there is the first data from the second processing element 1k and the second data from the first memory 1i2 at the same time, according to the data transmission priority of the second processing element 1k and the first memory 1i2, it is determined whether the first data or the second data is used as the data to be transmitted, or whether both the first data and the second data are used as the data to be transmitted.

[0086] In the embodiment of the present disclosure, when the data transmission priority of the second processing element 1k is higher than the data transmission priority of the first memory 1i2, the data to be transmitted is obtained from the second processing element 1k, so that the buffer of the second processing element 1k can release part of the buffer space, ensuring that there is always at least one buffer in the data transmission path that is not full, effectively avoiding the deadlock problem. When the data transmission priority of the second processing element 1k and the first memory 1i2 is the same, the data to be transmitted can be obtained from the second processing element 1k and the first memory 1i2 respectively, ensuring data transmission efficiency.

[0087] In some optional embodiments, the first arbitrator 1i4 is further configured to:

[0088] In response to the current cache state being the first preset state, suspending acquisition of the data to be transmitted.

[0089] Among them, if the current cache state of the first cache 1i1 is the first preset state, it means that the first cache 1i1 is currently full and cannot store new data. Therefore, pausing the acquisition of data to be transmitted can effectively avoid the situation where the acquired data cannot be cached and cause data loss.

[0090] In some optional embodiments, after suspending the acquisition of the data to be transmitted, the method may further include: in response to the current cache state changing to the second preset state, resuming the acquisition of the data to be transmitted from the second processing element 1k. In response to the current cache state changing to the third preset state or the fourth preset state, resuming the acquisition of the data to be transmitted from the second processing element 1k and the first memory 1i2. In this way, the data source of the data to be transmitted can be dynamically adjusted or the acquisition of the data to be transmitted can be suspended according to the real-time change of the cache state of the first cache 1i1, thereby ensuring the smooth transmission of data on the data transmission path and avoiding deadlock problems.

[0091] In some optional embodiments, the current cache state of the first cache 1i1 can be represented as a combination of different preset values ​​of the first state signal, the second state signal, the third state signal and the fourth state signal. That is, the data transmission priority between the second processing element 1k and the first memory 1i2 can be determined directly according to the specific situation of the state signal output by the first cache 1i1. The operation of determining the current cache state based on the state signal and then determining the data transmission priority based on the current cache state is simplified to determining the data transmission priority based on the state signal. For example, the first arbitrator 1i4 is configured to: in response to the first state signal being the second preset value and the second state signal being the first preset value, determine the data transmission priority to preferentially obtain the transmission data from the second processing element 1k, that is, the priority of the second processing element 1k is higher than the priority of the first memory 1i2. In response to the second state signal being the second preset value and / or the third state signal being the first preset value, determine the data transmission priority to be the same as the priority of the second processing element 1k and the first memory 1i2.

[0092] In some optional embodiments, the first arbiter 1i4 is further configured to: in response to the first state signal being the second preset value and the second state signal being the first preset value, determine the data transmission priority to obtain the first data only from the second processing element 1k as the data to be transmitted, and suspend obtaining data from the first memory 1i2. In response to the second state signal changing to the second preset value and / or the third state signal being the first preset value, restart obtaining the data to be transmitted from the first memory 1i2, and cache the data to be transmitted to the first buffer 1i1.

[0093] In some optional embodiments, the first arbiter 1i4 is further configured to: in response to the first state signal being a first preset value, suspend acquisition of the data to be transmitted.

[0094] In some optional embodiments, the function of the first arbiter 1i4 of any of the above embodiments can be implemented by one or more of hardware logic devices such as comparators, data selectors, AND gates, OR gates, and NOT gates. For example, a logic component that determines the current cache state based on a state signal is formed by an AND gate, an OR gate, a NOT gate, etc., which is used to trigger a logic component of data transmission priority under different preset states. The logic component of data transmission priority can select the second processing element 1k and the first memory 1i2 through the data selector, and can also pause or restart the acquisition of data to be transmitted through the enable control of the data selector, etc. The specific structure of the first arbiter will not be repeated. Implementing the first arbiter through hardware can effectively improve processing efficiency, thereby improving the real-time performance of data transmission.

[0095] In some optional embodiments, since the current cache state of the first cache is the second preset state, there are two different types of data transmission priorities: namely, obtaining the data to be transmitted from the second processing element first (referred to as the first type), and obtaining the data to be transmitted only from the second processing element and pausing to obtain data from the first memory (referred to as the second type). For any two processing elements in the integrated circuit, the two processing elements may both adopt the first type, or both adopt the second type, or the two processing elements may respectively adopt the first type and the second type, without specific limitation.

[0096] Figure 4 It is a schematic diagram of the structure of a processing element provided by an exemplary embodiment of the present disclosure.

[0097] In some optional embodiments, such as Figure 4 As shown, the first interface 1i3 may include: a second arbitrator 1i31.

[0098] The second arbiter 1i31 is configured as:

[0099] Receive the third data from the second processing element 1k; transmit the third data to the first arbiter 1i4 according to the configured transmission control information, and / or store the third data in the first memory 1i2.

[0100] Among them, the transmission control information is pre-configured configuration information that controls the flow of data (called third data) from the second processing element 1k. The transmission control information may include control information indicating whether to transmit the third data from the second processing element 1k to the first arbitrator 1i4, and control information whether to store the third data in the local first memory 1i2.

[0101] In some optional embodiments, if it is determined according to the transmission control information that only the third data needs to be transmitted to the first arbitrator 1i4, the third data is transmitted to the first arbitrator 1i4, and the third data does not need to be stored in the local first memory 1i2. If it is determined according to the transmission control information that only the third data needs to be stored in the local first memory 1i2, the third data is stored in the local first memory 1i2. If it is determined according to the transmission control information that the third data needs to be transmitted to the first arbitrator 1i4 and stored in the local first memory 1i2, the third data is transmitted to the first arbitrator 1i4 and stored in the local first memory 1i2. The specific data flow path is set according to the needs of the actual application scenario, and the embodiment of the present disclosure is not limited. For example, in the intelligent driving scenario, the perception results of the perception processing element can be stored in the local memory in the positioning processing element, and the perception results can be cached in the buffer by the first arbitrator of the positioning processing element, and then transmitted to the planning control element through the buffer. The perception results stored in the local memory of the positioning processing element can be used in the positioning processing process to obtain the positioning results. The positioning results are stored in the local memory, and then the positioning results stored in the local memory are cached in the cache through the first arbitrator, and transmitted to the planning control element through the cache. That is, the planning control element can read the perception results and positioning results from the cache of the positioning processing element, and then plan and control based on the perception results and the positioning results to control the driving state of the vehicle.

[0102] In some optional embodiments, the second arbiter 1i31 is connected to the first arbiter 1i4 and the first memory 1i2 respectively.

[0103] In some optional embodiments, if the third data from the second processing element 1k is transmitted to the first arbiter 1i4, the third data is used as the first data from the second processing element in the above embodiments.

[0104] In the embodiment of the present disclosure, the second arbitrator in the first interface controls the flow of data from the second processing element so that each processing element can obtain the required data or transmit the data to the next processing element, thereby achieving effective flow of data and ensuring the normal operation of each processing element.

[0105] In some optional embodiments, the second arbiter 1i31 may be implemented based on any of hardware, software, a combination of hardware and software, etc. For example, the second arbiter 1i31 may implement the corresponding arbitration function through a combinational logic circuit to ensure the real-time performance of data transmission.

[0106] In some optional embodiments, the first processing element 1i may include a second interface, and the second interface includes a first arbiter 1i4 and a first buffer 1i1. The first interface 1i3 may be referred to as a slave interface, and the second interface may be referred to as a master interface. Figure 5 FIG. 1 is a schematic diagram of a structure of an integrated circuit for data transmission provided by another exemplary embodiment of the present disclosure. Figure 5As shown in the figure, each processing element 1i includes a Slave Interface (i.e., the first interface 1i3), a Master Interface (i.e., the second interface) and a Memory (i.e., the first memory). The Master Interface includes a first arbitrator (i.e., ARB1) and a first buffer (FIFO is used as an example in the figure). The Slave Interface includes ARB2 (i.e., the second arbitrator). The data loop is shown in the arrow flow direction in the figure. The processing element 11 receives data A from the processing element 1n through the Slave Interface, i.e., through the Slave Inerface reads data A from the FIFO of processing element 1n, so that the FIFO of processing element 1n releases part of the cache space to continue to transmit new data. ARB2 transmits data A to ARB1 and / or stores data A in Memory according to the configured transmission control information. When data A is transmitted to ARB1 and there is data B to be transmitted in the Memory of processing element 11, ARB1 in processing element 11 determines the data transmission priority between processing element 1n and the Memory of processing element 11 according to the status signal of FIFO, and uses data A and / or data B as data to be transmitted according to the data transmission priority. For example, if the data transmission priority of processing element 1n is higher than that of the Memory of processing element 11, data A is preferentially used as data to be transmitted. If the data transmission priority of processing element 1n is the same as that of the Memory of processing element 11, data A and data B are both used as data to be transmitted and cached in FIFO. The subsequent cascade circuit (for example, processing element 12) of processing element 11 receives the data through Slave. The interface reads data C from the FIFO of the processing element 11 (the data C may be data A and / or data B, or data cached before data A and / or B are cached), so that the FIFO of the processing element 11 releases part of the cache space, and so on, so that there is always at least one FIFO with free cache space in the data loop, ensuring data transmission efficiency and avoiding the situation where all FIFOs are full.For example, if the priority is not considered, the processing element 11 will continue to obtain the data to be transmitted from the processing element 1n and the Memory, that is, the data A and data B obtained each time will be cached into the FIFO. Since the cache space of the FIFO is limited, and data from the Memory is continuously added, and there is data from other FIFOs, this may cause each FIFO to be full. For example, after a loop data transmission, only the FIFO of the processing element 11 has a small amount of free cache space, and the FIFOs of other processing elements are full. At this time, if the processing element 11 obtains data B from the Memory and caches it into the FIFO, the FIFO of the processing element 11 will also be full, resulting in all FIFOs on the loop being full, and there is no remaining free cache space to support the data flow on the loop, which will cause a deadlock problem in the loop. Any first processing element in the embodiments of the present disclosure can determine the data source cached to the FIFO based on the real-time cache status of the internal FIFO. When the free cache space of the FIFO is small, the data from the FIFO of the second processing element cascaded previously is preferentially cached to the internal FIFO of the first processing element. Even if the internal FIFO of the first processing element is full at this time, since the data cached this time comes from the FIFO of the second processing element, the FIFO of the second processing element releases part of the cache space and can continue to support the flow of loop data, thereby ensuring that there is always at least one FIFO in the loop that is not full, effectively avoiding the deadlock problem of loop data transmission.

[0107] In some optional embodiments, the Master Interface in the first processing element 1i may include a control unit, which is connected to the local FIFO and the subsequent cascade circuit respectively. When there is valid data in the FIFO, the control unit pulls up the valid (data valid) signal connected to the subsequent cascade circuit (indicating validity) to enable the subsequent cascade circuit to read data from the FIFO buffer. The reading and writing principles of the FIFO are not described in detail.

[0108] The above-mentioned embodiments of the present disclosure may be implemented separately or in any combination without conflict. The specific configuration may be based on actual needs and the present disclosure does not limit this.

[0109] Exemplary Methods

[0110] Figure 6 is a flow chart of a data transmission method provided by an exemplary embodiment of the present disclosure. The method of this embodiment can be implemented by a corresponding integrated circuit embodiment of the present disclosure, such as Figure 6 The method shown may include the following steps:

[0111] Step 210 , based on a current cache state of a first cache in a first processing element, determine a data transmission priority between a first memory in the first processing element and a second processing element cascaded before the first processing element.

[0112] Step 220: Acquire the data to be transmitted according to the data transmission priority.

[0113] Step 230 , buffering the data to be transmitted into the first buffer, so that the data to be transmitted can be read by the subsequent cascade circuit of the first processing element.

[0114] The specific structure and interconnection relationship between the first processing element and the second processing element, as well as the specific operation of each step can be found in the above-mentioned embodiment, and will not be described in detail here.

[0115] Figure 7 It is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure.

[0116] In some optional embodiments, in the above Figure 6 Based on the illustrated embodiment, obtaining the data to be transmitted according to the data transmission priority in step 220 may include:

[0117] Step 2210 : In response to the data transmission priority of the second processing element being higher than the data transmission priority of the first memory, obtaining data to be transmitted from the second processing element.

[0118] Step 2220 , in response to the second processing element and the first memory having the same data transmission priority, obtaining data to be transmitted from the second processing element and the first memory.

[0119] Figure 8 It is a flowchart of a data transmission method provided by yet another exemplary embodiment of the present disclosure.

[0120] In some optional embodiments, based on any of the above embodiments, the method of the embodiment of the present disclosure may further include:

[0121] Step 310: Receive first data from a second processing element based on a first interface in the first processing element.

[0122] Determining the data transmission priority between the first memory in the first processing element and the second processing element cascaded before the first processing element based on the current cache state of the first cache in the first processing element in step 210 may include:

[0123] Step 2110 , determining the data transmission priority between the first memory and the second processing element according to the current cache state of the first cache by the first arbitrator in the first processing element.

[0124] The step 220 of acquiring the data to be transmitted according to the data transmission priority may include:

[0125] Step 22a0: Determine at least one of the first data and the second data in the first memory as data to be transmitted according to the data transmission priority.

[0126] Fig. 9 It is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure.

[0127] In some optional embodiments, based on any of the above embodiments, the method of the embodiment of the present disclosure may further include:

[0128] Step 410: Determine the current buffer state of the first buffer according to the state signal output by the first buffer.

[0129] Fig.10 It is a flowchart of a data transmission method provided by yet another exemplary embodiment of the present disclosure.

[0130] In some optional embodiments, the state signal includes a first state signal, a second state signal and a third state signal. Fig.10 As shown, step 410 of determining the current cache state of the first cache according to the state signal output by the first cache may include:

[0131] Step 4110: In response to a first state signal of the first buffer being a first preset value, determining that the current cache state is the first preset state.

[0132] Step 4120: In response to the first state signal of the first buffer being the second preset value and the second state signal being the first preset value, determining that the current buffer state is the second preset state.

[0133] Step 4130: In response to the second state signal of the first buffer being a second preset value, determining that the current cache state is a third preset state.

[0134] Step 4140: In response to the third state signal of the first buffer being the first preset value, determining that the current cache state is a fourth preset state.

[0135] In some optional embodiments, such as Fig.10 As shown, step 210 of determining the data transmission priority between the first memory in the first processing element and the second processing element cascaded before the first processing element based on the current cache state of the first cache in the first processing element may include:

[0136] Step 21a0: in response to the current cache state being the second preset state, determining the data transmission priority to preferentially obtain the to-be-transmitted data from the second processing element.

[0137] Step 21b0: in response to the current cache state being the third preset state or the fourth preset state, determining that the data transmission priority is the same as the priority of the second processing element and the first memory.

[0138] It should be noted that step 21a0 and step 21b0 are performed in no particular order.

[0139] In some optional embodiments, step 210 of determining the data transmission priority between the first memory in the first processing element and the second processing element cascaded before the first processing element based on the current cache state of the first cache in the first processing element may include: in response to the current cache state being the second preset state, determining the data transmission priority to obtain only the first data from the second processing element as the data to be transmitted, and suspending the acquisition of data from the first memory.

[0140] In some optional embodiments, the method of the embodiment of the present disclosure may also include: after pausing the acquisition of data from the first memory, in response to the current cache state changing to a third preset state or a fourth preset state, resuming the acquisition of the data to be transmitted from the first memory, and caching the data to be transmitted to the first cache.

[0141] In some optional embodiments, the method of the embodiment of the present disclosure may further include: in response to the current cache state being a first preset state, suspending acquisition of data to be transmitted.

[0142] Fig.11 It is a flowchart of a data transmission method provided by another exemplary embodiment of the present disclosure.

[0143] In some optional embodiments, based on any of the above embodiments, Fig.11 As shown, the method of the embodiment of the present disclosure may also include:

[0144] Step 510: Receive third data from the second processing element.

[0145] Step 520: transmit the third data to the first arbiter in the first processing element according to the configured transmission control information, and / or store the third data in the first memory in the first processing element.

[0146] Each step of the above-mentioned embodiments of the present disclosure may be executed by corresponding components in the above-mentioned integrated circuit embodiments, and the details will not be repeated herein.

[0147] The above-mentioned embodiments of the present disclosure may be implemented separately or in any combination without conflict. The specific configuration may be based on actual needs and the present disclosure does not limit this.

[0148] The beneficial technical effects corresponding to the exemplary embodiment of the method can be found in the corresponding beneficial technical effects of the above-mentioned exemplary integrated circuit part, which will not be repeated here.

[0149] Any data transmission method provided in the embodiments of the present disclosure may be executed by any appropriate electronic device with data processing capabilities, including but not limited to: electronic devices such as terminal devices and servers. Alternatively, any data transmission method provided in the embodiments of the present disclosure may be executed by a processor, such as a processor executing any data transmission method mentioned in the embodiments of the present disclosure by calling corresponding instructions stored in a memory. This will not be described in detail below.

[0150] Exemplary Electronic Devices

[0151] Fig.12 It is a structural diagram of an electronic device provided by an embodiment of the present disclosure, including at least one processor 91 and a second memory 92.

[0152] The processor 91 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 90 to perform desired functions.

[0153] The second memory 92 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 91 may execute one or more computer program instructions to implement the methods and / or other desired functions of the various embodiments of the present disclosure described above.

[0154] In one example, the electronic device 90 may further include: an input device 93 and an output device 94 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0155] The input device 93 may also include, for example, a touch screen, a microphone, various sensors, and the like. Sensors may include, for example, image sensors (such as cameras, cameras, etc.), laser radars, millimeter-wave radars, ultrasonic radars, positioning sensors, pressure sensors, air quality sensors, temperature sensors, and the like. Image sensors, laser radars, millimeter-wave radars, ultrasonic radars, and the like may be used to sense the surrounding environment, that is, to detect dynamic and static objects in the surrounding environment. Dynamic and static objects may include, for example, static objects such as lane lines, curbs, arrows, signs, trees, and buildings, as well as dynamic objects such as surrounding vehicles, pedestrians, and cyclists. Positioning sensors are used to realize the positioning of movable devices (such as self-vehicles, robots, etc.) where electronic devices are located. Positioning sensors may include, for example, inertial measurement units (Inertial Measurement Unit, referred to as: IMU), global positioning systems (Global Positioning System, referred to as: GPS), and the like. Pressure sensors may be used to detect seat pressure. Temperature sensors may be used to detect the temperature in the vehicle cabin. Air quality sensors may be used to detect the air quality in the vehicle cabin.

[0156] The output device 94 can output various information to the outside, and may include, for example, a display, a speaker, a communication network and a remote output device connected thereto, and the like.

[0157] Of course, to simplify, Fig.12 Only some of the components related to the present disclosure in the electronic device 90 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 90 may also include any other appropriate components.

[0158] An embodiment of the present disclosure further provides a chip, which includes the integrated circuit for data transmission provided by any of the above embodiments.

[0159] Exemplary computer program products and computer-readable storage media

[0160] In addition to the above methods and devices, embodiments of the present disclosure may also provide a computer program product, including computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the methods of various embodiments of the present disclosure described in the above “Exemplary Methods” section.

[0161] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0162] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon. When the computer program instructions are executed by a processor, the processor executes the steps in the method of various embodiments of the present disclosure described in the above “Exemplary Method” section.

[0163] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium is, for example, but not limited to, a system, device or device including electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0164] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and cannot be considered as necessary for each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, rather than limitation, and the above details do not limit the present disclosure to being implemented by adopting the above specific details.

[0165] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the present disclosure claims and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. An integrated circuit for data transmission, comprising: at least two processing elements, a first processing element of any one of the at least two processing elements comprising a first buffer and a first memory; The first processing element is configured to: determining, according to a current cache state of the first cache, a data transmission priority between the first memory and a second processing element cascaded before the first processing element; Acquire the data to be transmitted according to the data transmission priority; The data to be transmitted is cached in the first cache, so that the data to be transmitted can be read by a subsequent cascade circuit of the first processing element.

2. The integrated circuit according to claim 1, wherein: The first processing element is configured to: In response to the data transmission priority of the second processing element being higher than the data transmission priority of the first memory, acquiring the data to be transmitted from the second processing element; or, In response to the data transmission priorities of the second processing element and the first memory being the same, the to-be-transmitted data is acquired from the second processing element and the first memory.

3. The integrated circuit according to claim 1, wherein: The first processing element further includes: A first interface, configured to receive first data from the second processing element; A first arbitrator, wherein the first arbitrator is configured to: The data transmission priority between the first memory and the second processing element is determined according to the current cache state of the first cache; at least one of the first data received by the first interface and the second data in the first memory is determined as the data to be transmitted according to the data transmission priority, and the data to be transmitted is cached in the first cache.

4. The integrated circuit according to claim 3, wherein: The first arbitrator is further configured to: The current buffer state of the first buffer is determined according to the state signal output by the first buffer.

5. The integrated circuit according to claim 4, wherein: The state signal includes a first state signal, a second state signal and a third state signal; the first arbitrator is configured as: In response to the first state signal being a first preset value, determining that the current cache state is a first preset state; or, In response to the first state signal being a second preset value and the second state signal being the first preset value, determining that the current cache state is a second preset state; or, In response to the second state signal being the second preset value, determining that the current cache state is a third preset state; or, In response to the third state signal being the first preset value, determining the current cache state to be a fourth preset state.

6. The integrated circuit according to claim 3, wherein: The first arbitrator is configured as: In response to the current cache state being the second preset state, determining the data transmission priority to preferentially obtain the to-be-transmitted data from the second processing element; or, In response to the current cache state being the third preset state or the fourth preset state, determining the data transmission priority to be the same as the priority of the second processing element and the first memory.

7. The integrated circuit according to claim 3, wherein: The first arbitrator is configured as: In response to the current cache state being the second preset state, the data transmission priority is determined to obtain the first data only from the second processing element as the data to be transmitted, and the acquisition of data from the first memory is suspended.

8. The integrated circuit according to claim 7, wherein: The first arbitrator is configured as: After pausing to obtain data from the first memory, in response to the current cache state changing to a third preset state or a fourth preset state, resuming to obtain the data to be transmitted from the first memory and caching the data to be transmitted into the first buffer.

9. The integrated circuit according to claim 3, wherein: The first arbitrator is configured as: In response to the current cache state being a first preset state, suspending acquisition of the data to be transmitted.

10. The integrated circuit of claim 3, wherein: The first interface includes: a second arbitrator; The second arbitrator is configured as: receiving third data from the second processing element; According to the configured transmission control information, the third data is transmitted to the first arbitrator, and / or the third data is stored in the first memory.

11. A data transmission method, comprising: Determine, based on a current cache state of a first cache in a first processing element, a data transmission priority between a first memory in the first processing element and a second processing element cascaded before the first processing element; Acquire the data to be transmitted according to the data transmission priority; The data to be transmitted is cached in the first cache, so that the data to be transmitted can be read by a subsequent cascade circuit of the first processing element.

12. A computer-readable storage medium storing a computer program, wherein the computer program is used to execute the method according to claim 11.

13. An electronic device, comprising: processor; a second memory for storing instructions executable by the processor; The processor is configured to read the executable instructions from the second memory and execute the instructions to implement the method of claim 11.

14. A chip, comprising: An integrated circuit for data transmission as described in any one of claims 1 to 10.

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