A circuit diagram analysis method for automatically generating a netlist of an analog circuit

Abstract

The application discloses a circuit diagram analysis method for automatically generating a simulation circuit netlist, and comprises the following steps: using a target detection model to recognize an inputted circuit diagram to be processed, and outputting the types and positions of various components in the circuit diagram; removing the components from the circuit diagram to be processed to obtain a circuit diagram without components; calling representative template pictures of various components, calculating the matching degrees of the template pictures and the component regions recognized, and determining the pin functions and position coordinates of each recognized component; using a connected domain detection method to recognize the connection line segments in the circuit diagram without components, and combining the connection points to obtain the real connected circuit network in the circuit diagram; matching the pin ports of various components with the end points of the circuit network one by one, generating a netlist file of the circuit diagram to be processed, and checking and outputting the netlist file. The application can process circuit diagrams of different styles, and significantly improves the accuracy of circuit netlist conversion.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of electronic design automation (EDA), and particularly relates to a circuit diagram analysis method for automatically generating a netlist of an analog circuit. BACKGROUND

[0002] As the core of electronic design, a circuit diagram directly shows the layout and connection relationship of components in a circuit, while a netlist is a standardized data format that converts the circuit diagram into a format that can be processed by subsequent EDA tools. In modern electronic design, the accuracy of the netlist is crucial to design optimization, simulation analysis, layout and routing, and fault diagnosis. An accurate netlist can provide real component parameters and connection relationships for circuit simulation, allowing engineers to identify design problems in advance and avoid costly physical experiments and debugging. Through the netlist, designers can use automated layout and routing tools to design the circuit board, ensuring that the circuit design matches the actual production process. The netlist is also used for subsequent electrical rule checking (ERC) and design rule checking (DRC) to help designers ensure that the electrical performance and physical layout of the circuit meet design specifications and reduce potential manufacturing defects. Further, the automatic generation of the netlist can improve design efficiency, reduce errors and inconsistencies caused by manual operations, and make the design process more efficient and reliable. In summary, the conversion from a circuit diagram to a netlist is not only a key step in the electronic design process, but also provides strong support for subsequent simulation, layout and routing, optimization, and debugging tasks, thereby significantly improving the accuracy and efficiency of the design and having important practical application value.

[0003] In traditional methods, designers often need to manually draw a circuit schematic diagram and define the connection relationships and parameters of components according to the requirements of simulation software. This process is tedious and prone to errors, especially in complex circuit design, where inconsistencies or omissions in the manually generated netlist can cause errors, increasing debugging time and reducing design efficiency.

[0004] In existing design processes, designers typically need to manually draw a schematic diagram of the circuit in simulation software and further define the connection relationships and parameters of components. This process is not only tedious, but also prone to additional debugging and modification due to input errors. In the design of complex analog circuits, the types of components are numerous and the connection relationships are complex, and these manually generated netlists are prone to omissions or logical errors, which seriously affect design efficiency and the accuracy of simulation results. In addition, different simulation software has different requirements for netlist formats, which forces designers to draw circuit diagrams separately for each software. This incompatibility not only significantly increases the workload of designers, but also causes repetitive labor and unnecessary computational overhead.

[0005] Currently, there are some tools that can assist in generating netlists, which can improve the convenience of netlist generation to some extent, but still have many limitations. Most tools are based on graphical interfaces and rely on user manual adjustment of the layout and connection of components, and cannot directly process hand-drawn or existing analog circuit diagram images. At the same time, traditional methods lack support for complex circuits, especially circuits involving amplifiers, transistors and other active devices, and have low automation level. For large-scale unstructured analog circuit diagram data, the processing capacity of existing methods is also significantly insufficient. This not only restricts the further development of automated design, but also leads to a large amount of potential data value not being fully tapped and utilized.

[0006] The invention with publication number CN114417778B discloses a method for obtaining circuit netlist by node electrical characteristics, pre-acquires the electrical characteristics of each pin on the measured circuit board; in the empty pin set, an arbitrary pin is selected, and the electrical characteristics of all other pins in the empty pin set are compared to determine the same type of pin with an electrical characteristic error less than a specified preset value, and a node netlist is constructed based on the same type of pin; the pins in the node netlist are tested for connection, and the pins that are actually not connected are removed according to the test results to obtain the actual netlist of the node; all pins of the node are deleted from the empty pin set; in the remaining empty pin set, an arbitrary pin is selected to start obtaining the next node netlist, and the process is repeated until the empty pin set is empty, and the netlist of the entire circuit board is obtained. However, the invention mainly introduces the pin electrical characteristics as a constraint condition to shorten the generation time of the circuit netlist, and still cannot solve the problem of generating the netlist file for complex circuits or large-scale unstructured analog circuit diagram data.

[0007] The invention with publication number CN102323964B discloses a processing method for digital circuit netlist data, including: extracting netlist data from a plane circuit diagram; the netlist data includes attribute information of each element and attribute information of each line network in the plane circuit diagram; the attribute information of the element includes: element identification, element type; the attribute information of the line network includes line network identification; according to the corresponding relationship between the element type and the standard element type, each element type in the netlist data is replaced with the standard element type corresponding to the element type. The invention can simplify the plane circuit diagram while maintaining the logic function unchanged through processing of the netlist data; and does not involve the problem of generating the netlist file for complex circuits or large-scale unstructured analog circuit diagram data.

[0008] Therefore, it is of great technical value and application prospect to develop an intelligent tool to realize automatic conversion of analog circuit diagram to netlist. SUMMARY

[0009] The application discloses a circuit diagram analysis method for automatically generating an analog circuit netlist, and can solve the problems of low efficiency, poor robustness, complex logic judgment device pin port and low accuracy in the existing analog circuit diagram to circuit netlist conversion technology using Hough transform and OCR combined recognition of circuit diagram line segments, and effectively improves the correctness of the generated circuit netlist.

[0010] A circuit diagram analysis method for automatically generating an analog circuit netlist, the method comprising the following steps:

[0011] S1, labeling the original circuit diagram to determine the category of each component in the circuit diagram and its position in the image, and generating a training data set;

[0012] S2, training the neural network model using the training data set to construct a target detection model; the target detection model recognizes the input circuit diagram to be processed and outputs the type and position of each component in the circuit diagram;

[0013] S3, based on the result of the target detection model, removing the components from the circuit diagram to be processed to obtain a circuit diagram without components;

[0014] S4, calling representative template pictures of each component, calculating the matching degree of the template pictures and the recognized component area, and determining the pin function and position coordinates of each recognized component;

[0015] S5, using a connected component detection method to recognize the connection line segments in the circuit diagram without components, and combining the connection points to obtain the real connected circuit network in the circuit diagram;

[0016] S6, matching the pin ports of each component with the end points of the circuit network one by one to generate a netlist file of the circuit diagram to be processed, and checking and outputting the netlist file.

[0017] Step S1 further comprises the following steps:

[0018] Labeling the original circuit diagram to determine the category of each component in the circuit diagram and its position in the image, and generating an initial data set;

[0019] Enhancing the initial data set through cropping, scaling and rotating processing methods;

[0020] Adjusting the data in the enhanced initial data set to the standard format required by the target detection model to generate a training data set.

[0021] As one of the preferred examples, in step S2, the YOLOv11 neural network model is trained using the training data set to construct a target detection model, and the output result of the target detection model includes the category of each component and the coordinates of the corresponding bounding box.

[0022] Step S3 further includes the following steps:

[0023] According to the coordinates of the bounding box output by the target detection model, the corresponding region is extracted and filled or deleted, and the components contained in the circuit diagram are removed to obtain a circuit diagram without components.

[0024] Step S4 further includes the following steps:

[0025] S41, any one recognized component image is taken as a target region, a representative component template picture is selected according to the component type of the circuit schematic diagram, and the pin position of the component in the template picture is labeled;

[0026] S42, the template picture is rotated step by step, and the template picture is processed by mirroring and scaling, and the normalized correlation coefficient cv2.TM_CCOEFF_NORMED in the computer image processing software library opencv is used to evaluate the similarity between the template picture with different template transformation parameters and the target region:

[0027]

[0028] Wherein, R(x,y) represents the matching degree of the template picture T and the target region I at position (x,y), T'(x',y') represents the pixel value of the template picture T at position (x',y'), and I'(x+x',y+y') represents the pixel value of the target region I at position (x+x',y+y'); the template transformation parameters include the rotation angle, the mirror state and the scaling coefficient;

[0029] S43, the template picture corresponding to the best matching degree is found by the cv2.minMaxLoc function in opencv, and the template transformation parameter with the highest matching degree is recorded; the port coordinates in the component template picture are combined with the template transformation parameter to calculate the pin port position of the component in the target region;

[0030] S44, steps S41 to S43 are repeated until the pin port function and its coordinates of each recognized component are determined.

[0031] As one of the preferred examples, in step S42, the rotation interval angle is set according to the symmetry of the component.

[0032] As one of the preferred examples, in step S41, for the component with irregular shape or mark, a plurality of component template pictures with different initial rotation angles and scaling ratios are set and selected, and correspond to a plurality of placement modes of the component.

[0033] Step S5 further includes:

[0034] All connected domains in the circuit diagram without components are identified by breadth-first traversal, and the network with intersection but not actually connected in the circuit diagram is corrected by combining the connection point judgment algorithm, the effective connection points in the circuit are identified, and it is ensured that only the circuit networks actually connected are numbered as the same number, according to the identification result, the corresponding circuit network digital number is modified, and finally a unique number is generated for all circuit networks not connected to each other; at the same time, the endpoint coordinates of each circuit network are recorded, and the digital number of the corresponding circuit network is marked.

[0035] Step S6 further includes:

[0036] The Euclidean distance between the pin of each component in the circuit diagram and the endpoint of the circuit network is calculated, the pin closest to the endpoint of the circuit network is matched, and the circuit connection relationship is established; the calculation formula of the Euclidean distance is:

[0037]

[0038] Wherein, d is the Euclidean distance between two points, (x1, y1) and (x2, y2) are the coordinates of the pin of the component and the endpoint of the circuit network, respectively;

[0039] The circuit connection relationship established is converted into a netlist file of the circuit, and the integrity and accuracy of the netlist file are verified.

[0040] As one of the preferred examples, in step S6, whether all components and their pins in the circuit diagram are covered in the netlist file and the connectivity of the circuit network is checked and confirmed, so as to judge whether the netlist file is complete and accurate.

[0041] The beneficial effects of the present application are:

[0042] Firstly, the circuit diagram analysis method for automatically generating the netlist of the analog circuit of the present application can directly analyze the existing circuit diagram, automatically identify the components and their connection relationship therein, generate the required netlist file, and minimize human intervention in the process, thereby providing new support for complex analog circuit design and simulation, and effectively helping the electronic design automation to develop in a more efficient and intelligent direction.

[0043] Secondly, the circuit diagram analysis method for automatically generating an analog circuit netlist of the present application can not only accurately identify the types of circuit components and accurately identify the functions of component pins, but also accurately distinguish and label the circuit network. The overall algorithm has strong adaptability and can process circuit schematics of different styles, significantly improving the accuracy of circuit netlist conversion. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 A flowchart of the circuit diagram analysis method for automatically generating an analog circuit netlist of the present application is shown.

[0045] Figure 2 A flowchart of the multi-angle multi-template template matching of the present application is shown. DETAILED DESCRIPTION

[0046] The following examples enable a person skilled in the art to more fully understand the present application, but do not limit the present application in any way.

[0047] The present application discloses a circuit diagram analysis method for automatically generating an analog circuit netlist, which comprises the following steps:

[0048] S1, labeling the original circuit diagram to clearly identify the category of each component in the circuit diagram and its position in the image, and generating a training data set;

[0049] S2, training the neural network model using the training data set to build a target detection model; the target detection model identifies the input circuit diagram to be processed and outputs the type and position of each component in the circuit diagram;

[0050] S3, based on the result of the target detection model, removing the components from the circuit diagram to be processed to obtain a circuit diagram without components;

[0051] S4, calling representative template pictures of each component, calculating the matching degree of the template pictures and the identified component area, and determining the pin function and position coordinates of each identified component;

[0052] S5, using the connected component detection method to identify the connection line segments in the circuit diagram without components, and combining the connection points to obtain the real connected circuit network in the circuit diagram;

[0053] S6, matching the pin ports of each component with the end points of the circuit network one by one to generate a netlist file of the circuit diagram to be processed, and checking and outputting the netlist file.

[0054] As shown in Figure 1 The circuit diagram analysis method of the present embodiment specifically comprises the following steps:

[0055] Step S1, building and training the target detection model.

[0056] The embodiment adopts a YOLOv11 neural network model to construct a target detection model. In order to train the YOLOv11 neural network model to achieve accurate recognition of components in a circuit diagram, a large number of original circuit diagrams are labeled one by one to determine the category of each component and its position in the image. To further improve the robustness and adaptability of the model, various data enhancement techniques are introduced, such as cropping, scaling, rotating, etc., to expand the diversity of the data set. In addition, brightness adjustment and noise addition are also processed to simulate complex image scenarios. After data cleaning and enhancement, these labeled data are converted into the standard format required for training the YOLOv11 neural network model, a standardized data set is generated, and it is input into the YOLOv11 neural network model for training. By optimizing training hyperparameters such as learning rate, batch size, etc., the recognition accuracy of the model is further improved. Finally, the fully trained target detection model is evaluated and verified to ensure that its performance meets the needs of practical applications.

[0057] Step S2, using the trained YOLOv11 neural network model to recognize components in the circuit diagram, obtaining the type and position information of each component in the circuit diagram. The results output by the YOLOv11 target detection model include the category of each component, the coordinates of the bounding box, etc., where the component type includes common analog circuit components such as resistors, capacitors, diodes, transistors, MOS tubes, and operational amplifiers. By analyzing these output results, the position information of all components in the circuit diagram can be obtained, so as to locate the position of each component in the circuit diagram and its type.

[0058] Step S3, based on the results of the YOLOv11 neural network model recognition, the component region in the circuit diagram can be removed through image processing technology to generate an image containing only the circuit network connection relationship. According to the bounding box output by the YOLOv11 neural network model, the corresponding region is extracted and filled or deleted, and finally a circuit diagram without components is obtained. The image processed in this way can provide the required image data for subsequent circuit network connection relationship recognition and processing, helping to identify the wires and nodes in the circuit, and further generating a circuit netlist.

[0059] Step S4, use a multi-angle template matching algorithm to mark the pin functions of the components, and the overall flow is as follows Figure 2The matching process is shown in FIG. 6. First, any one of the identified component images is taken as the target region, and a representative component template picture is selected according to the component type of the circuit schematic diagram, and the positions of each component pin in the template picture are accurately labeled. On this basis, a multi-angle matching template algorithm is used to match the component template picture with the highest similarity and identify the component pins. Specifically, the template is gradually rotated and mirrored to improve the robustness of the matching. In addition, the template picture is also scaled to adapt to components of different sizes in the circuit diagram. In the matching process, the normalized correlation coefficient cv2.TM_CCOEFF_NORMED in the computer image processing software library opencv can be used to evaluate the similarity between the template and the target region, and the matching degree of the two is calculated. The formula of the normalized correlation coefficient is as follows:

[0060]

[0061] wherein R(x, y) represents the matching degree of the template T and the target region I at position (x, y), T'(x', y') represents the pixel value of the template T; and I'(x+x', y+y') represents the pixel value of the target region I at position (x+x', y+y').

[0062] In order to improve the robustness of the algorithm, the template picture will be gradually rotated and mirrored to ensure that components of different angles and orientations in the circuit diagram can be matched. The rotation process is usually from 0° to 360°, and the rotation interval can be simplified according to the symmetry of the component. For example, for components with strong symmetry, such as capacitors and resistors, a 90° rotation is sufficient, and there is no need to rotate every degree, which can significantly improve the running efficiency of the algorithm. In order to further improve the matching accuracy, the template image is also mirrored horizontally during the rotation process. This is because in the circuit diagram, components may be mirrored, and mirroring can enhance the adaptability of the algorithm and ensure that components of different orientations can be identified.

[0063] For example, for components with special shapes or irregular markings, multiple templates are designed, each corresponding to a typical placement of these components. Each template corresponds to a different initial angle and scaling ratio to ensure that the template can match components of various orientations in the circuit diagram.

[0064] In all matching attempts, the best matching position is recorded by the cv2.minMaxLoc function in opencv, which records the highest matching degree. According to the template type, rotation angle and mirror state of the matching result, combined with the pre-defined port coordinates in the template, the corresponding port positions in the target image are accurately calculated.

[0065] Based on the above method, the identified components in the circuit diagram are matched one by one to determine the pin function and coordinates of each component.

[0066] Step S5, using the connected component detection algorithm, all connected components in the circuit diagram after removing the circuit components are identified by breadth-first traversal, and some networks in the circuit diagram that exist intersection points but are not actually connected are corrected by combining the connection point judgment algorithm, the effective connection points in the circuit are identified, and the corresponding circuit network number is modified to ensure accurate identification of all circuit connections and avoid missed and false judgments. Finally, a unique circuit network number is generated for each unconnected line segment.

[0067] Step S6, based on the identified circuit connection points and component ports, the circuit connection relationship is established. Specifically, the Euclidean distance formula is used to calculate the distance between the pins and the connection points, and the pin coordinates of each component in the circuit diagram are matched with the circuit network, and the distance calculation formula is as follows:

[0068]

[0069] Where d is the Euclidean distance between two points, (x1, y1) and (x2, y2) are the coordinates of the component pins and the circuit network endpoints, respectively.

[0070] The closest component pin and circuit network endpoint are matched, all recorded circuit connection relationships are converted into a required circuit netlist format file, and the integrity and accuracy of the circuit netlist are verified. Check if all components and their pins in the circuit diagram are covered in the netlist and confirm the connectivity of the circuit network to avoid missed or false judgments; after passing the verification, the final netlist file is generated.

[0071] In summary, the circuit diagram analysis method based on multi-angle template matching and connected component detection algorithm involved in the embodiment has the following advantages compared to the prior art: by using the powerful image recognition capability of multi-angle template matching, the component and its pin function in the circuit diagram can be more accurately identified, and components with different angles and sizes can be adapted. At the same time, the connected component detection algorithm combined with the connection point judgment technology can effectively identify the effective connection relationship in the circuit, avoiding false and missed judgments. Finally, by generating a unique number for each circuit network, the network connection relationship in the circuit diagram is accurately recorded, and the circuit netlist is generated. This method ensures accurate identification of circuit connections and provides reliable data support for subsequent circuit design, simulation and optimization.

[0072] The above are only preferred embodiments of the present application, and the protection scope of the present application is not limited to the above-mentioned embodiments. Any technical scheme falling within the concept of the present application shall fall within the protection scope of the present application. It should be noted that, for ordinary skilled in the art, some improvements and refinements without departing from the principles of the present application shall be considered as the protection scope of the present application.

Claims

1. A circuit diagram analysis method for automatically generating a netlist of an analog circuit, characterized by, The method comprises the following steps: S1, labeling the original circuit diagram to determine the category of each component in the circuit diagram and its position in the image, and generating a training data set; S2, training a neural network model using the training data set to build a target detection model; the target detection model identifies the inputted circuit diagram to be processed and outputs the type and position of each component in the circuit diagram; S3, based on the result identified by the target detection model, removing the components from the circuit diagram to be processed to obtain a circuit diagram without components; S4, calling representative template pictures of each component, calculating the matching degree of the template pictures and the identified component area, and determining the pin function and position coordinates of each identified component; Step S4 further comprises the following steps: S41, taking any identified component image as a target area, selecting a representative component template picture according to the component type of the circuit schematic, and labeling the pin position of the component in the template picture; S42, gradually rotating the template picture, while performing mirror and scaling processing on the template picture, and using the normalized correlation coefficient cv2.TM_CCOEFF_NORMED in the computer image processing software library opencv to evaluate the similarity between the template picture with different template transformation parameters and the target area: ； Wherein, R(x, y) represents the matching degree of the template picture T and the target area I at position (x, y), T'(x', y') represents the pixel value of the template picture T at position (x', y'), and I'(x + x', y + y') represents the pixel value of the target area I at position (x + x', y + y'); the template transformation parameters include the rotation angle, the mirror state and the scaling coefficient; S43, find the template picture corresponding to the best matching degree through the cv2.minMaxLoc function in opencv and record the template transformation parameter with the highest matching degree; combine the pre-defined port coordinates in the component template picture and the template transformation parameter to calculate the pin port position of the component in the target area; S44, repeat steps S41 to S43 until the pin port function and coordinates of each identified component are determined; S5, using the connected component detection method to identify the connection line segments in the circuit diagram without components, and combining the connection points to obtain the real connected circuit network in the circuit diagram; S6, matching the pin ports of each component with the end points of the circuit network one by one to generate a netlist file of the circuit diagram to be processed, and checking and outputting the netlist file.

2. The circuit diagram parsing method for automatically generating a netlist of an analog circuit according to claim 1, wherein, Step S1 further comprises the following steps: Labeling the original circuit diagram to determine the category of each component in the circuit diagram and its position in the image, and generating an initial data set; Enhancing the initial data set through cropping, scaling and rotating processing methods; Adjusting the data in the enhanced initial data set to the standard format required by the target detection model to generate a training data set.

3. The circuit diagram parsing method for automatically generating a netlist of an analog circuit according to claim 1, wherein, In step S2, the YOLOv11 neural network model is trained using the training data set to construct a target detection model. The output results of the target detection model include the category of each component and the coordinates of the corresponding bounding box.

4. The circuit diagram parsing method for automatically generating a netlist of an analog circuit according to claim 1, wherein, Step S3 further includes the following steps: According to the coordinates of the bounding box output by the target detection model, the corresponding region is extracted and filled or deleted, and the components contained in the circuit diagram are removed to obtain a circuit diagram without components.

5. The circuit diagram parsing method for automatically generating a netlist of an analog circuit according to claim 1, wherein, In step S42, the rotation interval angle is set according to the symmetry of the component.

6. The circuit diagram parsing method for automatically generating a netlist of an analog circuit according to claim 1, wherein, In step S41, for components with irregular shapes or marks, multiple component template pictures with different initial rotation angles and scaling ratios are set and selected, respectively corresponding to multiple placement modes of the components.

7. The circuit diagram parsing method for automatically generating a netlist of an analog circuit according to claim 1, wherein, Step S5 further includes: All connected domains in the circuit diagram without components are identified by breadth-first traversal, and the network with intersection points but not actually connected in the circuit diagram is corrected by combining the connection point judgment algorithm, the effective connection points in the circuit are identified, the truly connected circuit networks are classified into the same number, the corresponding circuit network digital number is modified according to the identification result, and finally a unique number is generated for all circuit networks that are not connected to each other; The endpoint coordinates of each circuit network are recorded and the digital number of the corresponding circuit network is marked.

8. The circuit diagram parsing method for automatically generating a netlist of an analog circuit according to claim 1, wherein, Step S6 further includes: The Euclidean distance between the pins of each component in the circuit diagram and the endpoint of the circuit network is calculated, the nearest component pin and circuit network endpoint are matched, and the circuit connection relationship is established; The calculation formula of the Euclidean distance is: ； Where d is the Euclidean distance between two points, (x1, y1) and (x2, y2) are the coordinates of the component pin and the circuit network endpoint, respectively; The established circuit connection relationship is converted into a netlist file of the circuit, and the completeness and accuracy of the netlist file are verified.

9. The circuit diagram parsing method for automatically generating a netlist of an analog circuit according to claim 1, wherein, In step S6, it is checked whether all components and their pins in the netlist file cover the circuit diagram and the connectivity of the circuit network is confirmed to determine whether the netlist file is complete and accurate.

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