Access delay analysis method and related device

Abstract

The embodiment of the invention provides an access delay analysis method and a related device. The access delay analysis method comprises the following steps: acquiring a path number of a target access path; determining a functional unit passed by the target access path based on the path number; acquiring characteristic signals of all access paths passing through the functional unit; the characteristic signal comprises an input characteristic signal passing through the functional unit and an output characteristic signal; acquiring a waveform file at least comprising the target access path, and determining an input timestamp of the input feature signal and an output timestamp of the output feature signal according to the waveform file and the feature signal; determining the input characteristic signal and the output characteristic signal which belong to the same access so as to determine the input timestamp and the output timestamp which belong to the same access; a delay is calculated using the corresponding output timestamps and the input timestamps. According to the embodiment of the invention, the delay analysis efficiency of the signal can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and in particular to an access delay analysis method and related devices. Background Art

[0002] In the chip R&D process, performance analysis is an indispensable part. Fast, accurate and systematic performance analysis methods can effectively improve R&D efficiency. As the performance requirements of chips become higher and higher, chips are also used in more diverse scenarios, which leads to an increase in the scale and complexity of chips. With the increase in chip complexity, the traditional processing methods for access delay analysis in performance analysis rely heavily on manual calculations and can no longer meet current R&D needs. Therefore, how to improve the efficiency of access delay analysis has become a problem that people in this field need to solve urgently. Summary of the invention

[0003] In view of this, an embodiment of the present application provides an access delay analysis method and a related device to improve the efficiency of access delay analysis.

[0004] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0005] First,

[0006] Get the path number of the target access path;

[0007] Determine the functional unit through which the target access path passes based on the path number; wherein the functional unit includes an input port and an output port;

[0008] Acquire characteristic signals of all access paths passing through the functional unit; the characteristic signals include input characteristic signals passing through input ports of the functional unit and output characteristic signals passing through output ports of the functional unit;

[0009] Acquire a waveform file including at least the target access path, and determine an input timestamp corresponding to the input characteristic signal and an output timestamp corresponding to the output characteristic signal according to the waveform file and the characteristic signal;

[0010] Determine all the input characteristic signals and output characteristic signals belonging to the same access path, so as to determine all the input timestamps and output timestamps belonging to the same access path;

[0011] A delay is calculated using the corresponding output timestamp and the input timestamp.

[0012] In a second aspect, an embodiment of the present application provides an access delay analysis device, including:

[0013] A path parsing unit, configured to obtain a path number of a target access path; determine a functional unit through which the target access path passes based on the path number; wherein the functional unit includes an input port and an output port; obtain characteristic signals of all access paths through the functional unit; the characteristic signals include an input characteristic signal through the input port of the functional unit, and an output characteristic signal through the output port of the functional unit;

[0014] A data extraction module, used to obtain a waveform file including at least the target access path, and determine an input timestamp corresponding to the input characteristic signal and an output timestamp corresponding to the output characteristic signal according to the waveform file and the characteristic signal;

[0015] A reordering module, used to determine all the input characteristic signals and output characteristic signals belonging to the same access path, so as to determine all the input timestamps and output timestamps belonging to the same access path;

[0016] The access delay analysis unit is used to calculate the delay using the corresponding output timestamp and input timestamp.

[0017] In a third aspect, an embodiment of the present application further provides a computing system, comprising the access delay analysis device as described above.

[0018] In a fourth aspect, an embodiment of the present application further provides a computer device, including a processor and a memory, wherein the memory stores computer instructions, and the processor executes the computer instructions to implement the access delay analysis method as described above.

[0019] In a fifth aspect, an embodiment of the present application further provides a computer program, which is executed to implement the access delay analysis method as described above.

[0020] The access delay analysis method provided in an embodiment of the present application includes obtaining a path number of a target access path; determining a functional unit through which the target access path passes based on the path number; wherein the functional unit includes an input port and an output port; obtaining characteristic signals of all access paths passing through the functional unit; the characteristic signal includes an input characteristic signal passing through the input port of the functional unit, and an output characteristic signal passing through the output port of the functional unit; obtaining a waveform file including at least the target access path, and determining an input timestamp corresponding to the input characteristic signal and an output timestamp corresponding to the output characteristic signal according to the waveform file and the characteristic signal; determining all the input characteristic signals and output characteristic signals belonging to the same access path to determine all the input timestamps and output timestamps belonging to the same access path; and calculating delay using the corresponding output timestamps and input timestamps.

[0021] In this way, for a target access path, the path number of the target access path is used to determine the characteristic signals of the functional units and all access paths passing through the functional units, and based on the output port and input port of the functional unit, the at least one functional unit characteristic signal is distinguished into an input characteristic signal and an output characteristic signal, and then all the input characteristic signals and output characteristic signals belonging to the same access path are determined, and all the input timestamps and output timestamps belonging to the same access path are determined. Therefore, the delay caused by a single functional unit or multiple functional units in the signal path can be calculated based on the time difference between the input timestamps and the output timestamps belonging to the same access path. This can simplify the process of calculating delay data and greatly improve the efficiency of analyzing the access delay of a single signal. At the same time, based on the target access paths of the same type, the analysis of the access delay of the signal can be processed in batches, which improves the efficiency of analyzing large batches of access delays. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0023] Figure 1 It is a structural diagram of a general SoC system;

[0024] Figure 2 It is a detailed structural diagram of a general SoC system;

[0025] Figure 3 A schematic diagram of a flow chart of a method for analyzing access delay provided in an embodiment of the present application;

[0026] Figure 4 Another schematic diagram of a flow chart of a method for analyzing access delay provided in an embodiment of the present application;

[0027] Figure 5 A schematic diagram of the structure of a characteristic signal container provided in an embodiment of the present application;

[0028] Figure 6 A schematic diagram of the structure of a matching data container provided in an embodiment of the present application;

[0029] Figure 7 A schematic diagram of the structure in the matching data secondary container provided in an embodiment of the present application;

[0030] Figure 8 A schematic diagram of the structure of the matching data container after reordering provided in an embodiment of the present application;

[0031] Fig. 9 A schematic diagram of the structure of an access delay analysis device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] With the rapid development of artificial intelligence, the Internet of Things and other fields, the performance requirements of chips are getting higher and higher, and chips are also used in more diverse scenarios, which leads to an increase in the scale and diversity of chips. In the chip research and development process, performance analysis is an indispensable part. Rapid, accurate and systematic analysis of chip performance can effectively improve research and development efficiency. Among them, analyzing the delay of the chip helps to evaluate the outstanding (suspended transaction) capabilities of each part in the design stage, analyze the congestion of the data path, and is of great significance for locating the performance bottleneck of the entire SoC system. The outstanding capability is a measure of the maximum number of transactions that a system or component can process or suspend simultaneously without blocking.

[0034] Figure 1 The schematic diagram is a general SoC system structure, which mainly includes: a processor 1 (processor such as a CPU), peripherals 2 (peripherals such as IO devices), an on-chip interconnect network (NOC, Network-on-Chip) 3, and a memory 4.

[0035] Among them, the processor 1 is connected to the on-chip interconnect network 3 through CM (Coherent Master) as a master device that sends signals. CM is used to receive requests from the processor 1 and forward the requests to the on-chip interconnect network 3. The peripheral 2 can be both a master device and a slave device that receives signals. It is connected to the on-chip interconnect network 3 through IOMS (IO Coherent Master & Slave). The memory 4 is connected to the on-chip interconnect network 3 through CS (Coherent Slave) as a slave device. When the master device sends a request (i.e. Req) to access the slave device, the slave device will send a response (i.e. Rsp) to respond to the master device. The time from the master device sending Req to receiving Rsp is usually defined as the delay between the request and the response (Req-Rsp Latency).

[0036] The CPU subsystem 11, the IO subsystem 21, the first memory subsystem 41 and the second memory subsystem 42 belong to different subsystems. Requests and responses within different subsystems and between different subsystems are transmitted in the format of packets. Since different subsystems are designed based on different protocols, the formats of the packets are different.

[0037] The above functional units CM, CS, and IOMS are used to build a bridge for different subsystems to communicate with each other. They are responsible for normalizing the formats of data packets of different subsystems and converting them into data packets of the same format, so as to facilitate the use of the on-chip interconnection network 3 to transmit data packets between different subsystems and complete the interaction and transmission of information. Since CM, IOMS, and CS are all used to process the conversion between their respective subsystems and the NOC subsystem, the CM, IOMS, and CS all belong to their respective subsystems and the NOC subsystem, such as the input of IOMS belongs to the IO subsystem, and the output of IOMS belongs to the NOC subsystem; the input of CM belongs to the CPU subsystem, and the output of CM belongs to the NOC subsystem; the input of CS belongs to the NOC subsystem, and the output of CS belongs to the memory subsystem.

[0038] A method for analyzing access delays, which uses sampling analysis to analyze access delays, that is, to select performance simulation analysis of several typical scenarios, and to use manual analysis of delays and path congestion. However, with the increasing complexity of chip design, the increase in application scenarios, different technology types, and protocols, the information required for performance analysis will be complex and the amount of data will be large. It may be necessary to analyze thousands of cases and test waveforms to ensure that the various application scenarios of the chip are covered. At this time, it is difficult to use manual analysis of massive data. In addition, when data is transmitted across protocols, request matching is difficult, and different waveforms are likely to have different configurations, which further increases the difficulty of manual analysis.

[0039] Furthermore, when the structure of the general SoC system is relatively complex, the structural diagram of the further detailed structure in the above SoC system is as follows: Figure 2 As shown, the functional units in the CPU subsystem 11 include CPU_F0, CPU_F1, CPU_F2 and the input end of CM; the functional units in the IO subsystem 21 include IO_F0, IO_F1, IO_F2 and the input end of IOMS; the functional units in the NOC subsystem 31 include RU0, RU1, RU2, RU3, the output end of CM, the output end of IOMS and the input end of CS; the first memory subsystem 41 and the second memory subsystem 42 include the output ends of CS Memory_F0, Memory_F1 and Memory_F2 respectively.

[0040] At this time, if the CPU subsystem 11 or the IO subsystem 21 performs large-scale continuous memory read and write access operations, it is necessary to analyze the delay of each access request (Req) and response (Rsp) of the CPU subsystem 11 or the IO subsystem 21 in each subsystem and each functional unit within the subsystem. It can be seen that from the CPU subsystem 11 or the IO subsystem 21 to the first memory subsystem 41 or the second memory subsystem 42, the request and response need to pass through multiple functional units when going back and forth. These large amounts of delay data are difficult to analyze manually, and an automated and efficient analysis method is required to build a large data delay model for the entire system, so as to analyze the performance issues of the entire system and optimize the design.

[0041] In addition, in terms of physical implementation, if the physical distance between two functional units or two subsystems is far, it is usually necessary to add a relay structure to solve the timing problem of long-distance transmission, so there may also be a delay between two adjacent functional units. It can be seen that with the increase in chip complexity, the efficiency of sampling and manual analysis methods can no longer meet current R&D needs.

[0042] To solve the above problems, the embodiment of the present application provides an access delay analysis method, which improves the delay verification efficiency by using timestamps to calculate the delay of each functional unit. As an optional implementation, Figure 3 FIG. 1 is a flow chart showing a method for analyzing access delay provided in an embodiment of the present application. Figure 3 As shown, the access delay analysis method provided in the embodiment of the present application includes the following steps.

[0043] Step S10: Obtain the path number of the target access path.

[0044] It should be noted that, in one possible implementation, the target access path includes a request path and a response path; the path number records the functional units that the request and response of the target access path pass through during the transmission process. Figure 2 As shown, each device and functional unit in the device in the SoC system has a unique number, so the path number can record the numbers of the device and the functional unit to record the functional units that the request and response pass through during the transmission process.

[0045] Furthermore, in an optional implementation, the path number includes the number of the device and / or the number of the functional unit through which the request and response of the target access path pass. For example, a signal request is issued by the IO subsystem (B), passes through the functional units RU1 and RU2 in the NOC subsystem (C), and is finally sent to the memory subsystem (E). At this time, the path number of the request is B->RU1->RU2->E.

[0046] Please continue to refer to Figure 3 The access delay analysis method provided in the embodiment of the present application further includes step S20: determining the functional unit through which the target access path passes based on the path number; wherein the functional unit includes an input port and an output port.

[0047] It should be noted that after obtaining the path number, the path number needs to be parsed to determine the functional unit through which the target access path passes. Further, in an optional implementation, Figure 4 As shown, the step S20 includes step S21: parsing the path number to determine at least one functional unit through which the target access path passes, wherein the functional unit includes an input port and an output port.

[0048] Taking the path number B->RU1->RU2->E mentioned above as an example, by parsing the path number, it can be determined that the target access path is issued by the IO subsystem (B), passes through the functional units RU1 and RU2 in the NOC subsystem (C), and is finally sent to the memory subsystem (E). The IO subsystem (B) includes functional units IO_F0, IO_F1, and IO_F2, and the memory subsystem (E) includes functional units Memory_F0, Memory_F1, and Memory_F2. The B->RU1->RU2->E is connected to the NOC subsystem (C) through IOMS, and the NOC subsystem (C) is connected to the memory subsystem (E) through CS. After finally parsing the path number, the result is the functional units that the target access path passes through, including: IO_F0, IO_F1, IO_F2, IOMS, RU1, RU2, CS, memory_F0, memory_F1, and memory_F2. The above functional units are the functional units that need to be analyzed for delay.

[0049] Please continue to refer to Figure 3 The access delay analysis method provided in the embodiment of the present application also includes step S30: obtaining characteristic signals of all access paths passing through the functional unit; the characteristic signals include input characteristic signals passing through the input port of the functional unit, and output characteristic signals passing through the output port of the functional unit.

[0050] It should be noted that for complex SoC systems, it is difficult to directly obtain the delay of the target access path. Therefore, the delay of the request and response of the target access path when passing through each functional unit can be obtained and summarized as the delay of the target access path. In order to obtain the time taken by the request and response of the target access path to pass through each functional unit, it is necessary to obtain the time difference between the request and response of the target access path when it is input into each functional unit and when it is output from each functional unit. In order to obtain the above time difference, it is necessary to first obtain the input characteristic signal corresponding to the input port of each functional unit of the request and response of the target access path, and the output characteristic signal corresponding to the output port of each functional unit of the request and response of the target access path, and then obtain the timestamp based on the input characteristic signal and the output characteristic signal to calculate the time difference.

[0051] The characteristic signal is data that characterizes the request and response of the target access path. Each request or response has a unique set of characteristic signals. The content of the characteristic signal includes but is not limited to a valid signal (Valid), an address signal (Addr), an ID tag (Tag), a request type or a response type (Type), etc. These characteristic signals can exist in the form of a separate bus signal or in the form of a data packet. If they exist in the form of a data packet, the data packet needs to be disassembled according to the packing rules to obtain the characteristic signal.

[0052] Step S40: Acquire a waveform file of the target access path, and acquire an input timestamp corresponding to the input characteristic signal and an output timestamp corresponding to the output characteristic signal according to the waveform file.

[0053] It should be noted that the waveform file is data including the timestamp-related information of the request and response of the target access path through each functional unit. The waveform file is a simulation waveform binary file, which is a file used to store the simulation results of a digital circuit or system. It saves waveform data representing the changes of the signal during the simulation, including the timestamp of the signal and the corresponding value change, such as the switching of logic "0" or "1".

[0054] Furthermore, the waveform file stores each characteristic signal included in the target access path and the timestamp corresponding to the characteristic signal. Then, the acquired input characteristic signal and output characteristic signal are matched with the characteristic signal stored in the waveform file to obtain the input timestamp and output timestamp corresponding to the input characteristic signal and the output characteristic signal.

[0055] Step S50: Determine the intervals between all the input characteristic signals and output characteristic signals belonging to the same access path, so as to determine the intervals between all the input timestamps and output timestamps belonging to the same access path.

[0056] It should be noted that, since the functional units may use parallel processing to improve performance, or due to different queue scheduling and caching mechanisms, the requests and responses of the target access path may be out of order after passing through each functional unit. Therefore, for the input port and output port of the same functional unit, the input characteristic signal and the output characteristic signal obtained are not one-to-one corresponding. Therefore, the input timestamp and the output timestamp obtained are also not corresponding. At this time, the input timestamp and the output timestamp cannot be used to calculate the delay. In particular, between two functional units, the output characteristic signal of the output port of the previous functional unit and the input characteristic signal of the input port of the next functional unit must correspond, and no disorder will occur.

[0057] For example, the characteristic signal of the first input request of the input port of a functional unit and the characteristic signal of the first output request of the functional unit may not belong to the same request, or the characteristic signal of the first input response of the input port of a functional unit and the characteristic signal of the first output response of the functional unit may not belong to the same response.

[0058] Therefore, it is necessary to reorder the acquired input characteristic signals and output characteristic signals to determine all the input characteristic signals and output characteristic signals belonging to the same access path, and then determine all the input timestamps and output timestamps belonging to the same access path, so that the input timestamps and the output timestamps can be used to calculate the delay.

[0059] Step S60: Calculate delay using the corresponding output timestamp and input timestamp.

[0060] In this way, for a target access path, the path number of the target access path is used to determine the functional unit through which the target access path passes and the characteristic signals of all access paths that pass through the functional unit, and based on the output port and input port of the functional unit, the at least one functional unit characteristic signal is distinguished into an input characteristic signal and an output characteristic signal, and then all the input characteristic signals and output characteristic signals belonging to the same access path are determined, and all the input timestamps and output timestamps belonging to the same access are determined. Therefore, based on the time difference between the input timestamps and the output timestamps belonging to the same access path, the delay caused by a single functional unit or multiple functional units in the signal path can be calculated. This can simplify the process of calculating delay data, greatly improving the efficiency of analyzing the access delay of a single signal. At the same time, based on the target access path of the same type, the analysis of the access delay of the signal can be processed in batches, improving the efficiency of analyzing large batches of access delays.

[0061] Further, such as Figure 4 As shown, in an optional implementation, the step S30 includes step S31: obtaining a characteristic signal set, obtaining a characteristic signal set of the input port and the output port of each of the functional units within the characteristic signal set; the characteristic signal set of the functional unit includes an input characteristic signal set corresponding to the input port of the functional unit, and an output characteristic signal set corresponding to the output port.

[0062] It should be noted that the characteristic signal set is a list of characteristic signals that appear at the input ports and output ports of all functional units of all subsystems in the SoC system during the simulation process. By searching in the characteristic signal set using the number of each functional unit in the path number, the input characteristic signal and the output characteristic signal of the functional unit can be obtained. Furthermore, since at least one characteristic signal will appear at the input port and output port of each functional unit during the simulation process, after searching using the number of the functional unit, the number of each functional unit corresponds to at least one input characteristic signal and an output characteristic signal, and the at least one input characteristic signal and the output characteristic signal are stored in the form of a set, stored as an input characteristic signal set, and an output characteristic signal set.

[0063] At this time, the characteristic signal obtained is a dynamically changing physical or logical signal, so the characteristic signal cannot be used for access delay analysis. The characteristic signal needs to be further processed to obtain a characteristic value. The characteristic value is a quantitative description extracted or calculated from the data, which can reflect certain characteristics or attributes of the data. Therefore, the characteristic value can be used for access delay analysis.

[0064] Furthermore, in order to obtain the characteristic value through the characteristic signal, it is also necessary to determine the matching method for extracting the characteristic value according to the protocol of the subsystem where the characteristic signal is located, and then call the matching algorithm corresponding to the matching method to extract the characteristic value. Figure 4 As shown, in an optional implementation, the step S31 further includes a step S32: obtaining a corresponding matching method according to the subsystem to which the functional unit belongs. The matching method is used to determine a matching algorithm for extracting feature values. Since the matching method is determined by the protocol of the subsystem, the matching algorithm implementation methods of the functional units belonging to different subsystems are also different.

[0065] Specifically, for the characteristic signal, the characteristic value Valid is used to represent the valid request or response of the characteristic signal. In the same subsystem, the functional units are designed based on the same protocol, that is, the characteristic values ​​of the characteristic signals (Addr, Tag, Type, etc.) will not be converted when transmitted between functional units in the same subsystem. Between different subsystems, since different subsystems are designed based on different protocols, the characteristic values ​​of the characteristic signals (Addr, Tag, Type, etc.) will be converted when transmitted between functional units belonging to different subsystems.

[0066] The characteristic values ​​of the input characteristic signal and the characteristic values ​​of the output characteristic signal belonging to the same subsystem can be directly matched. If the characteristic values ​​of the input characteristic signal and the characteristic values ​​of the output characteristic signal are consistent, it indicates that the input characteristic signal and the output characteristic signal are characteristic signals belonging to the same request or response. Between two functional units, there will be no disorder between the output port of the previous functional unit and the input port of the next functional unit.

[0067] In addition, for cross-subsystem functional units such as CM, CS, and IOMS, the matching algorithm includes a conversion algorithm that converts the characteristic value of one subsystem into the characteristic value of another subsystem. For cross-subsystem functional units such as CM, CS, and IOMS, the input characteristic signals and output characteristic signals of these functional units cannot be matched directly. It is necessary to convert the input characteristic signal of the input port into the format of the output port according to the design rules between different subsystems, or convert the output characteristic signal of the output port into the format of the output port according to the design rules between different subsystems, and then perform matching.

[0068] Furthermore, after obtaining the characteristic signal set and the matching method, the characteristic signal set and the matching method of each target access path need to be stored for subsequent calls. Specifically, the data set structure of the container storing the characteristic signal set and the matching method is as follows: Figure 5 shown. Figure 5 The feature signal container in stores the feature signal set of all target access paths and the matching method, wherein the feature signal container includes at least one feature signal sub-container, and each feature signal sub-container stores a feature signal set of the target access path and the matching method. Each feature signal sub-container includes at least one feature signal sub-container, and each feature signal sub-container stores a feature signal set of a functional unit and the matching method. Specifically, each feature signal sub-container includes two rows of data, wherein the first row is the input feature signal set of the functional unit input port and the matching method of the input port; the second row is the output feature signal set of the functional unit output port and the matching method of the output port.

[0069] Furthermore, it is necessary to continue to use the matching method to process the characteristic signal set to obtain the characteristic value. Figure 4 In an optional implementation, before step S40, step S41 is included: calling a corresponding matching algorithm according to the matching method, extracting and storing a feature value group from the feature signal. Each of the feature value groups includes at least one feature value; the feature value groups include an input feature value group and an output feature value group.

[0070] It should be noted that each of the characteristic signals may include multiple data, so each of the characteristic signals can extract at least one characteristic value, and at least one characteristic value of each of the characteristic signals constitutes a characteristic value group, that is, each of the characteristic signals corresponds to a characteristic value group, and the characteristic value group includes at least one characteristic value. Since the functional unit and the characteristic signal have input ports and output ports, the characteristic value group also includes an input characteristic value group of the input port and an output characteristic value group of the output port. And since the characteristic signal corresponds to the timestamp, the characteristic value group obtained according to the characteristic signal also corresponds to the timestamp.

[0071] After obtaining the feature value group and the corresponding timestamp, the feature value group and the corresponding timestamp need to be stored for use in subsequent calculation of delay, wherein each feature value group and the corresponding timestamp is a set of matching data. Specifically, in an optional implementation, the matching data container is used to store the matching data of all target access paths, the matching data container includes at least one matching data sub-container, the matching data sub-container is used to store the matching data of a target access path, the matching data sub-container includes at least one matching data secondary container, and the matching data secondary container is used to store the matching data of a functional unit.

[0072] Specifically, the structure of the matching data container storing the matching data is as follows: Figure 6 shown. Figure 6 In the embodiment, the matching data container is divided into a request matching data container, which is used to store the matching data of all requests in the target access path; and a response matching data container, which is used to store the matching data of all responses in the target access path. The data structure of the request matching data container and the response matching data container is the same. Taking the request matching data container as an example, each of the request matching data containers includes at least one request matching data sub-container, and each of the request matching data sub-container stores all the matching data of a request and a corresponding timestamp. In the request matching data sub-container, at least one request matching data secondary container is included, and each request matching data secondary container stores all the matching data of a functional unit. In each of the request matching data secondary containers, two rows of data are stored, wherein the first row of data is an input port group, including the matching data of the input port of the functional unit; and the second row of data is an output port group, including the matching data of the output port of the functional unit. Similarly, the response matching data container includes a response matching data sub-container and a response matching data secondary container in the response matching data sub-container.

[0073] Figure 6In the above, each Reqi is a matching data of the request, where i represents the order of the matching data in the input or output port of the current functional unit, and i is from 1 to N. For example, Req1 is the first matching data, Req2 is the second matching data, and ReqN is the Nth matching data. Similarly, each Rsqi is the i matching data of the response, for example, Rsq1 is the first matching data, Rsq2 is the second matching data, and RsqN is the Nth matching data.

[0074] Furthermore, since the matching data includes at least one characteristic value and a timestamp, in the request matching data sub-container and the response matching data sub-container, the storage structure of the matching data of the input port or output port of each functional unit is as follows: Figure 7 As shown, each matching data is composed of a timestamp and several characteristic values, wherein the timestamp is located at the first position, and taking a timestamp as the starting point, the characteristic value between the timestamp and the next timestamp is a matching data.

[0075] Further, after obtaining the matching data, the sorting of the characteristic signals becomes the sorting of the matching data. At this time, the characteristic values ​​in the matching data need to be used to complete the sorting. Please continue to refer to Figure 4 In an optional implementation, the step S50 includes a step S51: obtaining the first matching data in the unreordered matching data in the input port group of the first matching data sub-container in the matching data sub-container as the first matching data. Figure 6 The first matching data is the first matching data from left to right in the matching data sub-container.

[0076] Step S52: traverse the matching data sub-container to search for second matching data having a feature value group that matches the feature value group of the first matching data;

[0077] Step S53: updating the second matching data to the first matching data in the matching data that has not been reordered in the input port group or the output port group where the second matching data is located.

[0078] Repeating the steps S51 to S53 until all the matching data in the input port group of the first matching data secondary container in the matching data subcontainer are reordered can ensure that all the matching data in the matching data secondary container are reordered.

[0079] Specifically, the Figure 6Take the data of the request matching data sub-container 1 in the request matching data as an example. First, obtain the matching data Req1 of the input port group of the first, that is, the first request matching data sub-container in the request matching data sub-container 1 as the first matching data; then, traverse the request matching data sub-container 1 to find the second matching data with a feature value group that matches the feature value group of the first matching data. For example, the matching data Req2 of the input port group of the second request matching data sub-container and the matching data Req3 of the output port group of the second request matching data sub-container are traversed and obtained as the second matching data. At this time, since the request and the response will not be out of order at the output port of the previous functional unit and the input port of the next functional unit, it can also be determined that the matching data Req2 of the output port group of the first request matching data sub-container and the first matching data belong to the same request. After updating the above two matching data, the result obtained is as follows. Figure 8 As shown, the first matching data of the output port group of the first request matching data secondary container is Req2, the first matching data of the input port group of the second request matching data secondary container is Req2, and the first matching data of the output port group of the second request matching data secondary container is Req3.

[0080] In this way, after reordering, it can be ensured that in one matching data subcontainer, the matching data of the same order in each input port and output port of each matching data secondary container belong to the same request or response. Figure 8 In the request matching data sub-container shown, the first matching data of each input port and output port of each request matching data secondary container belongs to the same request. Therefore, all input timestamps and output timestamps belonging to the same access path can be determined, and the disorder of the request or response after passing through the functional unit can be eliminated, and then the obtained feature value group and timestamp can be used to calculate the various delays that occur in the transmission process of the target access path.

[0081] After the reordering of the first matching data in the input port group of the first matching data secondary container is completed, the second matching data in the input port group of the first matching data secondary container needs to be reordered. When reordering the second matching data, the feature value group matching the feature value group of the second matching data needs to be updated to the first matching data in the matching data that has not been reordered in the input port group or output port group where the second matching data is located, that is, updated to the second matching data in the input port group or output port group where the second matching data is located.

[0082] In this way, after all reordering is completed, the matching data belonging to the same request are in the same order at the input ports or the order of the input ports of the respective request matching data sub-containers; thus, within the request matching data sub-container, the request matching data of the input port group and the output port group of the request matching data sub-container with the same order can correspond to the transmission order of the same request in the path; the matching data of the response is similar, the response matching data of the input port group and the output port group of the response matching data sub-container with the same order can correspond to the transmission order of the same response in the path.

[0083] Further, after all input timestamps and output timestamps belonging to the same access path are determined, the delay can be calculated using the timestamps. Specifically, the delay includes multiple types of delays, and the acquisition method of each type of delay is different.

[0084] In an optional implementation, to obtain the delay of a request or response passing through a functional unit, step S60 includes: subtracting the timestamp of a certain bit of the output port group of the matching data secondary container from the timestamp of the same bit of the output port group to obtain the delay of the request or response corresponding to the matching data of the bit passing through the functional unit.

[0085] In another optional implementation, in order to obtain the delay of a request or response being transmitted from one functional unit to another functional unit, step S60 may further include: subtracting the timestamp of a certain bit of the input port group of the subsequent matching data secondary container from the timestamp of the same bit of the output port group of the previous matching data secondary container, to obtain the delay of the request or response corresponding to the matching data of the bit being transmitted from the previous matching data secondary container to the next matching data secondary container.

[0086] In another optional implementation, in order to obtain the delay of a request or response passing through a subsystem, the step S60 may further include: using the timestamp of a certain bit of the output port group of the last matching data subcontainer in the matching data subcontainer belonging to the same subsystem, minus the timestamp of the same bit of the input port group of the first matching data subcontainer, to obtain the delay of the request or response corresponding to the matching data of the bit passing through the subsystem.

[0087] In another optional implementation, in order to obtain the delay of a request or response traversing the entire system path, the step S60 may further include: using the timestamp of a certain bit of the output port group of the last matching data secondary container in the matching data subcontainer, minus the timestamp of the same bit of the input port group of the first matching data secondary container, to obtain the delay of the request or response corresponding to the matching data of that bit traversing the entire system path.

[0088] In another optional implementation, for the delay from the request to the response of the target access path, step S60 may also include: adding the delay of the request of the target access path passing through the entire system path and the delay of the response passing through the entire system path.

[0089] The embodiment of the present application also provides an access delay analysis device, which improves the delay verification efficiency by using a timestamp to calculate the delay of each functional unit. As an optional implementation, Fig. 9 FIG. 2 shows a schematic diagram of the structure of an access delay analysis device provided in an embodiment of the present application. Fig. 9 As shown, the access delay analysis device provided in the embodiment of the present application includes the following structure.

[0090] The path parsing unit 100 is used to obtain the path number of the target access path; determine the functional unit through which the target access path passes based on the path number; wherein the functional unit includes an input port and an output port; obtain characteristic signals of all access paths passing through the functional unit; the characteristic signals include input characteristic signals passing through the input port of the functional unit, and output characteristic signals passing through the output port of the functional unit.

[0091] The data extraction module 200 is used to obtain a waveform file including at least the target access path, and determine an input timestamp corresponding to the input characteristic signal and an output timestamp corresponding to the output characteristic signal according to the waveform file and the characteristic signal.

[0092] The reordering module 300 is used to determine all the input characteristic signals and output characteristic signals belonging to the same access path, so as to determine all the input timestamps and output timestamps belonging to the same access path.

[0093] The access delay analysis unit 400 is used to calculate the delay using the corresponding output timestamp and input timestamp.

[0094] Furthermore, in an optional implementation, the path parsing unit 100 is also used to obtain a corresponding matching method according to the subsystem to which the functional unit belongs; the matching method is used to determine a matching algorithm for extracting feature values.

[0095] Furthermore, in an optional implementation, the matching algorithm includes a conversion algorithm for converting a feature value of one subsystem into a feature value of another subsystem.

[0096] Further, such as Fig. 9As shown, in an optional implementation, the access delay analysis device provided in the embodiment of the present application also includes: a matching algorithm unit 210, which is used to call the corresponding matching algorithm according to the matching method to extract and store a feature value group from the feature signal; wherein each of the feature value groups includes at least one feature value; the feature value group includes an input feature value group and an output feature value group.

[0097] Furthermore, in an optional implementation, each of the feature value groups and the corresponding timestamp is a group of matching data, and the access delay analysis device also includes: a matching data container, used to store the matching data; the matching data container includes at least one matching data sub-container, and the matching data sub-container is used to store the matching data of a target access path; the matching data sub-container includes at least one matching data secondary container, and the matching data secondary container is used to store the matching data of a functional unit.

[0098] In an alternative implementation, Fig. 9 As shown, the matching data container includes a request matching data container 221 for storing the matching data of the request of the target access path; and a response matching data container 222 for storing the matching data of the response of the target access path.

[0099] Furthermore, in an optional implementation, the path parsing unit 100 is used to obtain a characteristic signal set, and obtain a characteristic signal set of each functional unit within the characteristic signal set; the characteristic signal set of the functional unit includes an input characteristic signal set corresponding to the input port of the functional unit, and an output characteristic signal set corresponding to the output port.

[0100] Further, such as Fig. 9 As shown, in an optional implementation, the access delay analysis device provided in the embodiment of the present application further includes: a characteristic signal container 110, which is used to store the characteristic signal and the matching method.

[0101] The characteristic signal container includes at least one characteristic signal sub-container, and each of the characteristic signal sub-containers stores a characteristic signal of the target access path and the matching method.

[0102] The characteristic signal sub-container includes at least one characteristic signal secondary container, and each of the characteristic signal secondary containers stores a characteristic signal of a functional unit and the matching method.

[0103] The characteristic signal secondary container includes two rows of data, wherein the first row is the input characteristic signal of the functional unit input port and the matching method of the input port; the second row is the output characteristic signal of the functional unit output port and the matching method of the output port.

[0104] Further, in an optional implementation, the reordering module 210 is used to obtain the first matching data in the unreordered matching data in the input port group of the first matching data secondary container in the matching data sub-container as the first matching data; traverse the matching data sub-container to search for the second matching data having a feature value group that matches the feature value group of the first matching data; update the second matching data to the first matching data in the unreordered matching data in the input port group or the output port group where the second matching data is located; and repeatedly obtain the first matching data until all the matching data in the input port group of the first matching data secondary container in the matching data sub-container are reordered.

[0105] Furthermore, in an optional implementation, the access delay analysis unit 400 is used to obtain delay information by subtracting the timestamp of the input feature value group from the timestamp of the output feature value group of each functional unit.

[0106] Furthermore, in an optional implementation, the path number includes the number of the device and / or the number of the functional unit through which the request and response of the target access path pass.

[0107] The path parsing unit 100 is used to parse the path number to determine at least one functional unit through which the target access path passes.

[0108] In this way, for a target access path, the path number of the target access path is used to determine the functional unit through which the target access path passes and the characteristic signals of all access paths that pass through the functional unit, and based on the output port and input port of the functional unit, the at least one functional unit characteristic signal is distinguished into an input characteristic signal and an output characteristic signal, and then all the input characteristic signals and output characteristic signals belonging to the same access path are determined, and all the input timestamps and output timestamps belonging to the same access path are determined. Therefore, based on the time difference between the input timestamps and the output timestamps belonging to the same access path, the delay caused by a single functional unit or multiple functional units in the signal path can be calculated. This can simplify the process of calculating delay data and greatly improve the efficiency of analyzing the access delay of a single signal. At the same time, based on the target access path of the same type, the analysis of the access delay of the signal can be processed in batches, which improves the efficiency of analyzing large batches of access delays.

[0109] An embodiment of the present application further provides a computer device, including a processor and a memory, wherein the memory stores computer instructions, and the processor executes the computer instructions to implement the access delay analysis method as described above.

[0110] An embodiment of the present application also provides a computer program, which is executed to implement the access delay analysis method as described above.

[0111] An embodiment of the present application further provides a storage medium, wherein the storage medium stores computer instructions, and when the computer instructions are executed, the access delay analysis method as described above is implemented.

[0112] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for analyzing access delay, characterized in that: include: Get the path number of the target access path; Determine the functional unit through which the target access path passes based on the path number; wherein the functional unit includes an input port and an output port; Acquire characteristic signals of all access paths passing through the functional unit; the characteristic signals include input characteristic signals passing through input ports of the functional unit and output characteristic signals passing through output ports of the functional unit; Acquire a waveform file including at least the target access path, and determine an input timestamp corresponding to the input characteristic signal and an output timestamp corresponding to the output characteristic signal according to the waveform file and the characteristic signal; Determine all the input characteristic signals and output characteristic signals belonging to the same access path, so as to determine all the input timestamps and output timestamps belonging to the same access path; A delay is calculated using the corresponding output timestamp and the input timestamp.

2. The access delay analysis method according to claim 1, characterized in that: After the step of acquiring the characteristic signal of the at least one functional unit, the method further includes: A corresponding matching method is obtained according to the subsystem to which the functional unit belongs; the matching method is used to determine a matching algorithm for extracting feature values.

3. The access delay analysis method according to claim 2, characterized in that: The matching algorithm includes a conversion algorithm for converting the characteristic value of one subsystem into the characteristic value of another subsystem.

4. The access delay analysis method according to claim 3, characterized in that: After the step of obtaining the waveform file of the target access path and obtaining the input timestamp corresponding to the input characteristic signal and the output timestamp corresponding to the output characteristic signal according to the waveform file, the method further includes: According to the matching method, the corresponding matching algorithm is called to extract and store feature value groups from the feature signal; each of the feature value groups includes at least one feature value; the feature value groups include an input feature value group and an output feature value group.

5. The access delay analysis method according to claim 4, characterized in that: Each of the feature value groups and the corresponding timestamp is a group of matching data, and the matching data is stored in a matching data container; The matching data container includes at least one matching data sub-container, and the matching data sub-container is used to store matching data of a target access path; The matching data sub-container includes at least one matching data secondary container, and the matching data secondary container is used to store the matching data of a functional unit.

6. The access delay analysis method according to claim 3, characterized in that: The step of acquiring the characteristic signal of the at least one functional unit comprises: Acquire a characteristic signal set, and acquire a characteristic signal set of each functional unit in the characteristic signal set; the characteristic signal set of the functional unit includes an input characteristic signal set corresponding to an input port of the functional unit, and an output characteristic signal set corresponding to an output port.

7. The access delay analysis method according to claim 6, characterized in that: The characteristic signal and the matching method are stored in a characteristic signal container; The characteristic signal container includes at least one characteristic signal sub-container, each of which stores a characteristic signal of the target access path and the matching method; The characteristic signal sub-container includes at least one characteristic signal secondary container, each of which stores a characteristic signal of a functional unit and the matching method; The characteristic signal secondary container includes two rows of data, wherein the first row is the input characteristic signal of the functional unit input port and the matching method of the input port; the second row is the output characteristic signal of the functional unit output port and the matching method of the output port.

8. The method for analyzing access delay according to claim 5, characterized in that: The step of determining the intervals between all the input characteristic signals and the output characteristic signals belonging to the same access path, so as to determine the intervals between all the input timestamps and the output timestamps belonging to the same access path, comprises: Acquire the first matching data in the unreordered matching data in the input port group of the first matching data secondary container in the matching data subcontainer as the first matching data; Traversing the matching data sub-container to search for second matching data having a feature value group that matches the feature value group of the first matching data; updating the second matching data to the first matching data in the matching data that has not been reordered in the input port group or the output port group where the second matching data is located; The first matching data is repeatedly obtained until all the matching data in the input port group of the first matching data secondary container in the matching data sub-container are reordered.

9. The access delay analysis method according to claim 5, characterized in that: The step of calculating the delay using the corresponding output timestamp and input timestamp comprises: Subtract the timestamp of a certain bit of the output port group of the matching data secondary container from the timestamp of the same bit of the output port group to obtain a delay of the request or response corresponding to the matching data of the bit passing through the functional unit; Or, the timestamp of a certain bit of the input port group of the next matching data sub-container is subtracted from the timestamp of the same bit of the output port group of the previous matching data sub-container to obtain the delay of the request or response corresponding to the matching data of the bit being transmitted from the previous matching data sub-container to the next matching data sub-container; Or, in the matching data sub-container belonging to the same sub-system, the timestamp of a certain bit of the output port group of the last matching data sub-container is subtracted from the timestamp of the same bit of the input port group of the first matching data sub-container to obtain the delay of the request or response corresponding to the matching data of the bit passing through the sub-system. Or, the timestamp of a certain bit of the output port group of the last matching data subcontainer in the matching data subcontainer is subtracted from the timestamp of the same bit of the input port group of the first matching data subcontainer to obtain the delay of the request or response corresponding to the matching data of the bit passing through the entire system path; Or add the delay of the request of the target access path through the entire system path and the delay of the response through the entire system path.

10. The access delay analysis method according to claim 1, characterized in that: The access types include request and response; The path number includes the number of the device and / or the number of the functional unit through which the request and response of the target access path pass.

11. The access delay analysis method according to claim 10, characterized in that: The step of determining the functional units through which the target access path passes based on the path number includes: parsing the path number to determine the functional units through which the target access path passes.

12. An access delay analysis device, characterized in that: include: A path parsing unit, used to obtain a path number of a target access path; Determine the functional unit through which the target access path passes based on the path number; wherein the functional unit includes an input port and an output port; obtain characteristic signals of all access paths passing through the functional unit; the characteristic signals include input characteristic signals passing through the input port of the functional unit and output characteristic signals passing through the output port of the functional unit; A data extraction module, used to obtain a waveform file including at least the target access path, and determine an input timestamp corresponding to the input characteristic signal and an output timestamp corresponding to the output characteristic signal according to the waveform file and the characteristic signal; A reordering module, used to determine all the input characteristic signals and output characteristic signals belonging to the same access path, so as to determine all the input timestamps and output timestamps belonging to the same access path; The access delay analysis unit is used to calculate the delay using the corresponding output timestamp and input timestamp.

13. The access delay analysis device according to claim 12, characterized in that: The path parsing unit is used to obtain a corresponding matching method according to the subsystem to which the functional unit belongs; the matching method is used to determine a matching algorithm for extracting feature values.

14. The access delay analysis device according to claim 13, characterized in that: The matching algorithm includes a conversion algorithm for converting the characteristic value of one subsystem into the characteristic value of another subsystem.

15. The access delay analysis device according to claim 14, characterized in that: Also includes: A matching algorithm unit is used to extract and store a feature value group from a feature signal by calling a corresponding matching algorithm according to the matching method; each of the feature value groups includes at least one feature value; and the feature value groups include an input feature value group and an output feature value group.

16. The access delay analysis device according to claim 14, characterized in that: Each of the characteristic value groups and the corresponding timestamps is a group of matching data, and the access delay analysis device further includes: a matching data container for storing the matching data; The matching data container includes at least one matching data sub-container, and the matching data sub-container is used to store matching data of a target access path; The matching data sub-container includes at least one matching data secondary container, and the matching data secondary container is used to store the matching data of a functional unit.

17. The access delay analysis device according to claim 14, characterized in that: The path parsing unit is used to obtain a characteristic signal set, and obtain a characteristic signal set of each functional unit within the characteristic signal set; the characteristic signal set of the functional unit includes an input characteristic signal set corresponding to the input port of the functional unit, and an output characteristic signal set corresponding to the output port.

18. The access delay analysis device according to claim 17, characterized in that: Also includes: A characteristic signal container, used for storing characteristic signals and the matching method; The characteristic signal container includes at least one characteristic signal sub-container, each of which stores a characteristic signal of the target access path and the matching method; The characteristic signal sub-container includes at least one characteristic signal secondary container, each of which stores a characteristic signal of a functional unit and the matching method; The characteristic signal secondary container includes two rows of data, wherein the first row is the input characteristic signal of the functional unit input port and the matching method of the input port; the second row is the output characteristic signal of the functional unit output port and the matching method of the output port.

19. The access delay analysis device according to claim 16, characterized in that: The reordering module is used to obtain the first matching data in the unreordered matching data in the input port group of the first matching data secondary container in the matching data subcontainer as the first matching data; Traversing the matching data sub-container to search for second matching data having a feature value group that matches the feature value group of the first matching data; updating the second matching data to the first matching data in the matching data that has not been reordered in the input port group or the output port group where the second matching data is located; The first matching data is repeatedly obtained until all the matching data in the input port group of the first matching data secondary container in the matching data sub-container are reordered.

20. The access delay analysis device according to claim 16, characterized in that: The access delay analysis unit is used to obtain delay information by subtracting the timestamp of the input feature value group from the timestamp of the output feature value group of each functional unit.

21. The access delay analysis device according to claim 12, characterized in that: The target access path includes a request path and a response path; The path number includes the number of the device and / or the number of the functional unit through which the request and response of the target access path pass.

22. The access delay analysis device according to claim 12, characterized in that: A path parsing unit is used to parse the path number to determine at least one functional unit through which the target access path passes.

23. A computer device, characterized in that: The method comprises a processor and a memory, wherein the memory stores computer instructions, and the processor executes the computer instructions to implement the access delay analysis method according to any one of claims 1 to 11.

24. A computer program, characterized in that The method comprises computer instructions, which, when executed, implement the access delay analysis method as described in any one of claims 1 to 11.

25. A storage medium, characterized in that: The storage medium stores computer instructions, and when the computer instructions are executed, the access delay analysis method according to any one of claims 1 to 11 is implemented.

Images