Chip surface defect detection method and system

Abstract

The invention discloses a chip surface defect detection method and system, and relates to the technical field of defect detection.According to the system, a morphological feature set Xi, a texture feature set Wi and an edge feature set Bi of a chip surface are extracted through a feature extraction module, and a defect probability Pdefect is calculated in combination with a CNN deep learning model. In the defect evaluation module, according to a preset defect threshold value F1, the defects on the surface of the current chip are preliminarily evaluated, and whether the defects exist or not is determined. Then, a support vector machine (SVM) algorithm is used for carrying out detailed classification on the detected defects, a defect severity score Sdefect is obtained, and a score interval [Pf1, Pf2] is preset to carry out grade division on the severity of the defects; the multi-level defect evaluation and classification method not only can identify the defects, but also can evaluate the severity of the defects and the influence of the severity of the defects on chip functions, and provides comprehensive reference for production and quality control.

Description

Technical Field

[0001] The present invention relates to the technical field of defect detection, and in particular to a chip surface defect detection method and system. Background Art

[0002] Chip, usually refers to integrated circuit, is a microelectronic device made of semiconductor materials. Chips are the core components of modern electronic devices and are widely used in various devices such as computers, mobile phones, home appliances, and automobiles. Chip defect detection is an important step to ensure the quality and reliability of integrated circuits (ICs) during the manufacturing process and in the final product. Due to the complexity and precision of chip manufacturing processes, even tiny defects may cause chip failure or performance degradation. The purpose of defect detection is to identify and eliminate these defects to ensure that the function and performance of the chip meet the expected standards.

[0003] At present, traditional defect detection methods rely on manual visual inspection, which is not only inefficient, but also easily affected by human factors, resulting in missed detection and false detection. At the same time, traditional methods are susceptible to noise interference and have limited recognition capabilities for complex image features, resulting in inaccurate detection results, affecting subsequent processing and repair work. In addition, the lack of unified evaluation standards and automated tools makes defect evaluation highly subjective, making it difficult to ensure the consistency and objectivity of evaluation results. Summary of the invention

[0004] In view of the deficiencies in the prior art, the present invention provides a chip surface defect detection method and system, which solves the problems mentioned in the background technology.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: including an image acquisition module, a feature extraction module, a defect detection module, a defect assessment module and a defect classification module;

[0006] The image acquisition module is used to acquire chip surface images using a high-resolution camera and a microscope device, and to pre-process the acquired chip surface images;

[0007] The feature extraction module is used to extract the morphological feature set Xi, texture feature set Wi and edge feature set Bi of the chip surface after preprocessing the chip surface image using a machine learning algorithm;

[0008] The defect detection module is used to build a deep learning model and use the convolutional neural network (CNN) algorithm to calculate and analyze the extracted chip surface features to obtain the defect probability P. defect ;

[0009] The defect assessment module is used to obtain the defect probability P defectPreset defect threshold F1 for preliminary evaluation and analyze the defects on the current chip surface;

[0010] The defect classification module is used to classify the identified defects using the support vector machine (SVM) algorithm to obtain the defect severity score S defect , and evaluate the impact of defects, generate reports and annotate defects.

[0011] Preferably, the image acquisition module includes an image acquisition unit and an image preprocessing unit;

[0012] The image acquisition unit is used to fix a high-resolution industrial camera with a resolution of tens of millions pixels on a chip detection workbench, and at the same time, in combination with a microscope device, adjust the focal length of the camera according to the unevenness of the chip surface and the fine structure that needs to be captured, and use multi-angle and multi-light source imaging technology to capture the surface details of the chip at different angles, obtain the chip surface image, and summarize these images to generate a chip surface image set I.

[0013] Preferably, the image preprocessing unit is used to preprocess the acquired chip surface image set I through a preprocessing algorithm, and the preprocessing method includes denoising and contrast optimization;

[0014] The denoising process is performed on the collected chip surface image set I by a denoising algorithm to obtain the denoised chip surface image set I denoised ;

[0015] The first chip surface image set I after denoising denoised Obtained through the following algorithm formula;

[0016] I = Denoise (I);

[0017] Wherein Denoise(I) represents the operation of denoising the chip surface image set I, and Denoise represents any denoising algorithm and method among Gaussian filtering, median filtering, wavelet denoising, non-local mean denoising and total variation denoising, which depends on the denoising technology selected in the actual application;

[0018] The optimized contrast is used to optimize the first chip surface image set I after denoising. denoised , improve the image contrast by optimizing the image contrast method, and obtain the second chip surface image set I after contrast optimization processing enhanced ,

[0019] The chip surface image set I enhanced Obtained through the following algorithm formula;

[0020] I enhanced =EnhanceConteast(Idenoised );

[0021] Wherein, EnhanceContrast represents an operation of optimizing image contrast, and the specific operation includes any one of histogram equalization, adaptive histogram equalization, contrast stretching and CLAHE to optimize image contrast, depending on the image optimization operation selected in the actual application.

[0022] Preferably, the feature extraction module is used to extract the second chip surface image set I from the pre-processed enhanced The chip defect feature extraction is performed in the chip defect detection method, and the specific feature extraction method includes edge detection, texture analysis and morphological feature extraction, and the morphological feature set Xi, texture feature set Wi and edge feature set Bi are obtained;

[0023] The morphological feature set Xi includes expansion degree X1, corrosion area X2, scratch length X3, edge burr X4 and hole number X5;

[0024] The texture feature set Wi includes texture uniformity W1, texture contrast W2 and texture entropy W3;

[0025] The edge feature set Bi includes chip size B1, chip position accuracy B2 and solder joint accuracy B3.

[0026] Preferably, the defect detection module includes a defect detection model unit and a defect calculation unit;

[0027] The defect detection model unit includes a model building unit and a model training unit;

[0028] The model building unit is used to build a deep learning model and design a convolutional neural network (CNN) structure, wherein the convolutional neural network (CNN) structure includes a convolutional layer, a pooling layer, a fully connected layer, and an activation function;

[0029] Through the convolution layer, different features are detected through different convolution kernels for the extracted morphological feature set Xi, texture feature set Wi and edge feature set Bi, and the spatial dimension of the feature image is improved through the pooling layer, the amount of calculation is optimized while retaining the main features, and then the convolution layer output chip feature image set is converted into the final classification output, and then the nonlinear expression ability of the network is optimized through the activation function;

[0030] The model training unit is used to use the historical second chip surface image set I enhanced The deep learning model is trained and the cross entropy loss function is selected to measure the difference between the model output and the true label. The network parameters are adjusted through the Adam optimizer, the learning rate, batch size and number of training rounds are set, and the network parameters are updated through the back propagation algorithm to iteratively learn the model.

[0031] Preferably, the defect calculation unit is used to take a picture of the chip currently being tested, perform preprocessing and feature extraction, input the morphological feature set Xi, texture feature set Wi and edge feature set Bi of the current chip image into the deep learning model, analyze and calculate the feature set through the convolutional neural network CNN algorithm, and obtain the defect probability P defect ;

[0032] The defect probability P defect Obtained through the following algorithm formula;

[0033] P defect =f[W*(Xi,Wi,Bi)+b];

[0034] In the formula, W and b represent the weight value and bias value of the neural network respectively, f represents the activation function, and W*(Xi, Wi, Bi) represents the weight of any defect in the morphological feature set Xi, the texture feature set Wi, and the edge feature set Bi.

[0035] Preferably, the defect assessment module is used to determine the defect probability P according to the obtained defect probability P. defect , preset defect threshold F1, and the current detected chip defect probability P defect Conduct a preliminary assessment and analyze the current chip defects. The specific assessment contents are as follows;

[0036] When the defect probability P defect > defect threshold F1, it is determined that there is a defect, and the chip defects are further classified;

[0037] When the defect probability P defect ≤defect threshold F1, there is no defect.

[0038] Preferably, the defect classification module includes a defect classification algorithm unit, a classification evaluation unit and a report generation unit;

[0039] The defect classification algorithm unit is used to execute the second set of algorithm formulas for detailed evaluation and classification based on the preliminary evaluation results, and to construct a support vector machine (SVM) model, input the extracted feature set into the trained support vector machine (SVM) model, and calculate and analyze the feature set by using the support vector machine (SVM) algorithm to obtain the defect severity score S. defect ;

[0040] The defect severity score S defect Obtained through the following algorithm formula;

[0041] S defect =Classify[(Xi, Wi, Bi), P defect ];

[0042] In the formula, Classify represents the classification operation, which is used to analyze the extracted features and classify them into different types of defects while evaluating their severity.

[0043] Preferably, the classification evaluation unit is used to evaluate the defect severity score S according to the characteristics and classification results. defect , the severity of the defects is graded using the preset scoring interval [Pf1, Pf2], and the specific classification is as follows;

[0044] When the defect severity score S defect >Pf1, it is marked as a first-level defect, indicating that the current defect has an abnormal impact on the chip function and needs to be scrapped or complicated repairs;

[0045] When Pf2≤defect severity score S defect When ≤Pf1, it is marked as a secondary defect, indicating that the current defect affects the chip function and needs to be repaired;

[0046] When the defect severity score S defect When <Pf2, it is marked as a secondary defect, indicating that the current defect has no effect on the chip function and no further operation is required;

[0047] The report generation unit is used to mark the location of the defect on the image based on the classification and evaluation results, mark each defect next to the image as belonging to any defect in the morphological feature set Xi, the texture feature set Wi and the edge feature set Bi, and then assign the marked defects a defect severity score S defect , shown in the report.

[0048] A chip surface defect detection method comprises the following steps:

[0049] S1. Use a high-resolution industrial camera and a microscope to adjust the focal length, use multi-angle and multi-light source imaging technology to collect chip surface images and summarize them to generate a chip surface image set I, and then pre-process the image set I to obtain the first chip surface image set I denoised and the second chip surface image set I enhanced ;

[0050] S2, from the pre-processed second chip surface image set I enhanced Extract morphological feature set X, texture feature set Wi, and edge feature set Bi;

[0051] S3, design a convolutional neural network (CNN) structure, detect different features through different convolution kernels, and then use the second chip surface image set I of the historical image enhanced Perform model training, then transfer the current chip image feature set to the deep learning model for analysis to obtain the defect probability Pdefect ;

[0052] S4. Based on the obtained defect probability P defect , set the preset defect threshold F1 to determine the existence of current chip defects;

[0053] S5. Build a support vector machine (SVM) model, input the extracted feature set into the trained SVM model, and calculate and analyze the defect severity score S through the SVM algorithm. defect , then evaluate and divide the severity of the defects according to the scoring range [Pf1, Pf2], and then generate a classification report based on the classification and evaluation results.

[0054] The present invention provides a chip surface defect detection method and system, which has the following beneficial effects:

[0055] (1) The system uses high-resolution cameras and microscopes to capture images of the chip surface. Multi-angle and multi-light source imaging technology ensures that the captured images are of high quality and detail. Image preprocessing improves image clarity and contrast, providing a good foundation for subsequent feature extraction and defect detection. Using convolutional neural networks (CNN) for deep learning analysis enables the system to accurately identify and detect tiny defects on the chip surface, thereby improving the accuracy and reliability of defect detection.

[0056] (2) The system extracts the morphological features, texture features, and edge features of the chip surface through the feature extraction module, and combines it with the CNN deep learning model to calculate the defect probability P defect In the defect assessment module, the defects on the current chip surface are preliminarily assessed according to the preset defect threshold to determine whether there are defects. Subsequently, the detected defects are classified in detail using the support vector machine (SVM) algorithm to obtain the defect severity score S defect This multi-level defect assessment and classification method can not only identify defects, but also assess the severity of defects and their impact on chip functions, providing a comprehensive reference for production and quality control.

[0057] (3) Based on the defect classification and evaluation results, the system can mark the location of defects on the image and mark the type and severity score of each defect. The report generation unit integrates this information into the final inspection report, providing intuitive defect distribution and classification results. This report can not only be used for real-time defect management on the production line, but also provide detailed data support for subsequent maintenance and quality improvement. By automatically generating reports, the efficiency of defect management is improved, the time and workload of manual analysis are reduced, thereby improving the efficiency and quality of the overall production process. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 The figure is a schematic flow chart of a chip surface defect detection system according to the present invention.

[0059] Figure 2 The figure is a schematic diagram of the steps of a chip surface defect detection method of the present invention. DETAILED DESCRIPTION

[0060] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0061] Example 1

[0062] See also Figure 1 , the present invention provides a chip surface defect detection system. To achieve the above purpose, the present invention is implemented through the following technical scheme: including an image acquisition module, a feature extraction module, a defect detection module, a defect assessment module and a defect classification module;

[0063] The image acquisition module is used to acquire chip surface images using a high-resolution camera and a microscope device, and to pre-process the acquired chip surface images;

[0064] The feature extraction module is used to extract the morphological feature set Xi, texture feature set Wi and edge feature set Bi of the chip surface after preprocessing the chip surface image using a machine learning algorithm;

[0065] The defect detection module is used to build a deep learning model and use the convolutional neural network (CNN) algorithm to calculate and analyze the extracted chip surface features to obtain the defect probability P. defect ;

[0066] The defect assessment module is used to obtain the defect probability P defect Preset defect threshold F1 for preliminary evaluation and analyze the defects on the current chip surface;

[0067] The defect classification module is used to classify the identified defects using the support vector machine (SVM) algorithm to obtain the defect severity score S. defect , and evaluate the impact of defects, generate reports and annotate defects.

[0068] In this embodiment, the system uses the cooperation of five modules to start with collecting chip surface images with a high-resolution camera and microscope, improve image quality through preprocessing, and then use machine learning algorithms to extract morphological features, texture features, and edge features. A deep learning model is constructed, and the extracted features are calculated and analyzed through a convolutional neural network (CNN) to obtain the defect probability P. defect . Finally, the support vector machine (SVM) algorithm is used to classify defects, evaluate the severity of defects and generate detailed reports. This system realizes the accurate identification, analysis and classification of chip surface defects, ensuring the improvement of production quality. Compared with traditional technical means, this system can not only realize the acquisition and preprocessing of high-resolution images, but also accurately identify and classify defects on the chip surface through machine learning and deep learning algorithms. This multi-level and multi-step detection method enables the system to conduct a comprehensive and detailed analysis of defects, which not only improves the accuracy of defect detection, but also greatly reduces the false alarm rate and missed alarm rate.

[0069] Example 2

[0070] This embodiment is explained in Example 1, please refer to Figure 1 ,Specifically: the image acquisition module includes an image acquisition unit and an image preprocessing unit;

[0071] The image acquisition unit is used to fix a high-resolution industrial camera with a resolution of tens of millions pixels on the chip detection workbench. At the same time, combined with a microscope device, the focal length of the camera is adjusted according to the unevenness of the chip surface and the fine structure that needs to be captured, and multi-angle and multi-light source imaging technology is used to capture the surface details of the chip at different angles, obtain the chip surface image, and summarize these images to generate a chip surface image set I.

[0072] The image preprocessing unit is used to preprocess the acquired chip surface image set I through a preprocessing algorithm, and the preprocessing method includes denoising and contrast optimization;

[0073] Denoising The collected chip surface image set I is denoised by a denoising algorithm to obtain a denoised chip surface image set I denoised ;

[0074] The first chip surface image set I after denoising denoised Obtained through the following algorithm formula;

[0075] I = Denoise (I);

[0076] Wherein Denoise(I) represents the operation of denoising the chip surface image set I, and Denoise represents any denoising algorithm and method among Gaussian filtering, median filtering, wavelet denoising, non-local mean denoising and total variation denoising, which depends on the denoising technology selected in the actual application;

[0077] Optimizing contrast is used for the first chip surface image set I after denoising denoised , improve the image contrast by optimizing the image contrast method, and obtain the second chip surface image set I after contrast optimization processing enhanced ,

[0078] Chip Surface Image Set I enhanced Obtained through the following algorithm formula;

[0079] I enhanced =EnhanceConteast(I denoised );

[0080] Wherein, EnhanceContrast represents an operation of optimizing image contrast, and the specific operation includes any one of histogram equalization, adaptive histogram equalization, contrast stretching and CLAHE to optimize image contrast, depending on the image optimization operation selected in the actual application.

[0081] In this embodiment, the system includes an image acquisition unit and an image preprocessing unit through an image acquisition module, which brings significant beneficial effects. The image acquisition unit uses a high-resolution industrial camera and a microscope device, combined with multi-angle and multi-light source imaging technology to ensure that the fine structure and uneven details of the chip surface are captured. This high-precision image acquisition method can obtain a comprehensive and detailed chip surface image, form a complete image set, and lay a solid foundation for subsequent defect detection. The image preprocessing unit processes the collected image set through preprocessing algorithms such as denoising and contrast optimization. The denoising process uses a variety of denoising algorithms such as Gaussian filtering, median filtering, wavelet denoising, non-local mean denoising and total variation denoising to significantly reduce the noise in the image and obtain a clearer chip surface image set. The optimized contrast processing further improves the contrast of the image and enhances the detail performance of the image through methods such as histogram equalization, adaptive histogram equalization, contrast stretching and CLAHE. These preprocessing operations not only improve the image quality, but also enhance the recognizability of the image, providing high-quality image data for feature extraction and defect detection.

[0082] Example 3

[0083] This embodiment is explained in Example 2. Please refer to Figure 1Specifically: the feature extraction module is used to extract the second chip surface image set I from the pre-processed enhanced The chip defect feature extraction is performed in the chip defect detection method, and the specific feature extraction method includes edge detection, texture analysis and morphological feature extraction, and the morphological feature set Xi, texture feature set Wi and edge feature set Bi are obtained;

[0084] The morphological feature set Xi includes expansion degree X1, corrosion area X2, scratch length X3, edge burr X4 and number of holes X5;

[0085] The texture feature set Wi includes texture uniformity W1, texture contrast W2 and texture entropy W3;

[0086] The edge feature set Bi includes chip size B1, chip position accuracy B2 and solder joint accuracy B3.

[0087] The defect detection module includes a defect detection model unit and a defect calculation unit;

[0088] The defect detection model unit includes a model building unit and a model training unit;

[0089] The model building unit is used to build a deep learning model and design a convolutional neural network (CNN) structure. The convolutional neural network (CNN) structure includes a convolutional layer, a pooling layer, a fully connected layer, and an activation function.

[0090] Through the convolution layer, different features are detected through different convolution kernels for the extracted morphological feature set Xi, texture feature set Wi and edge feature set Bi, and the spatial dimension of the feature image is improved through the pooling layer, the amount of calculation is optimized while retaining the main features, and then the convolution layer output chip feature image set is converted into the final classification output, and then the nonlinear expression ability of the network is optimized through the activation function;

[0091] The model training unit is used to use the historical second chip surface image set I enhanced The deep learning model is trained and the cross entropy loss function is selected to measure the difference between the model output and the true label. The network parameters are adjusted through the Adam optimizer, the learning rate, batch size and number of training rounds are set, and the network parameters are updated through the back propagation algorithm to iteratively learn the model.

[0092] In this embodiment, the system realizes efficient and accurate chip surface defect detection through a variety of innovative technologies through the feature extraction module and the defect detection module, bringing significant beneficial effects. The feature extraction module obtains detailed morphological feature sets Xi, texture feature sets Wi and edge feature sets Bi from the preprocessed image through edge detection, texture analysis and morphological feature extraction. This comprehensive feature extraction method ensures the comprehensive capture of chip surface features and provides a rich and accurate data basis for subsequent defect detection. The defect detection module effectively improves the accuracy and efficiency of defect detection by constructing a deep learning model and designing a convolutional neural network CNN structure. The convolution layer uses different convolution kernels to perform multi-level feature detection on the morphological feature set Xi, texture feature set Wi and edge feature set Bi, and the pooling layer optimizes the spatial dimension of the feature image, reducing the amount of calculation while retaining the main features. Finally, through the fully connected layer and activation function, the nonlinear expression ability of the network is enhanced to ensure the accuracy of the detection results. The model training unit uses historical data to train the deep learning model, measures the difference between the model output and the true label through the cross entropy loss function, and uses the Adam optimizer to adjust the network parameters. Through the back-propagation algorithm, the network parameters are iteratively updated to make the model more generalizable and accurate.

[0093] Example 4

[0094] This embodiment is explained in Example 3, please refer to Figure 1 Specifically: the defect calculation unit is used to take a picture of the chip being tested, perform preprocessing and feature extraction, and then input the morphological feature set Xi, texture feature set Wi and edge feature set Bi of the current chip image into the deep learning model, and analyze and calculate the feature set through the convolutional neural network CNN algorithm to obtain the defect probability P defect ;

[0095] Defect probability P defect Obtained through the following algorithm formula;

[0096] P defect =f[W*(Xi,Wi,Bi)+b];

[0097] In the formula, W and b represent the weight value and bias value of the neural network respectively, f represents the activation function, and W*(Xi, Wi, Bi) represents the weight of any defect in the morphological feature set Xi, the texture feature set Wi, and the edge feature set Bi.

[0098] The defect assessment module is used to obtain the defect probability P defect , preset defect threshold F1, and calculate the defect probability P of the chip currently detected defectConduct a preliminary assessment and analyze the current chip defects. The specific assessment contents are as follows;

[0099] When the defect probability P defect > defect threshold F1, it is determined that there is a defect, and the chip defects are further classified;

[0100] When the defect probability P defect ≤defect threshold F1, there is no defect.

[0101] In this embodiment, the system achieves efficient and accurate defect detection and evaluation through advanced deep learning technology through the defect calculation unit and defect assessment module, bringing significant beneficial effects. The defect calculation unit inputs the preprocessed chip image feature set into the deep learning model, and uses the convolutional neural network CNN to analyze and calculate the feature set to obtain the defect probability P defect The use of CNN algorithm can not only process a large amount of data efficiently, but also accurately identify and locate various defects on the chip through a multi-layer neural network structure. The defect assessment module sets a preset defect threshold F1 and evaluates the defect probability P defect Specifically, when the defect probability P defect When the defect probability P is greater than the preset threshold F1, the system determines that the chip has defects and further classifies the defects in detail. defect When it is less than or equal to the preset threshold F1, the system determines that the chip does not have defects. In this way, by reasonably setting the defect threshold, the system can effectively distinguish between defective and non-defective chips, ensuring the reliability and accuracy of the detection results.

[0102] Example 5

[0103] This embodiment is explained in Example 4. Please refer to Figure 1 ,Specifically: the defect classification module includes a defect classification algorithm unit, a ,classification evaluation unit and a report generation unit;

[0104] The defect classification algorithm unit is used to execute the second set of algorithm formulas for detailed evaluation and classification based on the preliminary evaluation results. By building a support vector machine (SVM) model, the extracted feature set is input into the trained support vector machine (SVM) model. The feature set is calculated and analyzed by using the support vector machine (SVM) algorithm to obtain the defect severity score S. defect ;

[0105] Defect severity score S defect Obtained through the following algorithm formula;

[0106] S defect =Classify[(Xi, Wi, Bi), P defect ];

[0107] In the formula, Classify represents the classification operation, which is used to analyze the extracted features and classify them into different types of defects while evaluating their severity.

[0108] The classification evaluation unit is used to classify the defect severity score S according to the characteristics and classification results. defect , the severity of the defects is graded using the preset scoring interval [Pf1, Pf2], and the specific classification is as follows;

[0109] When the defect severity score S defect >Pf1, it is marked as a first-level defect, indicating that the current defect has an abnormal impact on the chip function and needs to be scrapped or complicated repairs;

[0110] When Pf2≤defect severity score S defect When ≤Pf1, it is marked as a secondary defect, indicating that the current defect affects the chip function and needs to be repaired;

[0111] When the defect severity score S defect When <Pf2, it is marked as a secondary defect, indicating that the current defect has no effect on the chip function and no further operation is required;

[0112] The report generation unit is used to mark the location of defects on the image based on the classification and evaluation results, and mark each defect next to the image as belonging to any defect in the morphological feature set Xi, texture feature set Wi and edge feature set Bi, and then assign the marked defects a defect severity score S defect , shown in the report.

[0113] In this embodiment, the system uses the support vector machine (SVM) model through the defect classification algorithm unit to perform detailed evaluation and classification on the feature set after preliminary evaluation. Through the SVM algorithm, the system can accurately calculate and analyze the defect severity score S defect This precise classification method can effectively distinguish different types of defects and evaluate their impact on chip functions, ensuring the accuracy and reliability of the classification results. The classification evaluation unit scores the defect severity S based on the obtained defect , the defects are graded. When the defect severity score S defect When the defect severity score is greater than the preset score interval Pf1, it is marked as a first-level defect, indicating that the defect has a serious impact on the chip function and needs to be scrapped or repaired in a complex manner. defect When the defect severity score is between Pf2 and Pf1, it is marked as a level 2 defect, indicating that the defect has a certain impact on the chip function and needs to be repaired. defectWhen it is less than Pf2, it is marked as a level 3 defect, indicating that the defect has no effect on the chip function and no further operation is required. This classification method not only improves the accuracy of defect assessment, but also can reasonably allocate resources and improve maintenance efficiency. Based on the classification and evaluation results, the report generation unit marks the location of the defect and its classification results on the image, annotates each defect in detail as any defect in the morphological feature set Xi, texture feature set Wi and edge feature set Bi, and displays its severity score S defect This report generation method not only displays the test results intuitively and clearly, but also provides an important reference for subsequent repairs and quality control. Overall, the system has greatly improved the efficiency and accuracy of defect detection and processing through precise defect classification and detailed report generation, significantly improved quality control in the chip production process, and ensured high-quality product output.

[0114] Example 6

[0115] See also Figure 1 and Figure 2 , a chip surface defect detection method, comprising the following steps:

[0116] S1. First, receive and send communication signals through 5G base stations, deploy sensors and monitoring equipment, collect communication data in real time, and then summarize and obtain communication data sets to store in the database;

[0117] S2. Use filters and smoothing algorithms to remove outliers, missing data, and noise data, unify the data to the same dimension and range, and perform feature extraction on the communication data set to obtain the average delay D. avg , average signal strength S avg and the average signal-to-noise ratio SNR avg ;

[0118] S3, calculating the signal jitter coefficient J according to the delay D, and comparing and evaluating the signal jitter coefficient J with the preset jitter threshold F1;

[0119] S4. When the signal jitter is abnormal, further calculation is required to obtain the signal strength fluctuation coefficient S var SNR var , and then the average delay D avg Correlate with the signal jitter coefficient J to obtain the comprehensive evaluation index Q;

[0120] S5. Finally, the comprehensive evaluation index Q is compared with the preset comprehensive evaluation threshold F2 to comprehensively evaluate the performance and stability of the 5G communication network, and optimization measures are implemented based on the evaluation results.

[0121] While the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that many changes, modifications, substitutions and variations can be made to the embodiments without departing from the principles and spirit of the invention.

Claims

1. A chip surface defect detection system, characterized in that: It includes image acquisition module, feature extraction module, defect detection module, defect assessment module and defect classification module; The image acquisition module is used to acquire chip surface images using a high-resolution camera and a microscope device, and to pre-process the acquired chip surface images; The feature extraction module is used to extract the morphological feature set Xi, texture feature set Wi and edge feature set Bi of the chip surface after preprocessing the chip surface image using a machine learning algorithm; The defect detection module is used to build a deep learning model and use the convolutional neural network (CNN) algorithm to calculate and analyze the extracted chip surface features to obtain the defect probability P. defect ; The defect assessment module is used to obtain the defect probability P defect Preset defect threshold F1 for preliminary evaluation and analyze the defects on the current chip surface; The defect classification module is used to classify the identified defects using the support vector machine (SVM) algorithm to obtain the defect severity score S defect , and evaluate the impact of defects, generate reports and annotate defects.

2. A chip surface defect detection system according to claim 1, characterized in that: The image acquisition module includes an image acquisition unit and an image preprocessing unit; The image acquisition unit is used to fix a high-resolution industrial camera with a resolution of tens of millions pixels on a chip detection workbench, and at the same time, in combination with a microscope device, adjust the focal length of the camera according to the unevenness of the chip surface and the fine structure that needs to be captured, and use multi-angle and multi-light source imaging technology to capture the surface details of the chip at different angles, obtain the chip surface image, and summarize these images to generate a chip surface image set I.

3. A chip surface defect detection system according to claim 2, characterized in that: The image preprocessing unit is used to preprocess the acquired chip surface image set I through a preprocessing algorithm, and the preprocessing method includes denoising and contrast optimization; The denoising process is performed on the collected chip surface image set I by a denoising algorithm to obtain the denoised chip surface image set I denoised ; The first chip surface image set I after denoising denoised Obtained through the following algorithm formula; I = Denoise (I); Wherein Denoise(I) represents the operation of denoising the chip surface image set I, and Denoise represents any denoising algorithm and method among Gaussian filtering, median filtering, wavelet denoising, non-local mean denoising and total variation denoising, which depends on the denoising technology selected in the actual application; The optimized contrast is used to optimize the first chip surface image set I after denoising. denoised , improve the image contrast by optimizing the image contrast method, and obtain the second chip surface image set I after contrast optimization processing enhanced , The chip surface image set I enhanced Obtained through the following algorithm formula; I enhanced =EnhanceConteast(I denoised ); Wherein, EnhanceContrast represents an operation of optimizing image contrast, and the specific operation includes any one of histogram equalization, adaptive histogram equalization, contrast stretching and CLAHE to optimize image contrast, depending on the image optimization operation selected in the actual application.

4. A chip surface defect detection system according to claim 3, characterized in that: The feature extraction module is used to extract the second chip surface image set I from the pre-processed enhanced The chip defect feature extraction is performed in the chip defect detection method, and the specific feature extraction method includes edge detection, texture analysis and morphological feature extraction, and the morphological feature set Xi, texture feature set Wi and edge feature set Bi are obtained; The morphological feature set Xi includes expansion degree X1, corrosion area X2, scratch length X3, edge burr X4 and hole number X5; The texture feature set Wi includes texture uniformity W1, texture contrast W2 and texture entropy W3; The edge feature set Bi includes chip size B1, chip position accuracy B2 and solder joint accuracy B3.

5. A chip surface defect detection system according to claim 4, characterized in that: The defect detection module includes a defect detection model unit and a defect calculation unit; The defect detection model unit includes a model building unit and a model training unit; The model building unit is used to build a deep learning model and design a convolutional neural network (CNN) structure, wherein the convolutional neural network (CNN) structure includes a convolutional layer, a pooling layer, a fully connected layer, and an activation function; Through the convolution layer, different features are detected through different convolution kernels for the extracted morphological feature set Xi, texture feature set Wi and edge feature set Bi, and the spatial dimension of the feature image is improved through the pooling layer, the amount of calculation is optimized while retaining the main features, and then the convolution layer output chip feature image set is converted into the final classification output, and then the nonlinear expression ability of the network is optimized through the activation function; The model training unit is used to use the historical second chip surface image set I enhanced The deep learning model is trained and the cross entropy loss function is selected to measure the difference between the model output and the true label. The network parameters are adjusted through the Adam optimizer, the learning rate, batch size and number of training rounds are set, and the network parameters are updated through the back propagation algorithm to iteratively learn the model.

6. A chip surface defect detection system according to claim 5, characterized in that: The defect calculation unit is used to take a picture of the chip being tested, perform preprocessing and feature extraction, and then input the morphological feature set Xi, texture feature set Wi and edge feature set Bi of the current chip image into the deep learning model, and analyze and calculate the feature set through the convolutional neural network CNN algorithm to obtain the defect probability P defect ; The defect probability P defect Obtained through the following algorithm formula; Q defect =f[W*(Xi,Wi,Bi)+b]; In the formula, W and b represent the weight value and bias value of the neural network respectively, and f represents the activation function.

7. A chip surface defect detection system according to claim 6, characterized in that: The defect assessment module is used to obtain the defect probability P defect , preset defect threshold F1, and the current detected chip defect probability P defect Conduct a preliminary assessment and analyze the current chip defects. The specific assessment contents are as follows; When the defect probability P defect > defect threshold F1, it is determined that there is a defect, and the chip defects are further classified; When the defect probability P defect ≤defect threshold F1, there is no defect.

8. A chip surface defect detection system according to claim 6, characterized in that: The defect classification module includes a defect classification algorithm unit, a classification evaluation unit and a report generation unit; The defect classification algorithm unit is used to execute the second set of algorithm formulas for detailed evaluation and classification based on the preliminary evaluation results, and to construct a support vector machine (SVM) model, input the extracted feature set into the trained support vector machine (SVM) model, and calculate and analyze the feature set by using the support vector machine (SVM) algorithm to obtain the defect severity score S. defect ; The defect severity score S defect Obtained through the following algorithm formula; S defect =Classify[(Xi,Wi,Bi),P defect ]: In the formula, Classify represents the classification operation.

9. A chip surface defect detection system according to claim 8, characterized in that: The classification evaluation unit is used to evaluate the defect severity score S according to the characteristics and classification results. defect , the severity of the defects is graded using the preset scoring interval [Pf1, Pf2], and the specific classification is as follows; When the defect severity score S defect >Pf1, it is marked as a first-level defect, indicating that the current defect has an abnormal impact on the chip function and needs to be scrapped or complicated repairs; When Pf2≤defect severity score S defect When ≤Pf1, it is marked as a secondary defect, indicating that the current defect affects the chip function and needs to be repaired; When the defect severity score S defect When <Pf2, it is marked as a secondary defect, indicating that the current defect has no effect on the chip function and no further operation is required; The report generation unit is used to mark the location of the defect on the image based on the classification and evaluation results, mark each defect next to the image as belonging to any defect in the morphological feature set Xi, the texture feature set Wi and the edge feature set Bi, and then assign the marked defects a defect severity score S defect , shown in the report.

10. A chip surface defect detection method, comprising a chip surface defect detection system according to any one of claims 1 to 9, characterized in that: The following steps are involved: S1. Use a high-resolution industrial camera and a microscope to adjust the focal length, use multi-angle and multi-light source imaging technology to collect chip surface images and summarize them to generate a chip surface image set I, and then pre-process the image set I to obtain the first chip surface image set I denoised and the second chip surface image set I enhanced ; S2, from the pre-processed second chip surface image set I enhanced Extract morphological feature set X, texture feature set Wi, and edge feature set Bi; S3, design a convolutional neural network (CNN) structure, detect different features through different convolution kernels, and then use the second chip surface image set I of the historical image enhanced Perform model training, then transfer the current chip image feature set to the deep learning model for analysis to obtain the defect probability P defect ; S4. Based on the obtained defect probability P defect , set the preset defect threshold F1 to determine the existence of current chip defects; S5. Build a support vector machine (SVM) model, input the extracted feature set into the trained SVM model, and calculate and analyze the defect severity score S through the SVM algorithm. defect , then evaluate and divide the severity of the defects according to the scoring range [Pf1, Pf2], and then generate a classification report based on the classification and evaluation results.

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