Display panel, preparation method and control method thereof, and display device

Abstract

The application belongs to the technical field of display, and discloses a display panel, a preparation method and a control method thereof, and a display device, the display panel comprising a plurality of sub-pixels and a pixel driving circuit, the plurality of sub-pixels comprising a target sub-pixel, the target sub-pixel forming a gamma calibration area, the pixel driving circuit comprising a first sub-pixel driving circuit arranged in the gamma calibration area and a plurality of second sub-pixel driving circuits arranged outside the gamma calibration area; the first sub-pixel driving circuit comprising a first driving transistor having a first channel region; the second sub-pixel driving circuit comprising a second driving transistor having a second channel region, the width-length ratio of the corresponding second channel region of each second driving transistor being the same; and the width-length ratio of the first channel region being greater than the width-length ratio of the second channel region. The display panel can make the brightness of the target sub-pixel in the gamma calibration area the brightest of the display panel, improve the pixel uniformity compensation effect, and thus improve the brightness uniformity of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, a control method thereof, and a display device. Background Art

[0002] After all the hardware production of the display panel is completed, two electrical processes will be carried out: one is the photoelectric curve calibration, called gamma calibration (Gammer tuning), and the other is pixel uniformity compensation (PUC). PUC will use the brightness of the gamma target area as the target brightness. When the brightness of a pixel is lower than the target brightness, the input grayscale will be increased; when the brightness of a pixel is higher than the target brightness, the input grayscale will be reduced. When the picture is at low grayscale, if there is an area with a brightness higher than the target area, the grayscale of the area will be reduced after compensation, and it may enter the range of inaccurate gamma fitting, resulting in inaccurate brightness after PUC compensation. When the target area is the brightest area of ​​the panel, the grayscale of the remaining areas will be increased after compensation, and the grayscale will be in the range of accurate gamma fitting, and the brightness after compensation will be accurate. Therefore, if the area with lower screen brightness is used as the gamma calibration area, the PUC effect will be poor, affecting the uniformity of the brightness of the display panel. Summary of the Invention

[0003] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a display panel, a manufacturing method thereof, a control method thereof, and a display device.

[0004] In a first aspect, a display panel is provided, comprising: a plurality of sub-pixels and a pixel driving circuit, wherein the plurality of sub-pixels include a target sub-pixel, the target sub-pixel forming a gamma calibration area, the pixel driving circuit comprising a first sub-pixel driving circuit disposed within the gamma calibration area and a plurality of second sub-pixel driving circuits disposed outside the gamma calibration area;

[0005] The first sub-pixel driving circuit includes a first driving transistor, the first driving transistor includes a first channel region; the second sub-pixel driving circuit includes a second driving transistor, the second driving transistor includes a second channel region, and the second channel regions corresponding to the second driving transistors have the same width-to-length ratio;

[0006] The width-to-length ratio of the first channel region is greater than the width-to-length ratio of the second channel region; wherein the width-to-length ratio is the ratio of the width and length of the corresponding channel region, the length of the channel region is the length of the path of current flowing in the channel region, and the width of the channel region is the channel dimension perpendicular to the direction of current flow.

[0007] In addition, the display panel of the present invention may also have the following additional technical features:

[0008] In some embodiments, the width-to-length ratio of the first channel region is increased by 10-20% relative to the width-to-length ratio of the second channel region.

[0009] In some embodiments, the pixel driving circuit is provided with a substrate on a side away from the sub-pixel, and the first channel region and the second channel region have the same or different projected shapes on the substrate.

[0010] In some embodiments, the first channel region and the second channel region each include a first connecting segment, a second connecting segment, and a third connecting segment, and the second connecting segment is bently connected to the first connecting segment and the third connecting segment at two ends thereof.

[0011] In some embodiments, the first connecting segment, the second connecting segment, and the third connecting segment each have a square projected shape on the substrate.

[0012] In some embodiments, the first connecting segment and the third connecting segment are located on the same side of the second connecting segment, the first connecting segment is perpendicular to the second connecting segment, the third connecting segment is perpendicular to the second connecting segment, and the path length of the first connecting segment and the third connecting segment along the current flow direction is equal.

[0013] In some embodiments, the path length of the second connecting segment of the first channel region along the current flow direction is less than the path length of the second connecting segment of the second channel region along the current flow direction.

[0014] or / and,

[0015] the path length of the first connecting segment of the first channel region along the current flow direction is less than the path length of the first connecting segment of the second channel region along the current flow direction.

[0016] or / and,

[0017] the channel dimension of the second connecting segment of the first channel region along a direction perpendicular to the current flow direction is greater than the channel dimension of the second connecting segment of the second channel region along a direction perpendicular to the current flow direction.

[0018] In some embodiments, the second connecting segment of the first channel region and the second connecting segment of the second channel region have different projected shapes on the substrate, and the channel dimension of the second connecting segment of the first channel region along a direction perpendicular to the current flow direction is greater than the channel dimension of the second connecting segment of the second channel region along a direction perpendicular to the current flow direction.

[0019] In some embodiments, the second connecting section of the first channel region includes oppositely arranged first and second end faces, at least one of the first and second end faces is an arc-shaped face or a V-shaped face, and a projection of the second connecting section of the second channel region on the substrate is a square; a distance between the first and second end faces is greater than a channel dimension of the second connecting section of the second channel region in a direction perpendicular to a current flow direction.

[0020] In some embodiments, the target sub-pixel is one or more, each of the target sub-pixels is arranged one-to-one with the first sub-pixel driving circuit, and the target sub-pixel is located in a central region of the display panel.

[0021] In a second aspect, a manufacturing method of a display panel is provided, including:

[0022] forming a pixel driving circuit on a substrate, the pixel driving circuit including a first sub-pixel driving circuit and a plurality of second sub-pixel driving circuits, the first sub-pixel driving circuit including a first driving transistor, the first driving transistor including a first channel region; the second sub-pixel driving circuit including a second driving transistor, the second driving transistor including a second channel region, each of the second driving transistors corresponding to a second channel region with a same aspect ratio; wherein the aspect ratio is a ratio of a width and a length of a corresponding channel region, the length of the channel region is a path length of a current flow in the channel region, and the width of the channel region is a channel dimension perpendicular to the current flow direction;

[0023] forming a plurality of sub-pixels on a side of the pixel driving circuit away from the substrate, wherein a sub-pixel corresponding to the first pixel driving circuit is a target sub-pixel, and the target sub-pixel forms a gamma calibration region.

[0024] In some embodiments, the aspect ratio of the first channel region is greater than the aspect ratio of the second channel region by increasing a width of the first channel region or / and reducing a length of the first channel region.

[0025] In some embodiments, the aspect ratio of the first channel region is greater than the aspect ratio of the second channel region by changing a shape of the first channel region.

[0026] In a third aspect, a control method of a display panel is provided, the control method being used to control the display panel of any of the embodiments of the present application or the display panel obtained by the manufacturing method of any of the embodiments of the present application, and the control method includes:

[0027] The first sub-pixel driving circuit and the second sub-pixel driving circuit drive the corresponding sub-pixels to work under the same driving voltage, so that the brightness of the sub-pixels in the gamma calibration region is greater than the brightness of the sub-pixels outside the gamma calibration region.

[0028] In a fourth aspect, a display panel is provided. The display device includes the display panel described in any of the embodiments of the present application, or the display panel obtained by the preparation method of the display panel described in any of the embodiments of the present application.

[0029] The display panel and the preparation method, the control method and the display device thereof provided by the present disclosure. The display panel is obtained by differentiating the pixel driving circuit structure. The width-length ratio of the first channel region of the first sub-pixel driving circuit in the gamma calibration region is greater than the width-length ratio of the second channel region of the second sub-pixel driving circuit outside the gamma calibration region. The brightness of the target sub-pixel in the gamma calibration region is always the brightest in the display panel. After gamma calibration and pixel uniformity compensation, the brightness uniformity of the display panel can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only some of the drawings of the embodiments of the present disclosure. Those skilled in the art can also obtain other drawings from these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0031] Figure 1 The Gamma gray scale and voltage schematic diagram provided by the present application;

[0032] Figure 2 The position diagram of the gamma calibration region in the display panel provided by the present application;

[0033] Figure 3 The exemplary structure diagram of the first driving transistor provided by the embodiments of the present application;

[0034] Figure 4 The arrangement physical diagram of the second sub-pixel driving circuit in the peripheral region of the display panel provided by the embodiments of the present application;

[0035] Figure 5 The Figure 4 The circuit structure diagram of one second sub-pixel driving circuit;

[0036] Figure 6 The arrangement physical diagram of the first sub-pixel driving circuit in the gamma calibration region of the display panel provided by the embodiments of the present application;

[0037] Figure 7 A first exemplary structure diagram of the first sub-pixel driving circuit provided by the embodiment of the present application is provided.

[0038] Figure 8 A second exemplary structure diagram of the first sub-pixel driving circuit provided by the embodiment of the present application is provided.

[0039] Figure 9 A third exemplary structure diagram of the first sub-pixel driving circuit provided by the embodiment of the present application is provided.

[0040] Figure 10 A fourth exemplary structure diagram of the first sub-pixel driving circuit provided by the embodiment of the present application is provided.

[0041] Figure 11 A circuit diagram of the sub-pixel driving circuit 7T1C provided by the embodiment of the present application is provided.

[0042] Figure 12 A driving principle diagram of the sub-pixel driving circuit 7T1C provided by the embodiment of the present application is provided. (a) is an initialization stage; (b) is a data writing and compensation stage; (c) is a light emitting stage.

[0043] Figure 13 A timing diagram of the sub-pixel driving circuit 7T1C provided by the embodiment of the present application is provided.

[0044] Figure 14 A structure diagram of the display device provided by the embodiment of the present application is provided.

[0045] In the above figures:

[0046] 10 display panel; 101 gamma calibration area; 11 substrate substrate; 12 first sub-pixel driving circuit; 121 first driving transistor; 1210 active layer; 1211 first channel region; 1212 source region; 1213 drain region; 1220 gate; 1221 source; 1222 drain; 1230 gate insulating layer; 13 second sub-pixel driving circuit; 131 second driving transistor; 1310 second channel region;

[0047] 100 display device. DETAILED DESCRIPTION

[0048] The technical solutions in some embodiments of the present disclosure will be described clearly and completely below in combination with the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present disclosure.

[0049] Unless otherwise required by context, as used herein the terms "comprise", "comprises", "comprising", "includes", "including", "have", "has", "having", or variants thereof are to be construed as open- ended, i.e., to mean "including, but not limited to", or "including at least". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "one or more of", when preceding a list of two or more items, denote that individual items can be replaced by "at least one" of the listed items or by any single one of the listed items. Expressions such as "one or more of", when preceding a list of two or more items, denote that individual items can be replaced by "at least one" of the listed items or by any single one of the listed items. The term "plurality" means two or more, unless otherwise required by context.

[0050] Hereinafter, the terms "first" and "second" are used only for the purpose of description, and cannot be understood to indicate or imply relative importance or to implicitly indicate the number of the technical features indicated. Thus, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "plurality" is two or more, unless otherwise specified.

[0051] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0052] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0053] It should be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0054] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized illustrations. In the interest of clarity, not all of the layer and regions are labeled in each figure. There can be variations to the shapes of the layers and regions from the shapes of the illustrated regions, such as a result of, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes illustrated herein, but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are to be merely used to facilitate describing the exemplary embodiments.

[0055] After all the hardware production of the display panel is completed, two electrical processes are performed: one is photoelectric curve calibration, referred to as gamma correction (Gamma tuning), and the other is pixel uniformity compensation (PUC). Among them, gamma correction, also known as gamma nonlinearity or gamma encoding, is a nonlinear operation or inverse operation for the luminance or tristimulus value of light in a film or image system. In display devices, gamma correction is a process of setting different driving voltages for different gray scales through feedback adjustment. If it is a multi-luminance level (DBV, Display Brightness value) screen, the screen with adjustable DBV, such as a mobile phone screen or a tablet screen, will have multiple DBV gamma correction processes and multiple gamma correction curves. The basic principle of gamma correction is that in order to make the display panel reach the specified brightness and chroma, the existing process uses an optical probe to perform Gamma calibration at the center of the panel (industry default), that is, to find the corresponding voltage of the RGB sub-pixel several gray scale binding points at the target brightness and chroma under the specified DBV, and to obtain the voltage corresponding to the gray scale outside the binding points through linear interpolation. Due to the limitation of process time, several points will be selected in 0~255 gray scales according to the requirements of the algorithm to find the feedback of the target brightness and chroma and the corresponding voltage. These points are called binding points, and the target brightness and chroma and the voltage outside the binding points are defined by interpolation.

[0056] After gamma correction is performed, the non-uniformity of each production link in the production process will cause differences in device performance, which can be attributed to two aspects: backplane characteristics and electroluminescence (EL) device differences. The backplane characteristics mainly refer to the differences in threshold voltage (Vth) ) and coefficient K caused by temperature, film thickness, etc., which ultimately manifest as non-uniformity of the entire screen brightness. PUC is a method for compensating for display brightness non-uniformity between pixels, and its principle is to obtain the brightness of each sub-pixel through an external sensor and calculate the gray scale that needs to be increased or decreased for each sub-pixel to reach the target brightness.

[0057] The voltage corresponding to 0 gray scale is the black state voltage, i.e., the minimum voltage when the display panel does not emit light, so the difference between the voltage interpolated between 0 gray scale and the lowest binding point gray scale and the actual required voltage is large, as shown in Figure 1 , which will cause the brightness of other gray scales between 0 gray scale and the lowest binding point gray scale to be inaccurate. Moreover, during gamma correction, the lower the gray scale, the wider the range of target brightness and chroma corresponding to the gray scale, and the combined effect of the two will cause inaccurate gamma fitting at low gray scales.

[0058] The PUC takes the brightness of the gamma target region as the target brightness, and when the brightness of a pixel is lower than the target brightness, the input gray scale is raised; when the brightness of a pixel is higher than the target brightness, the input gray scale is lowered. When the picture is in a low gray scale, if there is a region whose brightness is higher than the target region brightness, the gray scale of the region after compensation will be lowered, and it may enter the inaccurate interval of gamma fitting, resulting in inaccurate brightness after compensation. When the target region is the brightest region of the panel, the gray scale of the remaining regions after compensation is increased, and the gray scale is in the accurate interval of gamma fitting, and the brightness after compensation is accurate. Therefore, if the gamma calibration region is in a region with low screen brightness, that is, the center brightness of the screen is the lowest, the PUC effect will be poor. However, the non-uniformity of screen brightness is affected by the position of the display panel on the large panel on the one hand, and by the uncertainty of the process on the other hand, which is difficult to control.

[0059] To solve the above technical problems, with reference to Figures 2 to 10 In a first aspect, a display panel 10 is provided, comprising: a plurality of sub-pixels and a pixel driving circuit, the plurality of sub-pixels comprising a target sub-pixel, the target sub-pixel forming a gamma calibration region 101, the pixel driving circuit comprising a first sub-pixel driving circuit 12 disposed within the gamma calibration region 101 and a plurality of second sub-pixel driving circuits 13 disposed outside the gamma calibration region 101;

[0060] The first sub-pixel driving circuit 12 comprises a first driving transistor 121, the first driving transistor 121 comprising a first channel region 1211; the second sub-pixel driving circuit 13 comprises a second driving transistor 131, the second driving transistor 131 comprising a second channel region 1310, and the width-length ratio of the corresponding second channel region 1310 of each second driving transistor 131 is the same;

[0061] The width-length ratio of the first channel region 1211 is greater than the width-length ratio of the second channel region 1310; wherein the width-length ratio is the ratio of the width and length of the corresponding channel region, the length of the channel region is the path length of the current flowing in the channel region, and the width of the channel region is the channel dimension perpendicular to the direction of current flow.

[0062] Specifically, the display panel 10 comprises a pixel driving circuit disposed on a substrate 11, and the pixel driving circuit is provided with a pixel definition layer on the side away from the substrate 11, the pixel definition layer has a plurality of opening regions arranged at intervals, and each opening region is provided with a sub-pixel, each sub-pixel in each opening region can be any one of a red sub-pixel (R), a green sub-pixel (G) or a blue sub-pixel (B), a pixel generally comprises a plurality of sub-pixels, such as RGB constituting a pixel, and each pixel on the display panel 10 is arranged in an array.

[0063] The plurality of sub-pixels of the display panel 10 includes target sub-pixels, and the target sub-pixels on the display panel 10 form a gamma calibration region 101, where the gamma calibration region 101 is a gamma calibration optical probe detection region, and a region on the display panel 10 other than the gamma calibration region 101 is a peripheral region. The drive circuit layer is configured to form a plurality of array-distributed sub-pixel drive circuits, and the plurality of sub-pixel drive circuits includes a first sub-pixel drive circuit 12 and a second sub-pixel drive circuit 13. The first sub-pixel drive circuit 12 is arranged in one-to-one correspondence with the target sub-pixels in the gamma calibration region 101, so as to realize independent driving control of each target sub-pixel. The second sub-pixel drive circuit 13 is arranged in one-to-one correspondence with each sub-pixel in the peripheral region, so as to realize independent driving control of each sub-pixel in the peripheral region.

[0064] It should be noted that, as shown in Figure 3 and Figure 4 , in the sub-pixel drive circuit, generally only one driving transistor is provided. The driving transistor includes an active layer 1210, the active layer 1210 includes a channel region (a first channel region or a second channel region) and a source region 1212 and a drain region 1213 located on both sides of the channel region, the source region 1212, the channel region, and the drain region 1213 are arranged side by side to form the active layer 1210, a gate insulating layer 1230 is arranged on the active layer 1210 in a stacked manner, a gate 1220 is formed on a side of the gate insulating layer 1230 away from the active layer 1210, a source electrode 1221 (S pole) is overlapped on the source region 1212, a drain electrode 1222 (D pole) is overlapped on the drain region 1213, and the gate 1220 is located between the source electrode 1221 and the drain electrode 1222. The gate voltage (or the gate 1220 voltage) of the driving transistor is controlled to control the source-drain (SD) current of the driving transistor, so as to control the corresponding sub-pixel to be bright. According to the current I formula:

[0065] I=

[0066] wherein, K is a coefficient, including parameters such as the mobility of the driving transistor; is the length of the channel region of the driving transistor, and the length of the channel region is the path length of the current flowing in the channel region; is the width of the channel region of the driving transistor, and the width of the channel region is the channel size perpendicular to the current flow direction; is the voltage of the gate 1220 to the source electrode 1221, is the threshold voltage of the driving transistor.

[0067] As can be seen from the above current formula, in , , KThe width-length ratio of the first channel region 1211 of the first driving transistor 121 corresponding to the first sub-pixel driving circuit 12 is greater than the width-length ratio of the second channel region 1310 of the second driving transistor 131 corresponding to the second sub-pixel driving circuit 13. The current is directly affected by the size, and in turn the brightness of the corresponding sub-pixel. The greater the current, the brighter the brightness of the sub-pixel.

[0068] In the embodiment of the present application, the width-length ratio of the first channel region 1211 of the first driving transistor 121 corresponding to the first sub-pixel driving circuit 12 is greater than the width-length ratio of the second channel region 1310 of the second driving transistor 131 corresponding to the second sub-pixel driving circuit 13. Under the same driving voltage, the brightness of the target sub-pixel in the gamma calibration area 101 is greater than the brightness of each sub-pixel in the peripheral area, and in turn the brightness of the target sub-pixel on the display panel 10 is the brightest sub-pixel on the display panel 10. The target sub-pixel forming area is taken as the gamma calibration area 101, that is, the area detected by the optical probe for gamma calibration covers at least the target sub-pixel forming area, reduces the probability that the brightness of the gamma calibration area 101 is less than the brightness of the peripheral area of the display panel 10, improves the PUC effect, and in turn improves the brightness uniformity of the display panel 10.

[0069] In this example, by differentiating the pixel driving circuit structure on the substrate 11, the brightness of the target sub-pixel in the gamma calibration area 101 is always the brightest sub-pixel in the display panel 10, so that the gamma calibration area 101 is the area with the highest brightness in the display panel 10 before PUC. Under this gamma calibration premise, the effect of PUC can be much better than the existing display panel 10 structure design, and after PUC, the brightness non-uniformity caused by the differentiated backplane structure itself can be eliminated, and the brightness uniformity of the display panel 10 can be improved.

[0070] In some embodiments, the width-length ratio of the first channel region 1211 is increased by 10% to 20% relative to the width-length ratio of the second channel region 1310.

[0071] For example, if the width-to-length ratio of the first channel region 1211 is d1, the width-to-length ratio d2 of the second channel region 1310 is: d1 = d2 (1 + a), where a is 10% to 20%. Under the same driving voltage, before PUC, the width-to-length ratio of the first channel region 1211 increases by 10% to 20% relative to the width-to-length ratio of the second channel region 1310, such as by 10%, 12%, 15%, 18%, or 20%. The brightness of the target subpixel driven by the first subpixel driving circuit 12 is greater than the brightness of the subpixel driven by the second subpixel driving circuit 13. Even if the display panel 10 has brightness non-uniformity due to process uniformity, the gamma calibration area 101 will still be the brightest area of ​​the display panel 10. This can reduce the brightness uniformity between different display panels 10 after PUC, stabilize the brightness uniformity of display panels 10 from different panels or batches, and improve the quality of the display panel 10. Among them, as analyzed above, in the backplane characteristics, the threshold voltage caused by temperature, film thickness, etc. ( ) and the coefficient K The difference may also cause uneven brightness of the display panel 10. The width-to-length ratio of the first channel region 1211 increases by less than 10% relative to the width-to-length ratio of the second channel region 1310. Due to the difference in backplane characteristics, the brightness of the target sub-pixel may not be the brightest in the display panel 10; the width-to-length ratio of the first channel region 1211 increases by more than 20% relative to the width-to-length ratio of the second channel region 1310, which exceeds the compensation capability of the PUC, and ultimately leads to poor uniformity of the display panel 10.

[0072] In some embodiments, a base substrate 11 is provided on a side of the pixel driving circuit away from the sub-pixel, and the projection shapes of the first channel region 1211 and the second channel region 1310 on the base substrate 11 are the same or different.

[0073] For example, Figures 4 to 9 As shown, the first channel region 1211 and the second channel region 1310 can have the same shape. By increasing the width of the first channel region 1211 and / or decreasing its length relative to the second channel region 1310, the width-to-length ratio of the first channel region 1211 can be greater than the width-to-length ratio of the second channel region 1310. For example, if the projections of the first channel region 1211 and the second channel region 1310 on the substrate 11 are both square, the shortest distance between the opposing edges of the source 1221 and the drain 1222 is the length of the channel region, and the channel dimension perpendicular to the current flow direction of the source 1221 and the drain 1222 is the width of the channel region. For another example, the projections of the first channel region 1211 and the second channel region 1310 on the substrate 11 are in the shape of a Chinese character "几", which will be described in detail later and will not be further explained here.

[0074] For example, Figure 10As shown, the shapes of the first channel region 1211 and the second channel region 1310 can be different. By changing the shape of the first channel region 1211, the width-to-length ratio of the first channel region 1211 can be greater than the width-to-length ratio of the second channel region 1310. For example, the projection of the second channel region 1310 on the base substrate 11 is a square, and the square structure has a first horizontal end surface and a second horizontal end surface oppositely disposed along the stacking direction of the gate 1220. The projection of the first channel region 1211 on the base substrate 11 has a different shape from that of the second channel region 1310. At least one of the first and second horizontal end surfaces in the second channel region 1310 is modified into an arcuate end surface or a V-shaped surface to make the width of the first channel region 1211 greater than that of the second channel region 1310. The principles for other shape changes are similar and are not further detailed in this application.

[0075] In some embodiments, as Figures 4 to 10 As shown, the first channel region 1211 and the second channel region 1310 both include a first connecting segment, a second connecting segment and a third connecting segment, and two ends of the second connecting segment are bent and connected to the first connecting segment and the third connecting segment respectively.

[0076] Specifically, the first, second, and third connecting segments, which are connected by bending in sequence, form a "J"-shaped channel region. By changing the width and / or length, as well as the shape, of at least one of the first, second, and third connecting segments, the width-to-length ratio of the first channel region 1211 can be greater than the width-to-length ratio of the second channel region 1310. The angle at which the first and second connecting segments are bent can be the same as or different from the angle at which the second and third connecting segments are bent. The bending angle can be set according to actual needs, for example, from 35° to 145°, and can be set by those skilled in the art based on actual needs. The first and third connecting segments are located on the same side of the second connecting segment, and the first and third connecting segments are arranged perpendicularly or obliquely relative to the second connecting segment. The first and third connecting segments can be inclined relative to the second connecting segment toward a side away from the second connecting segment.

[0077] Among them, such as Figure 5 As shown, the length of the channel region is the length of the current flow path in the first connection section , the length of the current flow path in the second connecting section and the length of the current flow path in the third connecting segment The sum of + The width of the first connecting segment, the width of the second connecting segment and the width of the third connecting segment are equal and are greater than the length of the channel region. equal, or the width of the first connecting segment, the width of the second connecting segment, and the width of the third connecting segment are different, the length of the channel region The maximum value or the average value of the width of the first connecting segment, the width of the second connecting segment, and the width of the third connecting segment can be taken.

[0078] In some embodiments, as shown in FIG. 1, the first connecting segment, the second connecting segment, and the third connecting segment are all square in the projection shape of the substrate 11. Figures 4 to 9

[0079] Specifically, the shapes of the first channel region 1211 and the second channel region 1310 are the same, the width of at least one of the first connecting segment, the second connecting segment, and the third connecting segment in the first channel region 1211 is increased relative to the width of the corresponding connecting segment in the second channel region 1310, or / and, the length of at least one of the first connecting segment, the second connecting segment, and the third connecting segment in the first channel region 1211 is reduced relative to the length of the corresponding connecting segment in the second channel region 1310, or / and, the shape of at least one of the first connecting segment, the second connecting segment, and the third connecting segment in the first channel region 1211 is changed relative to the shape of the corresponding connecting segment in the second channel region 1310, all of which can achieve that the aspect ratio of the first channel region 1211 is greater than the aspect ratio of the second channel region 1310.

[0080] In some embodiments, as shown in FIG. 1, the first connecting segment and the third connecting segment are located on the same side of the second connecting segment, the first connecting segment is perpendicular to the second connecting segment, the third connecting segment is perpendicular to the second connecting segment, and the path lengths of the first connecting segment and the third connecting segment along the current flow direction are equal. Figures 4 to 9

[0081] Specifically, the first connecting segment and the third connecting segment are located on the same side of the second connecting segment and have equal lengths, which can simultaneously reduce the lengths of the first connecting segment and the third connecting segment of the first channel region 1211 (the length reduction ratios of the first connecting segment and the third connecting segment can be the same or different), or / and reduce the length of the second connecting segment of the first channel region 1211, so that the aspect ratio of the first channel region is greater than the aspect ratio of the second channel region 1310. Alternatively, the widths of the first connecting segment and the third connecting segment of the first channel region 1211 and the third connecting segment can be simultaneously increased (the width increase ratios of the three connecting segments can be the same or different), so that the aspect ratio of the first channel region is greater than the aspect ratio of the second channel region 1310.

[0082] Further, in some embodiments, the path length of the second connecting segment of the first channel region 1211 along the current flow direction is less than the path length of the second connecting segment of the second channel region 1310 along the current flow direction. ​​

[0083] or / and,

[0084] the path length of the first connecting segment of the first channel region 1211 along the current flow direction is less than the path length of the first connecting segment of the second channel region 1310 along the current flow direction;

[0085] or / and,

[0086] the channel dimension of the second connecting segment of the first channel region 1211 along the direction perpendicular to the current flow direction is greater than the channel dimension of the second connecting segment of the second channel region 1310 along the direction perpendicular to the current flow direction.

[0087] Embodiments of the present application take the first sub-pixel drive circuit 12 and the second sub-pixel drive circuit 13 as examples, both of which are 7T1C drive circuits, wherein the transistor T3 is a drive transistor, and the specific embodiments are as follows.

[0088] As shown in Figure 5 and Figure 7 the path length (L21) of the second connecting segment of the first channel region 1211 of the transistor T3 of the first sub-pixel drive circuit 12 along the current flow direction is less than the path length (L22) of the second connecting segment of the second channel region 1310 of the transistor T3 of the second sub-pixel drive circuit 13 along the current flow direction, i.e. L21 < L22, and the other parameters (such as the length and width of the first connecting segment, and the width of the second connecting segment, the length and width of the third connecting segment, etc.) of the first channel region 1211 of the transistor T3 of the first sub-pixel drive circuit 12 are the same as the parameters of the transistor T3 of the second sub-pixel drive circuit 13, and under the same driving voltage, the luminance of the target sub-pixel in the gamma calibration region 101 can be greater than the luminance of the sub-pixel in the surrounding region.

[0089] As shown in Figure 5 and Figure 8As shown, the path length (L11) of the first connecting section of the first channel region 1211 of the transistor T3 of the first sub-pixel driving circuit 12 along the current flow direction is less than the path length (L12) of the first connecting section of the second channel region 1310 of the transistor T3 of the second sub-pixel driving circuit 13 along the current flow direction, i.e. L11 < L12, and the path length of the third connecting section of the first channel region 1211 of the transistor T3 of the first sub-pixel driving circuit 12 along the current flow direction is less than the path length of the third connecting section of the second channel region 1310 of the transistor T3 of the second sub-pixel driving circuit 13 along the current flow direction, and the other parameters (such as the width of the first connecting section, and the length and width of the second connecting section, the width of the third connecting section, etc.) of the first channel region 1211 of the transistor T3 of the first sub-pixel driving circuit 12 are the same as those of the transistor T3 of the second sub-pixel driving circuit 13, so that the luminance of the target sub-pixel in the gamma calibration region 101 is greater than the luminance of the sub-pixel in the surrounding region under the same driving voltage.

[0090] As shown in FIG. 1, the first sub-pixel driving circuit 12 and the second sub-pixel driving circuit 13 are arranged in the gamma calibration region 101 of the display panel 100. Figure 5 and Figure 9 As shown, the channel dimension (W2) of the second connecting section of the first channel region 1211 of the transistor T3 of the first sub-pixel driving circuit 12 along the direction perpendicular to the current flow direction is greater than the channel dimension (W1) of the second connecting section of the second channel region 1310 of the transistor T3 of the second sub-pixel driving circuit 13 along the direction perpendicular to the current flow direction, i.e. W2 > W1. Similarly, the other parameters (such as the length and width of the first connecting section, and the length of the second connecting section, the length and width of the third connecting section, etc.) of the first channel region 1211 of the transistor T3 of the first sub-pixel driving circuit 12 are the same as those of the transistor T3 of the second sub-pixel driving circuit 13, so that the luminance of the target sub-pixel in the gamma calibration region 101 is greater than the luminance of the sub-pixel in the surrounding region under the same driving voltage.

[0091] It can be understood that the channel dimension of the first connecting section of the first channel region 1211 along the direction perpendicular to the current flow direction is greater than the channel dimension of the first connecting section of the second channel region 1310 along the direction perpendicular to the current flow direction, or / and the channel dimension of the third connecting section of the first channel region 1211 along the direction perpendicular to the current flow direction is greater than the channel dimension of the third connecting section of the second channel region 1310 along the direction perpendicular to the current flow direction, and the same can also be achieved that the aspect ratio of the first channel region 1211 is greater than the aspect ratio of the second channel region 1310.

[0092] In some embodiments, as shown in FIG. 1, the first sub-pixel driving circuit 12 and the second sub-pixel driving circuit 13 are arranged in the gamma calibration region 101 of the display panel 100. Figure 5 and Figure 10As shown, the second connecting section of the first channel region 1211 and the second connecting section of the second channel region 1310 have different projected shapes on the substrate 11, and the channel size of the second connecting section of the first channel region 1211 along the direction perpendicular to the current flow is larger than the channel size of the second connecting section of the second channel region 1310 along the direction perpendicular to the current flow.

[0093] Specifically, by changing the shape of any one of the first connecting segment, the second connecting segment, and the third connecting segment of the first channel region 1211 , the width-to-length ratio of the first channel region 1211 can be made greater than that of the second channel region 1310 .

[0094] Furthermore, in some embodiments, the second connecting section of the first channel region 1211 includes a first end face and a second end face arranged opposite to each other, at least one of the first end face and the second end face is an arc-shaped surface or a V-shaped surface, and the projection shape of the second connecting section of the second channel region 1310 on the base substrate 11 is a square; the distance between the first end face and the second end face is greater than the channel size of the second connecting section of the second channel region 1310 along the direction perpendicular to the current flow.

[0095] For example, Figure 5 and Figure 10 As shown, the second connecting segment of the first channel region 1211 is different in shape from the second connecting segment of the second channel region 1310. The projection of the second connecting segment of the second channel region 1310 on the substrate 11 is a square, that is, the second connecting segment has a first horizontal end face and a second horizontal end face that are relatively set along the stacking direction of the gate 1220. The first channel region 1211 replaces one of the first horizontal end face and the second horizontal end face with an arc-shaped end face, thereby increasing the distance between the two end faces, so that the width-to-length ratio of the second connecting segment of the first channel region 1211 is greater than the width-to-length ratio of the second connecting segment of the second channel region 1310.

[0096] It should be noted that if Figure 5 As shown, the channel region further includes a fourth connecting segment connected to the first connecting segment in a zigzag manner, and a fifth connecting segment connected to the third connecting segment in a zigzag manner. One of the fourth connecting segment and the fifth connecting segment is connected to the source 1221, and the other connecting segment is connected to the drain 1222. Accordingly, the length of the channel region is is the length of the current flow path in the first connection section , the length of the current flow path in the second connecting section , the length of the current flow path in the third connection segment , the length of the current flow path in the fourth connecting segment , and the length of the current flow path in the fifth connecting segment The sum of + + + The width of the first connecting section, the width of the second connecting section, the width of the third connecting section, the width of the fourth connecting section, and the width of the fifth connecting section are equal, and the length of the channel region is equal to the width of the first connecting section, the width of the second connecting section, the width of the third connecting section, the width of the fourth connecting section, and the width of the fifth connecting section. Alternatively, the width of the first connecting section, the width of the second connecting section, and the width of the third connecting section, the width of the fourth connecting section, and the width of the fifth connecting section are different, and the length of the channel region can be the maximum value or the average value of the width of the first connecting section, the width of the second connecting section, the width of the third connecting section, the width of the fourth connecting section, and the width of the fifth connecting section.

[0097] It can be understood that the change in the length or / and width of the fourth connecting section or / and the fifth connecting section of the first channel region 1211 and the change in the shape can also achieve that the aspect ratio of the first channel region 1211 is greater than the aspect ratio of the second channel region 1310, for example, the length of the fourth connecting section of the first channel region 1211 is less than the length of the fourth connecting section of the second channel region 1310, and for another example, the width of the fourth connecting section of the first channel region 1211 is greater than the width of the fourth connecting section of the second channel region 1310.

[0098] In some embodiments, as shown in FIG. 1, the target sub-pixel is one or more, and each target sub-pixel is arranged one-to-one with the first sub-pixel driving circuit 12, and the target sub-pixel is located in the center region of the display panel 10. Figure 2 Specifically, in actual application, due to uncertainty and production convenience, the optical probe is generally placed in the center region of the display panel 10 for gamma calibration, and the detection region of the optical probe is generally a circular region covering the center position of the display panel 10. The target sub-pixel is arranged in the center region of the display panel 10 in the present application, so that the gamma calibration region 101 covers the center region of the display panel 10, and the brightness of the target sub-pixel in the gamma calibration region 101 is the brightest in the display panel 10 under the same driving voltage, that is, the brightest region of the display panel 10 is always located in the center region of the display panel 10. The center region of the display panel 10 is used as the gamma calibration region 101. Under this gamma calibration premise, after PUC, the brightness uniformity of the display panel 10 is improved.

[0099]

[0100] ​​It can be understood that the sub-pixel driving circuit can include a plurality of transistors, capacitors, and driving elements of the transistors, and the like. For example, the sub-pixel driving circuit can each include three transistors and one capacitor, forming 3T1C (i.e., one driving transistor, two switching transistors, and one capacitor). It can also include more than three transistors and at least one capacitor, such as 4T1C (i.e., one driving transistor, three switching transistors, and one capacitor), 5T1C (i.e., one driving transistor, four switching transistors, and one capacitor), or 7T1C (i.e., one driving transistor, six switching transistors, and one capacitor), and the like. Among them, the transistors can be thin film transistors (TFT), metal oxide semiconductors (MOS), or other switching devices with the same characteristics. The thin film transistor can be selected from any one of a low-temperature polysilicon (LTPS) TFT, an oxide TFT, or a low-temperature poly-oxide (LTPO) TFT.

[0101] As shown in FIG. 1, the first sub-pixel driving circuit 12 and the second sub-pixel driving circuit 13 are both 7T1C driving circuits, and the T3 transistor in the 7T1C driving circuit is a driving transistor, and the remaining six transistors are switching transistors. Figure 11 The width-length ratio of the channel region of the T3 transistor in the first sub-pixel driving circuit 12 is greater than the width-length ratio of the channel region of the T3 transistor in the second sub-pixel driving circuit 13, so that under the same driving voltage, the brightness of the target sub-pixel corresponding to the first sub-pixel driving circuit 12 is greater than the brightness of the sub-pixel corresponding to the second sub-pixel driving circuit 13, and the brightness in the gamma calibration region 101 formed by the target sub-pixel is the region with the highest brightness of the display panel 10.

[0102] As shown in FIG. 2 and FIG. 3, the working principle of the 7T1C driving circuit is as follows: Figure 12 Figure 13

[0103] Initialization stage: the control signal Reset is turned on (EM and Gate are turned off), the Reset signal is at a low level, the EM and Gate signals are at a high level, T1 and T3 are turned on, and the remaining transistors are turned off. The voltage Vint is a reset voltage to charge N1 point and OLED anode voltage for reset, the purpose is to close the OLED and initialize the voltage of N1 point;

[0104] ​​Data write compensation stage: control signal Gate is opened (Reset and EM are closed), Gate low voltage signal, Reset and EM high voltage signal, T2, T3, T4 and T7 are turned on, and the rest of the transistors are turned off, Data voltage is charged to N1 point, and the light emitting effect of OLED is adjusted through the compensation mechanism.

[0105] Light emitting stage: control signal EM is opened (Reset and Gate are closed), EM low voltage signal, Reset and Gate high voltage signal, T3, T5 and T6 are turned on, and the rest of the transistors are turned off, VDD flows to VSS, and OLED is turned on to emit light.

[0106] In a second aspect, a preparation method of a display panel 10 is provided, comprising:

[0107] Forming a pixel driving circuit on the substrate 11, the pixel driving circuit comprising a first sub-pixel driving circuit 12 and a plurality of second sub-pixel driving circuits 13, the first sub-pixel driving circuit 12 comprising a first driving transistor 121, the first driving transistor 121 comprising a first channel region 1211; the second sub-pixel driving circuit 13 comprising a second driving transistor 131, the second driving transistor 131 comprising a second channel region 1310, the width-length ratio of the corresponding second channel region 1310 of each second driving transistor 131 being the same; wherein the width-length ratio is the ratio of the width and length of the corresponding channel region, the length of the channel region is the path length of the current flowing in the channel region, and the width of the channel region is the channel size perpendicular to the current flowing direction;

[0108] Forming a plurality of sub-pixels on the side of the pixel driving circuit away from the substrate 11, wherein the sub-pixel corresponding to the first pixel driving circuit is a target sub-pixel, and the target sub-pixel forms a gamma calibration area 101.

[0109] Specifically, a pixel driving circuit is formed on a base substrate 11. The pixel driving circuit includes a plurality of sub-pixel driving circuits arranged in an array, including a target sub-pixel driving circuit. A pixel definition layer is formed on a side of the pixel driving circuit away from the base substrate 11. The pixel definition layer has a plurality of openings, within which sub-pixels are disposed. The sub-pixels correspond to the sub-pixel driving circuits one-to-one to achieve independent drive control of each sub-pixel. The plurality of sub-pixels includes a target sub-pixel, which forms a gamma calibration area 101. The sub-pixel driving circuit corresponding to the target sub-pixel is a first sub-pixel driving circuit 12, and the sub-pixel driving circuits corresponding to the remaining sub-pixels are a second sub-pixel driving circuit 13. Since the width-to-length ratio of the first channel region 1211 of the first driving transistor 121 of the first sub-pixel driving circuit 12 is greater than the width-to-length ratio of the second channel region 1310 of the second driving transistor 131 of the second sub-pixel driving circuit 13, the first sub-pixel driving circuit 12 and the second sub-pixel driving circuit 13 can, under the same driving voltage, make the brightness of the target sub-pixel within the gamma calibration area 101 greater than the brightness of the sub-pixel outside the gamma calibration area 101, so that the brightness within the gamma calibration area 101 formed by the target sub-pixel is the area with the highest brightness in the display panel 10. After gamma calibration and PUC, the brightness uniformity of the display panel 10 can be improved. Among them, gamma calibration and PUC are conventional technical means in this field and will not be elaborated in this application.

[0110] It should be noted that in the embodiment of the present application, although the brightness of the target sub-pixel driven by the first sub-pixel driving circuit 12 on the base substrate 11 is different from the brightness of the sub-pixel driven by the second sub-pixel driving circuit 13, it does not affect the final display effect of the display panel 10. This is because the UC itself is a pixel-level brightness compensation. When all sub-pixels on the final display panel 10 display the same brightness, their driving voltages will also be different. It can be understood that each sub-pixel has an independent gamma calibration curve.

[0111] It is understandable that the first sub-pixel driving circuit 12 and the second sub-pixel circuit can be formed by the same patterning process, without increasing the number of masks and process flow, wherein the patterning process includes conventional technical means such as coating photoresist, mask exposure, development, etching, and stripping photoresist.

[0112] In some embodiments, the width of the first channel region 1211 is increased and / or the length of the first channel region 1211 is decreased so that the width-to-length ratio of the first channel region 1211 is greater than the width-to-length ratio of the second channel region 1310 .

[0113] Specifically, such as Figures 7 to 9As shown, by changing the width or / and length of the first channel region 1211, the aspect ratio of the first channel region 1211 can be made greater than the aspect ratio of the second channel region 1310.

[0114] In some embodiments, the aspect ratio of the first channel region 1211 is made greater than the aspect ratio of the second channel region 1310 by changing the shape of the first channel region 1211.

[0115] Specifically, as shown, by changing the shape of the first channel region 1211, the aspect ratio of the first channel region 1211 can be made greater than the aspect ratio of the second channel region 1310. Figure 10

[0116] It can be understood that the preparation method of the display panel 10 provided in the embodiments of the present application is used to obtain the display panel 10 described in any embodiment of the present application, and the specific technical features and technical effects are consistent with the display panel 10, which will not be described in detail in the embodiments of the present application.

[0117] Test

[0118] Comparative Example 1

[0119] The center area of the existing display panel 10 is taken as the gamma calibration area 101, and the brightness results of the display panel 10 after PUC are shown in Table 1; the aspect ratios of the channel regions of the driving transistors of the pixel driving circuits corresponding to each sub-pixel in the existing display panel 10 are all equal, as shown in Figure 5 As shown, the aspect ratio of the channel region of the driving transistor in the gamma calibration area is equal to the aspect ratio of the second channel region of the second sub-pixel driving circuit.

[0120] Example 1

[0121] The target sub-pixel (the target sub-pixel is located in the center area of the display panel 10) of the display panel 10 provided in the present application is taken as the gamma calibration area 101, and the brightness results of the display panel 10 after PUC are shown in Table 1, wherein the aspect ratio of the first channel region 1211 of the first driving transistor corresponding to the target sub-pixel in the gamma calibration area 101 is greater than the aspect ratio of the second channel region 1310 of the second driving transistor corresponding to the sub-pixel outside the gamma calibration area 101.

[0122] Table 1 is the PUC result of the gamma calibration of different display panels

[0123]

[0124] Wherein, Y represents the brightness value, d Y ​The micro-change amount or difference value of the luminance represented by the display panel 10 luminance DBV is used to accurately describe the change of the luminance under different conditions. u and v are color coordinates in the CIE1976 UCS (Uniform Color Space), and duv represents the difference value between the color coordinates u and v and the target color coordinates, which is used to measure the degree of color deviation from the ideal state, reflecting the accuracy and consistency of the display color. A smaller duv value means that the color performance of the panel is more accurate and stable, and can better restore the true color of the image and video.

[0125] As can be seen from Table 1, in the comparative example 1, the luminance of the pixels in the gamma calibration region 101 is lower than that of the pixels in other regions of the screen, resulting in poor final PUC effect and affecting the luminance uniformity of the display panel 10. The display panel 10 provided in the embodiment 1 of the present application can improve the optical compensation uniformity of the display panel 10.

[0126] In a third aspect, a control method of a display panel 10 is provided. The control method is used to control the display panel 10 according to any of the embodiments of the present application, or the display panel 10 obtained by the preparation method of the display panel 10 according to any of the embodiments of the present application. The control method comprises:

[0127] The first sub-pixel driving circuit 12 and the second sub-pixel driving circuit 13 drive the corresponding sub-pixels to work under the same driving voltage, so that the luminance of the sub-pixels in the gamma calibration region 101 is greater than that of the sub-pixels outside the gamma calibration region 101.

[0128] In a fourth aspect, a display device 100 is provided. The display device 100 comprises the display panel 10 according to any of the embodiments of the present application, or the display panel 10 obtained by the preparation method of the display panel 10 according to any of the embodiments of the present application.

[0129] The display device 100 comprises the display panel 10 as described above, and of course can also comprise other components, for example, can comprise a circuit for providing an electrical signal to the display panel 10 to drive the display panel 10 to emit light. The circuit can be referred to as a control circuit, and can comprise a circuit board and / or an IC (Integrated Circuit) electrically connected to the display panel 10.

[0130] In some embodiments, the display device 100 can be a lighting device, in which case the display device 100 is used as a light source to realize the lighting function. For example, the display device 100 can be a backlight module in a liquid crystal display device 100, a lamp for internal or external lighting, or various signal lights, etc.

[0131] In other embodiments, the display device 100 may be a display substrate for displaying images (i.e., screens). The display device 100 may include a display or a product containing a display. The display may be a flat panel display (FPD), a microdisplay, or the like. Based on whether the user can see the back of the display, the display may be a transparent display or an opaque display. Based on whether the display can be bent or rolled, the display may be a flexible display or a conventional display (also referred to as a rigid display).

[0132] Examples of products that include displays include computer monitors, televisions, billboards, laser printers with display capabilities, telephones, cell phones, personal digital assistants (PDAs), laptop computers, digital cameras, camcorders, viewfinders, vehicles, large-area walls, theater screens, or stadium signs.

[0133] The technical features and beneficial effects of the above-mentioned display device 100 are the same as the technical features and beneficial effects of the display panel 1010 provided in the above-mentioned embodiment of the present disclosure, and are not repeated here.

[0134] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention herein is not limited to technical solutions formed by a specific combination of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the inventive concept. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A display panel, characterized in that: include: a plurality of sub-pixels and a pixel driving circuit, the plurality of sub-pixels including a target sub-pixel, the target sub-pixel forming a gamma calibration area, the pixel driving circuit including a first sub-pixel driving circuit disposed within the gamma calibration area and a plurality of second sub-pixel driving circuits disposed outside the gamma calibration area; The first sub-pixel driving circuit includes a first driving transistor, the first driving transistor includes a first channel region; the second sub-pixel driving circuit includes a second driving transistor, the second driving transistor includes a second channel region, and the second channel regions corresponding to the second driving transistors have the same width-to-length ratio; The width-to-length ratio of the first channel region is greater than the width-to-length ratio of the second channel region, so that the brightness of the target sub-pixel in the gamma calibration area is always the brightest in the display panel; wherein the width-to-length ratio is the ratio of the width and length of the corresponding channel region, the length of the channel region is the length of the path of current flowing in the channel region, and the width of the channel region is the channel dimension perpendicular to the direction of current flow.

2. The display panel according to claim 1, wherein: The width-to-length ratio of the first channel region is increased by 10% to 20% relative to the width-to-length ratio of the second channel region.

3. The display panel according to claim 1, wherein: A base substrate is provided on a side of the pixel driving circuit away from the sub-pixel, and the projection shapes of the first channel region and the second channel region on the base substrate are the same or different.

4. The display panel according to claim 3, wherein: The first channel region and the second channel region each include a first connecting segment, a second connecting segment, and a third connecting segment. Two ends of the second connecting segment are respectively connected to the first connecting segment and the third connecting segment in a bent manner.

5. The display panel according to claim 4, wherein: The projection shapes of the first connecting segment, the second connecting segment and the third connecting segment on the base substrate are all square.

6. The display panel according to claim 4, wherein: The first connecting segment and the third connecting segment are located on the same side of the second connecting segment, the first connecting segment is perpendicular to the second connecting segment, the third connecting segment is perpendicular to the second connecting segment, and the path lengths of the first connecting segment and the third connecting segment along the current flow direction are equal.

7. The display panel according to claim 4, wherein: The path length of the second connecting section of the first channel region along the current flow direction is shorter than the path length of the second connecting section of the second channel region along the current flow direction; or / and, The path length of the first connecting section of the first channel region along the current flow direction is shorter than the path length of the first connecting section of the second channel region along the current flow direction; or / and, A channel size of the second connecting segment of the first channel region along a direction perpendicular to the current flow is larger than a channel size of the second connecting segment of the second channel region along a direction perpendicular to the current flow.

8. The display panel according to claim 4, wherein: The second connecting section of the first channel region and the second connecting section of the second channel region have different projected shapes on the substrate, and the channel size of the second connecting section of the first channel region along the direction perpendicular to the current flow is larger than the channel size of the second connecting section of the second channel region along the direction perpendicular to the current flow.

9. The display panel according to claim 8, wherein: The second connecting section of the first channel region includes a first end face and a second end face arranged opposite to each other, at least one of the first end face and the second end face is an arc-shaped surface or a V-shaped surface, and the projection shape of the second connecting section of the second channel region on the substrate is a square; the distance between the first end face and the second end face is greater than the channel dimension of the second connecting section of the second channel region along a direction perpendicular to the current flow.

10. The display panel according to any one of claims 1 to 9, characterized in that: There are one or more target sub-pixels, each of which is provided in a one-to-one correspondence with the first sub-pixel driving circuit, and the target sub-pixels are located in a central area of ​​the display panel.

11. A method for preparing a display panel according to any one of claims 1 to 10, characterized in that: include: A pixel driving circuit is formed on a substrate, the pixel driving circuit comprising a first sub-pixel driving circuit and a plurality of second sub-pixel driving circuits, the first sub-pixel driving circuit comprising a first driving transistor, the first driving transistor comprising a first channel region; the second sub-pixel driving circuit comprising a second driving transistor, the second driving transistor comprising a second channel region, and the second channel regions corresponding to the second driving transistors having the same width-to-length ratio; wherein the width-to-length ratio is a ratio of a width to a length of a corresponding channel region, the length of the channel region being the length of a path for current flow in the channel region, and the width of the channel region being a channel dimension perpendicular to a current flow direction; A plurality of sub-pixels are formed on a side of the pixel driving circuit away from the base substrate, wherein the sub-pixels corresponding to the first sub-pixel driving circuit are target sub-pixels, and the target sub-pixels form a gamma calibration area.

12. The method for manufacturing a display panel according to claim 11, wherein: The width of the first channel region is increased or / and the length of the first channel region is decreased so that the width-to-length ratio of the first channel region is greater than the width-to-length ratio of the second channel region.

13. The method for manufacturing a display panel according to claim 11, wherein: The shape of the first channel region is changed so that the width-to-length ratio of the first channel region is greater than the width-to-length ratio of the second channel region.

14. A method for controlling a display panel, characterized in that: The control method is used to control the display panel according to any one of claims 1 to 10, or is used to control the display panel obtained by the method for manufacturing the display panel according to any one of claims 11 to 13, and the control method includes: The first sub-pixel driving circuit and the second sub-pixel driving circuit drive corresponding sub-pixels to operate at the same driving voltage, so that the brightness of the sub-pixels in the gamma calibration area is greater than the brightness of the sub-pixels outside the gamma calibration area.

15. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 10, or comprises a display panel obtained by the method for preparing a display panel according to any one of claims 11 to 13.

Images