Gate drive circuit and display panel

Abstract

The present application discloses a gate drive circuit and a display panel, wherein the gate drive circuit includes: the gate drive circuit includes a multi-stage cascaded gate drive unit, the gate drive unit includes: a first output unit for outputting a first pulse signal, wherein the first pulse signal is a low-voltage pulse with a normal high voltage; a second output unit for outputting a second pulse signal, wherein the second pulse signal is a pulse width modulation signal accompanied by a high-voltage pulse; a first control unit connected to the control end of the first output unit, for controlling the first output unit to output the first pulse signal; a second control unit connected to the control end of the second output unit, for controlling the second output unit to output the second pulse signal. Through the above circuit, the output of the scanning signal and the switching signal is realized.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a gate drive circuit and a display panel. Background Art

[0002] With the development of display technology, OLED (Organic Light Emitting Display) products have begun to enter the public's field of vision. Unlike LCD products, OLED uses current to drive organic light-emitting substances to emit light. According to the saturation current formula: It can be seen that the threshold voltage Vth of the transistor TFT will have a greater impact on the current.

[0003] A typical OLED pixel driver circuit includes a reset process controlled by the previous scan signal Pscan(n-1), a sampling process controlled by the current row's scan signal Pscan(n), and a light-emitting process controlled by the current row's switching signal EM(n). Unlike LCDs, the switching signal periodically switches the equivalent circuit of the light-emitting process on and off, achieving PWM dimming. Summary of the Invention

[0004] The main technical problem solved by the present application is to provide a gate drive circuit and a display panel to realize the output of two signals: a scanning signal and a switching signal.

[0005] To solve the above problems, the present application provides a gate drive circuit, wherein the gate drive circuit includes a multi-stage cascaded gate drive unit, and the gate drive unit includes: a first output unit for outputting a first pulse signal, wherein the first pulse signal is a low-voltage pulse with a normal high voltage; a second output unit for outputting a second pulse signal, wherein the second pulse signal is a pulse width modulation signal accompanied by a high-voltage pulse; a first control unit connected to the control end of the first output unit, for controlling the first output unit to output the first pulse signal; and a second control unit connected to the control end of the second output unit, for controlling the second output unit to output the second pulse signal.

[0006] Among them, the first output unit includes a first sub-output unit and a second sub-output unit; the first sub-output unit is connected to the high-potential signal line, and is used to output a high-potential pulse according to the control signal output by the first control unit; the second sub-output unit is connected to the low-potential signal line, and is used to output a low-potential pulse according to the control signal output by the first control unit.

[0007] Among them, the first control unit includes: a first sub-control unit, connected to the control end of the first sub-output unit, used to output a conduction signal to the first sub-output unit to control the first sub-output unit to output a high-voltage pulse; a low-voltage control unit, connected to the control ends of the first sub-control unit and the second sub-output unit, used to transmit a low-voltage control signal to the control ends of the first sub-control unit and the second sub-output unit, thereby controlling the second sub-output unit and controlling the first sub-output unit through the first sub-control unit; a high-voltage holding unit, connected to the control ends of the first sub-control unit and the second sub-output unit, used to keep the control ends of the first sub-control unit and the second sub-output unit at a high voltage, thereby controlling the output of the first sub-output unit and the second sub-output unit.

[0008] In which, the first control unit also includes: a first cascade unit, connected to the first output unit of the previous level, for receiving the first pulse signal transmitted by the first output unit of the previous level; a first storage unit, connected to the first cascade unit, for storing the potential signal of the first pulse signal of the previous level; wherein, the potential signal includes a high potential and a low potential; a delay control unit, connecting the first storage unit and the control end of the low potential control unit, for transmitting the potential signal stored in the first storage unit to the control end of the low potential control unit to control the on / off of the low potential control unit.

[0009] Wherein, the control ends of the first cascade unit and the delay control unit are connected to a group of control signal lines with opposite pulse phases.

[0010] Wherein, the first sub-control unit includes: a low-potential signal line; a first transistor, the input end of the first transistor is connected to the low-potential signal line, the output end of the first transistor is connected to the control end of the first sub-output unit, the control end of the first transistor is connected to the high-potential holding unit and the low-potential control unit, and is used to control the low-potential signal line to output a conduction signal to the first sub-output unit according to the control signals output by the high-potential holding unit and the low-potential control unit; wherein, the first transistor is an N-type transistor.

[0011] The high potential holding unit includes a high potential signal line and a first resistor, and the high potential signal line is connected to the control terminals of the first sub-control unit and the first sub-output unit through the first resistor.

[0012] In which, the second output unit includes a third sub-output unit, a fourth sub-output unit and a fifth sub-output unit; the third sub-output unit is connected to the low-potential signal line, and is used to output a low-potential pulse according to the first pulse width control signal; the fourth sub-output unit is connected to the high-potential signal line, and is used to output a high-potential pulse of the pulse width control signal according to the second pulse width control signal; the fifth sub-output unit is connected to the high-potential signal line, and is used to output a high potential according to the control signal output by the second control unit; the first pulse width modulation unit is connected to the control end of the third sub-output unit, and is used to output the first pulse width control signal to the control end of the third sub-output unit; the second pulse width modulation unit is connected to the control end of the fourth sub-output unit, and is used to output the second pulse width control signal to the control end of the fourth sub-output unit; wherein, the first pulse width control signal and the second pulse width control signal are a set of level signals with opposite pulse phases.

[0013] Wherein, the second control unit includes: a first potential control unit, whose input end is connected to the high potential signal line, and whose output end is connected to the control ends of the first pulse width modulation unit, the second pulse width modulation unit and the fifth sub-output unit, and is used to transmit a high potential control signal to the control ends of the first pulse width modulation unit, the second pulse width modulation unit and the fifth sub-output unit; a second potential control unit, whose input end is connected to the low potential signal line, and whose output end is connected to the control ends of the first pulse width modulation unit, the second pulse width modulation unit and the fifth sub-output unit, and is used to transmit a low potential control signal to the control ends of the first pulse width modulation unit, the second pulse width modulation unit and the fifth sub-output unit.

[0014] In which, the second control unit also includes: a high potential control unit, connected to the control ends of the first potential control unit and the second potential control unit, for controlling the on / off of the first potential control unit and the second potential control unit; a low potential holding unit, connected to the control ends of the first potential control unit and the second potential control unit and the output end of the high potential control unit, for controlling the control ends of the first potential control unit and the second potential control unit to be at a low potential when the high potential control unit does not output; In which, the first potential control unit and the second potential control unit include a group of transistors with opposite driving characteristics.

[0015] In which, the second control unit also includes: a second cascade unit, connected to the second output unit of the previous level, for receiving the second pulse signal output by the second output unit of the previous level; a first storage control unit, connected to the second cascade unit, for transmitting a control signal according to the second cascade unit; a third storage unit, connected to the first storage control unit, for storing the control signal transmitted by the first storage control unit; a second storage control unit, connected to the third storage unit, for controlling the third storage unit to transmit the control signal to the control end of the high potential control unit; a fourth storage unit, connected to the second storage control unit, for storing the control signal transmitted by the second storage control unit; wherein, the control ends of the first storage control unit and the second storage control unit are respectively connected to two control signal lines with opposite pulse phases.

[0016] The second control unit further includes a reset signal line connected to the third storage unit, configured to transmit a reset signal to the third storage unit and further transmit the reset signal to the fourth storage unit.

[0017] The low potential holding unit includes a low potential signal line and a second resistor, and the low potential signal line is connected to the control terminals of the first potential control unit and the second potential control unit through the second resistor.

[0018] The second control unit further includes: a reset unit including a low potential signal line and a third resistor, connected to the input end of the first storage control unit, and used for transmitting a low potential reset signal to the third storage unit and the fourth storage unit.

[0019] To solve the above problem, the present application provides a display panel in a second aspect, wherein the display panel includes the gate driving circuit described in any embodiment of the first aspect.

[0020] The beneficial effect of the present application is that by designing the gate drive circuit, while minimizing the use of input signals, a gate drive circuit can output scanning signals and switching signals to each row of pixel units in sequence to control the light-emitting devices in the surface to emit light, saving circuit expenses and reducing the border width. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 A schematic structural diagram of an embodiment of a gate drive circuit provided in this application;

[0023] Figure 2 A timing diagram of the first pulse signal and the second pulse signal provided in this application;

[0024] Figure 3 This is a schematic structural diagram of a first specific embodiment of a gate driving unit provided in this application;

[0025] Figure 4 A schematic structural diagram of a second specific embodiment of a gate driving unit provided in this application;

[0026] Figure 5 A partial structural diagram of a third specific embodiment of a gate driving unit provided in this application;

[0027] Figure 6 A partial structural diagram of a fourth specific embodiment of a gate driving unit provided in this application;

[0028] Figure 7 A partial structural diagram of a fifth specific embodiment of a gate driving unit provided in this application;

[0029] Figure 8 A partial structural diagram of a sixth specific embodiment of the gate drive circuit provided in this application;

[0030] Figure 9 A partial structural diagram of a seventh specific embodiment of the gate drive circuit provided in this application;

[0031] Figure 10 A partial structural diagram of an eighth specific embodiment of a gate driving unit provided in this application;

[0032] Figure 11 A partial structural diagram of a ninth specific embodiment of a gate driving unit provided in this application;

[0033] Figure 12 A partial structural diagram of a tenth specific embodiment of a gate driving unit provided in this application;

[0034] Figure 13 A schematic diagram of the circuit structure of a specific embodiment of the gate drive unit provided in this application;

[0035] Figure 14 A driving timing diagram of a specific embodiment of the gate driving unit provided in this application;

[0036] Figure 15 A circuit diagram of the first driving stage of a specific embodiment of the gate driving unit provided in this application;

[0037] Figure 16 A circuit diagram of the second driving stage of a specific embodiment of the gate driving unit provided in this application;

[0038] Figure 17 A circuit diagram of the third driving stage of a specific embodiment of the gate driving unit provided in this application;

[0039] Figure 18 A circuit diagram of the fourth driving stage of a specific embodiment of the gate driving unit provided in this application;

[0040] Figure 19 A schematic structural diagram of an embodiment of a display panel provided in this application;

[0041] Figure 20 This is a structural diagram of an embodiment of a pixel driving circuit provided in this application.

[0042] First output unit 10; second output unit 20; first control unit 11; second control unit 21; first pulse signal Pscan(n); previous stage first pulse signal Pscan(n-1); previous two stage first pulse signal Pscan(n-2); second pulse signal EM(n); high potential signal line VGH; low potential signal line VGL; first sub-control unit 111; high potential holding unit 113; low potential control unit 112; delay control unit 115; first cascade unit 114; first sub-output unit 101; second sub-output unit 102; third sub-output unit 201; fourth sub-output unit 202; fifth sub-output unit 203; first storage control unit 215; second storage control unit 216; low potential holding unit 214; high potential control unit 213; first potential control unit 211; second potential control unit 212; first pulse width modulation unit 220; second pulse width modulation unit 230; cascade control unit 243; first sub-cascade unit 241; second sub-cascade unit 242;

[0043] A first control signal line XCK; a second control signal line CK; a first pulse width control signal PWM-CK; a second pulse width control signal PWM-XCK;

[0044] a first transistor T1; a second transistor T2; a third transistor T3; a fourth transistor T4; a low potential signal line VGL1; a fifth transistor T5; a high potential signal line VGH1; a sixth transistor T6; a seventh transistor T7; an eighth transistor T8; a ninth transistor T9; a tenth transistor T10; an eleventh transistor T11; a twelfth transistor T12; a thirteenth transistor T13; a fourteenth transistor T14; a fifteenth transistor T15; a sixteenth transistor T16; a seventeenth transistor T17; an eighteenth transistor T18; a nineteenth transistor T19; and a twentieth transistor T20.

[0045] Display panel 100 ; display area 1001 ; non-display area 1002 . DETAILED DESCRIPTION

[0046] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0047] The terms used in the examples of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in the examples of this application and the appended claims are also intended to include plural forms. Unless otherwise clearly indicated above, "a plurality" generally includes at least two, but does not exclude the inclusion of at least one.

[0048] It should be understood that the term "and / or" as used herein is merely a description of the association relationship between associated objects, indicating that three possible relationships exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship. The terms "first," "second," etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0049] It should be understood that the terms "comprises," "comprising," or any other variations thereof as used herein are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0050] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), such directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0051] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0052] The present application provides a gate drive circuit, which includes: a plurality of cascaded gate drive units, for details, please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the gate drive circuit provided by this application. Figure 1 As shown, each gate driving unit GOA at least includes: a first output unit 10 , a second output unit 20 , a first control unit 11 , and a second control unit 21 .

[0053] The first output unit 10 is used to output a first pulse signal Pscan(n), which is a low-voltage pulse with a normal high voltage. The first pulse signal Pscan(n) is a low-voltage scanning signal used to control the writing of data signals in the display panel.

[0054] The second output unit 20 is used to output a second pulse signal EM(n), which is a pulse width modulation signal accompanied by a high potential pulse. Specifically, the second pulse signal EM(n) is a switching signal that modulates the light emission frequency of the light emitting unit.

[0055] Specifically, the first output unit 10 and the second output unit 20 are both connected to the high potential signal line VGH and the low potential signal line VGL, and the first output unit 10 and the second output unit 20 control the output of the first pulse signal Pscan(n) and the second pulse signal EM(n).

[0056] The first control unit 11 is connected to the control end of the first output unit 10 and is used to control the first output unit 10 to output the first pulse signal Pscan(n).

[0057] The second control unit 21 is connected to the control terminal of the second output unit 20 and is used to control the second output unit 20 to output the second pulse signal EM(n).

[0058] Please refer to Figure 2 , Figure 2 This is a timing diagram of the first pulse signal and the second pulse signal provided in this application. Figure 2As shown, both the first pulse signal Pscan(n) and the second pulse signal EM(n) include high-potential pulses (high voltage) and low-potential pulses (low voltage). The duty ratios of the high and low voltages in the first pulse signal Pscan(n) and the second pulse signal EM(n) are different, and their timings are also different. In this preferred embodiment, the second pulse signal EM(n) lags behind the first pulse signal Pscan(n) by one timing sequence / phase. Preferably, the pulse frequency of the second pulse signal EM(n) is greater than the pulse frequency of the first pulse signal Pscan(n). Specifically, the pulse frequency of the second pulse signal EM(n) is greater than an integer multiple of the pulse frequency of the first pulse signal Pscan(n). As shown in this embodiment, within a timing sequence, the pulse frequency of the second pulse signal EM(n) is three times the pulse frequency of the first pulse signal Pscan(n). That is, the three second pulse signals EM(n) use the same timing sequence as the one first pulse signal Pscan(n), that is, the comparison is performed within the same phase width.

[0059] Specifically, see Figure 3 , Figure 3 This is a schematic structural diagram of the first specific embodiment of the gate drive unit provided in this application. Figure 3 As shown, the first output unit 10 includes a first sub-output unit 101 and a second sub-output unit 102. The first sub-output unit 101 is connected to the high-potential signal line VGH and is configured to output a high-potential pulse (i.e., a high-potential level) of the first pulse signal Pscan(n) in accordance with the control signal output by the first control unit 11. The second sub-output unit 102 is connected to the low-potential signal line VGL and is configured to output a low-potential pulse (a low-potential level) of the first pulse signal Pscan(n) in accordance with the control signal output by the first control unit 11. The first pulse signal Pscan(n) is a pulse signal formed by alternating high and low potentials.

[0060] In one embodiment, the output terminal of the first control unit 11 is connected to the control terminals of both the first sub-output unit 101 and the second sub-output unit 102. The first sub-output unit 101 and the second sub-output unit 102 include two transistors with opposite driving characteristics. Specifically, when the first sub-output unit 101 is turned on, the second sub-output unit 102 is turned off, and when the second sub-output unit 102 is turned on, the first sub-output unit 101 is turned off. Thus, the first control unit 11 controls the first sub-output unit 101 and the second sub-output unit 102 to alternately turn on and off, thereby generating the output of the first pulse signal Pscan(n).

[0061] In a further embodiment, the second output unit 20 includes a third sub-output unit 201 , a fourth sub-output unit 202 , and a fifth sub-output unit 203 .

[0062] The third sub-output unit 201 is connected to the low-potential signal line VGL and is configured to output a low-potential pulse of a pulse-width-modulated signal. The fourth sub-output unit 202 is connected to the high-potential signal line VGH and is configured to output a high-potential pulse of a pulse-width-modulated signal. The fifth sub-output unit 203 is connected to the high-potential signal line VGH and is configured to output a high-potential pulse in accordance with a control signal output by the second control unit.

[0063] It should be noted that the second pulse signal EM(n) includes a normal high-voltage pulse and a high-voltage pulse and a low-voltage pulse during the pulse-width modulation signal. Specifically, the high-voltage pulse and the low-voltage pulse of the pulse-width modulation signal refer to the high-voltage pulse and the low-voltage pulse during the pulse-width modulation phase (light-emitting phase). The normal high-voltage pulse refers to the high-voltage pulse during the non-light-emitting phase.

[0064] In further embodiments, please refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of the second specific embodiment of the gate drive unit provided in this application. Figure 4 As shown, the third and fourth sub-output units 201 and 202 also include a pulse-width modulation unit 210, which is configured to output a pulse-width modulation control signal to cause the third and fourth sub-output units 201 and 202 to alternately conduct during the light-emitting phase, generating a pulse-width modulation signal. The pulse-width modulation signal comprises at least one set of alternating high and low pulses. In one embodiment, the pulse-width modulation unit 210 may include a first pulse-width modulation unit and a second pulse-width modulation unit, as described in subsequent embodiments. In this embodiment, the pulse-width modulation unit 210 may also consist of a single modulation unit, outputting alternating high / low pulse modulation signals to control the alternating conduction of the third and fourth sub-output units 201 and 202. In this case, the third and fourth sub-output units 201 and 202 each include two transistors (an N-type transistor and a P-type transistor) with opposite driving characteristics.

[0065] Furthermore, the pulse width modulation units 210 in the third and fourth sub-output units 201, 202 have opposite driving characteristics to those of the fifth sub-output unit 203. That is, when the third and fourth sub-output units 201, 202 are operating, the fifth sub-output unit 203 is inoperative, thereby outputting a pulse width modulation signal (light-emitting phase). When the third and fourth sub-output units 201, 202 are inoperative, the fifth sub-output unit 203 is inoperative, outputting a normally high-voltage pulse (non-light-emitting phase).

[0066] Furthermore, the first control unit 11 includes a first sub-control unit 111, a high potential holding unit 113, and a low potential control unit 112. Figure 5 , Figure 5This is a partial structural diagram of the third specific embodiment of the gate drive unit provided in this application. Figure 5 As shown, the first sub-control unit 111 is connected to the control end of the first sub-output unit 101 and is used to output a conduction signal to the control end of the first sub-output unit 101 to control the first sub-output unit 101 to output a high-potential pulse.

[0067] In this specific embodiment, the first sub-control unit 111 also includes a low-potential signal line VGL, and the conduction signal is a low-potential signal. The first sub-control unit 111 is used to control the transmission of the low-potential signal to the control end of the first sub-output unit 101 to control the conduction of the first sub-output unit 101.

[0068] The low-voltage control unit 112 is connected to the control ends of the first sub-control unit 111 and the second sub-output unit 102, and is used to transmit a low-voltage control signal to the control ends of the first sub-control unit 111 and the second sub-output unit 102, thereby controlling the output of the second sub-output unit 102 and controlling the output of the first sub-output unit 101 through the first sub-control unit 111.

[0069] The high potential holding unit 113 is connected to the control ends of the first sub-control unit 111 and the second sub-output unit 102, and is used to keep the control ends of the first sub-control unit 111 and the second sub-output unit 102 at a high potential, thereby controlling the output of the first sub-output unit 101 and the second sub-output unit 102.

[0070] The first sub-control unit 111 and the second sub-output unit 102 include a set of transistors with opposite driving characteristics. That is, when the first sub-control unit 111 is turned on, the second sub-output unit 102 is turned off; when the second sub-output unit 102 is turned on, the first sub-control unit 111 is turned off. When the first sub-control unit 111 is turned on, it can control the first sub-output unit 101 to also be turned on. The first sub-output unit 101 and the second sub-output unit 102 include transistors with the same driving characteristics, specifically, both are P-type transistors that are turned on at a low potential. It is understood that the first sub-output unit 101 and the second sub-output unit 102 can also be N-type transistors that are turned on at a high potential, in which case each conduction signal or control signal is also a high potential signal.

[0071] In this embodiment, the control terminals of the first sub-control unit 111 and the second sub-output unit 102 are maintained at a high potential by the high potential holding unit 113, thereby keeping the first sub-output unit 101 normally open and the second sub-output unit 102 normally closed. The low potential control unit 112 transmits a control signal (a low potential control signal) to the control terminals of the first sub-control unit 111 and the second sub-output unit 102, thereby turning off the first sub-output unit 101 and turning on the second sub-output unit 102, thereby outputting a low potential pulse of the first pulse signal Pscan(n).

[0072] Furthermore, the low-potential control unit 112 includes a low-potential signal line VGL and a switching transistor. The high-potential holding unit 113 includes a high-potential signal line VGH and a first resistor R1. The first resistor R1 is a large resistor, and the speed at which the low-potential control unit 112 transmits the low-potential signal to the control end of the first sub-control unit 111 and the second sub-output unit 102 is greater than the high-potential signal transmission speed of the high-potential holding unit 113, thereby enabling the low-potential control unit 112 to control the first sub-control unit 111 and the second sub-output unit 102 more effectively than the high-potential holding unit 113. In other embodiments, the high-potential holding unit 113 may also be composed of a high-potential signal line VGH and a switching transistor, which is not limited here.

[0073] The control terminal of the low potential control unit 112 is also connected to the cascade unit. Figure 6 , Figure 6 This is a partial structural diagram of the fourth specific embodiment of the gate drive unit provided in this application. Figure 6 As shown, the first control unit 11 further includes a first cascade unit 114, which is connected to the first output unit 10 of the previous stage and is configured to receive the first pulse signal Pscan(n-1) transmitted by the first output unit 10 of the previous stage. Specifically, the input end of the first cascade unit 114 is connected to the output end of the first output unit 10 of the previous stage.

[0074] The first storage unit C1 is connected to the first cascade unit 114 and is used to store the potential signal of the previous stage first pulse signal Pscan(n), wherein the potential signal includes a high potential pulse signal and a low potential pulse signal.

[0075] The delay control unit 115 is set at the control end of the first storage unit C1 and the low-potential control unit 112, and is used to control the connection between the first storage unit C1 and the control end of the low-potential control unit 112, and control the potential signal stored in the first storage unit C1 to be transmitted to the control end of the low-potential control unit 112 to control the on / off of the low-potential control unit 112.

[0076] Specifically, the first plate of the first storage unit C1 is connected to the output terminal of the first cascade unit 114 and the input terminal of the delay control unit 115 to store the first pulse signal Pscan(n-1) transmitted by the first cascade unit 114 in the previous timing sequence and transmit the stored first pulse signal Pscan(n-1) to the control terminal of the low-potential control unit 112 via the delay control unit 115 in the next timing sequence. In one specific embodiment, the second plate of the first storage unit C1 is connected to the low-potential signal line VGL. In other embodiments, the second plate of the first storage unit C1 can also be connected to the high-potential signal line VGH, or to the ground line, or to the common potential line, which is not limited here.

[0077] In this specific embodiment, the control terminals of the first cascade unit 114 and the delay control unit 115 are connected to a set of control signal lines with opposite phases, specifically including a first control signal line XCK and a second control signal line CK. The control signals transmitted by the first control signal line XCK and the second control signal line CK have opposite phases, thereby controlling the delay control unit 115 to be off when the first cascade unit 114 is on; or, alternatively, controlling the delay control unit 115 to be on when the first cascade unit 114 is off. In this specific embodiment, the first cascade unit 114 and the delay control unit 115 include transistors with identical driving characteristics. In other embodiments, the control terminals of the first cascade unit 114 and the delay control unit 115 may also be connected to the same control signal line, where the control signal includes a high / low level signal, in which case the first cascade unit 114 and the delay control unit 115 include a set of transistors with opposite driving characteristics.

[0078] Specifically, in the first stage, the first pulse signal Pscan(n-1) of the previous stage is transmitted to the first storage unit C1 via the first cascade unit 114 as a low-level pulse of the first pulse signal Pscan(n-1). In this stage, the high-level holding unit 113 transmits a high-level signal to the control terminals of the first sub-control unit 111 and the second sub-output unit 102 to control the first sub-control unit 111 to conduct, thereby causing the first sub-control unit 111 to control the first sub-output unit 101 to output a high-level pulse of the first pulse signal Pscan(n).

[0079] In the second stage, the first storage unit C1 transmits the stored low-voltage pulse to the control end of the low-voltage control unit 112 through the delay control unit 115 to control the transistor in the low-voltage control unit 112 to turn on, and then transmits the low-voltage control signal to the control end of the first sub-control unit 111 and the second sub-output unit 102, so that the transistor in the first sub-control unit 111 is turned off, and the second sub-output unit 102 is turned on, outputting the low-voltage pulse of the first pulse signal Pscan(n).

[0080] Furthermore, the first output unit 10 further includes a second storage unit C2, which is connected to the control terminal of the second sub-output unit 102 and is used to accelerate the shutdown of the second sub-output unit 102. The second storage unit C2 is a Miller capacitor that acts as a buffer against the Miller effect, accelerating the rapid shutdown of the second sub-output unit 102 after the second stage, thereby ensuring normal operation of the light-emitting stage after the second stage.

[0081] The first plate of the second storage unit C2 is connected to the control terminal of the second sub-output unit 102, and the second plate is connected to the output terminal of the second sub-output unit 102. In the second phase, both the first and second plates of the second storage unit C2 store low potentials. In the light-emitting phase after the second phase, the second plate of the second storage unit C2 stores a high potential. Therefore, due to capacitive coupling, the first plate of the second storage unit C2 is coupled to a high potential, thereby accelerating the shutdown of the second sub-output unit 102.

[0082] In one embodiment, the first sub-control unit 111 includes a low-potential signal line VGL and a first transistor T1 that is turned on at a high potential. The input terminal of the first transistor T1 is connected to the low-potential signal line VGL, and the output terminal is connected to the control terminal of the first sub-output unit 101, for transmitting a low-potential turn-on signal to the control terminal of the first sub-output unit 101. The first transistor T1 is an N-type transistor.

[0083] In another specific embodiment, the first sub-control unit 111 includes a low-potential signal line VGL, a first transistor T1 that is turned on at a high potential, and a second transistor T2 that is turned on at a low potential. The second transistor T2 is disposed between the control terminal of the first transistor T1. The control terminal of the second transistor T2 is connected to the output unit of the first transistor T1 and is turned on by receiving a low-potential signal. The input terminal of the second transistor T2 is connected to the low-potential signal line VGL, and the output terminal of the second transistor T2 is connected to the control terminal of the first sub-output unit 101. The second transistor T2 is configured to control the low-potential signal line VGL to output a conduction signal to the control terminal of the first sub-output unit 101 based on the control signal output by the first transistor T1. The first transistor T1 is an N-type transistor, and the second transistor T2 is a P-type transistor.

[0084] Please refer to the following for details: Figure 7 , Figure 7 This is a partial structural diagram of the fifth specific embodiment of the gate driving unit provided in this application.

[0085] In one specific embodiment, the pulse width modulation unit 210 includes a first pulse width modulation unit 220 and a second pulse width modulation unit 230. The first pulse width modulation unit 220 is connected to the control terminal of the third sub-output unit 201 and is configured to output a first pulse width modulation signal PWM-CK to the control terminal of the third sub-output unit 201. The second pulse width modulation unit 230 is connected to the control terminal of the fourth sub-output unit 202 and is configured to output a second pulse width modulation signal PWM-XCK to the control terminal of the fourth sub-output unit 202. The first pulse width modulation signal PWM-CK and the second pulse width modulation signal PWM-XCK are a set of level signals with opposite pulse phases and the same frequency. That is, when the first pulse width modulation signal PWM-CK turns on the third sub-output unit 201, the second pulse width modulation signal PWM-XCK turns off the fourth sub-output unit 202. When the first pulse width modulation signal PWM-CK turns off the third sub-output unit 201, the second pulse width modulation signal PWM-XCK turns on the fourth sub-output unit 202. The frequencies of the first pulse-width control signal PWM-CK and the second pulse-width control signal PWM-XCK are greater than the frequency of the first pulse signal Pscan(n). Preferably, the pulse frequencies of the first pulse-width control signal PWM-CK and the second pulse-width control signal PWM-XCK are integer multiples of the pulse frequency of the first pulse signal Pscan(n), specifically integer multiples greater than 1, such as 2 times, 3 times, 4 times, etc. Therefore, during the light-emitting phase, the first pulse-width control signal PWM-CK and the second pulse-width control signal PWM-XCK include at least one set of low and high levels, thereby causing the second pulse signal EM(n) to output an on signal and an off signal during the light-emitting phase. In this specific embodiment, the third sub-output unit 201 and the fourth sub-output unit 202 include transistors with identical drive characteristics, both being P-type transistors.

[0086] The second control unit 21 outputs alternating high-level signals and low-level signals to control the conduction of the first pulse width modulation unit 220 , the second pulse width modulation unit 230 and the fifth sub-output unit 203 .

[0087] Further, see Figure 8 , Figure 8 This is a partial structural diagram of the sixth specific embodiment of the gate drive unit provided in this application. Figure 8 As shown, the second control unit 21 at least includes a first potential control unit 211 and a second potential control unit 212 .

[0088] Among them, the input end of the first potential control unit 211 is connected to the high potential signal line VGH, and the output end is connected to the control ends of the first pulse width modulation unit 220, the second pulse width modulation unit 230 and the fifth sub-output unit 203, and is used to transmit a high potential control signal to the control ends of the first pulse width modulation unit 220, the second pulse width modulation unit 230 and the fifth sub-output unit 203 to control the first pulse width modulation unit 220 and the second pulse width modulation unit 230 to be turned on and the fifth sub-output unit 203 to be turned off.

[0089] The second potential control unit 212 has an input terminal connected to the low-potential signal line VGL, and an output terminal connected to the control terminals of the first PWM unit 220, the second PWM unit 230, and the fifth sub-output unit 203. The second potential control unit 212 is configured to transmit a low-potential control signal to the control terminals of the first PWM unit 220, the second PWM unit 230, and the fifth sub-output unit 203 to control the first PWM unit 220 and the second PWM unit 230 to be turned off and the fifth sub-output unit 203 to be turned on. It should be noted that the terms "on" and "off" herein may also refer to the two states of operation and non-operation, that is, the first PWM unit 220 and the second PWM unit 230 are operated and the fifth sub-output unit 203 is non-operated, or the fifth sub-output unit 203 is operated and the first PWM unit 220 and the second PWM unit 230 are non-operated.

[0090] In this specific embodiment, the first pulse width modulation unit 220 and the second pulse width modulation unit 230 include N-type transistors that conduct at a high potential, and the fifth sub-output unit 203 includes a P-type transistor that conducts at a low potential. In other embodiments, the first pulse width modulation unit 220 and the second pulse width modulation unit 230 may also include P-type transistors, and the fifth sub-output unit 203 may include an N-type transistor. In this case, the first potential control unit 211 is used to transmit a low potential control signal, and the second potential control unit 212 is used to transmit a high potential control signal.

[0091] See further Figure 9 , Figure 9 This is a partial structural diagram of the seventh specific embodiment of the gate drive unit provided in this application. Figure 9 As shown, the second control unit 21 further includes a high potential control unit 213 and a low potential holding unit 214. The output terminals of the high potential control unit 213 and the low potential holding unit 214 are both connected to the control terminals of the first potential control unit 211 and the second potential control unit 212, and are used to control the first potential control unit 211 to be turned on or the second potential control unit 212 to be turned on.

[0092] In this specific embodiment, the first potential control unit 211 and the second potential control unit 212 include a group of transistors with opposite driving characteristics. It is conceivable that in other embodiments, the control terminals of the first potential control unit 211 and the second potential control unit 212 may also be controlled by a pulse signal line, which may be a low-potential pulse with a normally high potential or a high-potential pulse with a normally low potential. The pulse signal line may be a cascaded first pulse signal line.

[0093] The high-potential control unit 213 is configured to transmit a high-potential signal to the control terminals of the first potential control unit 211 and the second potential control unit 212, thereby controlling the first potential control unit 211 to be turned on and the second potential control unit 212 to be turned off. The low-potential holding unit 214 is configured to transmit a low-potential signal to the control terminals of the first potential control unit 211 and the second potential control unit 212, thereby controlling the first potential control unit 211 to be turned off and the second potential control unit 212 to be turned on.

[0094] When the high potential control unit 213 is not working, the low potential holding unit 214 keeps the control terminals of the first potential control unit 211 and the second potential control unit 212 at a low potential, thereby enabling the fifth sub-output unit 203 to output a normal high potential pulse.

[0095] See further Figure 10 , Figure 10 This is a partial structural diagram of the eighth specific embodiment of the gate drive unit provided in this application. Figure 10 As shown, the second cascade unit 240, the first storage control unit 215, the third storage unit C3, the second storage control unit 216, and the fourth storage unit C4.

[0096] Specifically, the second cascade unit 240 is connected to the output end of the second output unit 20 of the previous level, and is used to receive the second pulse signal EM(n-1) output by the second output unit output 20 of the previous level, and control the transmission of a control signal to the control end of the high potential control unit 213 according to the second pulse signal EM(n-1) output by the second output unit output 20 of the previous level, and the control signal is a high potential voltage.

[0097] The first storage control unit 215 is connected to the second cascade unit 240 and is configured to control the transmission of a control signal to the control terminal of the high-voltage control unit 213 based on the on / off status of the second cascade unit 240. Specifically, the input terminal of the first storage control unit 215 is connected to the high-voltage signal line VGH, and the output terminal is connected to the third storage unit C3. In this embodiment, the input terminal of the first storage control unit 215 is connected to the high-voltage signal line VGH through the second cascade unit 240. In other embodiments, the second cascade unit 240 is connected to the control terminal of the first storage control unit 215 to control the transmission of a control signal from the first storage control unit 215 to the high-voltage control unit 213.

[0098] The third storage unit C3 is connected to the output end of the first storage control unit 215 and is used to store the control signal transmitted by the first storage control unit 215 .

[0099] The second storage control unit 216 is connected to the third storage unit C3 and is used to control the third storage unit C3 to transmit a control signal to the control terminal of the high potential control unit 213 .

[0100] It also includes a fourth storage unit C4, which is connected to the output end of the second storage control unit 216 and is used to store the control signal transmitted by the second storage control unit 216 until the arrival of the next timing cut-off signal (low potential voltage), thereby ensuring that the high potential control unit 213 is in the on state before then.

[0101] In this specific embodiment, the control terminals of the first storage control unit 215 and the second storage control unit 216 are respectively connected to two control signal lines (CK and XCK) with opposite pulse phases.

[0102] For further information, please refer to Figure 11 , Figure 11 This is a partial structural diagram of the ninth specific embodiment of the gate drive unit provided in this application. Figure 11 As shown, the second cascade unit 240 includes a first sub-cascade unit 241 , a second sub-cascade unit 242 , and a cascade control unit 243 .

[0103] Among them, the control end of the first sub-cascade unit 241 is connected to the output end of the first output unit 10 of the upper two levels, and the input end is connected to the output end of the second output unit 20 of the upper level, and is used to control the reception of the second pulse signal EM(n-1) output by the second output unit 20 of the upper level according to the first pulse signal Pscan(n-2) of the upper two levels.

[0104] The control end of the second sub-cascade unit 242 is connected to the output end of the first output unit 10 of the previous level, and the input end is connected to the output end of the second output unit 20 of the previous level, and is used to control the reception of the second pulse signal EM(n-1) output by the second output unit 20 of the previous level according to the first pulse signal Pscan(n-1) of the previous level.

[0105] The control end of the cascade control unit 243 is connected to the output ends of the first sub-cascade unit 241 and the second sub-cascade unit 242, and is used to control the transmission of the control signal to the control end of the high potential control unit 213 according to the second pulse signal EM(n-1) of the previous stage.

[0106] In the above embodiment, the low potential holding unit 214 includes a low potential signal line VGL and a second resistor R2. The low potential signal line VGL is connected to the control terminals of the first potential control unit 211 and the second potential control unit 212 via the second resistor R2. In other embodiments, the low potential holding unit 214 may be controlled by a transistor, which is not limited here.

[0107] In this specific embodiment, the second control unit 21 also includes a reset signal line CLR, which is connected to the third storage unit C3 and is used to transmit a reset signal to the third storage unit C3, and then transmit the reset signal to the fourth storage unit C4 through the second storage control unit 216, so that the potential stored in the third storage unit C3 and the fourth storage unit C4 is reset.

[0108] In some specific embodiments, the second control unit 21 further includes a reset unit 250, see Figure 12 , Figure 12 This is a partial structural diagram of the tenth specific embodiment of the gate drive unit provided in this application. The reset unit 250 includes a low-voltage signal line VGL and a third resistor R3. The reset unit 250 is connected to the input of the first storage control unit 215 and is used to transmit a low-voltage reset signal to the third storage unit C3 and the fourth storage unit C4. Specifically, the reset unit 250 is connected to the input of the first storage control unit 215 and the output of the cascade control unit 243.

[0109] Specifically, when the first storage control unit 215 is turned on, the high potential stored in the third storage cell C3 is discharged through the first storage control unit 215 and the reset unit 250. When the second storage control unit 216 is turned on, the high potential stored in the fourth storage cell C4 is discharged and reset.

[0110] It should be noted that the reset unit 250 is a low-voltage reset unit in each gate driver unit stage. The reset signal line CLR connects all gate driver units. The reset signal on the reset signal line CLR is arranged during the light-emitting cycle of other gate driver units, generally during the blanking period. To avoid timing conflicts and insufficient thrust caused by placing the reset signal during the blanking period, the reset unit 250 is added to each gate driver unit stage.

[0111] See further Figure 13 , Figure 13 This is a schematic diagram of the circuit structure of a specific embodiment of the gate drive unit provided in this application.

[0112] The first sub-control unit 111 includes a first transistor T1 and a second transistor T2. The high potential holding unit 113 includes a first resistor R1. The low potential control unit 112 includes a third transistor T3. The delay control unit 115 includes a fourth transistor T4. The first cascade unit 114 includes a fifth transistor T5. The first sub-output unit 101 includes a sixth transistor T6, and the second sub-output unit 102 includes a seventh transistor T7.

[0113] The third sub-output unit 201 includes an eighth transistor T8. The fourth sub-output unit 202 includes a ninth transistor T9. The fifth sub-output unit 203 includes a tenth transistor T10. The first storage control unit 215 includes an eleventh transistor T11. The second storage control unit 216 includes a twelfth transistor T12. The low potential holding unit 214 includes a second resistor R2. The high potential control unit 213 includes a thirteenth transistor T13. The first potential control unit 211 includes a fourteenth transistor T14. The second potential control unit 212 includes a fifteenth transistor T15. The first pulse width modulation unit 220 includes a sixteenth transistor T16. The second pulse width modulation unit 230 includes a seventeenth transistor T17. The cascade control unit 243 includes an eighteenth transistor T18. The first sub-cascade unit 241 includes a nineteenth transistor T19. The second sub-cascade unit 242 includes a twentieth transistor T20.

[0114] In this embodiment, the first transistor T1, the thirteenth transistor T13, the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, and the eighteenth transistor T18 are N-type transistors, and the other transistors are P-type transistors. In other embodiments, the PMOS and NMOS can also be reversed, which is not limited here.

[0115] This application also provides a driving timing diagram of a gate driving unit. Figure 14 , Figure 14 This is a driving timing diagram of a specific embodiment of the gate driving unit provided in this application. Figure 14 As shown in Figure 1, the driving phase includes the preparation phase, the reset phase, the sampling phase, and the light-emitting phase. Figures 15 to 18 . Figure 15 This is a circuit diagram of the first driving stage of a specific embodiment of the gate driving unit provided in this application. Figure 16 This is a circuit diagram of the second driving stage of a specific embodiment of the gate driving unit provided in this application. Figure 17 This is a circuit diagram of the third driving stage of a specific embodiment of the gate driving unit provided in this application. Figure 18 This is a circuit diagram of the fourth driving stage of a specific embodiment of the gate driving unit provided in this application.

[0116] During the preparation phase, the first control signal line XCK is at a low potential, and the second control signal line CK is at a high potential. At this point, the fourth transistor T4 is turned on, and the fifth transistor T5 is turned off. The high potential stored in the first storage cell C1 during the previous cycle passes through the gate of the fourth transistor T4, turning off the third transistor T3. This pulls up the gates of the first transistor T1 and the sixth transistor T6, turning on the first transistor T1 and turning off the sixth transistor T6. The low potential signal line VGL is transmitted through the first transistor T1 to the gate of the second transistor T2, turning on the second transistor T2. This in turn causes the low potential signal line VGL to pass through the second transistor T2 to the gate of the seventh transistor T7, turning on the seventh transistor T7. At this point, the high potential signal line VGH outputs a high potential pulse of the first pulse signal Pscan(n) through the seventh transistor T7.

[0117] At this time, the first pulse signal Pscan(n-2) of the previous two stages is a low-level pulse, and the first pulse signal Pscan(n-1) of the previous stage is a high-level pulse. The nineteenth transistor T19 is turned on, and the twentieth transistor T20 is turned off. The high-level pulse of the second pulse signal EM(n-1) of the previous stage is applied to the gate of the eighteenth transistor T18 through the nineteenth transistor T19, turning on the eighteenth transistor T18. At this time, the high level of the first control signal line XCK turns on the eleventh transistor T11. The high-level signal line VGH passes through the eighteenth transistor T18 and the eleventh transistor T11 to the top plate of the third storage cell C3, thereby storing the high-level pulse signal. At this time, the fourth storage cell C4 stores a low-level signal in the previous cycle, turning off the thirteenth transistor T13. At this time, the low-level signal of the low-level signal line VGL passes through the second resistor R2 to the gates of the fourteenth transistor T14 and the fifteenth transistor T15, turning on the fourteenth transistor T14 and turning off the fifteenth transistor T15. The high-voltage signal line VGH transmits a high-voltage signal to the gates of the sixteenth transistor T16, the seventeenth transistor T17, and the tenth transistor T10 via the fourteenth transistor T14, turning on the sixteenth and seventeenth transistors T16 and T17 and turning off the tenth transistor T10. The first pulse-width modulation signal line PWM-CK transmits a first pulse-width modulation signal to the gate of the eighth transistor T8 via the sixteenth transistor T16, and the second pulse-width modulation signal line PWM-XCK transmits a second pulse-width modulation signal to the gate of the ninth transistor T9 via the seventeenth transistor T17. The first and second pulse-width modulation signals control the eighth and ninth transistors T8 and T9 to alternately turn on and off, thereby outputting high and low voltage pulses of the second pulse signal EM(n).

[0118] During the reset phase, the first control signal line XCK is at a high potential and the second control signal line CK is at a low potential. At this time, the fourth transistor T4 is turned off and the fifth transistor T5 is turned on. The first pulse signal Pscan(n-1) of the previous stage is a low potential pulse, and this low potential pulse is transmitted to the first storage unit C1 for storage through the fifth transistor T5. The third transistor T3 remains off, and the high potential signal line VGH pulls up the gate of the first transistor T1 and the gate of the sixth transistor T6 through the first resistor R1, turning on the first transistor T1 and turning off the sixth transistor T6. The low potential signal line VGL is transmitted to the gate of the second transistor T2 through the first transistor T1, controlling the second transistor T2 to turn on. In turn, the low potential signal line VGL is transmitted to the gate of the seventh transistor T7 through the second transistor T2, controlling the seventh transistor T7 to turn on. At this time, the high potential signal line VGH outputs a high potential pulse of the first pulse signal Pscan(n) through the seventh transistor T7.

[0119] At this time, the first pulse signals Pscan(n-2) of the previous two stages are high-voltage pulses, and the first pulse signal Pscan(n-1) of the previous stage is low-voltage pulse. The nineteenth transistor T19 is turned off, and the twentieth transistor T20 is turned on. The high-voltage pulse of the second pulse signal EM(n-1) of the previous stage is applied to the gate of the eighteenth transistor T18 through the twentieth transistor T20, controlling the eighteenth transistor T18 to turn on. At this time, the low voltage of the second control signal line CK controls the twelfth transistor T12 to turn on. The high-voltage pulse stored in the third storage unit C3 is transmitted to the fourth storage unit C4 and the control terminal of the thirteenth transistor T13 through the twelfth transistor T12, controlling the thirteenth transistor T13 to turn on. The high-voltage signal line VGH transmits a high voltage to the gates of the fourteenth transistor T14 and the fifteenth transistor T15 through the thirteenth transistor T13, controlling the fourteenth transistor T14 to turn off and the fifteenth transistor T15 to turn on. The low-potential signal line VGL transmits a high potential to the gates of the sixteenth transistor T16, the seventeenth transistor T17, and the tenth transistor T10 via the fifteenth transistor T15, thereby turning off the sixteenth and seventeenth transistors T16 and T17 and turning on the tenth transistor T10. The high-potential signal line VGH outputs a high-potential pulse of the second pulse signal EM(n) via the tenth transistor T10.

[0120] During the sampling phase, the first control signal line XCK is at a low potential and the second control signal line CK is at a high potential. At this point, the fourth transistor T4 is turned on and the fifth transistor T5 is turned off. The low potential stored in the first storage cell C1 in the previous cycle is transmitted to the gate of the third transistor T3 via the fourth transistor T4, turning on the third transistor T3. The low potential signal line VGL is transmitted to the gates of the first transistor T1 and the sixth transistor T6 via the third transistor T3, turning off the first transistor T1 and turning on the sixth transistor T6. At this point, the low potential signal line VGL outputs a low potential pulse of the first pulse signal Pscan(n) via the sixth transistor T6.

[0121] At this time, the first pulse signals Pscan(n-2) of the upper two levels are high-potential pulses, and the first pulse signal Pscan(n-1) of the upper level is a high-potential pulse. The nineteenth transistor T19 is turned off, and the twentieth transistor T20 is turned off. The eighteenth transistor T18 is turned off. At this time, the high potential of the first control signal line XCK controls the eleventh transistor T11 to be turned on, and the low-potential signal line VGL is transmitted to the upper board storage of the third storage unit C3 through the third resistor R3 and the eleventh transistor T11, thereby storing the low-potential pulse signal. At this time, the fourth storage unit C4 stores a high-potential signal in the previous cycle, thereby controlling the thirteenth transistor T13 to be turned on. At this time, the high-potential signal line VGH transmits a high potential to the gates of the fourteenth transistor T14 and the fifteenth transistor T15 through the thirteenth transistor T13, controlling the fourteenth transistor T14 to be turned off and the fifteenth transistor T15 to be turned on. The low-potential signal line VGL transmits a high potential to the gates of the sixteenth transistor T16, the seventeenth transistor T17, and the tenth transistor T10 via the fifteenth transistor T15, thereby turning off the sixteenth and seventeenth transistors T16 and T17 and turning on the tenth transistor T10. The high-potential signal line VGH outputs a high-potential pulse of the second pulse signal EM(n) via the tenth transistor T10.

[0122] During the light-emitting phase, the first control signal line XCK is at a high potential, and the second control signal line CK is at a low potential. At this point, the fourth transistor T4 is turned off, the fifth transistor T5 is turned on, and the previous-stage first pulse signal Pscan(n-1) is a low-potential pulse. This low-potential pulse is transmitted to the first storage cell C1 through the fifth transistor T5 for storage. The third transistor T3 remains off, and the high-potential signal line VGH pulls up the gates of the first transistor T1 and the sixth transistor T6 through the first resistor R1, turning on the first transistor T1 and turning off the sixth transistor T6. The low-potential signal line VGL is transmitted through the first transistor T1 to the gate of the second transistor T2, turning on the second transistor T2. This in turn causes the low-potential signal line VGL to pass through the second transistor T2 to the gate of the seventh transistor T7, turning on the seventh transistor T7. At this point, the high-potential signal line VGH outputs a high-potential pulse of the first pulse signal Pscan(n) through the seventh transistor T7.

[0123] At this time, the first pulse signals Pscan(n-2) of the previous two stages are high-voltage pulses, and the first pulse signal Pscan(n-1) of the previous stage is high-voltage pulses. The nineteenth transistor T19 is turned off, and the twentieth transistor T20 is turned off. The eighteenth transistor T18 is turned off. At this time, the low voltage of the second control signal line CK controls the twelfth transistor T12 to turn on. The low voltage stored in the third storage cell C3 is transmitted to the fourth storage cell C4 and the gate of the thirteenth transistor T13 through the twelfth transistor T12, turning off the thirteenth transistor T13. At this time, the low voltage signal of the low voltage signal line VGL is transmitted to the gates of the fourteenth transistor T14 and the fifteenth transistor T15 through the second resistor R2, turning on the fourteenth transistor T14 and turning off the fifteenth transistor T15. The high voltage signal line VGH transmits a high voltage signal to the gates of the sixteenth transistor T16, the seventeenth transistor T17, and the tenth transistor T10 through the fourteenth transistor T14, turning on the sixteenth transistor T16 and the seventeenth transistor T17, and turning off the tenth transistor T10. The first pulse-width modulation signal line PWM-CK transmits a first pulse-width modulation signal to the gate of the eighth transistor T8 via the sixteenth transistor T16, and the second pulse-width modulation signal line PWM-XCK transmits a second pulse-width modulation signal to the gate of the ninth transistor T9 via the seventeenth transistor T17. The first pulse-width modulation signal and the second pulse-width modulation signal control the eighth transistor T8 and the ninth transistor T9 to alternately conduct, thereby outputting high / low potential pulses of the second pulse signal EM(n).

[0124] This application also provides a display panel. Figure 19 , Figure 19 This is a schematic diagram of the structure of an embodiment of a display panel provided by this application. Figure 19 As shown, the display panel 100 includes a display area 1001 and a non-display area 1002. The non-display area 1002 on one side or two opposite sides of the display panel 100 is provided with a gate driving circuit as described in any of the above embodiments. The gate driving circuit includes a plurality of cascaded gate driving units. The gate driving circuit sequentially transmits a first pulse signal Pscan(n) and a second pulse signal EM(n) to each row of pixel units in the display area 1001.

[0125] Each pixel unit in the display area 1001 includes a pixel driving circuit. Figure 20 , Figure 20This is a schematic diagram of the structure of an embodiment of the pixel driver circuit provided in this application. The gate driver circuit sequentially transmits a first pulse signal Pscan(n) and a second pulse signal EM(n) to the pixel driver circuit in each row of pixel units in the display area 1001. During the sampling phase, the first pulse signal Pscan(n) controls the data write transistor TF2 to write a data signal to the gate of the driver transistor DTFT of the pixel driver circuit. During the light-emitting phase, the second pulse signal EM(n) transmits a switching signal to the switching transistors TF4 and TF5, thereby causing the driver transistor DTFT to drive the light-emitting device OLED to emit light.

[0126] By designing the above-mentioned gate drive circuit, the present application enables a GOA circuit to transmit scanning signals and switching signals to the pixel unit while minimizing the use of input signals, thereby saving circuit expenses and reducing the border width.

[0127] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A gate drive circuit, characterized in that: The gate driving circuit includes a multi-stage cascaded gate driving unit, and the gate driving unit includes: A first output unit is configured to output a first pulse signal, wherein the first pulse signal is a low-potential pulse with a normal high potential; a second output unit, configured to output a second pulse signal, wherein the second pulse signal is a pulse width modulated signal accompanied by a high-potential pulse, and the second pulse signal includes a normal high-potential pulse and a high-potential pulse and a low-potential pulse in the pulse width modulated signal; the second output unit includes a third sub-output unit, a fourth sub-output unit, a fifth sub-output unit, and a pulse width modulation unit, the third sub-output unit being connected to the low-potential signal line and being configured to output the low-potential pulse of the pulse width modulated signal, the fourth sub-output unit being connected to the high-potential signal line and being configured to output the high-potential pulse of the pulse width modulated signal, and the fifth sub-output unit being connected to the high-potential signal line and being configured to output the normal high-potential pulse; the pulse width modulation unit being connected to the control terminals of the third sub-output unit and the fourth sub-output unit and being configured to output a pulse width modulation control signal so as to cause the third sub-output unit and the fourth sub-output unit to be alternately turned on during a light-emitting phase to generate a pulse width modulation signal; a first control unit connected to the control end of the first output unit, and configured to control the first output unit to output a first pulse signal; The second control unit is connected to the control end of the second output unit and is used to control the second output unit to output a second pulse signal.

2. The gate drive circuit according to claim 1, wherein: The first output unit includes a first sub-output unit and a second sub-output unit; The first sub-output unit is connected to the high-potential signal line and is used to output a high-potential pulse according to the control signal output by the first control unit; The second sub-output unit is connected to the low-potential signal line, and is configured to output a low-potential pulse according to the control signal output by the first control unit.

3. The gate drive circuit according to claim 2, wherein: The first control unit includes: The first sub-control unit is connected to the control terminal of the first sub-output unit, and is used to output a conduction signal to the first sub-output unit to control the first sub-output unit to output a high-potential pulse; a low-potential control unit, connected to the control terminals of the first sub-control unit and the second sub-output unit, and configured to transmit a low-potential control signal to the control terminals of the first sub-control unit and the second sub-output unit, thereby controlling the second sub-output unit and controlling the first sub-output unit via the first sub-control unit; A high potential holding unit is connected to the control ends of the first sub-control unit and the second sub-output unit, and is used to keep the control ends of the first sub-control unit and the second sub-output unit at a high potential, thereby controlling the output of the first sub-output unit and the second sub-output unit.

4. The gate driving circuit according to claim 3, wherein: The first control unit further includes: a first cascade unit, connected to the first output unit of the previous stage, and configured to receive a first pulse signal transmitted by the first output unit of the previous stage; a first storage unit connected to the first cascade unit, and configured to store a potential signal of the first pulse signal of the previous stage; wherein the potential signal includes a high potential and a low potential; A delay control unit is connected to the first storage unit and the control end of the low potential control unit, and is used to transmit the potential signal stored in the first storage unit to the control end of the low potential control unit to control the on / off of the low potential control unit.

5. The gate driving circuit according to claim 4, wherein: Control terminals of the first cascade unit and the delay control unit are connected to a group of control signal lines with opposite pulse phases.

6. The gate driving circuit according to claim 3, wherein: The first sub-control unit includes: Low potential signal line; A first transistor, wherein the input end of the first transistor is connected to the low-potential signal line, the output end of the first transistor is connected to the control end of the first sub-output unit, the control end of the first transistor is connected to the high-potential holding unit and the low-potential control unit, and is used to control the low-potential signal line to output a conduction signal to the first sub-output unit according to the control signals output by the high-potential holding unit and the low-potential control unit; wherein the first transistor is an N-type transistor.

7. The gate driving circuit according to claim 3, wherein: The high potential holding unit includes a high potential signal line and a first resistor. The high potential signal line is connected to the control terminals of the first sub-control unit and the first sub-output unit through the first resistor.

8. The gate driving circuit according to claim 1, wherein: The pulse width modulation unit comprises: a first pulse width modulation unit, connected to the control end of the third sub-output unit, and configured to output a first pulse width modulation signal to the control end of the third sub-output unit; a second pulse width modulation unit, connected to the control end of the fourth sub-output unit, and configured to output a second pulse width modulation signal to the control end of the fourth sub-output unit; The first pulse width control signal and the second pulse width control signal are a set of level signals with opposite pulse phases.

9. The gate driving circuit according to claim 8, wherein: The second control unit includes: a first potential control unit, having an input end connected to the high potential signal line and an output end connected to the control ends of the first pulse width modulation unit, the second pulse width modulation unit, and the fifth sub-output unit, for transmitting a high potential control signal to the control ends of the first pulse width modulation unit, the second pulse width modulation unit, and the fifth sub-output unit; a second potential control unit, whose input end is connected to the low potential signal line, and whose output end is connected to the control ends of the first pulse width modulation unit, the second pulse width modulation unit, and the fifth sub-output unit, for transmitting a low potential control signal to the control ends of the first pulse width modulation unit, the second pulse width modulation unit, and the fifth sub-output unit.

10. The gate driving circuit according to claim 9, wherein: The second control unit further includes: a high potential control unit connected to the control terminals of the first potential control unit and the second potential control unit, and configured to control on / off of the first potential control unit and the second potential control unit; a low potential holding unit connected to the control terminals of the first potential control unit and the second potential control unit and the output terminal of the high potential control unit, and configured to control the control terminals of the first potential control unit and the second potential control unit to be at a low potential when the high potential control unit does not output; The first potential control unit and the second potential control unit include a group of transistors with opposite driving characteristics.

11. The gate driving circuit according to claim 10, wherein: The second control unit further includes: A second cascade unit, connected to the second output unit of the previous stage, and configured to receive the second pulse signal output by the second output unit of the previous stage; a first storage control unit connected to the second cascade unit, and configured to transmit a control signal according to the second cascade unit; a third storage unit, connected to the first storage control unit, and configured to store the control signal transmitted by the first storage control unit; a second storage control unit connected to the third storage unit, and configured to control the third storage unit to transmit the control signal to the control terminal of the high potential control unit; a fourth storage unit, connected to the second storage control unit, and configured to store the control signal transmitted by the second storage control unit; The control ends of the first storage control unit and the second storage control unit are respectively connected to two control signal lines with opposite pulse phases.

12. The gate driving circuit according to claim 11, wherein: The second control unit further includes: A reset signal line is connected to the third storage unit and is used to transmit a reset signal to the third storage unit, and further transmit the reset signal to the fourth storage unit.

13. The gate driving circuit according to claim 10, wherein: The low potential holding unit includes a low potential signal line and a second resistor. The low potential signal line is connected to the control terminals of the first potential control unit and the second potential control unit through the second resistor.

14. The gate driving circuit according to claim 11, wherein: The second control unit further includes: The reset unit includes a low-potential signal line and a third resistor, is connected to the input end of the first storage control unit, and is used to transmit a low-potential reset signal to the third storage unit and the fourth storage unit.

15. A display panel, characterized in that: The display panel includes the gate driving circuit according to any one of claims 1 to 14.

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