EFUSE anti-miswriting protection system and method based on Ethernet chip, and storage medium

Abstract

The invention discloses an EFUSE anti-miswriting protection method and device based on an Ethernet chip and a storage medium. The method comprises a message receiving stage, an analysis stage used for identifying a specific message header and a verification stage. And the instruction sequence is verified according to the verification algorithm, and when verification fails, the current instruction sequence is discarded, so that backward transmission of an illegal instruction sequence is avoided. According to the method, a specific message with a built-in instruction sequence is constructed, and in order to ensure the confidentiality and integrity of the instruction sequence, a verification algorithm adopts the combination of an encryption algorithm and a digest algorithm. The construction method comprises the following steps of: calculating an original sequence by using an abstract algorithm to obtain an abstract, calculating an original instruction sequence and the abstract by using a symmetric encryption algorithm to obtain a ciphertext, filling the ciphertext into a corresponding field of a message, and packaging a lead code, a specific Ethernet message header and a frame verification sequence to form a frame of complete Ethernet message. And meanwhile, a receiving module, an analyzing module and the like built in the Ethernet chip are multiplexed to provide an instruction sequence for the OTPC, so that the hardware overhead is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of Ethernet chips and memory, and in particular to an EFUSE anti-miswrite protection method, device and storage medium based on an Ethernet chip. Background Art

[0002] The development trend in the chip field follows Moore's Law, which doubles the number of transistors that can be accommodated on an integrated circuit every two years. This leads to higher and higher integration of chips, more and more complex functions, and more complex influences between various subsystems, which leads to an increasing probability of misoperation that causes unexpected system failures. Therefore, it is necessary to consider how to prevent misoperation or reduce the impact after it occurs. As a one-time programming memory (OTP), EFUSE is widely used in the field of integrated chips. EFUSE is usually used to store key chip information, such as the key for the root of trust, the chip's unique identification code, circuit adjustment parameters, MAC address, etc. In the existing EFUSE usage scenarios, more consideration is given to providing redundant backup if the storage fuse of EFUSE itself fails, without considering the situation where misoperation causes the writing of erroneous data in complex systems. Such a combination of normal storage of erroneous data is likely to lead to a decrease in system robustness and vulnerability to hacker attacks. For example, if the value of the root of trust key in the original EFUSE is changed due to misoperation, the original encryption and decryption cannot be performed normally, resulting in a direct failure of chip startup. Therefore, it is necessary to consider and design a method to prevent miswriting of EFUSE, which can also improve the robustness and security of the system. Summary of the invention

[0003] In order to solve the above problems of the prior art solutions, the present invention proposes an anti-miswrite technical solution of EFUSE based on Ethernet chip to solve the above technical problems.

[0004] In order to achieve the above-mentioned object, the present invention adopts the following technical scheme: an EFUSE protection method for preventing miswriting based on an Ethernet chip, comprising a message receiving stage, in which the Ethernet chip receives a message through any Ethernet port and sends it to a parsing module, the parsing module identifies its specific message header, parses out the instruction sequence carried by the message according to its message format and sends it to a verification module;

[0005] The verification module verifies the instruction sequence according to the verification algorithm. When the verification fails, the current instruction sequence will be discarded to prevent some illegal instruction sequences from being passed backward.

[0006] Furthermore, the verification algorithm adopts a combination of an encryption algorithm and a digest algorithm, and its construction is through the following method: the digest algorithm is used to calculate the original sequence to obtain a digest, and then the original instruction sequence and the digest are calculated using a symmetric encryption algorithm to obtain a ciphertext, the ciphertext is filled into the corresponding field of the message, and then the leading code, the specific Ethernet message header and the frame check sequence are encapsulated to form a complete Ethernet message frame.

[0007] Furthermore, when the verification module is verified, the built-in receiving, parsing and other modules of the Ethernet chip are reused to provide instruction sequences for the OTPC, thereby reducing hardware overhead.

[0008] Furthermore, the format of the instruction sequence can determine whether the current instruction belongs to a timestamp threshold instruction or an address permission instruction according to the offset address a;

[0009] If it is a timestamp threshold instruction, the offset address [b:c] is the permission level, which can represent turning on or off the timestamp threshold judgment; the offset address [d:e] is the time threshold;

[0010] If it is an address permission instruction, the offset address [b:c] is the permission level, indicating whether the address range has operation permission; the offset address [d:e] is the address range.

[0011] Furthermore, it also includes the OTPC execution phase.

[0012] It includes a method for preventing timestamps from being written by mistake, specifically, a counter is built into the OTPC, and a counter threshold is set, which is the timestamp information in the message. When the threshold is exceeded, burning is prohibited;

[0013] And / or the method of preventing miswriting of the global restriction flag, specifically, setting the global restriction flag inside EFUSE, and OTPC automatically reads it out and latches it for standby after each chip startup, and determines whether to prohibit burning according to the flag bit value of the global restriction flag.

[0014] Furthermore, it also includes a method for preventing accidental writing of the storage range, specifically, the MAC address is fixed in an area of ​​EFUSE, and whether the address carried by the write operation is consistent with the EFUSE address storing the MAC is judged. It also includes a method for detecting and preventing accidental writing of the burned data, specifically, and checking whether the first 3 bytes of the data are consistent with the unique code applied by the chip manufacturer. If both are consistent, the operation is considered normal.

[0015] Furthermore, OTPC distributes the instruction sequence to the corresponding module according to the instruction sequence number, and the corresponding module resets its working state according to the configuration in the sequence;

[0016] After the Ethernet chip is powered on and reset is released, the OTPC reads the EFUSE internal security flag spontaneously through hardware and latches it for subsequent use;

[0017] The OTPC execution phase process is as follows:

[0018] STP1, global permission judgment stage, when the CPU sends a write EFUSE operation request, OTPC first judges the security bit of the global restriction flag. When the security bit is 1, it means that the current EFUSE prohibits burning and the actual burning operation will not occur; when it is 0, OTPC goes to the time threshold monitoring module;

[0019] STP2, time threshold judgment stage, the time threshold monitoring module does not work by default, allowing any write operation to pass the current monitoring module; after receiving the configuration time threshold sequence, it determines whether to start the internal counter according to the permission level, and updates the built-in time threshold according to the issued configuration timestamp. When the internal counter reaches the threshold, it will reject any write operation request and notify the exception handling unit that an erroneous write operation that exceeds the time threshold has occurred; if the threshold has not been reached, the write operation instruction will be passed backward;

[0020] STP3, address range judgment stage, the write operation enters the address range judgment module, which works by default and classifies the operation rights of the burning address carried in the write operation according to the default address range parameters; if the operation address is within the prohibited operation range, the OTPC will reject the write operation and notify the exception handling unit that an erroneous write operation that exceeds the operable address range has occurred; if the operation address is within the operable range, the OTPC sends the write operation to the specific content judgment module; OTPC implements the anti-erroneous write function of different address ranges within EFUSE through the current method;

[0021] STP4, specific content judgment stage, determines whether the address and content carried by the write operation meet the specific format requirements. If they meet the requirements, the current operation will be allowed to pass. If they do not meet the requirements, the exception handling unit will be notified that an erroneous write operation that does not meet the specific format has occurred.

[0022] STP5, the programming voltage judgment stage, uses a voltage sensor to detect the programming voltage of EFUSE. When entering the programming mode, the programming voltage is monitored. If the programming voltage is not within the required range, the current programming operation will be terminated and the exception handling unit will be notified that an erroneous write operation due to abnormal voltage has occurred during the programming process; if the programming voltage is normal, the current programming process will be continued until the current programming operation is completed and the programming success flag is returned.

[0023] The present invention also provides an EFUSE miswrite protection device based on an Ethernet chip, comprising:

[0024] Several Ethernet port modules, used for receiving message sequences and transmitting them to the parsing module;

[0025] The parsing module is used to identify its specific message header, parse out the instruction sequence carried by the message according to its message format and send it to the verification module;

[0026] The verification module verifies the instruction sequence according to the verification algorithm. When the verification fails, the current instruction sequence will be discarded to prevent some illegal instruction sequences from being passed backward.

[0027] Further, it also includes OTPC;

[0028] The OTPC distributes the instruction sequence to the corresponding module according to the instruction sequence number, and the corresponding module resets its working state according to the configuration in the sequence;

[0029] After the Ethernet chip is powered on and reset is released, the OTPC reads the EFUSE internal security flag spontaneously through hardware and latches it for subsequent use;

[0030] The OTPC execution phase process is as follows:

[0031] STP1, global permission judgment stage, when the CPU sends a write EFUSE operation request, OTPC first judges the security bit of the global restriction flag. When the security bit is 1, it means that the current EFUSE prohibits burning and the actual burning operation will not occur; when it is 0, OTPC goes to the time threshold monitoring module;

[0032] STP2, time threshold judgment stage, the time threshold monitoring module does not work by default, allowing any write operation to pass through the current monitoring module; when the configuration time threshold sequence is received, it determines whether to start the internal counter according to the permission level, and updates the built-in time threshold according to the issued configuration timestamp. When the internal counter reaches the threshold, it will reject any write operation request and notify the exception handling unit that an erroneous write operation that exceeds the time threshold has occurred; if the threshold has not been reached, the write operation instruction will be passed backward.

[0033] STP3, address range judgment stage, the write operation enters the address range judgment module, which works by default and classifies the operation rights of the burning address carried in the write operation according to the default address range parameters; if the operation address is within the prohibited operation range, the OTPC will reject the write operation and notify the exception handling unit that an erroneous write operation that exceeds the operable address range has occurred; if the operation address is within the operable range, the OTPC sends the write operation to the specific content judgment module; OTPC implements the anti-erroneous write function of different address ranges within EFUSE through the current method;

[0034] STP4, specific content judgment stage, determines whether the address and content carried by the write operation meet the specific format requirements. If they meet the requirements, the current operation will be allowed to pass. If they do not meet the requirements, the exception handling unit will be notified that an erroneous write operation that does not meet the specific format has occurred.

[0035] STP5, the programming voltage judgment stage, uses a voltage sensor to detect the programming voltage of EFUSE. When entering the programming mode, the programming voltage is monitored. If the programming voltage is not within the required range, the current programming operation will be terminated and the exception handling unit will be notified that an erroneous write operation due to abnormal voltage has occurred during the programming process; if the programming voltage is normal, the current programming process will be continued until the current programming operation is completed and the programming success flag is returned.

[0036] The present invention also provides a computer-readable storage medium containing a computer program, and when the computer program is executed by one or more processors, any of the above-mentioned EFUSE anti-miswrite protection methods based on Ethernet chips is implemented.

[0037] The advantage of the present invention is that a specific message with a built-in instruction sequence is constructed. In order to ensure the confidentiality and integrity of the instruction sequence, the verification algorithm adopts a combination of an encryption algorithm and a digest algorithm. The construction is carried out by the following method: the digest algorithm is used to calculate the original sequence to obtain a digest, and then the original instruction sequence and the digest are calculated using a symmetric encryption algorithm to obtain a ciphertext, the ciphertext is filled into the corresponding field of the message, and then the preamble, the specific Ethernet message header and the frame check sequence are encapsulated to form a complete Ethernet message. At the same time, the built-in receiving, parsing and other modules of the Ethernet chip are reused to provide the instruction sequence for the OTPC, thereby reducing the hardware overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a schematic diagram of the message processing flow in the receiving direction.

[0039] Figure 2 It is a schematic diagram of the various stages of OTPC in the execution process.

[0040] Figure 3 It is a diagram of the specific instruction sequence format.

[0041] Figure 4 It is a diagram of the instruction sequence workflow.

[0042] Figure 5 This is a schematic diagram of the flow chart for determining if specific content is written incorrectly.

[0043] Figure 6 It is a schematic diagram of the voltage monitoring and miswriting prevention process. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] The patent is an EFUSE protection method based on Ethernet chip to prevent accidental writing. The key points of the invention are that it provides a method for configuring a one-time programming storage controller (Once Time ProgramController, abbreviated as OTPC) through Ethernet messages in combination with chip applications in the Ethernet field; it also designs an anti-accidental writing method for four scenarios: product life cycle, storage range, specific content and hardware conditions.

[0046] like Figure 1-6 As shown, an EFUSE protection method for preventing miswriting based on an Ethernet chip includes a message receiving stage. In the message receiving stage, the Ethernet chip receives a message through any Ethernet port and sends it to a parsing module. The parsing module identifies its specific message header, parses out the instruction sequence carried by the message according to its message format, and sends it to a verification module;

[0047] The verification module verifies the instruction sequence according to the verification algorithm. When the verification fails, the current instruction sequence will be discarded to prevent some illegal instruction sequences from being passed backward.

[0048] Among them, the verification algorithm adopts a combination of an encryption algorithm and a digest algorithm, and its construction is through the following method: the digest algorithm is used to calculate the original sequence to obtain a digest, and then the original instruction sequence and the digest are calculated using a symmetric encryption algorithm to obtain a ciphertext, the ciphertext is filled into the corresponding field of the message, and then the leading code, the specific Ethernet message header and the frame check sequence are encapsulated to form a complete Ethernet message frame.

[0049] When verifying the module, the built-in receiving, parsing and other modules of the Ethernet chip are reused to provide instruction sequences for OTPC, reducing hardware overhead.

[0050] like Figure 3 As shown, the format of the instruction sequence can determine whether the current instruction is a timestamp threshold instruction or an address permission instruction according to the offset address a;

[0051] If it is a timestamp threshold instruction, the offset address [b:c] is the permission level, which can represent turning on or off the timestamp threshold judgment; the offset address [d:e] is the time threshold;

[0052] If it is an address permission instruction, the offset address [b:c] is the permission level, indicating whether the address range has operation permission; the offset address [d:e] is the address range.

[0053] exist Figure 1 In the example, the OTPC execution phase is also included.

[0054] It includes a method for preventing timestamps from being written by mistake, specifically, a counter is built into the OTPC, and a counter threshold is set, which is the timestamp information in the message. When the threshold is exceeded, burning is prohibited;

[0055] And / or the method of preventing miswriting of the global restriction flag, specifically, setting the global restriction flag inside EFUSE, and OTPC automatically reads it out and latches it for standby after each chip startup, and determines whether to prohibit burning according to the flag bit value of the global restriction flag.

[0056] It also includes a method for preventing accidental writing of the storage range. Specifically, the MAC address is fixed in an area of ​​EFUSE. It determines whether the address carried by the write operation is consistent with the EFUSE address storing the MAC. It also includes a method for detecting and preventing accidental writing of the burned data. Specifically, it checks whether the first 3 bytes of the data are consistent with the unique code applied by the chip manufacturer. If both are consistent, the operation is considered normal.

[0057] like Figure 2 , Figure 4 As shown in / 5 / 6, OTPC distributes the instruction sequence to the corresponding module according to the instruction sequence number, and the corresponding module resets its working state according to the configuration in the sequence;

[0058] After the Ethernet chip is powered on and reset is released, the OTPC reads the EFUSE internal security flag spontaneously through hardware and latches it for subsequent use;

[0059] The OTPC execution phase process is as follows:

[0060] STP1, global permission judgment stage, when the CPU sends a write EFUSE operation request, OTPC first judges the security bit of the global restriction flag. When the security bit is 1, it means that the current EFUSE prohibits burning and the actual burning operation will not occur; when it is 0, OTPC goes to the time threshold monitoring module;

[0061] STP2, time threshold judgment stage, the time threshold monitoring module does not work by default, allowing any write operation to pass through the current monitoring module; when the configuration time threshold sequence is received, it determines whether to start the internal counter according to the permission level, and updates the built-in time threshold according to the issued configuration timestamp. When the internal counter reaches the threshold, it will reject any write operation request and notify the exception handling unit that an erroneous write operation that exceeds the time threshold has occurred; if the threshold has not been reached, the write operation instruction will be passed backward.

[0062] STP3, address range judgment stage, the write operation enters the address range judgment module, which works by default and classifies the operation rights of the burning address carried in the write operation according to the default address range parameters; if the operation address is within the prohibited operation range, the OTPC will reject the write operation and notify the exception handling unit that an erroneous write operation that exceeds the operable address range has occurred; if the operation address is within the operable range, the OTPC sends the write operation to the specific content judgment module; OTPC implements the anti-erroneous write function of different address ranges within EFUSE through the current method;

[0063] STP4, the specific content judgment stage, determines whether it meets the specific format requirements based on the address and content carried by the write operation. If it meets the requirements, the current operation will be allowed to pass. If it does not meet the requirements, the exception handling unit will be notified that an erroneous write operation that does not meet the specific format has occurred. This method can effectively prevent the specific content inside EFUSE from being mistakenly written with erroneous data, causing abnormal chip operation.

[0064] STP5, the programming voltage judgment stage, uses a voltage sensor to detect the programming voltage of EFUSE. When entering the programming mode, the programming voltage is monitored. If the programming voltage is not within the required range, the current programming operation will be terminated, and the exception handling unit will be notified that an erroneous programming operation with abnormal voltage has occurred during the programming process; if the programming voltage is normal, the current programming process will continue until the current programming operation is completed and the programming success flag is returned. This method protects against erroneous writing in the case of hardware abnormalities and increases the number of times EFUSE is used.

[0065] like Figure 1 As shown, the present invention also provides an EFUSE anti-miswrite protection device based on an Ethernet chip, comprising:

[0066] Several Ethernet port modules, used for receiving message sequences and transmitting them to the parsing module;

[0067] The parsing module is used to identify its specific message header, parse out the instruction sequence carried by the message according to its message format and send it to the verification module;

[0068] The verification module verifies the instruction sequence according to the verification algorithm. When the verification fails, the current instruction sequence will be discarded to prevent some illegal instruction sequences from being passed backward.

[0069] Also includes OTPC; Figure 3The formats of two instruction sequences are shown. According to the offset address a, it can be obtained whether the current instruction belongs to the timestamp threshold instruction or the address permission instruction. If it is a timestamp threshold instruction, the offset address [b:c] is the permission level, which can represent whether the timestamp threshold judgment is turned on or off; the offset address [d:e] is the time threshold. If it is an address permission instruction, the offset address [b:c] is the permission level, indicating whether the address range has operation permission; the offset address [d:e] is the address range. OTPC will distribute the instruction sequence to the corresponding module according to the instruction sequence number, and the corresponding module will reset its working status according to the configuration in the sequence.

[0070] After the Ethernet chip is powered on and reset is released, the OTPC reads the EFUSE internal security flag spontaneously through hardware and latches it for subsequent use;

[0071] The OTPC execution phase process is as follows:

[0072] STP1, global permission judgment stage, when the CPU sends a write EFUSE operation request, OTPC first judges the security bit of the global restriction flag. When the security bit is 1, it means that the current EFUSE prohibits burning and the actual burning operation will not occur; when it is 0, OTPC goes to the time threshold monitoring module;

[0073] STP2, time threshold judgment stage, the time threshold monitoring module does not work by default, allowing any write operation to pass through the current monitoring module; when the configuration time threshold sequence is received, it determines whether to start the internal counter according to the permission level, and updates the built-in time threshold according to the issued configuration timestamp. When the internal counter reaches the threshold, it will reject any write operation request and notify the exception handling unit that an erroneous write operation that exceeds the time threshold has occurred; if the threshold has not been reached, the write operation instruction will be passed backward.

[0074] STP3, address range judgment stage, the write operation enters the address range judgment module, which works by default and classifies the operation rights of the burning address carried in the write operation according to the default address range parameters; if the operation address is within the prohibited operation range, the OTPC will reject the write operation and notify the exception handling unit that an erroneous write operation that exceeds the operable address range has occurred; if the operation address is within the operable range, the OTPC sends the write operation to the specific content judgment module; OTPC implements the anti-erroneous write function of different address ranges within EFUSE through the current method;

[0075] STP4, the specific content judgment stage, determines whether it meets the specific format requirements based on the address and content carried by the write operation. If it meets the requirements, the current operation will be allowed to pass. If it does not meet the requirements, the exception handling unit will be notified that an erroneous write operation that does not meet the specific format has occurred. This method can effectively prevent the specific content inside EFUSE from being mistakenly written with erroneous data, causing abnormal chip operation.

[0076] STP5, the programming voltage judgment stage, uses a voltage sensor to detect the programming voltage of EFUSE. When entering the programming mode, the programming voltage is monitored. If the programming voltage is not within the required range, the current programming operation will be terminated, and the exception handling unit will be notified that an erroneous programming operation with abnormal voltage has occurred during the programming process; if the programming voltage is normal, the current programming process will continue until the current programming operation is completed and the programming success flag is returned. This method protects against erroneous writing in the case of hardware abnormalities and increases the number of times EFUSE is used.

[0077] The OTPC execution phase is designed with five stages, namely: global permission judgment stage, time threshold judgment stage, address range judgment stage, specific content judgment stage, and burning voltage judgment stage. These five stages cover the anti-miswriting function in the above scenarios.

[0078] The present invention also provides a computer-readable storage medium containing a computer program, and when the computer program is executed by one or more processors, any of the above-mentioned EFUSE anti-miswrite protection methods based on Ethernet chips is implemented.

[0079] The present invention constructs a specific message with a built-in instruction sequence. To ensure the confidentiality and integrity of the instruction sequence, the verification algorithm adopts a combination of an encryption algorithm and a digest algorithm. The construction is carried out by the following method: the original sequence is calculated using a digest algorithm to obtain a digest, and then the original instruction sequence and the digest are calculated using a symmetric encryption algorithm to obtain a ciphertext, the ciphertext is filled into the corresponding field of the message, and then the preamble, the specific Ethernet message header and the frame check sequence are encapsulated to form a complete Ethernet message. At the same time, the built-in receiving, parsing and other modules of the Ethernet chip are reused to provide the instruction sequence for the OTPC, thereby reducing the hardware overhead.

[0080] OTPC uses timestamp and global restriction flag methods to ensure the implementation of anti-miswrite of Ethernet chip products in different life cycles. The chip product life cycle includes packaging, chip return verification, before sales, product use, product destruction and other stages. The timestamp anti-miswrite solution is specifically manifested as a built-in counter in OTPC. The counter threshold is the timestamp information in the message. Burning is prohibited after exceeding the threshold. The global restriction flag is located inside EFUSE. Every time the chip is started, OTPC will automatically read it out and latch it for standby. If this flag is 1, burning is prohibited.

[0081] Considering that each chip usually uses a considerable amount (>1K) of EFUSE storage space, and the data stored in EFUSE are of different categories, such as keys, trip parameters, chip unique identification codes, etc., and the security of the keys is undoubtedly important, so this patent implements the function of preventing miswriting of the storage range by dividing the address ranges with different operation permissions.

[0082] This patent combines Ethernet-specific applications to implement an anti-miswrite function for the MAC address stored in EFUSE under specific content. Each Ethernet chip will have a unique code when it is produced. The full name is Medium Access Control, also known as the physical address. The host needs to use this physical address to communicate in the network. The total length of the MAC address is 6 bytes, a total of 48 bits. The first 3 bytes represent the manufacturer, and each manufacturer's code is uniformly allocated by the IEEE and will not be repeated. Therefore, this module uses the manufacturer's code in the first 3 bytes of the MAC address as a basis for judgment. Specifically, the MAC address is fixed in an area of ​​EFUSE. By judging whether the address carried by the write operation is consistent with the EFUSE address storing the MAC, it also includes a method for detecting and preventing miswrites of burned data, specifically, and checking whether the first 3 bytes of the data are consistent with the unique code applied by the chip manufacturer. If both are consistent, the operation is considered normal.

[0083] A special feature of EFUSE is that the voltages for burning and reading are inconsistent. Taking the EFUSE of an on-board switching chip as an example, in the burning mode, the EFUSE burning voltage needs to be increased to 1.71V~1.98V. If the burning voltage is not within this range, it may cause the burning to fail or other EFUSE circuits to be damaged. In order to prevent the chip from being damaged due to voltage anomalies caused by the hardware environment during the burning process, this patent combines a voltage sensor to monitor the voltage during the EFUSE burning process.

[0084] This patent provides an anti-mistaken write protection method for the built-in EFUSE of the Ethernet chip, and provides special anti-mistaken write protection for some specific storage contents of the Ethernet. It combines time and space information and voltage monitoring methods to provide anti-mistaken write protection covering a variety of chip life cycle scenarios and extend the service life of EFUSE. At the same time, this patent also reuses the modules such as receiving and parsing inside the Ethernet chip, reducing the hardware overhead of this solution and providing chip cost advantages.

[0085] This patent also provides a method for selling chips in a tiered manner. The chip source manufacturer can set a global restriction bit on the eve of sales to prevent consumers from accidentally writing erroneous data and causing the chip to malfunction; or before selling to a partner with higher operating authority, the time during which EFUSE can be burned can be limited through a timestamp message to prevent the chip from flowing into manufacturers without operating authority.

[0086] The process described in the present invention also includes but is not limited to being implemented on integrated circuits including ASIC, FPGA, CPLD, etc.

[0087] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A protection method for preventing EFUSE from miswriting based on Ethernet chip, characterized in that: It includes a message receiving stage. In the message receiving stage, the Ethernet chip receives the message through any Ethernet port and sends it to the parsing module. The parsing module identifies its specific message header, parses out the instruction sequence carried by the message according to its message format and sends it to the verification module; The verification module verifies the instruction sequence according to the verification algorithm. When the verification fails, the current instruction sequence will be discarded to prevent some illegal instruction sequences from being passed backward.

2. The EFUSE protection method for preventing miswriting based on an Ethernet chip according to claim 1, characterized in that: The verification algorithm adopts a combination of an encryption algorithm and a digest algorithm, and its construction is through the following method: the digest algorithm is used to calculate the original sequence to obtain a digest, and then the original instruction sequence and the digest are calculated using a symmetric encryption algorithm to obtain a ciphertext, the ciphertext is filled into the corresponding field of the message, and then the leading code, the specific Ethernet message header and the frame check sequence are encapsulated to form a complete Ethernet message frame.

3. The EFUSE protection method for preventing miswriting based on Ethernet chip according to claim 2, characterized in that: When verifying the module, the built-in receiving, parsing and other modules of the Ethernet chip are reused to provide instruction sequences for OTPC, reducing hardware overhead.

4. The EFUSE protection method for preventing miswriting based on Ethernet chip according to claim 3 is characterized in that: The format of the instruction sequence can determine whether the current instruction is a timestamp threshold instruction or an address permission instruction according to the offset address a; If it is a timestamp threshold instruction, the offset address [b:c] is the permission level, which can represent turning on or off the timestamp threshold judgment; the offset address [d:e] is the time threshold; If it is an address permission instruction, the offset address [b:c] is the permission level, indicating whether the address range has operation permission; the offset address [d:e] is the address range.

5. The EFUSE protection method for preventing miswriting based on an Ethernet chip according to any one of claims 1 to 4, characterized in that: It also includes the OTPC execution phase, It includes a method for preventing timestamps from being written by mistake, specifically, a counter is built into the OTPC, and a counter threshold is set, which is the timestamp information in the message. When the threshold is exceeded, burning is prohibited; And / or the method of preventing miswriting of the global restriction flag, specifically, setting the global restriction flag inside EFUSE, and OTPC automatically reads it out and latches it for standby after each chip startup, and determines whether to prohibit burning according to the flag bit value of the global restriction flag.

6. The EFUSE protection method for preventing miswriting based on Ethernet chip according to claim 5, characterized in that: It includes a method to prevent accidental writing of the storage range. Specifically, the MAC address is fixed in an area of ​​EFUSE. It determines whether the address carried by the write operation is consistent with the EFUSE address storing the MAC. It also includes a method to detect and prevent accidental writing of the burned data. Specifically, it checks whether the first 3 bytes of the data are consistent with the unique code applied by the chip manufacturer. If both are consistent, the operation is considered normal.

7. The EFUSE protection method for preventing miswriting based on Ethernet chip according to claim 6 is characterized in that: OTPC distributes the instruction sequence to the corresponding module according to the instruction sequence number, and the corresponding module resets its working status according to the configuration in the sequence; After the Ethernet chip is powered on and reset is released, the OTPC reads the EFUSE internal security flag spontaneously through hardware and latches it for subsequent use; The OTPC execution phase process is as follows: STP1, global permission judgment stage, when the CPU sends a write EFUSE operation request, OTPC first judges the security bit of the global restriction flag. When the security bit is 1, it means that the current EFUSE prohibits burning and the actual burning operation will not occur; When it is 0, the OTPC moves to the time threshold monitoring module; STP2, time threshold judgment stage, the time threshold monitoring module does not work by default, allowing any write operation to pass the current monitoring module; after receiving the configuration time threshold sequence, it determines whether to start the internal counter according to the permission level, and updates the built-in time threshold according to the issued configuration timestamp. When the internal counter reaches the threshold, it will reject any write operation request and notify the exception handling unit that an erroneous write operation that exceeds the time threshold has occurred; if the threshold has not been reached, the write operation instruction will be passed backward; STP3, address range judgment stage, the write operation enters the address range judgment module, which works by default and classifies the operation rights of the burning address carried in the write operation according to the default address range parameters; if the operation address is within the prohibited operation range, the OTPC will reject the write operation and notify the exception handling unit that an erroneous write operation that exceeds the operable address range has occurred; if the operation address is within the operable range, the OTPC sends the write operation to the specific content judgment module; OTPC implements the anti-erroneous write function of different address ranges within EFUSE through the current method; STP4, specific content judgment stage, determines whether the address and content carried by the write operation meet the specific format requirements. If they meet the requirements, the current operation will be allowed to pass. If they do not meet the requirements, the exception handling unit will be notified that an erroneous write operation that does not meet the specific format has occurred. STP5, the programming voltage judgment stage, uses a voltage sensor to detect the programming voltage of EFUSE. When entering the programming mode, the programming voltage is monitored. If the programming voltage is not within the required range, the current programming operation will be terminated and the exception handling unit will be notified that an erroneous write operation due to abnormal voltage has occurred during the programming process; if the programming voltage is normal, the current programming process will be continued until the current programming operation is completed and the programming success flag is returned.

8. An EFUSE protection device for preventing miswriting based on an Ethernet chip, characterized in that: include: Several Ethernet port modules, used for receiving message sequences and transmitting them to the parsing module; The parsing module is used to identify its specific message header, parse out the instruction sequence carried by the message according to its message format and send it to the verification module; The verification module verifies the instruction sequence according to the verification algorithm. When the verification fails, the current instruction sequence will be discarded to prevent some illegal instruction sequences from being passed backward.

9. The EFUSE protection device for preventing miswriting based on Ethernet chip according to claim 8, characterized in that: It also includes OTPC; The OTPC distributes the instruction sequence to the corresponding module according to the instruction sequence number, and the corresponding module resets its working state according to the configuration in the sequence; After the Ethernet chip is powered on and reset is released, the OTPC reads the EFUSE internal security flag spontaneously through hardware and latches it for subsequent use; The OTPC execution phase process is as follows: STP1, global permission judgment stage, when the CPU sends a write EFUSE operation request, OTPC first judges the security bit of the global restriction flag. When the security bit is 1, it means that the current EFUSE prohibits burning and the actual burning operation will not occur; When it is 0, the OTPC moves to the time threshold monitoring module; STP2, time threshold judgment stage, the time threshold monitoring module does not work by default, allowing any write operation to pass the current monitoring module; after receiving the configuration time threshold sequence, it determines whether to start the internal counter according to the permission level, and updates the built-in time threshold according to the issued configuration timestamp. When the internal counter reaches the threshold, it will reject any write operation request and notify the exception handling unit that an erroneous write operation that exceeds the time threshold has occurred; if the threshold has not been reached, the write operation instruction will be passed backward; STP3, address range judgment stage, the write operation enters the address range judgment module, which works by default and classifies the operation rights of the burning address carried in the write operation according to the default address range parameters; if the operation address is within the prohibited operation range, the OTPC will reject the write operation and notify the exception handling unit that an erroneous write operation that exceeds the operable address range has occurred; if the operation address is within the operable range, the OTPC sends the write operation to the specific content judgment module; OTPC implements the anti-erroneous write function of different address ranges within EFUSE through the current method; STP4, specific content judgment stage, determines whether the address and content carried by the write operation meet the specific format requirements. If they meet the requirements, the current operation will be allowed to pass. If they do not meet the requirements, the exception handling unit will be notified that an erroneous write operation that does not meet the specific format has occurred. STP5, the programming voltage judgment stage, uses a voltage sensor to detect the programming voltage of EFUSE. When entering the programming mode, the programming voltage is monitored. If the programming voltage is not within the required range, the current programming operation will be terminated and the exception handling unit will be notified that an erroneous write operation due to abnormal voltage has occurred during the programming process; if the programming voltage is normal, the current programming process will be continued until the current programming operation is completed and the programming success flag is returned.

10. A computer-readable storage medium containing a computer program, characterized in that: When the computer program is executed by one or more processors, the EFUSE anti-miswrite protection method based on the Ethernet chip as described in any one of claims 1 to 7 is implemented.

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