Semiconductor test structure and method of testing the same

Abstract

The application provides a semiconductor test structure and a test method thereof. The semiconductor test structure is arranged on a scribe lane of a wafer and comprises a transistor including a substrate, a source, a drain and a gate, and an electrical fuse including a first end and a second end. The source is electrically connected to a first pad through a first metal wire, the second end of the electrical fuse is electrically connected to a second pad through a second metal wire, the drain, the substrate and the first end of the electrical fuse are respectively electrically connected to a third pad through corresponding third metal wires, and the gate is electrically connected to a fourth pad through a fourth metal wire. The resistance of the electrical fuse and the performance of the transistor are tested by applying voltages to the first pad, the second pad, the third pad and the fourth pad according to a preset rule. The above technical solution can realize in-line monitoring of the resistance of the electrical fuse and the performance of the transistor during wafer manufacturing, rapid adjustment of the process and improvement of the flexibility of the process.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a semiconductor testing structure and its testing method. Background Technology

[0002] Polysilicon fuses, as low-density embedded one-time programmable components, are widely used in integrated circuits. Based on electromigration theory, fuse technology stores information by detecting whether the fuse is broken by current. Before melting, the resistance of a polysilicon fuse is very low; after being broken by a sustained high current, the resistance can be considered infinite, and the broken state of the fuse is permanently retained. Fuse technology is widely used in redundant circuits to improve chip failure issues or for chip serial numbers, device basic codes, etc., replacing small-capacity one-time programmable memories.

[0003] For fuse programming performance verification, wafer testing (CP) is typically performed after wafer fabrication is complete, which is often time-consuming and lacks flexibility. Therefore, optimizing fuse testing methods to save testing time is a problem that needs to be solved. Summary of the Invention

[0004] The technical problem to be solved by this invention is how to optimize the electric fuse testing method, save testing time, and provide a semiconductor testing structure and its testing method.

[0005] To address the aforementioned problems, this invention provides a semiconductor testing structure disposed on a wafer dicing track, comprising: a transistor including a substrate, a source, a drain, and a gate; and an electro-fuse including a first end and a second end; wherein the source is electrically connected to a first pad via a first metal line, the second end of the electro-fuse is electrically connected to a second pad via a second metal line, the drain, the substrate, and the first end of the electro-fuse are respectively electrically connected to a third pad via corresponding third metal lines, and the gate is electrically connected to a fourth pad via a fourth metal line. By applying voltages to the first pad, the second pad, the third pad, and the fourth pad using preset rules, the resistance of the electro-fuse and the performance of the transistor can be tested.

[0006] To address the aforementioned problems, this invention provides a semiconductor testing method, comprising the following steps: providing a semiconductor testing structure, wherein the semiconductor testing structure adopts the semiconductor testing structure described in this invention; applying voltages to the first pad, the second pad, the third pad, and the fourth pad using preset rules to test the resistance of the electric fuse and to test the performance of the transistor.

[0007] The above technical solution, by placing the semiconductor test structure on the wafer dicing track and connecting the fuse and transistor to the pads respectively, allows for simultaneous in-line monitoring of the fuse resistance and transistor performance during wafer manufacturing, enabling rapid process adjustments and improved process flexibility. By using multiple pads to separate the programming circuit and the fuse and transistor, it facilitates variable control and allows for individual component performance testing, improving testing flexibility and accuracy. The semiconductor test structure shorts the drain, substrate, and the first end of the fuse to the same pad, reducing the number of pads in the semiconductor test, optimizing the circuit layout, and thus reducing the area of ​​the semiconductor test structure, saving wafer space.

[0008] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the accompanying drawings used in the description of the specific embodiments will be briefly introduced below. Obviously, the drawings described below are only some specific embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0010] Figure 1 This is a schematic diagram of an embodiment of the semiconductor testing structure described in this invention.

[0011] Figure 2 This is a flowchart illustrating the steps of an embodiment of the semiconductor testing method described in this invention. Detailed Implementation

[0012] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] Since the performance testing of electric fuse programming is usually performed during wafer testing after wafer fabrication is completed, real-time monitoring is not possible, resulting in significant lag in process adjustments. Therefore, this application proposes a semiconductor testing structure set on the scribe lane of the wafer, which enables in-line monitoring during wafer fabrication, thereby allowing for rapid process adjustments and greatly improving flexibility.

[0014] Please see Figure 1 This is a schematic diagram of an embodiment of the semiconductor testing structure described in this invention. The semiconductor testing structure is disposed on a wafer dicing track, such as... Figure 1 As shown, the semiconductor test structure includes a transistor 11 and an electric fuse 12. The transistor 11 includes a substrate 111, a source 112, a drain 113, and a gate 114. The electric fuse 12 includes a first end 121 and a second end 122. The source 112 is electrically connected to a first pad 141 via a first metal line 131; the second end 122 of the electric fuse 12 is electrically connected to a second pad 142 via a second metal line 132; the drain 113, the substrate 111, and the first end 121 of the electric fuse 12 are each electrically connected to a third pad 143 via a corresponding third metal line 133; and the gate 114 is electrically connected to a fourth pad 144 via a fourth metal line 134. Voltages are applied to the first pad 141, the second pad 142, the third pad 143, and the fourth pad 144 using a preset rule to test the resistance of the electric fuse 12 and the performance of the transistor 11.

[0015] The above technical solution, by placing the semiconductor test structure on the wafer dicing track and connecting the fuse and transistor to the pads respectively, enables inline simultaneous monitoring of the fuse resistance and transistor performance during wafer manufacturing, allowing for rapid process adjustments and improved process flexibility. By using multiple pads to separate the programming circuit and the fuse and transistor, it facilitates variable control and allows for individual component performance testing, improving testing flexibility and accuracy. The semiconductor test structure shorts the drain, substrate, and the first end of the fuse to the same pad, reducing the number of pads in the semiconductor test, optimizing the circuit layout, and thus reducing the area of ​​the semiconductor test structure, saving wafer space.

[0016] In some embodiments, the preset rules include: applying a test voltage to the second pad 142 and the third pad 143 before programming to test the resistance of the electric fuse 12, and applying a test voltage to the first pad 141, the third pad 143 and the fourth pad 144 to test the performance of the transistor 11; and / or applying a test voltage to the second pad 142 and the third pad 143 after programming to test the resistance of the electric fuse 12, and applying a test voltage to the first pad 141, the third pad 143 and the fourth pad 144 to test the performance of the transistor 11.

[0017] In some embodiments, the electrical fuse 12 reaches a predetermined resistance state after programming. The predetermined resistance state is a resistance value or shape set according to the programming purpose. In this embodiment, the predetermined resistance state is a preset resistance value. A test voltage is applied to the first pad 141, the second pad 142, and the fourth pad 144 to allow a predetermined current to flow through the electrical fuse 12, causing self-aligned silicide electromigration or silicon melting inside the electrical fuse 12, increasing the resistance value of the electrical fuse 12. The electrical fuse 12 is programmed until its resistance value reaches the preset resistance value, thereby writing information (i.e., programming) onto the electrical fuse 12. Specifically, the resistance state of the electrical fuse 12 before programming is taken as information "0", and the resistance state of the electrical fuse 12 after programming is taken as information "1".

[0018] In some embodiments, the first metal line 131, the second metal line 132, the third metal line 133, and the fourth metal line 134 are patterned from the same metal layer.

[0019] In this embodiment, an active region is defined within the substrate 111, the source electrode 112 and the drain electrode 113 are formed within the active region, and the gate electrode 114 is located on the surface of the active region, with the source electrode 112 and the drain electrode 113 located on both sides of the gate electrode 114. A gate dielectric layer is also formed between the gate electrode 114 and the active region.

[0020] In this embodiment, the material of the electric fuse 12 is polycrystalline silicon.

[0021] Based on the same inventive concept, an embodiment of the present invention also provides a semiconductor testing method.

[0022] Please see Figure 2 This is a flowchart illustrating the steps of an embodiment of the semiconductor testing method described in this invention. Figure 2As shown, the semiconductor testing method includes the following steps: Step S21, providing a semiconductor testing structure, wherein the semiconductor testing structure adopts the semiconductor testing structure described in this invention; Step S22, applying voltage to the first pad, the second pad, the third pad and the fourth pad using preset rules to test the resistance of the electric fuse and test the performance of the transistor.

[0023] Please refer to Figure 1 And in step S21, a semiconductor test structure is provided, wherein the semiconductor test structure adopts the present invention. Figure 1 The semiconductor test structure shown. Figure 1 The semiconductor test structure shown enables in-line monitoring of the electric fuse programming performance and transistor performance during wafer manufacturing. Furthermore, by optimizing the programming circuit layout, fewer pads are used, resulting in lower costs. At the same time, the area of ​​the semiconductor test structure can be reduced, saving wafer space.

[0024] Please refer to Figure 1 And in step S22, voltages are applied to the first pad 141, the second pad 142, the third pad 143 and the fourth pad 144 using preset rules to test the resistance of the electric fuse 12 and the performance of the transistor 11.

[0025] In some embodiments, the method further includes the step of applying a programming voltage to the first pad 141, the second pad 142, and the fourth pad 144 to program the electric fuse 12.

[0026] In some embodiments, the preset rules include: applying a test voltage to the second pad 142 and the third pad 143 before programming to test the resistance of the electric fuse 12, and applying a test voltage to the first pad 141, the third pad 143 and the fourth pad 144 to test the performance of the transistor 11; and / or applying a test voltage to the second pad 142 and the third pad 143 after programming to test the resistance of the electric fuse 12, and applying a test voltage to the first pad 141, the third pad 143 and the fourth pad 144 to test the performance of the transistor 11.

[0027] In some embodiments, the performance of transistor 11 is the threshold voltage or saturation current of transistor 11.

[0028] Specifically, in this embodiment, before programming, a test voltage of 0.2V to 0.5V is applied to the second pad 142, and a ground voltage is applied to the third pad 143. The current at the third pad 143 is then measured to test the resistance of the fuse 12. The current at the third pad 143 is controlled within the range of 1μA to 1mA to obtain an accurate resistance of the fuse 12. By monitoring the resistance of the fuse 12 in-line during wafer fabrication, the process can be quickly adjusted, improving the flexibility of testing.

[0029] Furthermore, before programming, a test voltage of 2V to 2.5V is applied to the first pad 141, a test voltage of 2V to 2.5V is applied to the fourth pad 144, and a ground voltage is applied to the third pad 143. The current at the third pad 143 is then measured to test the performance of the transistor 11. In this embodiment, the voltages applied to the first pad 141 and the fourth pad 144 are equal.

[0030] After testing the resistance of the fuse 12 and the performance of the transistor 11, the fuse 12 is programmed. In some embodiments, the fuse 12 reaches a predetermined resistance state after programming. The predetermined resistance state is the required resistance value or shape set according to the programming purpose. In this embodiment, the predetermined resistance state is a preset resistance value. Specifically, a programming voltage of 2V to 2.5V is applied to the second pad 142, a programming voltage of 2V to 2.5V is applied to the fourth pad 144, and a ground voltage is applied to the first pad 141, so that a predetermined current passes through the fuse 12, causing self-aligned silicide electromigration or silicon melting inside the fuse 12, increasing the resistance value of the fuse 12. The fuse 12 is programmed until its resistance value reaches the preset resistance value, thereby writing information onto the fuse 12 (i.e., programming). The resistance state of the electric fuse 12 before programming is taken as information "0", and the resistance state of the electric fuse 12 after programming is taken as information "1".

[0031] After programming, a test voltage of 0.2V to 0.5V is applied to the second pad 142, and a ground voltage is applied to the third pad 143. The current at the third pad 143 is measured to test the resistance of the programmed fuse 12. The current at the third pad 143 is controlled within the range of 1μA to 1mA to obtain the accurate resistance of the programmed fuse 12. If the difference between the resistance of the programmed fuse 12 and the preset resistance value is less than a preset threshold, the programmed fuse 12 is determined to meet the process requirements. If the difference between the resistance of the programmed fuse 12 and the preset resistance value is greater than the preset threshold, the programmed fuse 12 is determined to not meet the process requirements, and further adjustment of process parameters is needed to improve the process.

[0032] Furthermore, after programming, a test voltage of 2V to 2.5V is applied to the first pad 141, a test voltage of 2V to 2.5V is applied to the fourth pad 144, and a ground voltage is applied to the third pad 143. The current at the third pad 143 is then measured to test the performance of the programmed transistor 11. In this embodiment, the voltages applied to the first pad 141 and the fourth pad 144 are equal.

[0033] In theory, the performance of the programmed transistor 11 should be consistent with that of the unprogrammed transistor 11. If the performance of the programmed transistor 11 differs significantly from that of the unprogrammed transistor 11, the programming process parameters need to be adjusted to meet the process requirements.

[0034] The above technical solution, by placing the semiconductor test structure on the wafer dicing track and connecting the fuse and transistor to the pads respectively, allows for simultaneous in-line monitoring of the fuse resistance and transistor performance during wafer manufacturing, enabling rapid process adjustments and improved process flexibility. By using multiple pads to separate the programming circuit and the fuse and transistor, it facilitates variable control and allows for individual component performance testing, improving testing flexibility and accuracy. The semiconductor test structure shorts the drain, substrate, and the first end of the fuse to the same pad, reducing the number of pads in the semiconductor test, optimizing the circuit layout, and thus reducing the area of ​​the semiconductor test structure, saving wafer space.

[0035] It should be noted that references to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0036] Generally, terms can be understood at least partially from their usage in context. For example, the term "one or more," as used herein, depends at least partially on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or in a plural sense, to describe a combination of features, structures, or characteristics. Similarly, terms such as "a," "a," or "the" can also be understood, at least partially on the context, to express either a singular or plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather, alternatively, also at least partially on the context, to allow for the presence of other factors that are not necessarily explicitly described. It should also be noted in this specification that "connection / coupling" refers not only to a direct coupling of one component to another, but also to an indirect coupling of one component to another via an intermediate component.

[0037] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context. It should be understood that such data used interchangeably where appropriate. Furthermore, embodiments and features within embodiments of this invention can be combined with each other unless otherwise specified. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar or identical parts between embodiments can be referred to interchangeably.

[0038] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A semiconductor testing structure, characterized in that, The semiconductor test structure is disposed on a dicing track of a wafer and includes: a transistor, comprising a substrate, a source, a drain, and a gate; and an electric fuse, comprising a first end and a second end. The source is electrically connected to a first pad via a first metal line, the second end of the electric fuse is electrically connected to a second pad via a second metal line, the drain, the substrate, and the first end of the electric fuse are respectively electrically connected to a third pad via corresponding third metal lines, and the gate is electrically connected to a fourth pad via a fourth metal line. Voltages are applied to the first, second, third, and fourth pads using a preset rule to test the resistance of the electric fuse and the performance of the transistor. After testing the resistance of the electric fuse and the performance of the transistor, the electric fuse can be programmed by applying a programming voltage to the first, second, and fourth pads.

2. The semiconductor test structure according to claim 1, characterized in that, The preset rules include: before programming, applying a test voltage to the second pad and the third pad to test the resistance of the fuse, and applying a test voltage to the first pad, the third pad and the fourth pad to test the performance of the transistor; and / or after programming, applying a test voltage to the second pad and the third pad to test the resistance of the fuse, and applying a test voltage to the first pad, the third pad and the fourth pad to test the performance of the transistor.

3. The semiconductor test structure according to claim 1, characterized in that, The electric fuse reaches a predetermined resistance state after being programmed.

4. The semiconductor test structure according to claim 1, characterized in that, The first metal line, the second metal line, the third metal line, and the fourth metal line are patterned from the same metal layer.

5. The semiconductor test structure according to claim 1, characterized in that, The material of the electric fuse is polycrystalline silicon.

6. A semiconductor testing method, characterized in that, The method includes the following steps: providing a semiconductor test structure, wherein the semiconductor test structure adopts the semiconductor test structure as described in claim 1; applying voltages to the first pad, the second pad, the third pad, and the fourth pad using preset rules to test the resistance of the electric fuse and the performance of the transistor; and applying programming voltages to the first pad, the second pad, and the fourth pad to program the electric fuse.

7. The method according to claim 6, characterized in that, The preset rules include: before programming, applying test voltages to the second and third pads to test the resistance of the fuse, and applying test voltages to the first, third, and fourth pads to test the performance of the transistor; and / or after programming, applying test voltages to the second and third pads to test the resistance of the fuse, and applying test voltages to the first, third, and fourth pads to test the performance of the transistor.

8. The method according to claim 6, characterized in that, The electric fuse reaches a predetermined resistance state after being programmed.

9. The method according to claim 6, characterized in that, The performance of the transistor is its threshold voltage or saturation current.

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