Electric fuse storage unit and storage array
By designing elongated polysilicon fuses and parallel MOS transistors within the same active region, the problems of large layout area and uneven programming were solved, achieving area reduction and improved programming reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUALI INTEGRATED CIRCUIT CORP
- Filing Date
- 2024-11-07
- Publication Date
- 2026-05-08
AI Technical Summary
Existing electric fuse memory cells have a large layout area, and the MOS control transistor occupies the majority of the area, making it difficult to effectively reduce the area of the memory array. At the same time, the electromigration is uneven and the reliability is insufficient during programming.
The control transistor and fuse are formed in the same active region. A long strip polysilicon fuse is used in the parallel MOS transistor design. The fuse and the heavily doped drain region of the control transistor are aligned in the same direction. The metal layer is shorted through contact holes to form a centrally symmetrical pair of memory cells, reducing the layout area.
It significantly reduces the layout area of the electric fuse memory cell, improves the reliability and uniformity of programming, and ensures high reliability after programming, while also being easy to manufacture and control.
Smart Images
Figure CN122002803A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to semiconductor manufacturing technology, and in particular to an electronic fuse (efuse) memory cell and memory array. Background Technology
[0002] Most eFuse memory cell structures consist of a fuse and a MOS control transistor. It is based on electromigration (EM), which uses the principle of electromigration to achieve highly reliable on-chip programming by blowing the fuse.
[0003] Area is one of the main design specifications for eFuse memory. In a conventional eFuse memory layout, the eFuse cell array area is composed of combined eFuse cells, meaning it's made up of individual eFuse cell layouts. This cell array area occupies a large portion of the overall memory chip area. The area of an eFuse memory chip is primarily determined by the array of eFuse cells, with the MOS transistors occupying a significant portion of the total eFuse cell area. The MOS transistors are the core factor determining the overall area of the eFuse cell array. Improving the eFuse cell layout is one effective way to reduce the memory chip area.
[0004] The layout dimensions of an efuse memory cell using a metal fuse are as follows: Figure 1 As shown, this eFuse memory cell uses a 28nm high dielectric constant (HK) process and has an area of 14.4µm². The eFuse cell structure includes a MOS control transistor 103 and a fuse 104. The MOS control transistor 103 is typically an NMOS transistor and is located in the NMOS region. The fuse 104 is located in the fuse region. Figure 1 In the diagram, the dashed lines in the fuse area illustrate the structure of fuse 104. Fuse 104 consists of pads formed by two metal layers and a metal wire connecting the two pads. During programming, the metal wire is melted by applying voltage between the two pads via an EM (Electromagnetic Electromagnetic) method. Figure 2 In the existing efuse memory cell structure shown, the area of the MOS control transistor 103 occupies most of the entire memory cell area, which is the main area in the efuse memory cell layout. The MOS control transistor 103 is the core factor that determines the overall area of the efuse memory. Summary of the Invention
[0005] The technical problem to be solved by this invention is to reduce the layout area of the storage array, make it easy to manufacture and control the quality, ensure uniform and controllable electromigration during programming, and achieve high reliability after programming.
[0006] To solve the above-mentioned technical problems, the present invention provides an electric fuse storage unit, which includes a control transistor 1 composed of MOS transistors and a fuse 2;
[0007] The control tube 1 and the fuse 2 are formed in the same active region;
[0008] The fuse 2 is a long strip of polycrystalline silicon fuse, located on side A of the control tube 1; A can be left or right.
[0009] The source-end heavily doped region 207, the drain-end heavily doped region 208 of each MOS transistor of the control tube 1 and the fuse 2 are all in the front-back direction.
[0010] The front and rear ends of the heavily doped source region 207 and the heavily doped drain region 208 of each MOS transistor are aligned respectively;
[0011] The top of the heavily doped source region 207 of each MOS transistor is shorted to the source metal S formed on the first metal layer M1 through the contact hole 205;
[0012] The top of the heavily doped drain region 208 of each MOS transistor is shorted to the drain metal D formed on the second metal layer M2 through the contact hole 205;
[0013] The gate structure 206 of each MOS transistor is shorted to the word line metal W formed on the second metal layer M2 through the contact hole 205;
[0014] One end of the fuse 2 is shorted to the front or rear end of the heavily doped drain region 208 of the MOS transistor that forms the A-side of the control transistor 1, and the other end is located at the middle A-side of the drain region 208 in the front-back direction of the MOS transistor that forms the A-side of the control transistor 1, and is shorted to the bit line metal BL formed on the third metal layer M3 through the contact hole 205.
[0015] Preferably, the front or rear end of the heavily doped drain region 208 of the MOS transistor that forms the A-side of the control tube 1 extends towards the A-side in an L-shape.
[0016] The A side of the fuse 2 is aligned with the A side of the protruding portion of the front or rear end of the heavily doped region 208 of the drain terminal of the MOS transistor that constitutes the A side of the control tube 1.
[0017] Preferably, the source-side heavily doped region 207 and the drain-side heavily doped region 208 of each MOS transistor are self-aligned and formed in the active regions on the left and right sides of its gate structure 206.
[0018] The source-side heavily doped region 207, the drain-side heavily doped region 208, and the gate structure 206 of each MOS transistor are all elongated strips in the front-to-back direction.
[0019] Preferably, the gate structure 206 includes a gate dielectric layer and a gate polysilicon layer stacked sequentially.
[0020] The gate dielectric layer is made of a high dielectric constant material or silicon dioxide.
[0021] Preferably, the control transistor 1 is composed of N MOS transistors connected in parallel, where N is an integer greater than 1;
[0022] The gate structures 206 of each MOS transistor are arranged in a long strip shape in the front-to-back direction;
[0023] The source-end heavily doped region 207 or the drain-end heavily doped region 208 located between the two gate structures 206 are shared by two adjacent MOS transistor units.
[0024] Preferably, N is 2, 3, 4 or 5.
[0025] Preferably, the MOS transistor is an NMOS transistor.
[0026] To solve the above-mentioned technical problems, the present invention also provides an electric fuse storage array composed of the electric fuse storage units, which includes multiple storage unit pairs 4;
[0027] Each storage cell pair 4 includes a left-side fuse storage cell 41 and a right-side fuse storage cell 42;
[0028] The fuse 2 of the left-side electric fuse storage cell 41 is located on the left side of the control transistor 1. One end of the fuse 2 is short-connected to the front end of the heavily doped drain region 208 of the leftmost MOS transistor that makes up the control transistor 1, and the other end is located on the left side of the middle of the front-back direction of the heavily doped drain region 208 of the leftmost MOS transistor that makes up the control transistor 1.
[0029] The fuse 2 of the right-side electric fuse storage cell 42 is located on the right side of the control transistor 1. One end of the fuse 2 is short-connected to the rear end of the heavily doped drain region 208 of the rightmost MOS transistor that makes up the control transistor 1, and the other end is located on the right side of the middle of the front-back direction of the heavily doped drain region 208 of the rightmost MOS transistor that makes up the control transistor 1.
[0030] The fuse 2 of the left-side electric fuse storage unit 41 and the fuse 2 of the right-side electric fuse storage unit 42 are connected as one unit in the front-back direction.
[0031] Preferably, the middle connection of the fuse 2 of the left and right electric fuse memory cells in the memory cell pair is shorted to the bit line metal BL formed on the third metal layer M3 through the corresponding contact hole 205.
[0032] Each gate structure 206 of the left-side electric fuse memory cell is shorted to the first word line metal W1 formed on the second metal layer M2 through the corresponding contact hole 205;
[0033] Each gate structure 206 of the right-side electric fuse memory cell is shorted to the second word line metal W2 formed on the second metal layer M2 through the corresponding contact hole 205;
[0034] The top of the heavily doped drain region 208 of each MOS transistor in the left-side electric fuse memory cell is shorted to the first drain metal D1 formed on the second metal layer M2 through the contact hole 205.
[0035] The top of the heavily doped drain region 208 of each MOS transistor in the right-side electric fuse memory cell is shorted to the second drain metal D2 formed on the second metal layer M2 through the contact hole 205.
[0036] The top of the heavily doped region 207 of the source end of each MOS transistor in the left-side electric fuse memory cell is shorted to the first source metal S1 formed on the first metal layer M1 through the contact hole 205.
[0037] The top of the heavily doped source region 207 of each MOS transistor in the right-side electric fuse storage cell is shorted to the second source metal S2 formed on the first metal layer M1 through the contact hole 205.
[0038] Preferably, in the layout, the first drain metal D1 is divided into a front end first drain metal D1 and a rear end first drain metal D1;
[0039] The second drain metal D2 is divided into a front end second drain metal D2 and a rear end second drain metal D2;
[0040] The first drain metal D1 at the front end is located directly above the front end of the heavily doped drain region 208 of the left-side electric fuse memory cell. The first drain metal D1 at the front end is short-circuited to the front end of the heavily doped drain region 208 of the left-side electric fuse memory cell through a vertical contact hole.
[0041] The first drain metal D1 at the rear end is located directly above the rear end of the heavily doped drain region 208 of the left-side electric fuse storage cell. The first drain metal D1 at the rear end is short-circuited to the rear end of the heavily doped drain region 208 of the left-side electric fuse storage cell through a vertical contact hole.
[0042] The second drain metal D2 at the front end is located directly above the front end of the heavily doped drain region 208 of the right-side electric fuse storage cell. The second drain metal D2 at the front end is short-circuited to the front end of the heavily doped drain region 208 of the right-side electric fuse storage cell through a vertical contact hole.
[0043] The second drain metal D2 at the rear end is located directly above the rear end of the heavily doped drain region 208 of the right-side electric fuse storage cell. The second drain metal D2 at the rear end is short-circuited to the rear end of the heavily doped drain region 208 of the right-side electric fuse storage cell through a vertical contact hole.
[0044] The first source metal S1 is located directly above the middle of the heavily doped drain region 208 of the left-side electric fuse memory cell. The first source metal S1 is short-circuited to the middle of the heavily doped drain region 208 of the left-side electric fuse memory cell through a vertical contact hole.
[0045] The second source metal S2 is located directly above the middle of the heavily doped drain region 208 of the right-side electric fuse memory cell. The second source metal S2 is short-circuited to the middle of the heavily doped drain region 208 of the right-side electric fuse memory cell through a vertical contact hole.
[0046] The word line metal W and the bit line metal BL are perpendicular;
[0047] The word line metal W, drain metal D, and source metal S are arranged in parallel.
[0048] The left and right center lines of the first drain metal D1 and the second drain metal D2 are on the same straight line and are spaced apart.
[0049] The left and right center lines of the first drain metal D1 and the second drain metal D2 at the rear end are on the same straight line and are spaced apart on the left and right.
[0050] The vertical projections of the second word line metal W2, the front first drain metal D1, the first source metal S1, the rear first drain metal D1, and the first word line metal W1 are arranged in parallel from front to back.
[0051] The vertical projections of the second word line metal W2, the front second drain metal D2, the second source metal S2, the rear second drain metal D2, and the first word line metal W1 are arranged in parallel from front to back.
[0052] The electronic fuse (efuse) memory cell of this invention has two states: on and off. When the efuse memory cell structure is in its initial state, fuse 2 is in the on state; when the efuse memory cell structure is in the programming state, fuse 2 is in the off state. In this electronic fuse memory cell, the control transistor 1 and the polysilicon fuse 2 are formed in the same active area (AA). The elongated polysilicon fuse 2 is located on one side of the MOS control transistor, and one end is short-circuited to one end of the heavily doped drain region 208 of the nearest MOS control transistor. This significantly reduces the area of the electronic fuse memory cell and facilitates the direct combination and layout of memory cell pairs in a centrally symmetrical manner to form a memory cell array. This reduces the idle area in the layout of the memory array formed by the electronic fuse memory cells, thereby reducing the layout area of the memory array and significantly improving the layout efficiency of the memory array formed by the electronic fuse memory cells. In practice, the actual layout area of this electronic fuse memory cell can be reduced to less than 20% of the layout area of a conventional electronic fuse memory cell. In addition, using long strip polycrystalline silicon as fuse 2 is easy to manufacture and easy to control the quality. During programming, electromigration is uniform and controllable, and the reliability is high after programming is completed. Attached Figure Description
[0053] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0054] Figure 1 This is a schematic diagram of the layout area and dimensions of a fuse storage cell for a given metal fuse.
[0055] Figure 2 This is a schematic diagram of the polysilicon layer layout structure of an embodiment of the fuse memory cell of the present invention;
[0056] Figure 3 This is a schematic diagram of the polysilicon layer layout structure of a pair of memory cells in an embodiment of a memory array composed of fuse memory cells according to the present invention.
[0057] Figure 4 This is a schematic diagram of the polysilicon layer layout structure of a pair of memory cells in an embodiment of a memory array composed of fuse memory cells according to the present invention.
[0058] Figure 5 Is Figure 4 A schematic diagram of a layout structure with a metal layer superimposed on top of the existing structure;
[0059] Figure 6 yes Figure 5The diagram shows the equivalent circuit diagram of the memory cell layout.
[0060] Explanation of the reference numerals in the figure:
[0061] 1. Control transistor; 2. Fuse; 207. Source heavily doped region; 208. Drain heavily doped region; 205. Contact hole; 206. Gate structure; 4. Memory cell pair; 41. Left fuse memory cell; 42. Right fuse memory cell. Detailed Implementation
[0062] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0063] Example 1
[0064] like Figure 2 As shown, the electronic fuse (efuse) memory cell includes a control transistor 1 composed of MOS transistors and a fuse 2;
[0065] The control tube 1 and the fuse 2 are formed in the same active area (AA);
[0066] The fuse 2 is a long strip of polycrystalline silicon fuse, located on side A of the control tube 1; A can be left or right.
[0067] The source-end heavily doped region 207, the drain-end heavily doped region 208 of each MOS transistor of the control tube 1 and the fuse 2 are all in the front-back direction.
[0068] The front and rear ends of the heavily doped source region 207 and the heavily doped drain region 208 of each MOS transistor are aligned respectively;
[0069] The top of the heavily doped source region 207 of each MOS transistor is shorted to the source metal S formed on the first metal layer M1 through the contact hole 205;
[0070] The top of the heavily doped drain region 208 of each MOS transistor is shorted to the drain metal D formed on the second metal layer M2 through the contact hole 205;
[0071] The gate structure 206 of each MOS transistor is shorted to the word line metal W formed on the second metal layer M2 through the contact hole 205;
[0072] One end of the fuse 2 is shorted to the front or rear end of the heavily doped drain region 208 of the MOS transistor that forms the A-side of the control transistor 1, and the other end is located at the middle A-side of the drain region 208 in the front-back direction of the MOS transistor that forms the A-side of the control transistor 1, and is shorted to the bit line metal BL formed on the third metal layer M3 through the contact hole 205.
[0073] In the electronic fuse (efuse) memory cell of Embodiment 1, fuse 2 has two states: on and off. When the efuse memory cell structure is in its initial state, fuse 2 is in the on state; when the efuse memory cell structure is in the programming state, fuse 2 is in the off state. In this electronic fuse memory cell, the control transistor 1 and the polysilicon fuse 2 are formed in the same active area (AA). The elongated polysilicon fuse 2 is located on one side of the MOS control transistor, and one end is shorted to one end of the heavily doped drain region 208 of the nearest MOS control transistor. This significantly reduces the area of the electronic fuse memory cell and facilitates the direct combination and layout of memory cells in a centrally symmetrical manner to form a memory cell array. This reduces the idle area in the layout of the memory array composed of this electronic fuse memory cell, thereby reducing the layout area of the memory array and significantly improving the layout efficiency of the memory array composed of this electronic fuse memory cell. In practice, the actual layout area of this electronic fuse memory cell can be reduced to less than 20% of the layout area of a conventional electronic fuse memory cell. In addition, using long strip polycrystalline silicon as fuse 2 is easy to manufacture and easy to control the quality. During programming, electromigration is uniform and controllable, and the reliability is high after programming is completed.
[0074] Example 2
[0075] Based on the electronic fuse memory cell of Embodiment 1, the front or rear end of the heavily doped region 208 of the drain end of the MOS transistor that makes up the A side of the control tube 1 extends out to the A side in an L-shape.
[0076] The A side of the fuse 2 is aligned with the A side of the protruding portion of the front or rear end of the heavily doped region 208 of the drain terminal of the MOS transistor that constitutes the A side of the control tube 1.
[0077] Example 3
[0078] Based on the electric fuse memory cell of Embodiment 1, the source-end heavily doped region 207 and the drain-end heavily doped region 208 of each MOS transistor are self-aligned and formed in the active regions on the left and right sides of its gate structure 206.
[0079] The source-side heavily doped region 207, the drain-side heavily doped region 208, and the gate structure 206 of each MOS transistor are all elongated strips in the front-to-back direction.
[0080] Preferably, the gate structure 206 includes a gate dielectric layer and a gate polysilicon layer stacked sequentially.
[0081] Preferably, the gate dielectric layer is made of a high dielectric constant material.
[0082] Preferably, the gate dielectric layer is made of silicon dioxide.
[0083] Example 4
[0084] Based on the electric fuse storage unit of Embodiment 1, the control tube 1 is composed of N MOS transistors connected in parallel, where N is an integer greater than 1;
[0085] The gate structures 206 of each MOS transistor are arranged in a long strip shape in the front-to-back direction;
[0086] The source-end heavily doped region 207 or the drain-end heavily doped region 208 located between the two gate structures 206 are shared by two adjacent MOS transistor units.
[0087] Preferably, N is 2, 3, 4 or 5.
[0088] Figure 2 The image shows three MOS transistors, each corresponding to a gate structure 206, for a total of three gate structures 206. It also features two heavily doped source regions 207 and two heavily doped drain regions 208, from left to right: heavily doped source region 207, heavily doped drain region 208, and heavily doped drain region 208. The front end of the rightmost heavily doped drain region 208 is short-circuited to the front end of the fuse 2, and the rear end of the fuse 2 is located to the right of the center of the rightmost heavily doped drain region 208 in the front-back direction.
[0089] Preferably, the MOS transistor is an NMOS transistor. The equivalent circuit of the fuse memory cell is as follows: Figure 3 As shown, the fuse memory cell has three electrode ports for connection to external circuits: a source port, a word line port, and a bit line port. The drain metal D shorted at the top of the heavily doped drain region 208 of each MOS transistor does not directly form a port for connection to the outside; if the fuse 2 is in the on state, the drain metal D shorted at the top of the heavily doped drain region 208 of the MOS transistor will be connected to the external bit line port.
[0090] Example 5
[0091] An electric fuse storage array, composed of electric fuse storage units from Examples 1 to 4, includes multiple storage unit pairs 4;
[0092] like Figure 4As shown, each storage cell pair 4 includes a left-side electric fuse storage cell 41 and a right-side electric fuse storage cell 42;
[0093] The fuse 2 of the left-side electric fuse storage cell 41 is located on the left side of the control transistor 1. One end of the fuse 2 is short-connected to the front end of the heavily doped drain region 208 of the leftmost MOS transistor that makes up the control transistor 1, and the other end is located on the left side of the middle of the front-back direction of the heavily doped drain region 208 of the leftmost MOS transistor that makes up the control transistor 1.
[0094] The fuse 2 of the right-side electric fuse storage cell 42 is located on the right side of the control transistor 1. One end of the fuse 2 is short-connected to the rear end of the heavily doped drain region 208 of the rightmost MOS transistor that makes up the control transistor 1, and the other end is located on the right side of the middle of the front-back direction of the heavily doped drain region 208 of the rightmost MOS transistor that makes up the control transistor 1.
[0095] The fuse 2 of the left-side electric fuse storage unit 41 and the fuse 2 of the right-side electric fuse storage unit 42 are connected as one unit in the front-back direction.
[0096] The electric fuse storage array of Embodiment 5 is composed of multiple storage cell pairs 4 arranged repeatedly. On the layout, the left and right electric fuse storage cells of the storage cell pair are centrally symmetrical. The fuses 2 of the left and right electric fuse storage cells in the storage cell pair are connected in the front-back direction to form a long strip area in the front-back direction of the shared active area, which can effectively save the layout area.
[0097] Example 6
[0098] Based on the electric fuse storage array of Embodiment 5, such as Figure 5 As shown ( Figure 5 Is Figure 4 (Based on the layout with a metal layer superimposed), the middle connection of the fuse 2 of the left and right electric fuses of the memory cell is shorted to the bit line metal BL formed on the third metal layer M3 through the corresponding contact hole 205.
[0099] Each gate structure 206 of the left-side electric fuse memory cell is shorted to the first word line metal W1 formed on the second metal layer M2 through the corresponding contact hole 205;
[0100] Each gate structure 206 of the right-side electric fuse memory cell is shorted to the second word line metal W2 formed on the second metal layer M2 through the corresponding contact hole 205;
[0101] The top of the heavily doped drain region 208 of each MOS transistor in the left-side electric fuse memory cell is shorted to the first drain metal D1 formed on the second metal layer M2 through the contact hole 205.
[0102] The top of the heavily doped drain region 208 of each MOS transistor in the right-side electric fuse memory cell is shorted to the second drain metal D2 formed on the second metal layer M2 through the contact hole 205.
[0103] The top of the heavily doped region 207 of the source end of each MOS transistor in the left-side electric fuse memory cell is shorted to the first source metal S1 formed on the first metal layer M1 through the contact hole 205.
[0104] The top of the heavily doped source region 207 of each MOS transistor in the right-side electric fuse storage cell is shorted to the second source metal S2 formed on the first metal layer M1 through the contact hole 205.
[0105] Preferably, in the layout, the first drain metal D1 is divided into a front end first drain metal D1 and a rear end first drain metal D1;
[0106] The second drain metal D2 is divided into a front end second drain metal D2 and a rear end second drain metal D2;
[0107] The first drain metal D1 at the front end is located directly above the front end of the heavily doped drain region 208 of the left-side electric fuse memory cell. The first drain metal D1 at the front end is short-circuited to the front end of the heavily doped drain region 208 of the left-side electric fuse memory cell through a vertical contact hole.
[0108] The first drain metal D1 at the rear end is located directly above the rear end of the heavily doped drain region 208 of the left-side electric fuse storage cell. The first drain metal D1 at the rear end is short-circuited to the rear end of the heavily doped drain region 208 of the left-side electric fuse storage cell through a vertical contact hole.
[0109] The second drain metal D2 at the front end is located directly above the front end of the heavily doped drain region 208 of the right-side electric fuse storage cell. The second drain metal D2 at the front end is short-circuited to the front end of the heavily doped drain region 208 of the right-side electric fuse storage cell through a vertical contact hole.
[0110] The second drain metal D2 at the rear end is located directly above the rear end of the heavily doped drain region 208 of the right-side electric fuse storage cell. The second drain metal D2 at the rear end is short-circuited to the rear end of the heavily doped drain region 208 of the right-side electric fuse storage cell through a vertical contact hole.
[0111] The first source metal S1 is located directly above the middle of the heavily doped drain region 208 of the left-side electric fuse memory cell. The first source metal S1 is short-circuited to the middle of the heavily doped drain region 208 of the left-side electric fuse memory cell through a vertical contact hole.
[0112] The second source metal S2 is located directly above the middle of the heavily doped drain region 208 of the right-side electric fuse memory cell. The second source metal S2 is short-circuited to the middle of the heavily doped drain region 208 of the right-side electric fuse memory cell through a vertical contact hole.
[0113] The word line metal W and the bit line metal BL are perpendicular;
[0114] The word line metal W, drain metal D, and source metal S are arranged in parallel.
[0115] The left and right center lines of the first drain metal D1 and the second drain metal D2 are on the same straight line and are spaced apart.
[0116] The left and right center lines of the first drain metal D1 and the second drain metal D2 at the rear end are on the same straight line and are spaced apart on the left and right.
[0117] The vertical projections of the second word line metal W2, the front first drain metal D1, the first source metal S1, the rear first drain metal D1, and the first word line metal W1 are arranged in parallel from front to back.
[0118] The vertical projections of the second word line metal W2, the front second drain metal D2, the second source metal S2, the rear second drain metal D2, and the first word line metal W1 are arranged in parallel from front to back.
[0119] Figure 5 The equivalent circuit of the storage cell pair shown is as follows: Figure 6 As shown.
[0120] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. An electric fuse storage unit, characterized in that, It includes a control transistor (1) composed of MOS transistors and a fuse (2); The control tube and the fuse (2) are formed in the same active region; The fuse (2) is a long strip of polycrystalline silicon fuse, located on side A of the control tube (1); A is either left or right. The source-end heavily doped region (207), drain-end heavily doped region (208), and fuse (2) of each MOS transistor of the control tube (1) are all in the front-back direction; The front and rear ends of the heavily doped source region (207) and heavily doped drain region (208) of each MOS transistor are aligned respectively; The top of the heavily doped region (207) at the source end of each MOS transistor is shorted to the source metal formed on the first metal layer through a contact hole (205); The top of the heavily doped drain region (208) of each MOS transistor is shorted to the drain metal formed on the second metal layer through a contact hole (205); The gate structure (206) of each MOS transistor is shorted to the word line metal formed on the second metal layer through the contact hole (205); One end of the fuse (2) is shorted to the front or rear end of the heavily doped drain region (208) of the MOS transistor that forms the A side of the control tube (1), and the other end is located at the middle A side of the heavily doped drain region (208) of the MOS transistor that forms the A side of the control tube (1) in the front-back direction, and is shorted to the bit line metal formed on the third metal layer through the contact hole (205).
2. The electric fuse storage unit according to claim 1, characterized in that, The front or rear end of the heavily doped drain region (208) of the MOS transistor that makes up the A side of the control tube (1) extends out to the A side in an L-shape. The A side of the fuse (2) is aligned with the A side of the protruding portion of the front or rear end of the heavily doped region (208) of the drain terminal of the MOS transistor that constitutes the A side of the control tube (1).
3. The electric fuse storage unit according to claim 1, characterized in that, The source-end heavily doped region (207) and drain-end heavily doped region (208) of each MOS transistor are self-aligned and formed in the active regions on the left and right sides of its gate structure (206); The source-side heavily doped region (207), drain-side heavily doped region (208), and gate structure (206) of each MOS transistor are all elongated strips in the front-to-back direction.
4. The electric fuse storage unit according to claim 1, characterized in that, The gate structure (206) includes a gate dielectric layer and a gate polysilicon layer stacked sequentially; The gate dielectric layer is made of a high dielectric constant material or silicon dioxide.
5. The electric fuse storage unit according to claim 1, characterized in that, The control transistor (1) is composed of N MOS transistors connected in parallel, where N is an integer greater than 1; The gate structure (206) of each MOS transistor is arranged in a long strip shape in the front-to-back direction; The source-end heavily doped region (207) or drain-end heavily doped region (208) located between the two gate structures (206) is shared by two adjacent MOS transistor units.
6. The electric fuse storage unit according to claim 5, characterized in that, N is 2, 3, 4 or 5.
7. The electric fuse storage unit according to claim 1, characterized in that, The MOS transistor is an NMOS transistor.
8. An electric fuse storage array composed of electric fuse storage units as described in any one of claims 1 to 7, characterized in that, Includes multiple storage unit pairs (4); Each storage cell pair (4) includes a left-side fuse storage cell (41) and a right-side fuse storage cell (42); The fuse (2) of the left-side electric fuse storage cell (41) is located on the left side of the control tube (1). One end of the fuse (2) is short-connected to the front end of the heavily doped drain region (208) of the leftmost MOS transistor that makes up the control tube (1), and the other end is located on the left side of the middle of the front-back direction of the heavily doped drain region (208) of the leftmost MOS transistor that makes up the control tube (1). The fuse (2) of the right-side electric fuse storage cell (42) is located on the right side of the control tube (1). One end of the fuse (2) is short-connected to the rear end of the drain heavily doped region (208) of the rightmost MOS transistor that makes up the control tube (1), and the other end is located on the right side of the middle of the drain heavily doped region (208) of the rightmost MOS transistor that makes up the control tube (1). The fuse (2) of the left-side electric fuse storage unit (41) and the fuse (2) of the right-side electric fuse storage unit (42) are connected as one unit in the front-back direction.
9. The electro-fuse storage array according to claim 8, characterized in that, The fuses (2) of the left and right electric fuses in the memory cell pair are shorted to the bit line metal formed on the third metal layer through the corresponding contact hole (205) at the middle connection point; Each gate structure (206) of the left-side electric fuse memory cell is shorted to the first word line metal formed on the second metal layer through the corresponding contact hole (205); Each gate structure (206) of the right-side electric fuse memory cell is shorted to the second word line metal formed on the second metal layer through the corresponding contact hole (205); The top of the heavily doped drain region (208) of each MOS transistor in the left-side electric fuse memory cell is shorted to the first drain metal formed on the second metal layer through a contact hole (205); The top of the heavily doped region (208) at the drain end of each MOS transistor in the right-side electric fuse memory cell is shorted to the second drain metal formed on the second metal layer through the contact hole (205); The top of the heavily doped region (207) of the source end of each MOS transistor in the left-side electric fuse storage cell is shorted to the first source metal formed on the first metal layer through the contact hole (205); The top of the heavily doped region (207) of the source end of each MOS transistor in the right-side electric fuse storage cell is shorted to the second source metal formed on the first metal layer through the contact hole (205).
10. The electrofused fuse storage array according to claim 9, characterized in that, On the layout, the first drain metal is divided into a front end first drain metal and a rear end first drain metal; The second drain metal is divided into a front-end second drain metal and a rear-end second drain metal; The first drain metal at the front end is located directly above the front end of the heavily doped drain region (208) of the left-side electric fuse storage cell. The first drain metal at the front end is short-circuited to the front end of the heavily doped drain region (208) of the left-side electric fuse storage cell through a vertical contact hole. The first drain metal at the rear end is located directly above the rear end of the heavily doped drain region (208) of the left-side electric fuse storage cell. The first drain metal at the rear end is short-circuited to the rear end of the heavily doped drain region (208) of the left-side electric fuse storage cell through a vertical contact hole. The second drain metal at the front end is located directly above the front end of the heavily doped drain region (208) of the right-side electric fuse storage cell. The second drain metal at the front end is short-circuited to the front end of the heavily doped drain region (208) of the right-side electric fuse storage cell through a vertical contact hole. The second drain metal at the rear end is located directly above the rear end of the heavily doped drain region (208) of the right-side electric fuse storage cell. The second drain metal at the rear end is short-circuited to the rear end of the heavily doped drain region (208) of the right-side electric fuse storage cell through a vertical contact hole. The first source metal is located directly above the middle of the heavily doped drain region (208) of the left-side electric fuse memory cell. The first source metal is short-circuited to the middle of the heavily doped drain region (208) of the left-side electric fuse memory cell through a vertical contact hole. The second source metal is located directly above the middle of the heavily doped drain region (208) of the right-side electric fuse memory cell. The second source metal is short-circuited to the middle of the heavily doped drain region (208) of the right-side electric fuse memory cell through a vertical contact hole. The word line metal and the bit line metal are perpendicular; The word line metal, drain metal, and source metal are arranged in parallel. The left and right center lines of the first drain metal and the second drain metal at the front end are on the same straight line and are spaced apart on the left and right. The left and right center lines of the first drain metal and the second drain metal at the rear end are on the same straight line and are spaced apart on the left and right. The vertical projections of the second word line metal, the front first drain metal, the first source metal, the rear first drain metal, and the first word line metal are arranged in parallel from front to back. The vertical projections of the second word line metal, the front second drain metal, the second source metal, the rear second drain metal, and the first word line metal are arranged in parallel from front to back.