Reconfigurable power amplifier system

Abstract

The invention relates to a reconfigurable power amplifier system. An apparatus receives a first signal from a driver. The device comprises a first circuit, a second circuit, a third circuit and a fourth circuit. The first circuit provides a second signal having a first level. The second circuit detects the first level of the first signal and provides a third signal to control a third circuit of the device. The third circuit provides a fourth signal having a first level in response to a difference being less than a predetermined value and having a second level in response to the difference being greater than the predetermined value. The fourth circuit provides a fifth signal having a first level based at least on the second signal, and the fifth signal having a second level based at least on the second signal and the fourth signal.

Description

Technical Field

[0001] The present disclosure relates to signal amplification and amplifiers. Background Art

[0002] Amplifiers may have multiple classes and amplifiers of each class may have different characteristics. Summary of the invention

[0003] In one aspect, the present disclosure relates to a system, comprising: a driver, configured to provide a first signal to indicate a first power amount, and the first signal having a first level; and a device, in communication with the driver, the device comprising: a first circuit, configured to: provide a second signal having a first level based on the first level of the first signal in response to receiving the first signal; a second circuit, configured to: detect the first level of the first signal in response to receiving the first signal; and provide a third signal to control a third circuit of the device in response to detecting the first level of the first signal, wherein the third signal is controlled by defining the third level of the device. The invention relates to a method for controlling a third circuit by controlling a difference between a first terminal and a second terminal of a circuit; the third circuit is configured to: provide a fourth signal in response to receiving the first signal and the third signal, the fourth signal having a first level in response to the difference being less than a predetermined value, and the fourth signal having a second level in response to the difference being greater than the predetermined value; and a fourth circuit is configured to: provide a fifth signal in response to receiving the second signal and the fourth signal, the fifth signal having a first level based on the first level of the second signal, and the fifth signal having a second level based on the first level of the second signal and the second level of the fourth signal.

[0004] On the other hand, the present disclosure relates to a device that communicates with a driver, the device being configured to receive a first signal from the driver, and the device comprising: a first circuit configured to: provide a second signal having a first level based at least on a first level of the first signal in response to receiving the first signal; a second circuit configured to: detect the first level of the first signal in response to receiving the first signal; and provide a third signal to control a third circuit of the device in response to detecting the first level of the first signal, wherein the third signal controls the third circuit by defining a difference between a first terminal and a second terminal of the third circuit of the device; the third circuit being configured to: provide a fourth signal in response to receiving the first signal and the third signal, the fourth signal having a first level in response to the difference being less than a predetermined value, and the fourth signal having a second level in response to the difference being greater than the predetermined value; and a fourth circuit configured to: provide a fifth signal in response to receiving the second signal and the fourth signal, the fifth signal having a first level based at least on the first level of the second signal, and the fifth signal having a second level based at least on the first level of the second signal and the second level of the fourth signal.

[0005] On the other hand, the present disclosure relates to a method, comprising: receiving, by a device, a first signal from a driver to indicate a first amount of power and the first signal having a first level; providing, by a first circuit of the device, a second signal having a first level based at least on the first level of the first signal in response to receiving the first signal; detecting, by a second circuit of the device, the first level of the first signal in response to receiving the first signal; providing, by the second circuit of the device, a third signal to control a third circuit of the device in response to detecting the first level of the first signal, wherein the third signal controls the third circuit by defining a difference between a first terminal and a second terminal of the third circuit of the device; providing, by the third circuit of the device, a fourth signal in response to receiving the first signal and the third signal, the fourth signal having a first level in response to the difference being less than a predetermined value, and the fourth signal having a second level in response to the difference being greater than the predetermined value; and providing, by the fourth circuit of the device, a fifth signal in response to receiving the second signal and the fourth signal, the fifth signal having a first level based at least on the first level of the second signal, and the fifth signal having a second level based at least on the first level of the second signal and the second level of the fourth signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various objects, aspects, features and advantages of the present disclosure will become more apparent and better understood by reference to the detailed description taken in conjunction with the accompanying drawings, wherein the same reference symbols identify corresponding elements throughout. In the drawings, the same reference symbols generally indicate the same, functionally similar and / or structurally similar elements.

[0007] Figure 1 is a block diagram of a system for configuring an amplifier according to some embodiments.

[0008] Figure 2 According to some embodiments Figure 1 Schematic block diagram of one or more components of the system described in .

[0009] Figure 3 According to some embodiments Figure 1 Schematic block diagram of one or more components of the system described in .

[0010] Figure 4 According to some embodiments Figure 1 Schematic block diagram of one or more components of the system described in .

[0011] Figure 5 According to some embodiments Figure 1 Schematic block diagram of one or more components of the system described in .

[0012] Figure 6 According to some embodiments Figure 1 Schematic block diagram of one or more components of the system described in .

[0013] Figure 7 is a schematic block diagram illustrating biasing between one or more terminals of an amplifier according to some embodiments.

[0014] Figure 8 According to some embodiments Figure 1 Schematic block diagram of one or more components of the system described in .

[0015] Fig. 9 According to some embodiments Figure 1 Schematic block diagram of one or more components of the system described in .

[0016] Fig.10 According to some embodiments Figure 1 Schematic block diagram of one or more components of the system described in .

[0017] Fig.11 According to some embodiments Figure 1 Schematic block diagram of one or more components of the system described in .

[0018] Fig.12is a block diagram of a process for configuring an amplifier according to some embodiments. DETAILED DESCRIPTION

[0019] Some embodiments relate to systems and methods for configuring a power amplifier to control the efficiency of a power amplifier system. The efficiency of a power amplifier system may include the difference between the amount of power provided to the amplifier and the amount of power provided by the amplifier. As another example, the efficiency of a power amplifier system may include the difference between a saturation amount and the amount of power provided by the amplifier. The saturation amount may refer to and / or include an amount of power that, once exceeded, does not result in any additional amplification. The saturation amount of an amplifier may affect and / or affect the efficiency of the amplifier. For example, the efficiency of an amplifier may increase as the voltage level of an input signal approaches (but does not exceed) the saturation amount. Continuing with this example, the efficiency of an amplifier may decrease as the voltage level of an input signal exceeds the saturation amount.

[0020] The amplifier is typically electrically coupled to a power supply and the power supply provides power to the amplifier. The power supply typically provides power to the amplifier at a given voltage or current level (e.g., 0.7 volts, 1 volt, 5 volts, 10 volts, 12 volts, etc.). The given voltage or current may be direct current (DC), alternating current (AC), and / or other different combinations. The voltage level or current level provided to the amplifier may affect the efficiency of the amplifier. For example, the voltage level provided to the power supply terminal of the amplifier may establish the output range of the amplifier (e.g., the output of the amplifier cannot exceed the amount of power (e.g., voltage level) provided to the amplifier from the power supply). In addition, the characteristics of the input signal may also affect the efficiency of the amplifier.

[0021] The device may include an amplifier for one or more given functions and / or implementations. For example, the antenna may include a first amplifier and a second amplifier. Continuing with this example, the first amplifier may be implemented in a wireless local area network (WLAN) system and the second amplifier may be implemented in a Bluetooth system. The saturation amount of the WLAN signal and the Bluetooth signal may be different. The WLAN signal may be associated with a larger decibel level (relative to the Bluetooth signal). For example, the WLAN signal may include a signal with a decibel amount that is 5dB (e.g., 5 decibels) greater than the Bluetooth signal. Continuing with this example, the antenna may specify and / or include space for both the first amplifier and the second amplifier. Allocating space for the first amplifier and the second amplifier may increase the overall size of the antenna. The implementation of the antenna including the first amplifier and the second amplifier may result in a trade-off between the efficiency and the overall size of the antenna. For example, the overall size of the antenna may be reduced as one of the amplifiers is removed. The efficiency of the antenna may be affected because a single amplifier is then used in the above two use cases (e.g., WLAN signal and Bluetooth).

[0022] Some technical solutions and advantages of some embodiments relate to a system including a device that can control (e.g., turn on and / or turn off) an amplifier to adjust the efficiency of the system. For example, the device can determine the voltage level of the output signal controlled by the amplifier based on the voltage level of the input signal. The device can control the efficiency of the system by turning off the amplifier (when the saturation amount of the output signal is a first level) and by turning on the amplifier (when the saturation amount of the output signal is a second level). For example, the device can receive a first signal and the device can detect that the first signal is related to a WLAN signal. Continuing with this example, the device can turn on the first amplifier to increase the voltage level of the output signal.

[0023] In some embodiments, the device may include at least one circuit. For example, the device may include a first circuit, a second circuit, and a third circuit. In some embodiments, the device may communicate with a driver (e.g., a remote and / or external amplifier). In some embodiments, the communication between the device and the driver may be direct (e.g., the device is directly connected to the driver and the device communicates directly with the driver) and / or indirect (e.g., a component receives a signal from the driver and a component provides a signal to the device). The communication between the device and the driver may include the device and the driver being electrically coupled to each other.

[0024] A system may refer to and / or include at least one of an application specific integrated circuit (ASIC), a capacitive load component, a display driver, a touch screen, a keyboard sensor, a mobile device, and / or other possible touch controllers. In some embodiments, a device may refer to and / or include at least one of an integrated circuit, a general purpose processor, a multi-core processor, a software programmable device, a programmable logic controller, and / or other possible circuit systems and / or hardware. Similarly, the functionality of the device may be stored as software and / or as instructions in a memory and when the information stored in the memory (e.g., software and / or instructions) is executed by a processor, the processor causes the processor to perform the functionality of the device (e.g., the processor may monitor the output signal and control the amount of voltage provided to the driver) and / or perform the functionality of the components of the device (e.g., the first circuit, the second circuit, and / or the third circuit).

[0025] In some embodiments, a circuit may refer to and / or include at least one of an operational amplifier (Opamp), a comparator circuit, a filter, a digital signal processing engine, a pattern generator (e.g., a device that sends control signals to components of a device and / or system), a flip-flop, a logic gate, a latch, a state storage device, an integrated circuit, a software programmable device, a programmable logic controller, and / or other possible circuit systems and / or hardware.

[0026] In some embodiments, driver may refer to and / or include at least one of a driver circuit, an integrated circuit, an Opamp, a regulator, a software programmable device, a programmable logic controller, and / or other possible circuit systems and / or hardware. In some embodiments, level may refer to and / or include at least one of a voltage level of a signal, a voltage amount of a signal, a power amount of a signal, a current amount of a signal, and / or various combinations. Power amount may refer to and / or include at least one of a voltage level, a current level, and / or various components.

[0027] In some embodiments, a difference may refer to and / or include an indication of which signal (e.g., the first signal or the second signal) is larger and / or smaller relative to each other, a binary value (e.g., 0 or 1) indicating whether the first signal is higher and / or lower than the second signal, and / or various combinations. In some embodiments, a difference may also refer to a mathematical difference between two or more signals (e.g., a larger signal minus a smaller signal), a mathematical difference between two or more values ​​and / or levels, and / or various combinations. In some embodiments, an offset may refer to and / or include at least one of a phase shift of a signal, a time shift of a signal, a delay of a signal, a modification of a time constant, and / or various combinations.

[0028] In some embodiments, a component may refer to and / or include at least one of a voltage source (e.g., a battery, current through a resistor, etc.), circuit system hardware (e.g., a transistor, a resistor, a capacitor, an inductor, a diode, etc.), and / or various components. In some embodiments, the amount of resistance experienced by a circuit may refer to and / or include at least one of a load applied to a signal, an amount of resistance, an amount of impedance, an amount of inductance, a capacitance, and / or various combinations.

[0029] In some embodiments, a circuit positioned between the second circuit and the third circuit may refer to and / or include at least one of a circuit disposed between the second circuit and the third circuit, a circuit located between the second circuit and the third circuit, a circuit connected to the second circuit, and a circuit connecting the second circuit and the third circuit, and / or various combinations.

[0030] Some embodiments relate to a system. The system may include a driver and a device. The driver may provide a first signal to indicate a first amount of power and the first signal may have a first level. The device may communicate with the driver. The device may include a first circuit. The first circuit may provide a second signal having a first level based at least on the first level of the first signal in response to receiving the first signal. The device may also include a second circuit. The second circuit may detect the first level of the first signal in response to receiving the first signal. The second circuit may also provide a third signal in response to detecting the first level of the first signal to control a third circuit of the device, the third signal may control the third circuit by defining a difference between a first terminal and a second terminal of the third circuit of the device. The third circuit may provide a fourth signal in response to receiving the first signal and the third signal, the fourth signal may have a first level in response to the difference being less than a predetermined value, and the fourth signal may have a second level in response to the difference being greater than the predetermined value. The device may also include a fourth circuit. The fourth circuit may provide a fifth signal in response to receiving the second signal and the fourth signal, the fifth signal may have a first level based at least on the first level of the second signal, and the fifth signal may have a second level based at least on the first level of the second signal and the second level of the fourth signal.

[0031] In some embodiments, the fifth signal may have the first level in response to the fourth signal having the first level, and the fifth signal may have the second level in response to the fourth signal having the second level.

[0032] In some embodiments, the second level of the fifth signal may be greater than the second level of the fourth signal, and the second level of the fourth signal may be greater than the first level of the second signal.

[0033] In some embodiments, the first level of the second signal may be greater than the first level of the fourth signal, and the first level of the second signal may be less than the second level of the fourth signal.

[0034] In some embodiments, the first level of the first signal may have a first value in response to the first power amount being associated with a first mode of the device, and the first level of the first signal may have a second value in response to the first power amount being associated with a second mode of the device.

[0035] In some embodiments, the first mode of the device may relate to communications corresponding to a first protocol, and the second mode of the device may relate to communications corresponding to a second protocol.

[0036] In some embodiments, the device may include a fifth circuit. The fifth circuit may receive the fourth signal before the fourth circuit. The fifth circuit may also adjust a first resistance amount experienced by the first circuit from a first value to a second value in response to the fourth signal having the first level. The fifth circuit may also provide the fourth signal to the fourth circuit in response to the adjustment of the first resistance amount. The second value of the first resistance amount may specify the first level of the fifth signal. The second value of the first resistance amount may be greater than the first value of the first resistance amount.

[0037] In some embodiments, the fifth circuit can adjust the first resistance by modifying a second resistance associated with the fourth signal from a first value to a second value. The second value of the second resistance can be less than the second value of the first resistance.

[0038] In some embodiments, the fifth circuit may be positioned between the third circuit and the fourth circuit, and the fifth circuit may be positioned in series to the third circuit and the fourth circuit.

[0039] In some embodiments, the device may include a fifth circuit. The fifth circuit may receive the fourth signal before the fourth circuit. The fifth circuit may also adjust a first amount of resistance experienced by the first circuit from a first value to a second value in response to the fourth signal having the second level. The fifth circuit may also provide the fourth signal to the fourth circuit in response to the adjustment of the first amount of resistance. The second value of the first amount of resistance may be less than the first value of the first amount of resistance. An amount of the fifth signal based on the first level of the second signal may decrease in response to the first amount of resistance having the second value.

[0040] In some embodiments, the first circuit may receive a first instance of the first signal. The third circuit may receive a second instance of the first signal. The second instance of the first signal may be offset from the first instance of the first signal by a predetermined amount.

[0041] Some embodiments relate to a device. The device may receive a first signal from a driver. The device may include a first circuit. The first circuit may provide a second signal having a first level based at least on a first level of the first signal in response to receiving the first signal. The device may also include a second circuit. The second circuit may detect the first level of the first signal in response to receiving the first signal. The second circuit may also provide a third signal to control a third circuit of the device in response to detecting the first level of the first signal, the third signal may control the third circuit by defining a difference between a first terminal and a second terminal of the third circuit of the device. The third circuit may provide a fourth signal in response to receiving the first signal and the third signal, the fourth signal may have a first level in response to the difference being less than a predetermined value, and the fourth signal may have a second level in response to the difference being greater than the predetermined value. The device may also include a fourth circuit. The fourth circuit may provide a fifth signal in response to receiving the second signal and the fourth signal, the fifth signal may have a first level based at least on the first level of the second signal, and the fifth signal may have a second level based at least on the first level of the second signal and the second level of the fourth signal.

[0042] In some embodiments, the fifth signal may have the first level in response to the fourth signal having the first level, and the fifth signal may have the second level in response to the fourth signal having the second level.

[0043] In some embodiments, the second level of the fifth signal may be greater than the second level of the fourth signal, and the second level of the fourth signal may be greater than the first level of the second signal.

[0044] In some embodiments, the first level of the second signal may be greater than the first level of the fourth signal, and the first level of the second signal may be less than the second level of the fourth signal.

[0045] In some embodiments, the device may include a fifth circuit. The fifth circuit may receive the fourth signal before the fourth circuit. The fifth circuit may also adjust a first resistance amount experienced by the first circuit from a first value to a second value in response to the fourth signal having the first level. The fifth circuit may also provide the fourth signal to the fourth circuit in response to the adjustment of the first resistance amount. The second value of the first resistance amount may specify the first level of the fifth signal. The second value of the first resistance amount may be greater than the first value of the first resistance amount.

[0046] In some embodiments, the device may include a fifth circuit. The fifth circuit may receive the fourth signal before the fourth circuit. The fifth circuit may also adjust a first amount of resistance experienced by the first circuit from a first value to a second value in response to the fourth signal having the second level. The fifth circuit may also provide the fourth signal to the fourth circuit in response to the adjustment of the first amount of resistance. The second value of the first amount of resistance may be less than the first value of the first amount of resistance. An amount of the fifth signal based on the first level of the second signal may decrease in response to the first amount of resistance having the second value.

[0047] Some embodiments relate to a method. The method may include receiving, by a device, a first signal from a driver to indicate a first amount of power and the first signal having a first level. The method may also include providing, by a first circuit of the device, a second signal having a first level based at least on the first level of the first signal in response to receiving the first signal. The method may also include detecting, by a second circuit of the device, the first level of the first signal in response to receiving the first signal. The method may also include providing, by the second circuit of the device, a third signal to control a third circuit of the device in response to detecting the first level of the first signal, the third signal controlling the third circuit of the device by defining a difference between a first terminal and a second terminal of the third circuit of the device. The method may also include providing, by the third circuit of the device, a fourth signal in response to receiving the first signal and the third signal, the fourth signal having a first level in response to the difference being less than a predetermined value, and the fourth signal having a second level in response to the difference being greater than the predetermined value. The method may also include providing, by a fourth circuit of the device in response to receiving the second signal and the fourth signal, a fifth signal, the fifth signal may have a first level based at least on the first level of the second signal, and the fifth signal may have a second level based at least on the first level of the second signal and the second level of the fourth signal.

[0048] In some embodiments, the first level of the first signal may have a first value in response to the first power amount being associated with a first mode of the device. The first level of the first signal may have a second value in response to the first power amount being associated with a second mode of the device. The first mode of the device may be associated with communications corresponding to a first protocol, and the second mode of the device may be associated with communications corresponding to a second protocol.

[0049] In some embodiments, the method may also include receiving, by a fifth circuit of the device, the fourth signal before the fourth circuit. The method may also include adjusting, by the fifth circuit of the device, a first resistance amount experienced by the first circuit from a first value to a second value in response to the fourth signal having the first level. The method may also include providing, by the first circuit of the device, the fourth signal to the fourth circuit in response to the adjustment of the first resistance amount. The second value of the first resistance amount may dictate the first level of the fifth signal. The second value of the first resistance amount may be greater than the first value of the first resistance amount.

[0050] Figure 1 A block diagram of system 100 is depicted in accordance with some embodiments. System 100 may refer to and / or include at least one of the systems described herein. For example, system 100 may include a power amplifier system described herein. In some embodiments, various systems, devices, and / or components of system 100 may be added, removed, integrated, separated, rearranged, relocated, and / or replaced. For example, a first component of system 100 may be relocated from a first device to a second device. As another example, a device that includes one amplifier may be modified to include two amplifiers.

[0051] In some embodiments, system 100 may be implemented as and / or contained within a communication device. For example, system 100 may be included in an antenna. As another example, system 100 may be located in a transceiver. In some embodiments, system 100 and / or one or more components thereof may be included in and / or implemented as one or more components of a communication device (e.g., an antenna, a transmitter, a transceiver, a receiver, a radio frequency (RF) device, etc.). For example, a first component of system 100 may include a power amplifier driver and the first component may drive an antenna.

[0052] In some embodiments, system 100 may include at least one driver 105 and at least one device 110. In some embodiments, driver 105 may include at least one of the drivers described herein. In some embodiments, device 110 may include at least one of the devices described herein. In some embodiments, device 110 may provide some of the technical solutions described herein. For example, device 110 may control an amplifier to control the efficiency of system 100 and / or its components.

[0053] Driver 105 may communicate with device 110. For example, driver 105 may be coupled to device 110. In some embodiments, driver 105 may be directly coupled to device 110 (e.g., at least a portion of driver 105 is in contact with at least a portion of device 110). In some embodiments, driver 105 may be indirectly coupled to device 110. For example, driver 105 may be directly coupled to a component and the component may also be directly coupled to device 110. In some embodiments, driver 105 may be electrically coupled to device 110.

[0054] In some embodiments, the driver 105 may provide one or more signals. For example, the driver 105 may provide a first signal and a second signal. In some embodiments, the driver 105 may provide the signals via wired communication. For example, the driver 105 may be electrically coupled to the component via wires and / or cables. Continuing with this example, the driver 105 may provide the one or more signals to the component via wires. In some embodiments, the driver 105 may provide the signals via wireless communication. For example, the driver 105 may include a transceiver and the driver 105 may provide one or more wireless signals via the transceiver.

[0055] In some embodiments, driver 105 may include and / or be implemented as an operational amplifier (Opamp). For example, driver 105 may receive a first signal and driver 105 may provide a second signal that is an amplification of the first signal. In some embodiments, driver 105 may provide a signal to indicate an amount of power. For example, driver 105 may provide a signal having a voltage level of 5V and the voltage level of 5V may indicate an amount of power. As another example, driver 105 may provide an amplified signal and the amplified signal (based on a gain factor of driver 105) may indicate an amount of power.

[0056] In some embodiments, driver 105 may provide one or more signals to device 110. For example, driver 105 may provide a first signal and a second signal to device 110. The signals provided by driver 105 to device 110 are Figure 1 105 is shown as a driver signal. In some embodiments, driver 105 may provide one or more driver signals. The driver signal may include one or more levels. For example, the driver signal may include a first level and a second level. In some embodiments, the level of the driver signal may indicate an amount of power. In some embodiments, the level of the driver signal may have one or more values. For example, a first level of the driver signal may include a first value and / or a second value. As another example, a first driver signal may include a first level and a second driver signal may include a second level. Continuing with this example, the first level and the second level may be similar to each other (e.g., the same level) and / or different from each other (e.g., the first level is greater than and / or less than the second level).

[0057] In some embodiments, the level and / or value of the driver signal may be related to one or more modes of the system 100 and / or device 110. For example, the driver 105 may provide a first driver signal in response to selection of a first mode (via an input device). In some embodiments, one or more modes may refer to and / or include one or more protocols. For example, a first mode may be related to communication via Bluetooth (e.g., a protocol). As another example, a second mode may be related to communication via WLAN (e.g., a protocol).

[0058] In some embodiments, the first value of the first driver signal may indicate a first mode and the second value of the first driver signal may indicate a second mode. For example, the first mode may be related to communication via Bluetooth. Continuing with this example, the driver signal may have a first value (e.g., power amount) indicating the first mode. As another example, the driver signal may have a second value indicating the second mode.

[0059] Device 110 may receive one or more signals. For example, device 110 may receive a first signal and a second signal. In some embodiments, device 110 may receive a driver signal as described herein. In some embodiments, device 110 may control and / or implement communications via one or more protocols as described herein.

[0060] In some embodiments, the device 110 may include a signal analyzer 115 and one or more amplifiers 120. In some embodiments, the device 110 may include a first amplifier 120 and a second amplifier 120. In some embodiments, the amplifier 120 may be referred to and / or implemented as a Doherty amplifier. In some embodiments, the signal analyzer 115 may receive one or more signals. In some embodiments, the signal analyzer 115 may communicate with the driver 105. For example, the signal analyzer 115 may receive a driver signal. In some embodiments, the signal analyzer 115 may communicate with the amplifier 120. For example, the signal analyzer 115 may be directly coupled to the amplifier 120.

[0061] In some embodiments, the signal analyzer 115 may detect one or more levels of a signal. For example, the signal analyzer 115 may detect one or more levels of a driver signal. In some embodiments, the signal analyzer 115 may determine one or more modes in response to detecting the levels of the driver signal. For example, the signal analyzer 115 may determine that the first driver signal is associated with the first mode in response to the first driver signal having a first level indicating the first mode.

[0062] In some embodiments, the signal analyzer 115 may provide one or more signals. For example, the signal analyzer 115 may provide a first signal. In some embodiments, the signal analyzer 115 may provide a signal in response to the signal analyzer 115 receiving a driver signal. For example, the signal analyzer 115 may provide a first signal in response to the signal analyzer 115 receiving a first driver signal. In some embodiments, the signal analyzer 115 may provide one or more signals to the amplifier 120. The signals provided by the signal analyzer 115 to the amplifier 120 are Figure 1 . The envelope signal may refer to and / or include a bias signal. For example, the first envelope signal may establish and / or define a bias voltage between the terminals of the first amplifier 120.

[0063] In some embodiments, amplifier 120 may receive one or more signals. For example, amplifier 120 may receive an input signal. In some embodiments, amplifier 120 may receive a signal from driver 105. For example, amplifier 120 may receive a driver signal. In some embodiments, amplifier 120 may receive a signal from signal analyzer 115. For example, amplifier 120 may receive an envelope signal. In some embodiments, amplifier 120 may provide one or more signals. For example, amplifier 120 may provide an amplified signal. In some embodiments, amplifier 120 may provide an amplified signal as a driver signal. For example, amplifier 120 may receive a first driver signal having a voltage level of 3V. Continuing with this example, amplifier 120 may provide a signal (e.g., an amplified signal) having a voltage level of 4V. The signal provided by amplifier 120 is Figure 1 The output signal is shown in .

[0064] In some embodiments, the envelope signal may specify and / or control the output signal provided by the amplifier 120. For example, the envelope signal may define the difference between the terminals of the amplifier 120. Continuing with this example, the difference between the terminals may turn the amplifier 120 on and / or off. In other words, the difference between the terminals of the amplifier 120 may determine and / or specify whether the amplifier 120 provides an amplified signal. In some embodiments, the amplifier 120 may have a predetermined threshold (e.g., the difference between the terminals). For example, the predetermined threshold may be 1V. Continuing with this example, the amplifier 120 may provide an amplified signal (e.g., turned on) when the difference between the terminals is greater than 1V. As another example, the amplifier 120 may provide a non-amplified signal (e.g., turned off) when the difference between the terminals is less than 1V.

[0065] In some embodiments, the unamplified signal may refer to a signal having a voltage level that is different from the gain factor of the amplifier. For example, the first amplifier 120 may have a gain factor of 3 (e.g., the first amplifier 120 provides an amplified signal that is 3 times the received signal). Continuing with this example, the first amplifier 120 may receive a first signal having a voltage level of 1V. The first amplifier 120 may provide a signal having a voltage level of 1.1V (e.g., the unamplified signal). In the above example, the signal provided by the first amplifier 120 may be an unamplified signal because the voltage level of the signal is different from the gain factor of the first amplifier 120. In some embodiments, the amplifier 120 may provide an unamplified signal when the amplifier 120 is turned off.

[0066] In some embodiments, amplifier 120 may provide a signal having a voltage level of 0V (e.g., turned off) when the difference between the terminals is less than 1V. In some embodiments, amplifier 120 may provide a signal having a level less than the level of a received signal. For example, amplifier 120 may receive a signal having a voltage level of 2V. Continuing with this example, amplifier 120 may provide a signal having a voltage level of 1V. In some embodiments, amplifier 120 providing a signal having a voltage level less than the received signal may indicate that amplifier 120 has been turned off.

[0067] In some embodiments, amplifier 120 may receive the driver signal. Amplifier 120 may provide an amplified signal based on the driver signal (based on its gain factor). For example, amplifier 120 may provide the signal as an amplification of the driver signal. In some embodiments, the envelope signal may cause amplifier 120 to provide an unamplified signal in response to amplifier 120 receiving the driver signal.

[0068] Figure 2 Schematic block diagram 200 is depicted according to some embodiments. In some embodiments, schematic block diagram 200 may include one or more systems, devices, and / or components of system 100. For example, schematic block diagram 200 may include amplifier 120. In some embodiments, system 100 may include and / or be implemented as schematic block diagram 200. In some embodiments, at least one device and / or component of schematic block diagram 200 may be included in system 100 and / or implemented within system 100. In some embodiments, systems, devices, and / or components of schematic block diagram 200 may be added, removed, integrated, separated, rearranged, relocated, and / or replaced. For example, a device that does not include a transformer may be modified to include a transformer. As another example, a component shown as included in a first device may also be included in a second device (even if Figure 2 not shown).

[0069] In some embodiments, the schematic block diagram 200 may include a driver 105, at least one carrier power amplifier (PA) 210, at least one peak PA 215, at least one impedance inverter 220, at least one power combiner 225, at least one resistive element 230, at least one envelope detector 235, at least one constant bias 240, at least one adder 243, at least one offset device 245, and at least one transformer 250. The components and devices of the schematic block diagram 200 may communicate with each other. For example, the driver 105 may communicate with the carrier PA 210. In some embodiments, the resistive element 230 may include and / or provide at least one of resistance, impedance, capacitance, and / or inductance.

[0070] In some embodiments, device 110 may include and / or be implemented as a carrier PA 210 and a peak PA 215. For example, amplifier 120 may include carrier PA 210 and peak PA 215. As another example, carrier PA 210 may be a first amplifier 120 and peak PA 215 may be a second amplifier 120. Carrier PA 210 may be positioned in parallel and / or in series with peak PA 215. For example, carrier PA 210 may be coupled to a first node of schematic block diagram 200 and peak PA 215 may be coupled to the first node via carrier PA 210. Continuing with this example, carrier PA 210 and peak PA 215 may be considered to be in series (e.g., a signal provided to the first node will flow to carrier PA 210 before flowing to peak PA 215). As another example, both carrier PA 210 and peak PA 215 may be independently coupled to the first node (e.g., carrier PA 210 is directly coupled to the first node and peak PA 215 is directly coupled to the first node). Continuing with this example, carrier PA 210 and peaking PA 215 may be considered to be in parallel (eg, a signal provided to the first node may flow to at least one of carrier PA 210 and / or peaking PA 215). Figure 2 An example is depicted where carrier PA 210 and peaking PA 215 are positioned in parallel with each other.

[0071] In some embodiments, the driver 105 may be electrically coupled to the transformer 250. For example, the driver 105 may provide one or more signals to the transformer 250. In some embodiments, the driver 105 may provide a driver signal to the transformer 250. In some embodiments, the transformer 250 may modify, adjust, and / or change the driver signal. For example, the transformer 250 may be implemented as a step-up transformer (e.g., the transformer 250 increases the level of the driver signal). In some embodiments, the transformer may increase the voltage level of the driver signal.

[0072] The transformer 250 may be in communication with the carrier PA 210 and the peak PA 215. For example, the transformer 250 may provide a driver signal to the carrier PA 210 and the peak PA 215. In some embodiments, the transformer 250 may be directly coupled to the carrier PA 210 and / or the peak PA 215. For example, the transformer 250 may provide one or more signals directly to the carrier PA 210 and / or the peak PA 215.

[0073] In some embodiments, transformer 250 may be electrically coupled to carrier PA 210. For example, transformer 250 and carrier PA 210 may be electrically coupled to each other via line 255. In some embodiments, line 255 may electrically couple transformer 250 to one or more terminals of carrier PA 210. For example, line 255 may electrically couple transformer 250 to a non-inverting terminal and an inverting terminal of carrier PA 210. In some embodiments, line 255 may include at least one of a cable, a wire, a power line, and / or other possible physical components to electrically couple transformer 250 to carrier PA 210. In some embodiments, line 255 may include a wireless connection. For example, line 255 may illustrate the transmission of a wireless signal. Figure 2 An example is depicted where a driver signal is transmitted from transformer 250 to carrier PA 210 via line 255 .

[0074] In some embodiments, transformer 250 can be electrically coupled to offset device 245. For example, transformer 250 can be electrically coupled to offset device 245 via line 260. In some embodiments, the electrical coupling between transformer 250 and offset device 245 can be similar to at least one example of electrical coupling described herein. Transformer 250 can provide a driver signal to offset device 245 via line 260.

[0075] In some embodiments, carrier PA 210 may receive one or more signals. For example, carrier PA 210 may receive a driver signal. In some embodiments, carrier PA 210 may provide one or more signals. For example, carrier PA 210 may provide one or more signals to power combiner 225. In some embodiments, carrier PA 210 may amplify one or more signals. For example, carrier PA 210 may receive a first driver signal and carrier PA 210 may amplify the first driver signal. As another example, carrier PA 210 may receive a first signal having a voltage level of 2V and carrier PA 210 may amplify the first signal. The signals provided by carrier PA 210 to power combiner 225 are Figure 1 The carrier signal is shown in FIG.

[0076] In some embodiments, the offset device 245 and / or the offset 245 may receive one or more signals. For example, the offset device 245 may receive a driver signal. In some embodiments, the offset device 245 may adjust one or more signals. For example, the offset device 245 may adjust the signal provided to the offset device 245. In some embodiments, the offset device 245 may adjust the signal by modifying, shifting, changing and / or otherwise changing the signal. For example, the offset device 245 may perform a phase shift to adjust one or more signals. As another example, the offset device 245 may perform a 90 degree phase shift on the driver signal. In some embodiments, the offset device 245 may phase shift the signal so that the driver signal provided to the peak PA 215 is offset relative to the driver signal provided to the carrier PA 210. The signal provided to the peak PA 215 by the offset device 245 is at Figure 2 The offset signal is shown in .

[0077] In some embodiments, envelope detector 235 may receive one or more signals. For example, envelope detector 235 may receive a driver signal. In some embodiments, envelope detector 235 may receive a driver signal provided to carrier PA 210. For example, envelope detector 235 may be electrically coupled to line 255. As another example, envelope detector 235 may detect transmission of the driver signal via line 255. In some embodiments, envelope detector 235 may be included in and / or implemented as signal analyzer 115.

[0078] In some embodiments, envelope detector 235 may detect the level of one or more signals. For example, envelope detector 235 may detect the level of a driver signal. As another example, envelope detector 235 may detect the voltage level of a driver signal. In some embodiments, envelope detector 235 may perform functions similar to those of signal analyzer 115.

[0079] In some embodiments, envelope detector 235 may provide one or more signals. For example, envelope detector 235 may provide an envelope signal as described herein. In some embodiments, envelope detector 235 may provide a signal to one or more power supply terminals. For example, envelope detector 235 may provide a signal to a power supply terminal of amplifier 120. In some embodiments, envelope detector 235 provides a signal to adder 243. For example, envelope detector 235 may provide an envelope signal to adder 243.

[0080] In some embodiments, envelope detector 235 may provide a signal to control peak PA 215. For example, envelope detector 235 may provide a first signal to turn off peak PA 215. As another example, envelope detector 235 may provide a second signal to turn on peak PA 215. In some embodiments, envelope detector 235 may provide a signal to maintain a state of peak PA 215. For example, peak PA 215 may be turned on and envelope detector 235 may provide a first signal to keep peak PA 215 turned on (e.g., maintain the state).

[0081] In some embodiments, envelope detector 235 may control peak PA 215 by defining a difference between terminals of peak PA 215. For example, envelope detector 235 may define a difference (e.g., a bias voltage) between a first terminal and a second terminal of peak PA 215. In some embodiments, envelope detector 235 may turn on and / or off (e.g., control) peak PA 215 based on the difference.

[0082] In some embodiments, adder 243 may receive one or more signals. For example, adder 243 may receive an envelope signal. In some embodiments, adder 243 may receive the envelope signal from envelope detector 235. In some embodiments, adder 243 may receive a signal from constant bias 240. For example, constant bias 240 may include and / or be implemented as a power supply and constant bias 240 may provide a signal (e.g., power) to adder 243.

[0083] In some embodiments, adder 243 may combine one or more signals. For example, adder 243 may combine an envelope signal with a signal provided by constant bias 240. In some embodiments, adder 243 may combine signals by merging, integrating, combining, and / or otherwise fusing the signals. For example, adder 243 may receive a first signal and a second signal. Continuing with this example, the first signal may include a voltage level of 2V and the second signal may include a voltage level of 1V. In some embodiments, adder 243 may combine the first signal and the second signal to generate a signal having a voltage level of 3V (e.g., a combination of the signals). In some embodiments, adder 243 may combine the first signal and the second signal to generate a signal having a voltage level of 1V (e.g., a difference between the signals).

[0084] In some embodiments, adder 243 may be electrically coupled to peak PA 215. For example, adder 243 may be connected to peak PA 215 via one or more lines. In some embodiments, adder 243 may provide one or more signals to peak PA 215. For example, adder 243 may provide a signal that is a combination of an envelope signal and a signal provided by constant bias 240. The signal provided by adder 243 to peak PA 215 is Figure 2243 is shown as a bias signal. In some embodiments, the bias signal can control the peak PA 215. For example, the bias signal can turn the peak PA 215 on and / or off. In some embodiments, the adder 243 can provide the bias signal to one or more power supply terminals of the peak PA 215.

[0085] The offset device 245 may be electrically coupled to the peak PA 215. For example, the offset device 245 may be electrically coupled to the peak PA 215 via line 265. In some embodiments, the offset device 245 may provide an offset signal to the peak PA 215 via line 265. In some embodiments, the offset signal may be provided to the peak PA 215 along with the bias signal. For example, the offset device 245 may communicate with the envelope detector 235 to determine when to transmit the offset signal.

[0086] In some embodiments, peak PA 215 may receive one or more signals. For example, peak PA 215 may receive an offset signal. As another example, peak PA 215 may receive a bias signal. In some embodiments, peak PA 215 may receive a first signal and a second signal at a first point in time. In some embodiments, peak PA 215 may receive a first signal at a first point in time and may receive a second signal at a second point in time.

[0087] In some embodiments, peak PA 215 may provide one or more signals. For example, peak PA 215 may provide a first signal that is an amplification of one or more signals received by peak PA 215. As another example, peak PA 215 may receive a first signal and peak PA 215 may provide a second signal in response to receiving the first signal. In some embodiments, peak PA 215 may provide a signal having one or more levels. For example, peak PA 215 may provide a first signal having a first level and / or a second level. As another example, peak PA 215 may provide a first signal having a first level and a second signal having a second level.

[0088] In some embodiments, the peak PA 215 may provide a signal based on the difference defined by the envelope detector 235. For example, the difference may define and / or establish a bias voltage between power supply terminals of the peak PA 215 and the bias voltage may dictate the level of the signal provided by the peak PA 215. In some embodiments, the peak PA 215 may provide a signal having a first level in response to the difference being less than a predetermined value. For example, the bias voltage may be less than 1 V (e.g., a predetermined value) and the peak PA 215 may provide a signal having a voltage level of 0 V (e.g., a first level) in response to the bias voltage being less than 1 V. As another example, the peak PA 215 may provide a signal less than its gain factor in response to the bias voltage being less than a predetermined value.

[0089] In some embodiments, the peak PA 215 may provide a signal having a second level in response to the difference being greater than a predetermined value. For example, the peak PA 215 may provide an amplified signal in response to the bias voltage (e.g., the difference) between the terminals of the peak PA 215 being greater than a predetermined value. In some embodiments, the peak PA 215 may provide an amplified signal of at least one of the signals described herein. For example, the peak PA 215 may provide an amplified signal of a driver signal. As another example, the peak PA 215 may provide an amplified signal of an offset signal.

[0090] In some embodiments, peak PA 215 may provide a signal to impedance inverter 220. For example, peak PA 215 may be electrically coupled to impedance inverter 220 via line 270. Continuing with this example, peak PA 215 may provide a signal to impedance inverter 220 via line 270. The signal provided by peak PA 215 to impedance inverter 220 is Figure 2 The peak signal is shown in the figure.

[0091] In some embodiments, the impedance inverter 220 may receive one or more signals. For example, the impedance inverter 220 may receive a peak signal via line 270. In some embodiments, the impedance inverter 220 may invert one or more signals. For example, the impedance inverter 220 may receive a first signal having a first value and the impedance inverter 220 may invert the first signal from the first value to a second value. In some embodiments, the impedance inverter 220 may invert a signal by generating a signal that is opposite to and / or the inverse of the input signal. For example, the impedance inverter 220 may receive a first signal having a voltage level of 2V and the impedance inverter 220 may provide a signal having a voltage level of negative 2V (e.g., -2V). In some embodiments, the impedance inverter 220 may receive one or more signals having one or more resistances and / or impedance amounts. For example, the impedance inverter 220 may receive a first signal having a voltage level of 0V. Continuing with this example, the first signal having a voltage level of 0V may result in the resistance amount (associated with the first signal) being equal to infinity. In some embodiments, the impedance inverter 220 can invert the resistance from infinity (e.g., the first value) to zero (e.g., the second value). In some embodiments, the impedance inverter 220 can invert the resistance associated with the peak signal. For example, the impedance inverter 220 can invert the resistance of the peak signal from the first value to the second value.

[0092] In some embodiments, the impedance inverter 220 may receive the peak signal before the power combiner 225 receives the peak signal. For example, the impedance inverter 220 may receive the peak signal from the peak PA 215 and the impedance inverter 220 may provide the peak signal to the power combiner 225.

[0093] In some embodiments, the amount of resistance associated with the peak signal can affect and / or adjust the value and / or level of one or more signals described herein. For example, the amount of resistance of the peak signal can affect the output signal described herein. In some embodiments, the amount of resistance associated with the peak signal can affect the signal by adjusting the amount of resistance experienced by one or more signals. For example, carrier PA 210 can provide a first carrier signal having a first amount of current and the amount of resistance experienced by the first carrier signal can dictate a level (e.g., an amount of power of the carrier signal).

[0094] In some embodiments, the impedance inverter 220 can provide one or more signals. For example, the impedance inverter 220 can provide a signal to the power combiner 225. In some embodiments, the impedance inverter 220 can provide an inverted signal. For example, the impedance inverter 220 can provide a signal including and / or indicating a peak signal. As another example, the impedance inverter 220 can provide an inverted signal of the peak signal. The signal provided by the impedance inverter 220 to the power combiner 225 is Figure 2 In some embodiments, the anti-phase signal may be the inversion of the resistance amount associated with the peak signal.

[0095] In some embodiments, the power combiner 225 may receive one or more signals. For example, the power combiner 225 may receive a carrier signal. In some embodiments, the power combiner 225 may receive the carrier signal via line 280. For example, the power combiner 225 may be electrically coupled to the carrier PA 210 via line 280. In some embodiments, the power combiner 225 may receive an anti-phase signal. For example, the power combiner 225 may receive an anti-phase signal via line 275.

[0096] In some embodiments, the power combiner 225 may provide one or more signals. For example, the power combiner 225 may provide an output signal as described herein. In some embodiments, the power combiner 225 may provide a signal having one or more levels. For example, the power combiner 225 may provide a first signal having a first level. In some embodiments, the power combiner 225 may provide a signal based on a carrier signal and / or a peak signal. For example, the power combiner 225 may provide a first output signal having a first level, and the first level may be based on a carrier signal and / or a peak signal.

[0097] In some embodiments, the output signal may be a combination of a carrier signal and a peak signal. For example, the power combiner 225 may receive the carrier signal and the peak signal. Continuing with this example, the levels (e.g., the amount of power) of the carrier signal and the peak signal may be provided and / or applied to a load (e.g., the resistive element 230). In other words, the amount of current associated with the carrier signal and the peak signal may be provided to the resistive element 230 (e.g., the load). The amount of current provided to the resistive element 230 may define and / or generate one or more levels of the output signal.

[0098] As a non-limiting example, carrier PA 210 may receive a first driver signal via line 255. The first driver signal may include a voltage level of 5V (e.g., a first level). Continuing this example, offset device 245 and envelope detector 235 may receive the first driver signal. Offset device 245 may provide a first offset signal to peak PA 215 via line 265. Envelope detector 235 may detect that the first driver signal has the first level. Continuing this example, envelope detector 235 may control peak PA 215. Envelope detector 235 may turn off peak PA 215 (e.g., control) in response to the first driver signal having the first level. Continuing this example, carrier PA 210 may provide a first carrier signal. The first carrier signal may be based on the first driver signal. Continuing this example, peak PA 215 may provide a peak signal having a voltage level of 0V (e.g., a first level) in response to envelope detector 235 turning off peak PA 215. The peak signal may be provided to impedance inverter 220. Continuing with this non-limiting example, the peak signal may be associated with an infinite amount of resistance (based on the peak signal having a voltage level of 0V). Impedance inverter 220 may invert the peak signal. Continuing with this example, impedance inverter 220 may invert the peak signal from an infinite amount of resistance to zero resistance (e.g., an inverted signal). Power combiner 225 may receive the first carrier signal and the inverted signal. Continuing with this non-limiting example, power combiner 225 may provide a first output signal. The first output signal may be based on the level of the first carrier signal. Continuing with this non-limiting example, power combiner 225 may apply the first carrier signal to resistive element 230.

[0099] In some embodiments, at least one of the carrier PA 210 and / or the peak PA 215 may be electrically coupled to the resistive element 230. For example, the power combiner 225 may electrically couple the carrier PA 210 to the resistive element 230 (directly and / or indirectly). In some embodiments, the impedance inverter 220 may adjust the amount of resistance experienced by the carrier PA 210 from a first level to a second level. For example, when the inverted signal includes an amount of zero impedance, the carrier PA 210 may experience a first amount of resistance (e.g., an amount of resistance associated with the resistive element 230). As another example, when the inverted signal includes an amount of impedance greater than zero, the carrier PA 210 may experience a second amount of resistance (e.g., an amount different from the first amount of resistance). In some embodiments, the amount of resistance experienced by the carrier PA 210 may specify one or more levels of the carrier signal and / or the output signal. For example, the carrier PA 210 may provide a first carrier signal having a first level and the first output signal may have a first level when the first level of the first carrier signal is provided to the resistive element 230. As another example, the first output signal may have a second level when the first level of the first carrier signal is provided to only a portion of the resistive elements. In some embodiments, the output signal may have one or more first values ​​when the carrier PA 210 is applied to all of the resistive elements 230. For example, the amount of current associated with the carrier signal may be applied to the resistive elements 230.

[0100] In some embodiments, one or more signals described herein may have one or more levels. For example, the peak PA 215 may provide a signal having one or more levels. In some embodiments, the peak PA 215 may provide one or more signals having a first level. For example, the peak PA 215 may provide a first signal having a voltage level of 5V (e.g., a first level). As another example, the peak PA 215 may provide a second signal having a voltage level of 2V (e.g., a second level). In some embodiments, the carrier PA 210 may provide a carrier signal based on the driver signal. For example, the carrier signal may be an amplified signal based on the driver signal. In other words, the carrier PA 210 may receive the driver signal and the carrier PA 210 may provide an amplified signal (e.g., a carrier signal) based on the level of the driver signal.

[0101] In some embodiments, the levels and / or values ​​of the signals described herein may be different. For example, carrier PA 210 may provide a first carrier signal having a voltage level (e.g., a first level) of 3V. As another example, peak PA 215 may provide a first peak signal having a voltage level (e.g., a first level) of 5V. In some embodiments, the first level of the first peak signal may be different from the first level of the first carrier signal. For example, the first level of the first peak signal may be greater than the first level of the first carrier signal. In some embodiments, peak PA 215 may have a gain factor greater than the gain factor of carrier PA 210 (e.g., peak PA 215 may provide an amplified signal that is greater than the amplified signal provided by carrier PA 210).

[0102] In some embodiments, the levels and / or values ​​of the signals described herein may change. For example, the peak PA 215 may provide a first peak signal having a first level in response to the bias signal being greater than a predetermined difference. Continuing with this example, the first level of the first peak signal may be greater than the first level of the first carrier signal. In some embodiments, the carrier PA 210 may provide a carrier signal having a first level. In some embodiments, the carrier signal may be greater than the peak signal. For example, the carrier PA 210 may provide a signal having a voltage level of 5V. Continuing with this example, the peak PA 215 may provide a peak signal having a voltage level of 0V in response to the bias signal being less than a predetermined threshold (e.g., the peak PA 215 is turned off).

[0103] In some embodiments, one or more signals described herein may be provided at one or more time intervals. For example, peak PA 215 may receive an excursion signal at a first point in time and carrier PA 210 may also receive a driver signal at a first point in time. As another example, carrier PA 210 may receive a driver signal at a first point in time and envelope detector 235 may receive a driver signal at a second point in time.

[0104] In some embodiments, at least one component of the schematic block diagram 200 may be positioned within and / or between one or more second components. Figure 2 An example of an impedance inverter 220 located between the peak PA 215 and the power combiner 225 is depicted. Figure 2 As illustrated in , impedance inverter 220 is also shown connected in series to peak PA 215 and power combiner 225.

[0105] Figure 3Schematic block diagram 300 is depicted according to some embodiments. In some embodiments, schematic block diagram 300 may include at least one component of schematic block diagram 200. In some embodiments, at least one of schematic block diagram 200 and / or schematic block diagram 300 may refer to and / or include a first configuration and / or a first orientation of a component. For example, in schematic block diagram 200, a signal may be provided to an input terminal of a device. As another example, in schematic block diagram 300, a signal may be provided to an output signal.

[0106] In some embodiments, schematic block diagram 300 may include one or more systems, devices, and / or components of system 100. For example, schematic block diagram 300 may include amplifier 120. In some embodiments, system 100 may include and / or be implemented as schematic block diagram 300. In some embodiments, at least one device and / or component of schematic block diagram 300 may be included in system 100 and / or implemented within system 100. In some embodiments, systems, devices, and / or components of schematic block diagram 300 may be added, removed, integrated, separated, rearranged, relocated, and / or replaced.

[0107] In some embodiments, schematic block diagram 300 may include at least one amplifier 305. In some embodiments, amplifier 305 may include at least one amplifier described herein. For example, amplifier 305 may include amplifier 120. In some embodiments, amplifier 305 may refer to and / or include a preamplifier. Figure 3 , schematic block diagram 300 includes a first driver 105 and a second driver 105. In some embodiments, the first driver 105 may drive the carrier PA 210 and the second driver 105 may drive the peaking PA 215. For example, the first driver 105 may provide a first driver signal to the carrier PA 210 and the second driver 105 may provide a second driver signal to the peaking PA 215. In some embodiments, schematic block diagram 300 may refer to and / or include multiple stages of amplification.

[0108] like Figure 3 , envelope detector 235 is shown as receiving a signal corresponding to an input signal provided to first driver 105. In some embodiments, envelope detector 235 may provide the signal to an input terminal of second driver 105. For example, envelope detector 235 may control a bias voltage between terminals of second driver 105. In some embodiments, envelope detector 235 may provide the signal to an input terminal of peak PA 215. For example, envelope detector 235 may provide an envelope signal described herein to peak PA 215.

[0109] Figure 4A schematic block diagram 400 is depicted according to some embodiments. In some embodiments, the schematic block diagram 400 may include one or more systems, devices, and / or components of the system 100. In some embodiments, the schematic block diagram 400 may include an implementation of the system 100. In some embodiments, at least one device and / or component of the schematic block diagram 400 may be included in the system 100. In some embodiments, the systems, devices, and / or components of the schematic block diagram 400 may be added, removed, integrated, separated, rearranged, relocated, and / or replaced.

[0110] like Figure 4 , the envelope detector 235 may receive one or more first signals indicative of inputs of the first driver 105 and one or more second signals indicative of inputs of the carrier PA 210. For example, the envelope detector 235 may be electrically coupled to the input terminals of the first driver 105 and the envelope detector 235 may detect the one or more signals provided to the input terminals of the first driver 105.

[0111] In some embodiments, envelope detector 235 may control second driver 105 separate from peaking PA 215. For example, envelope detector 235 may control second driver 105 based on a signal provided to the input of first driver 105. As another example, envelope detector 235 may control peaking PA 215 based on a signal output by carrier PA 210. In some embodiments, the linearity of the output signal may be controlled and / or adjusted in response to envelope detector 235 controlling second driver 105 and peaking PA 215 separately.

[0112] Figure 5 Schematic block diagram 500 is depicted in accordance with some embodiments, which in some embodiments may include one or more systems, devices, and / or components of system 100. In some embodiments, schematic block diagram 500 may include an implementation of system 100. In some embodiments, systems, devices, and / or components of schematic block diagram 500 may be added, removed, integrated, separated, rearranged, relocated, and / or substituted.

[0113] like Figure 5 , the envelope detector 235 may receive one or more first signals indicative of the input of the first driver 105 and the envelope detector 235 may receive one or more second signals indicative of the output of the carrier PA 210. For example, the envelope detector 235 may be electrically coupled to the output terminal of the carrier PA 210 and the envelope detector 235 may detect the one or more signals provided by the carrier PA 210.

[0114] In some embodiments, the schematic block diagram 500 may include a feedback configuration. For example, the output of the carrier PA 210 may be used by the envelope detector 235 to control the peak PA 215. In some embodiments, the envelope detector 235 may use the output signal of the carrier PA 210 to detect saturation of the carrier PA 210 (e.g., the output signal provided by the carrier PA 210 is no longer amplified based on the gain factor of the carrier PA 210). In some embodiments, the transmission strength of the carrier signal may fluctuate and / or change. For example, the voltage standing wave ratio (VSWR) of the carrier signal may change based on one or more loads. In some embodiments, the envelope detector 235 may control the bias voltage of the peak PA 215 to control when the peak PA 215 is turned on and / or off. The envelope detector 235 may adjust the linear sensitivity of the carrier PA 210 by controlling the bias voltage of the peak PA 215.

[0115] Figure 6 Schematic block diagram 600 is depicted according to some embodiments. In some embodiments, schematic block diagram 600 may include one or more systems, devices, and / or components of system 100. In some embodiments, schematic block diagram 600 may include an implementation of system 100. In some embodiments, systems, devices, and / or components of schematic block diagram 600 may be added, removed, integrated, separated, rearranged, relocated, and / or replaced. In some embodiments, schematic block diagram 600 may include at least one component and / or device described herein. For example, schematic block diagram 600 may include at least one component of schematic block diagram 200. Figure 6 As shown in FIG. 1 , the envelope detector 235 receives a signal corresponding to the terminal (at Figure 6 In some embodiments, envelope detector 235 may provide a signal to control the cascode bias of peak PA 215.

[0116] Figure 7 700 according to some embodiments. In some embodiments, the schematic block diagram 700 may include and / or be implemented as a peak PA 215. Figure 7 , the cascode bias is shown as defining and / or representing a difference between the terminals of the peak PA 215. In some embodiments, the peak PA 215 may provide one or more signals having a first level in response to the cascode bias being above a given value. In some embodiments, the peak PA 215 may be turned off in response to the cascode bias being below a given value. The cascode bias between the terminals of the amplifier may affect the performance and / or reliability of the amplifier. For example, the drain node (e.g. Figure 7The A+ and A- shown in FIG. 2 may cause the cascade bias voltage of the amplifier to vary. In some embodiments, the envelope detector 235 may control and / or adjust the cascade bias voltage to maintain the difference between the terminals of the peak PA 215 to reduce the variation of the peak PA 215.

[0117] Figure 8 Schematic block diagram 800 is depicted according to some embodiments. In some embodiments, schematic block diagram 800 may include at least one component and / or device of schematic block diagram 200. For example, Figure 8 , schematic block diagram 800 includes carrier PA 210, peak PA 215, impedance inverter 220, and power combiner 225. In some embodiments, at least one device and / or component of schematic block diagram 800 may be included in and / or implemented within system 100. In some embodiments, systems, devices, and / or components of schematic block diagram 800 may be added, removed, integrated, separated, rearranged, relocated, and / or replaced. For example, a device shown as including two capacitors may be modified to include only one capacitor.

[0118] In some embodiments, the impedance inverter 220 may include at least one capacitor and / or at least one inductor. Figure 8 2 as including two capacitors and two inductors (shown as L1 and L2). In some embodiments, the L2 inductor may be combined and / or incorporated with a transformer of the power combiner 225. For example, the L2 inductor may be combined with a transformer that is electrically coupled to the impedance inverter 220. Figure 8 An example of impedance inverter 220 implemented as a high-pass type device is depicted.

[0119] Fig. 9 Schematic block diagram 900 according to some embodiments is depicted. In some embodiments, schematic block diagram 900 may include at least one component and / or device of schematic block diagram 200. For example, Fig. 9 , schematic block diagram 900 includes impedance inverter 220. In some embodiments, at least one device and / or component of schematic block diagram 900 may be included in and / or implemented within system 100. In some embodiments, systems, devices, and / or components of schematic block diagram 900 may be added, removed, integrated, separated, rearranged, relocated, and / or replaced. For example, a device shown as including two capacitors may be modified to include only one capacitor. Fig. 9 An example of impedance inverter 220 implemented as a low-pass type device is depicted. In some embodiments, as Fig. 9 As shown in , the L1 and L2 inductors may be combined and / or modified so that the impedance inverter 220 includes a single inductor.

[0120] Fig.10 Schematic block diagram 1000 is depicted according to some embodiments. In some embodiments, schematic block diagram 1000 may include at least one component and / or device of schematic block diagram 200. For example, schematic block diagram 1000 may include carrier PA 210, peak PA 215, impedance inverter 220, and power combiner 225. Fig.10 , impedance inverter 220 is illustrated as being implemented as a high pass filter. In some embodiments, systems, devices, and / or components of schematic block diagram 1000 may be added, removed, integrated, separated, rearranged, relocated, and / or replaced. For example, a device shown as including two capacitors may be modified to include only one capacitor.

[0121] In some embodiments, L2 may be integrated and / or merged with at least one transformer of power combiner 225. In some embodiments, at least one system, device, and / or component described herein may include configurable and / or tunable elements. For example, carrier PA 210, peak PA 215, and impedance inverter 220 may include one or more tuning capacitors. Fig.10 Depicted are examples of carrier PA 210 and peak PA 215 each including a tuning capacitor and an example of impedance inverter 220 including three tuning capacitors. In some embodiments, the amount and / or number of tuning components may be modified, adjusted, updated, and / or otherwise changed. For example, carrier PA 210 may include two tuning capacitors. As another example, impedance inverter 220 may include a single tuning capacitor.

[0122] Fig.11 Schematic block diagram 1100 according to some embodiments is depicted. In some embodiments, schematic block diagram 1100 may include at least one component and / or device of schematic block diagram 200. For example, Fig.11 , schematic block diagram 1100 includes offset 245 and peak PA 215. In some embodiments, at least one device and / or component of schematic block diagram 1100 may be included in system 100 and / or implemented within system 100.

[0123] In some embodiments, systems, devices, and / or components of schematic block diagram 1100 may be added, removed, integrated, separated, rearranged, relocated, and / or replaced. For example, a device shown as including an inductor may be modified to include two inductors. In some embodiments, schematic block diagram 1100 may represent and / or indicate a circuit equivalent diagram. In some embodiments, offset 245 and / or one or more components thereof may offset at least one of the various signals described herein. For example, offset 245 may phase shift a driver signal by 90 degrees.

[0124] Fig.12A block diagram depicting a process 1200 of controlling an amplifier according to some embodiments. In some embodiments, at least one of the various systems, devices, and / or components described herein may perform one or more steps of process 1200. For example, device 110 may perform at least one step of process 1200. In some embodiments, at least one step of process 1200 may be repeated, reproduced, and / or otherwise performed again. For example, steps including receiving a first signal may be repeated in response to the device transmitting a subsequent first signal.

[0125] In step 1205, a first signal may be received. For example, the first signal may be received by device 110. In some embodiments, the first signal may refer to and / or include at least one of the various signals described herein. For example, the first signal may refer to a driver signal described herein. In some embodiments, device 110 may receive the first signal from driver 105. For example, device 110 may receive the first signal in response to driver 105 transmitting the first signal.

[0126] In some embodiments, the first signal may indicate a first power amount. For example, the first signal may have a first level indicating the first power amount and the first signal may have a second level indicating the second power amount. In some embodiments, the first power amount may indicate at least one of the various protocols described herein. For example, the first power amount may indicate communication via Bluetooth.

[0127] In some embodiments, device 110 may receive a first signal in response to driver 105 receiving a communication signal. For example, driver 105 may receive a signal for transmission using Bluetooth and driver 105 may provide a signal (eg, a first signal) to indicate transmission using Bluetooth.

[0128] In step 1210, in some embodiments, a second signal may be provided. For example, the second signal may be provided by carrier PA 210. In some embodiments, the second signal may be provided in response to receipt of the first signal. For example, the second signal may be provided in response to the device having received the first signal. In some embodiments, carrier PA 210 may provide the second signal to power combiner 225. In some embodiments, the second signal may refer to and / or include at least one of the various signals described herein. For example, the second signal may include a carrier signal described herein.

[0129] In some embodiments, the second signal may have one or more levels. For example, the second signal may have a first level and a second level. In some embodiments, the level of the second signal may be based on the first signal received in step 1205. For example, the second signal may have a first level based on one or more levels of the first signal.

[0130] In step 1215, a first level of the first signal may be detected. For example, the envelope detector 235 may detect that the first signal received in step 1205 has a first level. In some embodiments, the envelope detector 235 may receive the first signal. For example, the driver 105 may provide the first signal to the envelope detector 235. In some embodiments, the envelope detector 235 may determine that the driver 105 provides the first signal. The envelope detector 235 may detect the first level of the first signal in response to determining that the driver 105 provides the first signal.

[0131] In some embodiments, envelope detector 235 may detect that the first signal includes a first level in response to envelope detector monitoring the amount of power transmitted via line 255. For example, envelope detector 235 may detect that the first signal includes a first level in response to envelope detector 235 detecting the transmission of the first amount of power via line 255.

[0132] In step 1220, in some embodiments, a third signal may be provided. For example, the envelope detector 235 may provide the third signal. In some embodiments, the third signal may be provided to the peak PA 215. For example, the envelope detector 235 may provide the third signal to the peak PA 215. In some embodiments, the third signal may control one or more circuits. For example, the third signal may control the peak PA 215. In some embodiments, the third signal may control the one or more circuits by turning on and / or off at least one of the one or more circuits.

[0133] In some embodiments, the third signal may refer to and / or include at least one of the various signals described herein. For example, the third signal may include a bias signal described herein. In some embodiments, the third signal may control one or more circuits by defining a difference between one or more terminals. For example, the third signal may define a bias (e.g., a difference) between the terminals of the peak PA 215.

[0134] In step 1225, a fourth signal may be provided. For example, the peak PA 215 may provide the fourth signal. In some embodiments, the peak PA 215 may provide the fourth signal to the power combiner 225. In some embodiments, the fourth signal may refer to and / or include at least one of the various signals described herein. For example, the fourth signal may include the peak signal described herein. In some embodiments, the fourth signal may have one or more levels. For example, the fourth signal may have a first level in response to the difference being less than a predetermined value. In other words, the difference defined by the envelope detector 235 in step 1220 may cause the fourth signal to have a first level.

[0135] In some embodiments, the fourth signal may have a first level in response to the bias voltage between the terminals of the peak PA 215 being less than a predetermined threshold. In some embodiments, the peak PA 215 may be turned off in response to the bias voltage between the terminals of the peak PA 215 being less than a predetermined threshold. For example, the first level of the fourth signal may be 0V (e.g., the peak PA is turned off). In some embodiments, the fourth signal may have a second level in response to the difference being greater than a predetermined value. For example, the peak PA 215 may be turned on and the peak PA 215 may provide an amplified signal (e.g., the fourth signal having the second level).

[0136] In step 1230, in some embodiments, a fifth signal may be provided. For example, the power combiner 225 may provide the fifth signal. In some embodiments, the power combiner 225 may provide the fifth signal to one or more of the various systems, devices, and / or components described herein. In some embodiments, the fifth signal may have one or more levels. For example, the fifth signal may have a first level and a second level.

[0137] In some embodiments, the fifth signal may have a first level based on at least the second signal. For example, the fifth signal may be an amplification of the second signal. In some embodiments, the fifth signal may have a first level in response to the peak PA 215 being turned off. For example, when the peak PA 215 is turned off, the power combiner 225 may receive signals only from the carrier PA 210.

[0138] In some embodiments, the fifth signal may have a second level based on the second levels of the second signal and the fourth signal. For example, the fifth signal may be an amplification of the second signal and the fourth signal. In some embodiments, the second level of the fifth signal may be greater than the first level of the fifth signal. For example, the second level of the fifth signal may include and / or indicate the second levels of the second signal and the fourth signal. As another example, the first level of the fifth signal may indicate only the second signal.

[0139] In some embodiments, the fifth signal may include a percentage and / or ratio of the second signal and the fourth signal. For example, the fifth signal may be based on the percentage of the resistance element 230 experienced by the second signal and / or the fourth signal. In some embodiments, when the peak PA 215 is turned off, the second signal may experience the entire resistance element 230. For example, the resistance element 230 may be a 50Ohm resistor and the second signal may experience a 50Ohm resistance. In some embodiments, when the peak PA 215 is turned on, the resistance amount experienced by the second signal and the fourth signal may be separated. For example, the resistance element 230 may be a 40Ohm resistor and the second signal and the fourth signal may both experience a 20Ohm resistance (e.g., both experience half of the resistance element 230). Although some examples of discussing one or more adjustments of resistance have been described with respect to one or more resistance amounts (e.g., Ohms), one or more adjustments of resistance may also include adjustments of inductance and / or one or more adjustments of capacitance. For example, the resistance element 230 may include a capacitance element and the capacitance experienced may be changed and / or adjusted.

[0140] In some embodiments, carrier PA 210 may provide a continuous and / or constant signal. For example, the carrier signal described herein may have a voltage level of 2V in response to carrier PA 210 having received a drive signal having a voltage level of 1V. In some embodiments, carrier signal constant may refer to the voltage level of the carrier signal changing only in response to the driver signal changing.

[0141] The hardware systems described herein may be implemented in many different ways and in many different combinations of hardware and software and circuit design. For example, all or part of an implementation may be a circuit system including an instruction processor, such as a central processing unit (CPU), a microcontroller, or a microprocessor; an application specific integrated circuit (ASIC), a programmable logic device (PLO), or a field programmable gate array (FPGA); or a circuit system including discrete logic or other circuit components, including analog circuit components, digital circuit components, or both; or any combination thereof. As an example, the circuit system may include discrete interconnected hardware components and / or may be combined on a single integrated circuit die, distributed among multiple integrated circuit dies, or implemented in a multi-chip module (MCM) of multiple integrated circuit dies in a common package. In some embodiments, the circuit system may be provided on one or more integrated circuit dies in an integrated circuit package. In some embodiments, the integrated circuit package may be a combination of two or more packages.

[0142] The circuit system may further include or access instructions (e.g., software or firmware) that are executed by the circuit system. The instructions may be stored in a tangible storage medium other than a transient signal, such as flash memory, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM); or on a magnetic or optical disk, such as a compact disk read-only memory (CDROM), a hard disk drive (HDD), or other magnetic or optical disk; or in or on another machine-readable medium. A product, such as a computer program product, may include a storage medium and instructions stored in or on the medium, and the instructions, when executed by the circuit system in a device, may cause the device to perform any of the processes described above or illustrated in the drawings.

[0143] The embodiments may be distributed as a circuit system among multiple system components, such as among multiple processors and memories, optionally including multiple distributed processing systems. Parameters, databases, and other data structures may be stored and managed separately, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented in many different ways, including as data structures such as linked lists, hash tables, arrays, records, objects, or implicit storage mechanisms. Programs may be parts of a single program (such as subroutines), separate programs, distributed across several memories and processors, or implemented in many different ways, such as in libraries such as shared libraries (such as dynamic link libraries (DLLs)). For example, a DLL may store instructions that, when executed by the circuit system, perform any of the processes described above or illustrated in the drawings.

[0144] The term "coupling" and its variations include causing two components to be directly or indirectly coupled to each other. The term "electrically coupled" and its variations include causing two components to be directly or indirectly coupled to each other through a conductive material (e.g., a metal or copper trace). This coupling may be fixed (e.g., permanent or fixed) or movable (e.g., removable or releasable). This coupling may be achieved by: the two components are directly coupled to each other; the two components are coupled to each other using a separate intermediary component and any additional intermediate components that are coupled to each other; or the two components are coupled to each other using an intermediary component that is integrally formed as a single entity with one of the two components. If "coupling" or its variations are modified by additional terms (e.g., direct coupling), the general definition of "coupling" provided above is modified by the ordinary language meaning of the additional terms (e.g., "direct coupling" means that the two components are coupled without any separate intermediary components), resulting in a narrower definition than the general definition of "coupling" provided above. This coupling may be mechanical, electrical, or fluid.

[0145] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions should not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications to the present disclosure without departing from the spirit and scope of the present disclosure.

[0146] It should be noted that certain paragraphs of the present disclosure may refer to terms (e.g., "first" and "second") related to transmission spatial streams, sounding frames, responses, and subsets of devices for identifying or distinguishing one from another or from others. These terms are not intended to relate entities (e.g., first device and second device) only in time or according to a sequence, but in some cases, these entities may include such a relationship. These terms also do not limit the number of possible entities that can operate within a system or environment. It should be understood that the above-mentioned system may provide any or multiple of those components and that these components may be provided on a stand-alone machine or, in some embodiments, on multiple machines in a distributed system. In addition, the above-mentioned systems and methods may be provided as one or more computer-readable programs or executable instructions embodied on or in one or more articles of manufacture (e.g., floppy disk, hard disk, CD-ROM, flash memory card, PROM, RAM, ROM, or tape). The program may be implemented in any programming language (e.g., LISP, PERL, C, C++, C#) or any bytecode language (e.g., JAVA). The software program or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0147] Although the above written description of the methods and systems enables a person of ordinary skill to make and use embodiments thereof, the person of ordinary skill should understand and appreciate that there are variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Therefore, the methods and systems of the present invention should not be limited to the above-described embodiments, methods, and examples, but should be limited to all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A system comprising: a driver configured to provide a first signal indicating a first amount of power and having a first level; and A device, which communicates with the driver, comprising: A first circuit is configured to: providing, in response to receipt of the first signal, a second signal having a first level based on the first level of the first signal; A second circuit is configured to: detecting the first level of the first signal in response to receipt of the first signal; and providing a third signal to control a third circuit of the device in response to detection of the first level of the first signal, wherein the third signal controls the third circuit of the device by defining a difference between a first terminal and a second terminal of the third circuit of the device; The third circuit is configured to: providing a fourth signal in response to receiving the first signal and the third signal, the fourth signal having a first level in response to the difference being less than a predetermined value, and the fourth signal having a second level in response to the difference being greater than the predetermined value; and A fourth circuit configured to: A fifth signal is provided in response to receipt of the second signal and the fourth signal, the fifth signal having a first level based on the first level of the second signal, and the fifth signal having a second level based on the first level of the second signal and the second level of the fourth signal.

2. The system of claim 1, wherein: the fifth signal has the first level in response to the fourth signal having the first level; and The fifth signal has the second level in response to the fourth signal having the second level. 3 . The system of claim 1 , wherein the second level of the fifth signal is greater than the second level of the fourth signal, and wherein the second level of the fourth signal is greater than the first level of the second signal. 4 . The system of claim 1 , wherein the first level of the second signal is greater than the first level of the fourth signal, and wherein the first level of the second signal is less than the second level of the fourth signal.

5. The system of claim 1 , wherein the first level of the first signal has a first value in response to the first power amount being associated with a first mode of the device, and wherein the first level of the first signal has a second value in response to the first power amount being associated with a second mode of the device.

6. The system of claim 5, wherein the first mode of the device is associated with communications corresponding to a first protocol, and wherein the second mode of the device is associated with communications corresponding to a second protocol.

7. The system of claim 1, further comprising: A fifth circuit configured to: receiving the fourth signal before the fourth circuit; adjusting a first amount of resistance seen by the first circuit from a first value to a second value in response to the fourth signal having the first level; and providing the fourth signal to the fourth circuit in response to adjustment of the first resistance amount; wherein the second value of the first resistance specifies the first level of the fifth signal; The second value of the first resistance is greater than the first value of the first resistance.

8. The system of claim 7, wherein the fifth circuit is configured to adjust the first resistance amount by: modifying a second resistance value associated with the fourth signal from a first value to a second value; and The second value of the second resistance is smaller than the second value of the first resistance.

9. The system of claim 7, wherein the fifth circuit is positioned between the third circuit and the fourth circuit, and wherein the fifth circuit is positioned in series to the third circuit and the fourth circuit.

10. The system of claim 1, further comprising: A fifth circuit configured to: receiving the fourth signal before the fourth circuit; adjusting a first amount of resistance seen by the first circuit from a first value to a second value in response to the fourth signal having the second level; and providing the fourth signal to the fourth circuit in response to adjustment of the first resistance amount; wherein the second value of the first resistance is less than the first value of the first resistance; wherein an amount of the fifth signal based on the first level of the second signal decreases in response to the first resistance amount having the second value.

11. The system of claim 1, further comprising: the first circuit configured to receive a first instance of the first signal; and the third circuit configured to receive a second instance of the first signal; Wherein the second instance of the first signal is offset from the first instance of the first signal by a predetermined amount.

12. A device in communication with a driver, the device being configured to receive a first signal from the driver, and comprising: A first circuit is configured to: In response to receiving the first signal, providing a first level based at least on the first signal a second signal of a first level; A second circuit is configured to: detecting the first level of the first signal in response to receipt of the first signal; and providing a third signal to control a third circuit of the device in response to detection of the first level of the first signal, wherein the third signal controls the third circuit of the device by defining a difference between a first terminal and a second terminal of the third circuit of the device; The third circuit is configured to: providing a fourth signal in response to receiving the first signal and the third signal, the fourth signal having a first level in response to the difference being less than a predetermined value, and the fourth signal having a second level in response to the difference being greater than the predetermined value; and A fourth circuit configured to: A fifth signal is provided in response to receiving the second signal and the fourth signal, the fifth signal having a first level based at least on the first level of the second signal, and the fifth signal having a second level based at least on the first level of the second signal and the second level of the fourth signal.

13. The device according to claim 12, wherein: the fifth signal has the first level in response to the fourth signal having the first level; and The fifth signal has the second level in response to the fourth signal having the second level.

14. The device of claim 12, wherein the second level of the fifth signal is greater than the second level of the fourth signal, and wherein the second level of the fourth signal is greater than the first level of the second signal.

15. The device of claim 12, wherein the first level of the second signal is greater than the first level of the fourth signal, and wherein the first level of the second signal is less than the second level of the fourth signal.

16. The apparatus of claim 12, further comprising: A fifth circuit configured to: receiving the fourth signal before the fourth circuit; adjusting a first amount of resistance seen by the first circuit from a first value to a second value in response to the fourth signal having the first level; and providing the fourth signal to the fourth circuit in response to adjustment of the first resistance amount; wherein the second value of the first resistance specifies the first level of the fifth signal; The second value of the first resistance is greater than the first value of the first resistance.

17. The apparatus of claim 12, further comprising: A fifth circuit configured to: receiving the fourth signal before the fourth circuit; adjusting a first amount of resistance seen by the first circuit from a first value to a second value in response to the fourth signal having the second level; and providing the fourth signal to the fourth circuit in response to adjustment of the first resistance amount; wherein the second value of the first resistance is less than the first value of the first resistance; wherein an amount of the fifth signal based on the first level of the second signal decreases in response to the first resistance amount having the second value.

18. A method comprising: receiving, by the device, a first signal from a driver indicating a first amount of power and having a first level; providing, by a first circuit of the device in response to receipt of the first signal, a second signal having a first level based at least on the first level of the first signal; detecting, by a second circuit of the device in response to receipt of the first signal, the first level of the first signal; providing, by the second circuit of the device in response to detection of the first level of the first signal, a third signal to control a third circuit of the device, wherein the third signal controls the third circuit of the device by defining a difference between a first terminal and a second terminal of the third circuit of the device; providing, by the third circuit of the device in response to receiving the first signal and the third signal, a fourth signal having a first level in response to the difference being less than a predetermined value, and having a second level in response to the difference being greater than the predetermined value; and A fifth signal is provided by a fourth circuit of the device in response to receiving the second signal and the fourth signal, the fifth signal having a first level based at least on the first level of the second signal, and the fifth signal having a second level based at least on the first level of the second signal and the second level of the fourth signal.

19. The method according to claim 18, wherein: the first level of the first signal having a first value in response to the first amount of power being associated with a first mode of the apparatus; the first level of the first signal having a second value in response to the first amount of power being associated with a second mode of the apparatus; The first mode of the apparatus relates to communications corresponding to a first protocol; and The second mode of the apparatus relates to communications corresponding to a second protocol.

20. The method of claim 18, further comprising: receiving, by a fifth circuit of the device, the fourth signal before the fourth circuit; adjusting, by the fifth circuit of the device, a first amount of resistance seen by the first circuit from a first value to a second value in response to the fourth signal having the first level; and providing, by the first circuit of the device, the fourth signal to the fourth circuit in response to the adjustment of the first resistance amount; wherein the second value of the first resistance specifies the first level of the fifth signal; The second value of the first resistance is greater than the first value of the first resistance.

Images