Communication method and communication device based on LDPC (Low Density Parity Check) code

Abstract

A communication method and a communication device based on LDPC code may perform encoding or decoding based on a storage matrix and indication information, the indication information may include first information, and each of a plurality of row pairs indicated by the first information includes two rows, a set composed of the column numbers of the columns where the non-zero elements in the first x elements of the first row in the two rows are located is a proper subset of a set composed of the column numbers of the columns where the non-zero elements in the first x elements of the second row in the two rows are located, and therefore splitting expansion is achieved in the low-code-rate expansion process. In other words, the first row can be eliminated on the basis of adding the second row, so that the orthogonality between the rows is improved. Moreover, the plurality of first rows indicated by the first information can form one or more row groups, and the first rows included in each row group have an association relationship, so that the orthogonality can be further improved based on the association relationship. Therefore, the orthogonality between rows can be improved, and the decoding performance can be improved.

Description

Technical Field

[0001] The present application relates to the field of coding, and more specifically, to a communication method and a communication device based on LDPC codes. Background Art

[0002] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. In current LDPC codes, the orthogonality between rows of the LDPC base matrix is ​​low, which affects the efficiency and performance of decoding. For example, the edge density of the high-rate part of the new radio (NR) LDPC code is large, and the rows are usually not orthogonal, and only quasi-cyclic (QC) blocks are supported for parallel decoding. Summary of the invention

[0003] The embodiments of the present application provide a communication method and a communication device based on LDPC codes, which are helpful to improve decoding performance.

[0004] In a first aspect, a communication method based on LDPC codes is provided, which can be executed by a transmitting device or by a module or unit in the transmitting device (eg, a chip). The transmitting device can be a terminal device or a network device.

[0005] The method comprises: acquiring an information bit sequence; performing LDPC encoding on the information bit sequence according to a first LDPC base matrix and indication information to obtain an LDPC codeword sequence; wherein the indication information comprises first information, the first information being used to indicate a plurality of row pairs, each row pair of the plurality of row pairs comprising a first row and a second row, a set consisting of column numbers of columns where non-zero elements among the first x elements of the first row of the row pair are located is a proper subset of a set consisting of column numbers of columns where non-zero elements among the first x elements of the second row of the row pair are located, and x is a positive integer; the plurality of first rows indicated by the first information constitute one or more row groups, each row group of the one or more row groups comprises at least two first rows, the column weight of each column of a matrix region constituted by the second rows corresponding to the at least two first rows is less than or equal to 2, and the at least two first rows are associated with each other; and the LDPC codeword sequence is sent.

[0006] Exemplarily, x is the total number of information columns and core check columns.

[0007] In the above method, each row pair of the multiple row pairs indicated by the first information includes two rows, and the set consisting of the column numbers of the columns where the non-zero elements in the first x elements of the first row of the two rows are located is a proper subset of the set consisting of the column numbers of the columns where the non-zero elements in the first x elements of the second row of the two rows are located, so that split expansion can be supported in the low code rate expansion process, that is, the first row can be eliminated on the basis of adding the second row to improve the orthogonality between rows. And the multiple first rows indicated by the first information can form one or more row groups, and at least two first rows included in each row group have an association relationship, so that the orthogonality can be further increased based on the association relationship. For example, based on the association relationship, the rows corresponding to the first row in a row group in the second LDPC base matrix and the rows corresponding to the second row in the row group in the second LDPC base matrix can be regrouped so that the rows in each newly obtained group are completely orthogonal. Therefore, based on the above method, the orthogonality between rows can be improved, which is helpful to realize row parallel decoding of the receiving end device, thereby improving the decoding performance.

[0008] In combination with the first aspect, in some implementations, performing LDPC encoding on the information bit sequence according to the first LDPC base matrix and the indication information to obtain an LDPC codeword sequence includes: obtaining a second LDPC base matrix according to the first LDPC base matrix and the indication information; performing LDPC encoding on the information bit sequence according to the second LDPC base matrix to obtain an LDPC codeword sequence, wherein the row of the second LDPC base matrix corresponding to the first row is obtained by eliminating the second row in the same row pair by the first row.

[0009] In the above implementation, when obtaining the second LDPC base matrix used for encoding, the row of the second LDPC base matrix corresponding to the first row is obtained by eliminating the second row in the same row pair by the first row. This can improve the orthogonality between rows, help to achieve row parallel decoding of the receiving device, and thus improve the decoding performance.

[0010] In combination with the first aspect or any implementation manner thereof, in other implementation manners, the association relationship includes a first association relationship and / or a second association relationship. The two first rows with the first association relationship are mutually orthogonal, and the union of the column numbers of the columns where the non-zero elements of the two first rows are located includes the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located; the two first rows with the second association relationship have the same connecting edge at the first position, and the column number at the first position belongs to the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located.

[0011] In the above implementation, a possible implementation of the association relationship between at least two first rows included in a row group is provided. Based on these possible implementations, the rows corresponding to the first rows in a row group in the second LDPC base matrix and the rows corresponding to the second rows in the first row in the row group in the second LDPC base matrix can be regrouped so that the rows in each newly obtained group are completely orthogonal.

[0012] Exemplarily, the rows in the second LDPC base matrix corresponding to the first row in a row group and the rows in the second LDPC base matrix corresponding to the second row corresponding to the first row in the row group can be divided into two groups, respectively referred to as the first row set and the second row set, wherein the union of the first row set and the second row set includes the rows in the second LDPC base matrix corresponding to the first row in a row group, and the rows in the second LDPC base matrix corresponding to the second row corresponding to the first row in the row group.

[0013] The first row set is composed of rows in the second LDPC base matrix corresponding to rows in the first subset and / or rows in the second LDPC base matrix corresponding to rows in the second subset. The rows in the first subset are all first rows, and the first rows in the first subset have a first association relationship with each other, and the rows in the second subset are all second rows, and the first row corresponding to the second row in the second subset has a second association relationship with the first row in the first subset.

[0014] The second row set is composed of rows in the second LDPC base matrix corresponding to rows in the third subset and / or rows in the second LDPC base matrix corresponding to rows in the fourth subset. The third subset is composed of the second row corresponding to the first row in the first subset, the fourth subset is composed of the first row corresponding to the second row in the second subset, and the first rows in the fourth subset have a first association relationship between each other.

[0015] It should be noted that when there is only one row in the first row set, the first subset, the second subset, the second row set, the third subset or the fourth subset, the definition of these sets may not involve the description of the first association relationship and / or the second association relationship.

[0016] In combination with the first aspect or any implementation thereof, in some other implementations, in any combination of the at least two first rows, the number of combinations having the first association relationship and the number of combinations having the second association relationship are related to the number of the first rows included in the at least two first rows.

[0017] In combination with the first aspect or any implementation manner thereof, in some other implementation manners, in any combination of the at least two first rows, The combination has the first association relationship, combinations have the second association relationship, wherein k is the number of the first rows included in the at least two first rows, represents the number of combinations of selecting two rows from ki rows, represents the number of combinations of selecting two rows from k rows, represents the number of combinations of any two rows selected from the i rows, Indicates rounding down.

[0018] Based on the quantitative relationship between the combinations with the first association relationship and the combinations with the second association relationship provided in the above embodiments, it is possible to regroup the rows corresponding to the first row in a row group in the second LDPC base matrix and the rows corresponding to the second row in the first row in the row group in the second LDPC base matrix so that the rows in each newly obtained group are completely orthogonal.

[0019] In combination with the first aspect or any implementation manner thereof, in other implementation manners, for a row group including k first rows, the number of combinations having the first association relationship and the number of combinations having the second association relationship are allocated in a total of In this case, in the combination of the first two rows in the row group, The combination has the first association relationship. The combination has a second association relationship, represents the number of combinations of selecting two rows from ki rows, represents the number of combinations of selecting two rows from k rows, represents the number of combinations of any two rows selected from the i rows, Indicates rounding up.

[0020] Based on the quantitative relationship between the combinations with the first association relationship and the combinations with the second association relationship provided in the above embodiments, it is possible to regroup the rows corresponding to the first row in a row group in the second LDPC base matrix and the rows corresponding to the second row in the first row in the row group in the second LDPC base matrix so that the rows in each newly obtained group are completely orthogonal.

[0021] In combination with the first aspect or any implementation manner thereof, in some other implementation manners, each row pair of the multiple row pairs corresponds to two rows of the first LDPC basis matrix; the indication information is in the form of a sequence, and the first information is a sequence consisting of the row number of the second row of each row pair in the one or more row pairs; in one of the row pairs, the position of the row number of the second row in the sequence corresponding to the indication information is the row number of the first row, and the position of the row number of the second row in the sequence corresponding to the indication information is greater than the row number of the first row.

[0022] In combination with the first aspect or any implementation manner thereof, in some other implementation manners, the sequence corresponding to the first information includes one or more segments, and the row number in the t-th segment of the one or more segments is {1, 2, ..., 2 t-1 M-1,2 t-1 M}, where t and M are positive integers.

[0023] Exemplarily, M may be the number of core rows.

[0024] In the above implementation, each row number appears only once in a round of splitting, so multiple splitting included in each round can be executed in parallel, which helps to improve the splitting efficiency.

[0025] In combination with the first aspect or any implementation thereof, in some other implementations, the indication information further includes second information, and the second information is used to indicate one or more third rows. The one or more third rows of the second LDPC base matrix are the same as the one or more third rows of the first LDPC base matrix.

[0026] The second information may correspond to a traditional extension or a normal extension.

[0027] In the above implementation, the indication information includes two types of information, one type of information is used to indicate one or more row pairs, corresponding to split expansion, and the other type of information is used to indicate one or more rows, corresponding to traditional expansion. In this way, the indication information can indicate two different low code rate expansion methods through these two types of information. In other words, in the low code rate expansion process, there are two ways to expand, and which of the two methods a certain expansion is can be determined by the indication information. In this way, compared with using only one expansion method, the low code rate expansion of the above method is more flexible, which helps to obtain an LDPC base matrix with better performance.

[0028] In combination with the first aspect or any implementation thereof, in some other implementations, the second information includes one or more first characters, and positions of the one or more first characters in the sequence corresponding to the indication information correspond to row numbers of the one or more third rows.

[0029] In combination with the first aspect or any implementation thereof, in some other implementations, the indication information further includes third information, and the third information is used to indicate one or more fourth rows. Wherein, the one or more fourth rows of the second LDPC base matrix are the same as the one or more fourth rows of the first LDPC base matrix. The row indicated by the fourth information can be a core row of the second LDPC base matrix.

[0030] In combination with the first aspect or any implementation thereof, in some other implementations, the third information includes M second characters or M row numbers, and the M row numbers are 1, 2, ..., M-1, M, respectively, where M is a positive integer.

[0031] Exemplarily, M may be the number of core rows.

[0032] In combination with the first aspect or any implementation thereof, in some other implementations, the first character and / or the second character is a value other than a row number of the first LDPC basis matrix.

[0033] By setting the first character or the second character to a value other than the row number of the first LDPC base matrix, the first character or the second character can be well distinguished from the row number in the first information.

[0034] In combination with the first aspect or any implementation manner thereof, in some other implementation manners, the sequence corresponding to the indication information includes a first segment, a second segment, a third segment, a fourth segment and a fifth segment in sequence, wherein the first segment is composed of the third information, the second segment is composed of the first part of the second information, the third segment is composed of the first part of the first information, the fourth segment is composed of the second part of the first information and the second part of the second information, and the fifth segment is composed of the third part of the second information.

[0035] Based on the above sequence, it helps to ensure that each expansion maintains the optimal edge density.

[0036] In combination with the first aspect or any implementation manner thereof, in some other implementation manners, the third segment includes one or more sub-segments, and the row number in the rth segment of the one or more sub-segments is {1, 2, ..., 2 r-1 (M+T)-1,2 r -1 (M+T)}, wherein r is a positive integer and T is the number of characters in the first part of the second information.

[0037] Exemplarily, M may be the number of core rows.

[0038] In the above implementation, each row number appears only once in a round of splitting, so multiple splitting included in each round can be executed in parallel, which helps to improve the splitting efficiency.

[0039] In a second aspect, a communication method based on LDPC codes is provided, which can be executed by a receiving device or by a module or unit in the receiving device (e.g., a chip). The receiving device can be a terminal device or a network device. The terms or features in the second aspect or its implementation that are the same or corresponding to those in the first aspect or its implementation can refer to the first aspect or its implementation, and its technical effects can refer to the technical effects in the first aspect or its implementation, and will not be repeated in the second aspect.

[0040] The method comprises: receiving an LDPC codeword sequence; decoding the LDPC codeword sequence according to a first LDPC base matrix and indication information; wherein the indication information comprises first information, the first information being used to indicate a plurality of row pairs, each of the plurality of row pairs comprising a first row and a second row, a set consisting of column numbers of columns where non-zero elements among the first x elements of the first row of the row pair are located is a proper subset of a set consisting of column numbers of columns where non-zero elements among the first x elements of the second row of the row pair are located, and x is a positive integer; the plurality of first rows indicated by the first information constitute one or more row groups, each of the one or more row groups comprises at least two first rows, a column weight of each column of a matrix region constituted by the second rows corresponding to the at least two first rows is less than or equal to 2, and the at least two first rows are associated with each other.

[0041] In combination with the second aspect, in some implementations, decoding the LDPC codeword sequence according to the first LDPC base matrix and the indication information includes: obtaining a second LDPC base matrix according to the first LDPC base matrix and the indication information; decoding the LDPC codeword sequence according to the second LDPC base matrix, wherein the row of the second LDPC base matrix corresponding to the first row is obtained by eliminating the second row in the same row pair by the first row.

[0042] In combination with the second aspect or any implementation manner thereof, in other implementation manners, the association relationship includes a first association relationship and / or a second association relationship. The two first rows with the first association relationship are mutually orthogonal, and the union of the column numbers of the columns where the non-zero elements of the two first rows are located includes the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located; the two first rows with the second association relationship have the same connecting edge at the first position, and the column number at the first position belongs to the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located.

[0043] In combination with the second aspect or any implementation manner thereof, in other implementation manners, the decoding of the LDPC codeword sequence according to the second LDPC base matrix includes: performing row-parallel decoding on the portion of the LDPC codeword sequence corresponding to the rows in the first row set, and performing row-parallel decoding on the portion of the LDPC codeword sequence corresponding to the rows in the second row set. Wherein, the union of the first row set and the second row set includes the rows corresponding to the at least two first rows in the second LDPC base matrix, and the rows corresponding to the second rows corresponding to the at least two first rows in the second LDPC base matrix. The first row set is composed of the rows corresponding to the rows in the first subset in the second LDPC base matrix and / or the rows corresponding to the rows in the second subset in the second LDPC base matrix, the rows in the first subset are all the first rows and the first rows in the first subset have the first association relationship between each other, and the rows in the second subset are all the second rows and the first rows corresponding to the second rows in the second subset have the second association relationship with the first rows in the first subset. The second row set consists of rows in the second LDPC base matrix corresponding to rows in the third subset and / or rows in the second LDPC base matrix corresponding to rows in the fourth subset, the third subset consists of the second rows corresponding to the first rows in the first subset, the fourth subset consists of the first rows corresponding to the second rows in the second subset, and the first rows in the fourth subset have the first association relationship in pairs.

[0044] In combination with the second aspect or any implementation thereof, in some other implementations, in any combination of the at least two first rows, the number of combinations having the first association relationship and the number of combinations having the second association relationship are related to the number of the first rows included in the at least two first rows.

[0045] In combination with the second aspect or any implementation manner thereof, in some other implementation manners, in any combination of the at least two first rows, The combination has the first association relationship, combinations have the second association relationship, wherein k is the number of the first rows included in the at least two first rows, represents the number of combinations of any two rows selected from ki rows, represents the number of combinations of selecting two rows from k rows, represents the number of combinations of any two rows selected from the i rows, Indicates rounding down.

[0046] In combination with the second aspect or any implementation manner thereof, in other implementation manners, for a row group including k first rows, the number of combinations having the first association relationship and the number of combinations having the second association relationship are allocated in a total of In this case, in the combination of the first two rows in the row group, The combination has the first association relationship. The combination has a second association relationship, represents the number of combinations of selecting two rows from ki rows, represents the number of combinations of selecting two rows from k rows, represents the number of combinations of any two rows selected from the i rows, Indicates rounding up.

[0047] In combination with the second aspect or any implementation manner thereof, in some other implementation manners, each row pair of the multiple row pairs corresponds to two rows of the first LDPC basis matrix; the indication information is in the form of a sequence, and the first information is a sequence consisting of the row number of the second row of each row pair in the one or more row pairs; in one of the row pairs, the position of the row number of the second row in the sequence corresponding to the indication information is the row number of the first row, and the position of the row number of the second row in the sequence corresponding to the indication information is greater than the row number of the first row.

[0048] In combination with the second aspect or any implementation manner thereof, in some other implementation manners, the sequence corresponding to the first information includes one or more segments, and the row number in the t-th segment of the one or more segments is {1, 2, ..., 2 t-1 M-1,2 t-1 M}, where t and M are positive integers.

[0049] In combination with the second aspect or any implementation manner thereof, in some other implementation manners, the indication information further includes second information, and the second information is used to indicate one or more third rows.

[0050] In combination with the second aspect or any implementation thereof, in some other implementations, the second information includes one or more first characters, and positions of the one or more first characters in the sequence corresponding to the indication information correspond to row numbers of the one or more third rows.

[0051] In combination with the second aspect or any implementation manner thereof, in some other implementation manners, the indication information further includes third information, and the third information is used to indicate one or more fourth rows.

[0052] In combination with the second aspect or any implementation thereof, in some other implementations, the third information includes M second characters or M row numbers, and the M row numbers are 1, 2, ..., M-1, M, respectively, where M is a positive integer.

[0053] In combination with the second aspect or any implementation thereof, in some other implementations, the first character and / or the second character is a value other than a row number of the first LDPC basis matrix.

[0054] In combination with the second aspect or any implementation manner thereof, in some other implementation manners, the sequence corresponding to the indication information includes a first segment, a second segment, a third segment, a fourth segment and a fifth segment in sequence, wherein the first segment is composed of the third information, the second segment is composed of the first part of the second information, the third segment is composed of the first part of the first information, the fourth segment is composed of the second part of the first information and the second part of the second information, and the fifth segment is composed of the third part of the second information.

[0055] In combination with the second aspect or any implementation manner thereof, in some other implementation manners, the third segment includes one or more sub-segments, and the row number in the rth segment of the one or more sub-segments is {1, 2, ..., 2 r-1 (M+T)-1,2 r -1 (M+T)}, wherein r is a positive integer and T is the number of characters in the first part of the second information.

[0056] In a third aspect, a communication device is provided, which is used to execute the method provided by any one of the above aspects or its implementation. Specifically, the device may include units and / or modules, such as a processing unit and / or a transceiver unit, for executing the method provided by any one of the above aspects or its implementation.

[0057] In one implementation, the apparatus is a transmitting end device or a receiving end device. When the apparatus is a transmitting end device or a receiving end device, the transceiver unit may be a transceiver, or an input / output interface, or a communication interface; the processing unit may be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0058] In another implementation, the device is a chip, a chip system or a circuit used in a transmitting device or a receiving device. When the device is a chip, a chip system or a circuit used in a transmitting device or a receiving device, the transceiver unit may be an input / output interface, an interface circuit, an output circuit, an input circuit, a pin or a related circuit on the chip, the chip system or the circuit; the processing unit may be at least one processor, a processing circuit or a logic circuit.

[0059] In a fourth aspect, a communication device is provided, comprising: a memory for storing programs; and at least one processor for executing computer programs or instructions stored in the memory to execute the method provided by any one of the above aspects or its implementation.

[0060] In one implementation, the apparatus is a transmitting end device or a receiving end device.

[0061] In another implementation, the apparatus is a chip, a chip system or a circuit used in a transmitting device or a receiving device.

[0062] In a fifth aspect, a communication device is provided, the device comprising: at least one processor and a communication interface, the at least one processor is used to obtain a computer program or instruction stored in a memory through the communication interface to execute the method provided by any one of the above aspects or its implementation. The communication interface can be implemented by hardware or software.

[0063] In one implementation, the device also includes the memory.

[0064] In a sixth aspect, a processor is provided for executing the methods provided in the above aspects.

[0065] For the operations such as sending and acquiring / receiving involved in the processor, if there is no special explanation, or if it does not conflict with its actual function or internal logic in the relevant description, then it can be understood as operations such as processor output and reception, input, etc., and can also be understood as sending and receiving operations performed by the radio frequency circuit and antenna. This application does not limit this.

[0066] In a seventh aspect, a computer-readable storage medium is provided, which stores a program code for execution by a device, wherein the program code includes a method for executing any of the above aspects or its implementation.

[0067] In an eighth aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to execute the method provided by any one of the above aspects or its implementation.

[0068] In a ninth aspect, a chip is provided, the chip comprising a processor and a communication interface, the processor reads instructions stored in a memory through the communication interface, and executes the method provided by any one of the above aspects or its implementation. The communication interface can be implemented by hardware or software.

[0069] Optionally, as an implementation method, the chip also includes a memory, in which a computer program or instructions are stored, and the processor is used to execute the computer program or instructions stored in the memory. When the computer program or instructions are executed, the processor is used to execute the method provided by any one of the above aspects or its implementation methods.

[0070] Among them, when the method provided by the present application is executed by a chip, the present application does not limit the number of chips that specifically implement the method of the present application. For example, it can be executed by one chip or by two or more chips. Moreover, when the number of chips that implement the method of the present application is two or more, the chip manufacturers are not limited and can be the same manufacturer or different manufacturers.

[0071] In a tenth aspect, a communication system is provided, comprising at least one of the transmitting device or the receiving device described above.

[0072] In an eleventh aspect, a computer program is provided, which, when executed on a computer, enables the method provided by any one of the above aspects or its implementation to be executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1 It is a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0074] Figure 2 Schematic diagram of an LDPC check matrix H.

[0075] Figure 3 is the Tanner graph of a LDPC check matrix H.

[0076] Figure 4 It is a schematic diagram of the structure of the check matrix.

[0077] Figure 5 An example of a non-column-regularized grouping structure and a column-regularized grouping structure is shown.

[0078] Figure 6 is an example of traditional expansion and split expansion.

[0079] Figure 7 It is a schematic flowchart of a communication method 700 based on LDPC code provided in the present application.

[0080] Figure 8 This is a schematic diagram of the first association relationship.

[0081] Fig. 9 This is a schematic diagram of the second association relationship.

[0082] Fig.10 It is an example of the technical solution of the embodiment of the present application.

[0083] Fig.11 It is another example of the technical solution of the embodiment of the present application.

[0084] Fig.12 It is another example of the technical solution of the embodiment of the present application.

[0085] Fig.13 It is another example of the technical solution of the embodiment of the present application.

[0086] Fig.14 This is a simulation result of the difference in signal-noise ratio (SNR) between the NR LDPC code and the LDPC code of the present application at different code rates.

[0087] Fig.15 This is the second simulation result of the difference between the SNR of the NR LDPC code and the LDPC code of this application at different code rates.

[0088] Fig.16 It is a structural schematic diagram of the device provided in the embodiment of the present application.

[0089] Fig.17 It is another structural schematic diagram of the device provided in an embodiment of the present application.

[0090] Fig.18 It is a schematic diagram of a chip system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0091] To facilitate understanding of the embodiments of the present application, the following points are explained before introducing the embodiments of the present application.

[0092] "For indicating" or "indicating" may include direct indication and indirect indication, or "for indicating" or "indicating" may be indicated explicitly and / or implicitly. The first, second, and other digital numbers are only used for the convenience of description, and are not used to limit the scope of the embodiments of the present application, such as distinguishing different messages, different information, etc. "Pre-definition" can be implemented by pre-saving the corresponding code, table or other methods that can be used to indicate relevant information in the device, and the present application does not limit its specific implementation method. The "protocol" involved may refer to a standard protocol in the field of communication, such as the long term evolution (LTE) protocol, the NR protocol, and related protocols used in future communication systems, and the present application does not limit this. "Example", "for example", "exemplarily", "as (another) example" and other words are used to indicate examples, illustrations or explanations. Any embodiment or design described as an "example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized. "At least one" means one or more, and "more than one" means two or more. "At most one" means one or zero. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or plural, respectively. The descriptions of network element A sending a message, information or data to network element B, and network element B receiving a message, information or data from network element A, are intended to explain to which network element the message, information or data is to be sent, but do not limit whether they are sent directly or indirectly via other network elements. Descriptions such as "when...", "under the circumstances of...", "if" and "if" all mean that the device will make corresponding processing under certain objective circumstances, but do not limit the time, nor do they require the device to have a judgment action when implementing, nor do they mean that there are other limitations.

[0093] In addition, the network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0094] A communication system to which the embodiments of the present application can be applied is described below.

[0095] Embodiments of the present application can be applied to various communication systems, including but not limited to: fifth generation (5th generation, 5G) system or NR system, LTE system, long term evolution-advanced (long term evolution-advanced, LTE-A) system, LTE frequency division duplex (frequency division duplex, FDD) system, LTE time division duplex (time division duplex, TDD) system, etc. It can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (device to device, D2D) communication, vehicle-to-everything (vehicle-to-everything, V2X) communication, machine to machine (machine to machine, M2M) communication, machine type communication (machine type communication, MTC), Internet of things (Internet of things, IoT) communication system, narrow band Internet of things system (narrow band-internet of things, NB-IoT) or other communication systems. In addition, the present invention can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and communication systems related to the 3rd generation partnership project (3GPP), without limitation.

[0096] The communication system applicable to the embodiments of the present application may include one or more transmitting end devices and one or more receiving end devices. Optionally, one of the transmitting end device and the receiving end device may be a terminal device, and the other may be a network device. Optionally, the transmitting end device and the receiving end device may both be terminal devices. Optionally, the transmitting end device and the receiving end device may both be network devices.

[0097] For example, Figure 1 A schematic diagram of a network architecture to which embodiments of the present application may be applied is shown.

[0098] like Figure 1 As shown, the embodiments of the present application can be applied to both uplink data transmission and downlink data transmission. Figure 1 Only uplink data transmission or downlink data transmission between a network device and two terminal devices (such as terminal device 1 and terminal device 2) is taken as an example. In uplink data transmission, the transmitting device in this article is a terminal device, and the receiving device is a network device; conversely, in downlink data transmission, the transmitting device is a network device, and the receiving device is a terminal device. In addition, the applicability of the embodiments of the present application in other communication scenarios is not limited. For example, it can also be applied to sidelink communication.

[0099] The terminal device of the present application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication device, user agent or user device, etc. The terminal device in the embodiment of the present application may refer to a device that provides voice and / or data connectivity to a user, and may be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer (pad), a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0100] The network device of the present application may be a device with wireless transceiver functions, and the network device may be a device that provides wireless communication function services, usually located on the network side, including but not limited to the next generation base station (gNodeB, gNB) in the 5G system, the base station in the sixth generation mobile communication system, the base station in the future mobile communication system, or the access node in the wireless fidelity (wireless fidelity, WiFi) system, the evolved node B (evolved node B, eNB) in the long term evolution (long term evolution, LTE) system, the radio network controller (radio network controller, RNC), node B (node ​​B, NB), base station controller (base station controller, BSC), home base station (for example, home evolved NodeB or home Node B, HNB), base band unit (base band unit, BBU), transmission reception point (transmission reception point, TRP), transmitting point (transmitting point, TP), base transceiver station (base transceiver station, BTS), satellite, drone, etc. In a network structure, the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, a relay station, a vehicle-mounted device, and a wearable device in a cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip used to be set in the aforementioned device or apparatus. The base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a 6G network, a device that performs the base station function in a future communication system, and the like. The base station can support networks with the same or different access technologies without limitation.

[0101] Unless otherwise specified, the device used to implement the function of the terminal device or network device in this application may refer to the terminal device or network device itself, or may refer to a device that can support the terminal device or network device to implement the function, such as a chip system or chip, specifically, a system on a chip (SoC), a modem. The device can be installed in the terminal device or network device. In the embodiment of the present application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0102] It should also be noted that some embodiments of this document use the 5G system as an example to introduce specific solution details. It is understandable that when the solution is used in other communication systems, such as the LTE system, or future communication systems, the messages, channels or information in the solution can be replaced by messages, channels or information in other communication systems that can achieve corresponding functions, and this application does not limit this.

[0103] In addition, the embodiments of the present application can be applied to various application scenarios, such as high throughput scenarios, high reliability scenarios, low latency scenarios, high reliability and low latency scenarios or low power consumption scenarios. Among them, the high throughput scenario can be, for example, an enhanced mobile broadband (Enhanced Mobile Broadband, eMBB) scenario, etc., the high reliability and low latency scenario can be, for example, a URLLC (UltraReliable Low Latency Communication) scenario, etc., and the low power consumption scenario can be, for example, an M2M scenario, an MTC scenario or an IoT scenario.

[0104] In order to facilitate the understanding of the embodiments of the present application, several concepts or terms involved in the embodiments of the present application are briefly explained. The concepts or terms introduced below are explained based on the concepts or terms specified in the reference protocol, but it does not mean that the embodiments of the present application can only be applied to currently existing systems. The concepts or terms involved in the embodiments of the present application can be applied to future systems. And the specific names of the concepts or terms (such as concepts or terms involving functional descriptions) can be adjusted with the development of future systems.

[0105] 1. LDPC Code

[0106] LDPC code is a linear block code, and its check matrix is ​​a sparse matrix. The number of zero elements in the LDPC check matrix is ​​much greater than the number of non-zero elements, or in other words, the row weight and column weight of the check matrix are very small numbers compared to the LDPC code length. Among them, the LDPC code with the information bit sequence length equal to q and the code length equal to n can be uniquely determined by its check matrix.

[0107] In 1981, Tanner expressed the LDPC codeword in the form of a graph. This graph is now called a Tanner graph. The Tanner graph corresponds to the check matrix one by one. The Tanner graph consists of two types of vertices. One type of vertex represents the codeword bits, called variable nodes, and the other type of vertex is a check node, which represents a check constraint relationship. Each check node represents a check constraint relationship. Figure 2 and Figure 3 Provide explanation.

[0108] Figure 2 Schematic diagram of an LDPC check matrix H.

[0109] Figure 2 In {V i} represents a variable node (VN) set, {C i} represents a check node (CN) set. Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, each column represents a code word bit, and each code word bit corresponds to a variable node. Figure 2 In the example, there are 8 variable nodes and 4 check nodes. If a code word bit is included in the corresponding check equation, a line is used to connect the variable node and the check node involved to obtain a Tanner graph.

[0110] Figure 3 is the Tanner graph of a LDPC check matrix H.

[0111] like Figure 3 As shown, the Tanner graph represents the check matrix of LDPC. For example, for a check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes, namely n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the check matrix H respectively, and the m check nodes correspond to the m rows of the check matrix H respectively. The cycle in the Tanner graph is composed of vertices connected to each other. The cycle uses one of the vertices in this group of vertices as both the starting point and the end point, and only passes through each node once. The length of the cycle is defined as the number of connections it contains, and the girth of the graph can also be called the size of the graph, which is defined as the minimum cycle length in the graph, such as Figure 3 In the figure, the girth is 4, such as Figure 3As shown by the black lines in the figure. The variable nodes in the Tanner graph correspond to each column of the check matrix H, that is, to each codeword bit of the LDPC. The check nodes in the Tanner graph correspond to each row of the check matrix H, that is, to the check bits of the LDPC. The connection between the two types of nodes corresponds to the value of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, it means that the value of the element (i, j) in the H matrix is ​​1. If there is no connection, the corresponding element is 0. The connection between the variable node and the check node can also be called an edge. There is a connection between the check node and the variable node, which can also be described as: there is a connection or an edge between the check node and the variable node. The edge relationship between the check node and the variable node can include two situations: the existence of an edge or the absence of an edge.

[0112] In addition, in the Tanner graph, a cycle refers to a closed loop consisting of variable nodes, check nodes, and edges connected end to end.

[0113] As mentioned above, LDPC is a linear block code. The linear block code divides the information sequence to be encoded into groups of q bits, and then the encoder performs linear operations on the q information bits to obtain m check bits. Then, the q information bits are combined with the m check bits to obtain a codeword of length n = q + m. The mapping relationship from q-bit information bits to codewords of length n bits is usually represented by a corresponding check matrix H. According to the check matrix H, a codeword sequence can be generated accordingly to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving device decodes the received signal accordingly to determine the original information bits.

[0114] 2. QC-LDPC Code

[0115] Quasi-cyclic low density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of its check matrix, it can be encoded using a simple feedback shift register, reducing the coding complexity of LDPC codes. When the code length is long, the check matrix H of the LDPC code will be very large, so H is usually represented in blocks: the complete check matrix H is regarded as a block consisting of multiple Z c ×Z c Specifically, the complete check matrix H can be generated from a base matrix H b Indicates that H b Each element in corresponds to a Z c ×Z c Each submatrix can be represented by the number of cyclic shift bits, thus greatly reducing the storage space required for the complete check matrix H.b The elements in can also be called QC blocks.

[0116] Based on the basis matrix H b And the improvement value Z c (lifting size), the basis matrix H b Expanded to a complete check matrix for encoding or decoding. c It may also be called expansion factor, lifting factor, expansion value, expansion coefficient, or lifting size, etc.

[0117] For example, the basis matrix H of the QC-LDPC code b As shown below:

[0118]

[0119] It can be seen that the basis matrix H b The size of the matrix H is 4 rows and 24 columns. b Each element in represents a Z c The square matrix of order, element represents the cyclic permutation matrix, i represents the cyclic shift value, and i is an integer. In addition, the basis matrix H b The "-1" in represents an all-zero matrix, and "0" represents the identity matrix.

[0120] For example, As shown below:

[0121]

[0122] Optionally, the basis matrix H b In addition to "-1", the zero elements in can also have other representations, such as using "-" or null values ​​to represent an all-zero matrix.

[0123] It should be noted that the above-mentioned base matrix can also be called a base graph (BG), and the base matrix will be used to describe the embodiments of the present application below.

[0124] 3. Non-zero elements and zero elements

[0125] In the check matrix, a zero element indicates that there is no connection between the variable node and the check node, and a non-zero element indicates that there is a connection between the variable node and the check node.

[0126] In the LDPC basis matrix, the zero element represents Z c An all-zero square matrix of order Z, with non-zero elements representing Z c The identity matrix of order or based on Z cThe circulant permutation matrix of the identity matrix of order, the value of the non-zero element represents the circulant shift value or offset value (shifting value) relative to the identity matrix.

[0127] This application does not limit the specific forms of zero elements and non-zero elements. Figure 2 In the check matrix H shown in the figure, "0" is used to represent a zero element, and "1" is used to represent a non-zero element. For another example, as described above, the base matrix H b In the example, "-1" is used to represent zero elements, and "non-negative values" are used to represent non-zero elements.

[0128] For the convenience of description, "0" is used below to represent a zero element and "1" is used to represent a non-zero element.

[0129] 4. Column weight and row weight

[0130] For a column of a matrix, the column weight can refer to the number of non-zero elements contained in the column. For a row of a matrix, the row weight can refer to the number of non-zero elements contained in the row. For example, Figure 2 As shown, the first column of the check matrix H has a column weight of 2 and the first row weight of 4. For another example, as described above, the base matrix H b The first column has a column weight of 4 and the first row has a row weight of 20.

[0131] 5. Structure of the check matrix

[0132] Figure 4 It is a schematic diagram of the structure of the check matrix.

[0133] like Figure 4 As shown in (a), the check matrix may include a high rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high rate region may include Figure 4 (b) shows part A and part B, where part A corresponds to information bits (or information bits, system bits, etc.), and part B is a square matrix and corresponds to core check bits (or core check bits). The all-zero area can correspond to Figure 4 Part C of (b) is an all-zero matrix. The incremental redundancy region can correspond to Figure 4 Part D of (b). The Lapter-like region may correspond to Figure 4 Part E of (b) can be a unit matrix, corresponding to the parity bits of the low code rate extension.

[0134] Figure 4The check matrix of the LDPC code shown in FIG. 1 adopts a "raptor-like" structure, which can be gradually extended to a low code rate through a high code rate core matrix. In actual use, Figure 4 As shown in (a), the first X rows and Y columns of the check matrix can be truncated. As the code rate decreases from high to low, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0135] It should be noted that the check matrix can be represented by the LDPC base matrix, so the structure of the LDPC base matrix is ​​similar to that of the check matrix, which will not be described in detail here.

[0136] 6. Information column and check column

[0137] The columns of the LDPC base matrix consist of information columns and check columns.

[0138] Information column: corresponds to the information bit (also called information bit, system bit, etc.), which is the column corresponding to part A.

[0139] Check column: corresponds to the check bit (or check digit, etc.), and can include a core check column and an extended check column, where the core check column is the column corresponding to part B, and the extended check column is the column corresponding to part C or part E. The extended check column can also be called a raptor-like column. The extended check column corresponds to the extended node.

[0140] 7. Core rows, core columns, and core matrices

[0141] Core rows: The core rows of the LDPC base matrix are the rows corresponding to the core check bits. In other words, the core rows are the rows corresponding to the high code rate region, or the rows corresponding to part A, part B, or part C.

[0142] Core columns: may include all information columns and all core check columns. In other words, core columns are columns corresponding to the high bit rate area, or columns corresponding to part A + part B.

[0143] Kernel Matrix: It is a matrix region consisting of all core rows and all core columns of the LDPC base matrix. In other words, the core matrix is ​​the high-rate region of the LDPC base matrix, or the portion consisting of Part A and Part B.

[0144] 8. Information transmission process

[0145] Figure 5 It is a schematic diagram of the information transmission process. Figure 5 As shown in the figure, information is sent from the source, and after source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, source recovery and other processing, it reaches the destination, completing the transmission of information from the source to the destination. Figure 5The processing shown in the upper layer (including source coding, channel coding and modulation, etc.) is performed at the transmitting end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end device. Figure 5 Source coding, channel coding, channel decoding and source recovery are shown.

[0146] 9. Traditional expansion and split expansion

[0147] Traditional expansion: also known as normal expansion, refers to a method of low code rate expansion based on the traditional method, in which the rows of the storage matrix are read as the rows of the LDPC basis matrix.

[0148] Split expansion: Different from the traditional expansion, when reading a row of the storage matrix as a newly added row of the LDPC base matrix, it is also necessary to use the newly added row to eliminate a row before the newly added row in the LDPC base matrix. The eliminated row and the newly added row are orthogonal except for the expansion node. It can also be understood that the eliminated row is split into the newly added row and the eliminated row. The eliminated row can correspond to the parent node, and the newly added row or the eliminated row can correspond to the child node.

[0149] Figure 6 is an example of traditional expansion and split expansion.

[0150] Figure 6 Take the splitting and expansion of the second row as an example.

[0151] Figure 6 (a) is the matrix before expansion. Figure 6 (b) is the matrix after adding a row. Figure 6 (a) to Figure 6 (b) is a traditional expansion. Figure 6 (c) is the matrix after eliminating row 2 using the added row, given by Figure 6 (a) to Figure 6 (b) Go to Figure 6 (c) is a split expansion. The eliminated rows are orthogonal to the newly added rows except for the last column.

[0152] In current LDPC codes, the orthogonality between rows of the LDPC base matrix is ​​low, which affects the efficiency and performance of decoding. For example, the edge density of the high-rate part of the NR LDPC code is large, and only the parallel decoding of the QC block is supported. Figure 6 In the split-extended LDPC code shown, the eliminated rows and the newly added rows are orthogonal except for the extended nodes, but there are overlapping elements at the extended nodes. Parallel decoding between rows can only be achieved through staggered beats or changes in message transmission methods, which affects the decoding efficiency and performance.

[0153] In view of the above problems, the present application provides a communication method and a communication device based on LDPC codes, in order to improve decoding efficiency and performance.

[0154] The following is a description of the method embodiments of the present application.

[0155] Figure 7 It is a schematic flowchart of a communication method 700 based on LDPC code provided in the present application.

[0156] Method 700 can be performed by a transmitting device and a receiving device. Unless otherwise specified, "transmitting device" or "receiving device" can refer to the transmitting device or the receiving device itself, or can refer to a device that can support the transmitting device or the receiving device to implement the function. For the convenience of description, the transmitting device and the receiving device are used uniformly in the following description. The transmitting device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0157] Method 700 may include at least part of the following.

[0158] Step 701: The transmitting end device obtains an information bit sequence.

[0159] That is to say, if the transmitting device needs to communicate with the receiving device, that is, the transmitting device needs to send a signal to the receiving device, the transmitting device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0160] The transmitting end device acquires the information bit sequence, which may refer to: the transmitting end device performs source coding on the source symbols to generate the information bit sequence. The transmitting end device acquires the information bit sequence, which may also refer to: the transmitting end device receives the information bit sequence from other communication devices.

[0161] Step 702: The transmitting end device performs LDPC encoding on the information bit sequence according to the first LDPC base matrix and the indication information to obtain an LDPC codeword sequence.

[0162] The first LDPC base matrix may refer to a matrix stored in the transmitting end device or a matrix predefined by the protocol. The indication information may indicate the correlation between rows in the first LDPC base matrix.

[0163] The transmitting device can determine the second LDPC base matrix according to the first LDPC base matrix and the indication information, and use the second LDPC base matrix to perform LDPC encoding on the information bit sequence to obtain an LDPC codeword sequence. Among them, the second LDPC base matrix is ​​the matrix actually used by the transmitting end for encoding. In the process of obtaining the second LDPC base matrix, the low code rate expansion method can be a split expansion method, or it can be a mixed method of split expansion and traditional expansion. In the low code rate expansion process, whether each expansion is a traditional expansion or a split expansion can be determined by the indication information. The description of split expansion and traditional expansion can be referred to above and will not be described in detail here.

[0164] In a possible implementation, the indication information may include first information, and the first information corresponds to split expansion. Optionally, the indication information also includes second information, and the second information corresponds to traditional expansion. When the indication information does not include the first information, in the process of obtaining the second LDPC base matrix, the low code rate expansion method is a split expansion method. When the indication information includes both the first information and the second information, in the process of obtaining the second LDPC base matrix, the low code rate expansion method is a mixed method of split expansion and traditional expansion.

[0165] The first information and the second information are described below.

[0166] The first information is used to indicate a plurality of row pairs, each of which includes a first row and a second row. The set consisting of the column numbers of the columns where the non-zero elements in the first x elements of the first row of a row pair are located is a true subset of the set consisting of the column numbers of the columns where the non-zero elements in the first x elements of the second row of the row pair are located, and x is a positive integer. Exemplarily, x is equal to the number of core columns of the first LDPC base matrix, that is, in a row pair, in the core column part, the set consisting of the column numbers of the columns where the non-zero elements of the first row are located is a true subset of the set consisting of the column numbers of the columns where the non-zero elements of the second row are located. The set consisting of the column numbers of the columns where the non-zero elements of the first row are located is a true subset of the set consisting of the column numbers of the columns where the non-zero elements of the second row are located, which can also be described as: the connection relationship, edge or non-zero element in the first row other than the extended node is truly included in the connection relationship, edge or non-zero element in the second row other than the extended node. The offset value of the non-zero element in the first row can be the same as the offset value of the non-zero element in the corresponding position of the second row, or it can differ by a fixed value without restriction.

[0167] For example, in a row pair, the first row is {1, 0, 0, 3, 0, 5, 0, 0, 1, 0}, and the second row is {1, 0, 2, 3, 4, 5, 0, 1, 0, 0}, where the first seven columns are core columns and the last three columns correspond to expansion nodes. 0 represents a zero element. In the first seven columns, the set composed of the column numbers of the columns where the non-zero elements of the first row are located is {1, 4, 6}, and the set composed of the column numbers of the columns where the non-zero elements of the second row are located is {1, 3, 4, 5, 6}. {1, 4, 6} is a proper subset of {1, 3, 4, 5, 6}, which can also be described as {1, 0, 0, 3, 0, 5, 0} is truly contained in {1, 0, 2, 3, 4, 5, 0}.

[0168] The embodiment of the present application does not limit the storage method of the first row and the second row in a row pair. In a possible implementation method, each row pair in a plurality of row pairs corresponds to two rows in the first LDPC base matrix or two rows in the first LDPC base matrix, that is, the second row can correspond to a row in the first LDPC base matrix or a row in the first LDPC base matrix, and the first row can correspond to a row in the first LDPC base matrix or a row in the first LDPC base matrix. In this case, each row pair in a plurality of row pairs is two rows in the same base matrix. In another possible implementation method, the second row can correspond to a row in the first LDPC base matrix or a row in the first LDPC base matrix, and the first row can correspond to a row in a matrix other than the first LDPC base matrix or a row in a matrix other than the first LDPC base matrix, that is, the first row and the second row in each row pair in a plurality of row pairs are stored in different base matrices respectively. The following describes the embodiment of the present application by taking each row pair in a plurality of row pairs corresponding to two rows in the first LDPC base matrix or two rows in the first LDPC base matrix as an example.

[0169] In the process of obtaining the second LDPC base matrix, for the first and second rows in a row pair, the row of the second LDPC base matrix corresponding to the first row is the same as the first row. In other words, the row of the second LDPC base matrix corresponding to the first row of the first LDPC base matrix is ​​obtained by directly reading the first row of the first LDPC base matrix. The row of the second LDPC base matrix corresponding to the second row is obtained by eliminating the corresponding second row using the first row of the first LDPC base matrix. In this way, the row of the second LDPC base matrix corresponding to the first row is orthogonal to the corresponding row corresponding to the second row except for the expanded node. It should be noted that the row of the second LDPC base matrix corresponding to the first row is the same as the first row, which should be understood as: when the row of the second LDPC base matrix corresponding to the first row is initially obtained, the row of the second LDPC base matrix corresponding to the first row is the same as the first row. If there is a situation in which the row corresponding to the first row of the second LDPC base matrix is ​​split and expanded as the parent node, the row is no longer the same as the first row of the first LDPC base matrix.

[0170] The second information is used to indicate one or more third rows. One or more third rows are rows used for traditional expansion. In the process of obtaining the second LDPC base matrix, the rows corresponding to one or more third rows of the second LDPC base matrix are the same as the one or more third rows of the first LDPC base matrix. In other words, the rows of the second LDPC base matrix corresponding to the third row of the first LDPC base matrix are obtained by directly reading the third row of the first LDPC base matrix. Similarly, the rows corresponding to the third row of the second LDPC base matrix are the same as the third row of the first LDPC base matrix, which should be understood as follows: when the rows corresponding to the third row of the second LDPC base matrix are initially obtained, the rows corresponding to the third row of the second LDPC base matrix are the same as the third row of the first LDPC base matrix. If there is a situation in which the rows corresponding to the third row of the second LDPC base matrix are split and expanded as parent nodes, the rows are no longer the same as the third row of the first LDPC base matrix.

[0171] The embodiments of the present application do not limit the specific form of the indication information. Exemplarily, the form adopted by the indication information may include: at least one of a sequence, a mapping table, or a mapping pair.

[0172] The following takes the case where the indication information is in the form of a sequence as an example to explain the indication information in two cases: including the second information and not including the second information.

[0173] Case 1: The indication information does not include the second information

[0174] The indication information does not include the second information, that is, the second LDPC base matrix is ​​obtained by splitting and expanding. In this case, the sequence corresponding to the indication information can be called a split sequence (split sequence), and the split sequence can be composed of the row number of the core row and the row number of the second row of each row pair in one or more row pairs mentioned above. The length of the split sequence is equal to the number of rows of the second LDPC base matrix. In a row pair, the position of the row number of the second row in the split sequence is the row number of the first row, and the position of the row number of the second row in the split sequence is greater than the row number of the first row. For example, the value of the 8th position of the split sequence is 3, which means that the row pair is the 8th row and the 3rd row, and the 8th row corresponds to the first row, and the 3rd row corresponds to the second row. When splitting and expanding, the transmitting device uses the 8th row to eliminate the 3rd row.

[0175] In a possible implementation, the sequence corresponding to the first information may include one or more segments, and the row number in the t-th segment of the one or more segments is {1, 2, ..., 2 t-1 M-1,2 t-1 M}, where t and M are positive integers. Each of the one or more segments corresponds to a round of splitting. For example, the splitting sequence can be {1, 2, 3, 4, 3, 4, 1, 2, 5, 2, 6, 8, 4, 7, 1, 3}, where M is 4, and the sequence corresponding to the first information is from the fifth element, that is, the sequence corresponding to the first information is {3, 4, 1, 2, 5, 2, 6, 8, 4, 7, 1, 3}, where t is 2, {3, 4, 1, 2} is the first segment, {5, 2, 6, 8, 4, 7, 1, 3} is the second segment, and the first segment {3, 4, 1, 2} is {1, 2, …, 2 1-1 ×4-1,2 1-1 ×4}={1,2,3,4}, the second segment {5,2,6,8,4,7,1,3} is {1,2,…,,2 2-1 ×4-1,2 2-1 ×4}=a permutation of {1, 2, 3, 4, 5, 6, 7, 8}.

[0176] Exemplarily, M is the number of core rows of the first LDPC base matrix. In other words, the core rows of the first LDPC base matrix can be split. This is because the edge density of the core region is relatively dense, and the corresponding core check equation usually does not have the characteristic of orthogonality. The orthogonality of the core region of the second LDPC base matrix is ​​increased by splitting and expanding. In this case, the specific characteristics of the split sequence can be as follows:

[0177] 1) If row i is generated by splitting row j, then j = f(i), row j is called the parent node of row i, and row i is the child node of row j;

[0178] 2) If there exists a row i=i0,i1,i2,…,i l =j, so that i k =f(i k-1 ), for k = 1, ..., l, then i~j, l are called positive integers;

[0179] 3) For the i-th element in the split sequence, define the set S i ={j≤i|i~j};

[0180] 4) Let C0 be the set of core rows of the core matrix, then row i∈S j , where row j∈C0;

[0181] 5) Each round of splitting is a complete split, that is, C0 and all current child nodes are split.

[0182] Each round of splitting is a complete splitting, which means that the splitting sequence includes one or more segments, each segment corresponds to a round of splitting, and the row number in the segment corresponding to the t-th round of splitting is {1,…,2 t-1 |C0|}, t is a positive integer, |C0| is the number of elements in set C0, that is, the number of core rows, which can correspond to M above.

[0183] In the above manner, each row number appears only once in a round of splitting, so multiple splitting included in each round can be executed in parallel, which helps to improve splitting efficiency.

[0184] Case 2: the indication information includes the first information and the second information

[0185] The indication information includes the first information and the second information, that is, the second LDPC base matrix is ​​obtained by a mixture of split expansion and traditional expansion. In this case, the indication information may also include the third information, and the third information is used to indicate one or more fourth rows, and the one or more fourth rows of the second LDPC base matrix are the same as the one or more fourth rows of the first LDPC base matrix. Similarly, the row corresponding to the fourth row of the second LDPC base matrix is ​​the same as the fourth row of the first LDPC base matrix. It should be understood that when the row corresponding to the fourth row of the second LDPC base matrix is ​​initially obtained, the row corresponding to the fourth row of the second LDPC base matrix is ​​the same as the fourth row of the first LDPC base matrix. If there is a situation in which the row corresponding to the fourth row of the second LDPC base matrix is ​​split and expanded as the parent node, the row is no longer the same as the fourth row of the first LDPC base matrix.

[0186] In this case, the length of the sequence corresponding to the indication information is equal to the number of rows of the second LDPC base matrix. Hereinafter, the sequence corresponding to the indication information is referred to as the indication sequence.

[0187] The first information may include the row number of the second row of each row pair in the one or more row pairs described above. In a row pair, the row number of the second row is located at the same position as the row number of the first row in the indication sequence, and the row number of the second row is located at a greater position than the row number of the first row in the indication sequence. For example, the value of the 8th position of the indication sequence is 3, which indicates that the row pair is the 8th row and the 3rd row, and the 8th row corresponds to the first row, and the 3rd row corresponds to the second row. When splitting and expanding, the sending end device uses the 8th row to eliminate the 3rd row.

[0188] The second information includes one or more first characters. The position of the one or more first characters in the indication sequence corresponds to the row number of one or more third rows. For example, the 7th position of the indication sequence is the first character, which means that the row of the second LDPC base matrix corresponding to the 7th row of the first LDPC base matrix obtained based on the traditional expansion, that is, the row of the second LDPC base matrix corresponding to the 7th row of the first LDPC base matrix is ​​the same as the 7th row of the first LDPC base matrix.

[0189] Exemplarily, the first character is a value other than a row number of the first LDPC base matrix.

[0190] The third information includes M second characters or M row numbers, wherein the M row numbers are respectively divided into 1, 2, ..., M, and M is a positive integer. Exemplarily, M is the number of core rows of the first LDPC base matrix. The positions of the M second characters in the indicator sequence correspond to the row numbers of one or more fourth rows. For example, the second position of the indicator sequence is the second character, which indicates that the row of the second LDPC base matrix corresponding to the second row of the first LDPC base matrix is ​​the same as the second row of the first LDPC base matrix.

[0191] Exemplarily, the second character is a value other than the row number of the first LDPC base matrix. The second character may be the same as or different from the first character, without limitation.

[0192] In a possible implementation, the indication sequence may have a segmented structure. As an example, the indication sequence may include a first segment, a second segment, a third segment, a fourth segment, and a fifth segment in sequence, wherein the first segment is composed of the third information, the second segment is composed of the first part of the second information, the third segment is composed of the first part of the first information, the fourth segment is composed of the second part of the first information and the second part of the second information, and the fifth segment is composed of the third part of the second information. As another example, the indication sequence may include a first segment, a second segment, a third segment, and a fourth segment in sequence, wherein the first segment is composed of the third information, the second segment is composed of the first part of the second information, the third segment is composed of the first part of the first information, and the fourth segment is composed of the second part of the first information and the second part of the second information.

[0193] Optionally, the third segment included in the indication sequence may include one or more sub - segments, and the line numbers in the r - th segment among the one or more sub - segments are in a permuted form of {1, 2, …, 2r−1(M + T)−1, 2r−1(M + T)}, where r is a positive integer and T is the number of characters in the first part of the second information. For a detailed description, reference may be made to the sequence corresponding to the first information.

[0194] Taking the indication sequence including the first segment, the second segment, the third segment, the fourth segment, and the fifth segment in sequence as an example, the generalized form of the indication sequence is given below.

[0195] Denoting the first character as 0 and the core number of rows of the core matrix as M, the indication sequence θ can be expressed as:

[0196]

[0197] It can be seen that the indication sequence is a five - segment piece - wise function. Among them, the first segment 1, …, M is the core segment, corresponding to the core matrix (or core check equation) of the first LDPC base matrix; the second segment 0 1×T is the traditional extension segment, corresponding to the traditional extension (or traditional extension check equation), and the second segment is completely composed of the first character 0; the third segment p1(1, …, M + T), p2(1, …, 2M + 2T) … is the split extension segment, corresponding to the split extension, and is completely composed of line numbers (this segment must contain the line numbers of the core matrix); the fourth segment γ(0, p x ) is a mixed segment of split extension and traditional extension. The fourth segment represents interleaving the first character 0 with the line numbers that have appeared before; the fifth segment also corresponds to the traditional extension, and the fifth segment is completely composed of the first character 0. Among them, T is the length of the second segment, that is, the number of characters. T’ is the length of the fifth segment, that is, the number of characters.

[0198] In a possible implementation, each segment of the indication sequence can be based on the code rate or line numbers. Exemplarily, if the indication sequence includes the first segment, the second segment, the third segment, the fourth segment, and the fifth segment, there exists a sequence position j i , such that for 1 ≤ j < j1, it corresponds to the first segment, j1 ≤ j < j2 corresponds to the second segment, …, until the last segment is j4 ≤ j.

[0199] In a possible implementation, j i is related to the code rate (the number of rows of the check equation) corresponding to the sequence, that is, there exists a threshold R for the code rate i , such that is the segment position described above, where P is the number of punctured columns and K is the number of information columns.

[0200] The above describes the low bit rate expansion of the implementation of this application in combination with the indication information. As can be seen from the above, in the process of split expansion, the eliminated rows and the newly added rows are only partially orthogonal, and there are still overlapping elements in the expansion nodes. In order to further improve the orthogonality between rows, the implementation of this application can design the association relationship between subnodes, which is described in detail below.

[0201] As explained above, the first information can be used to indicate one or more row pairs, in which the set consisting of the column numbers of the columns where the non-zero elements of the first x elements of the first row are located is a proper subset of the set consisting of the column numbers of the columns where the non-zero elements of the first x elements of the second row are located, and x is a positive integer.

[0202] Further, in an embodiment of the present application, the multiple first rows indicated by the first information may form one or more row groups. Each row group in the one or more row groups includes at least two first rows, and the column weight of each column of the matrix region, subgraph or matrix formed by the second rows corresponding to the at least two first rows is less than or equal to 2, and at least two first rows have an association relationship.

[0203] For example, the row pairs indicated by the first information include {6, 1)(7, 4)(8, 3)(9, 2)(10, 5)}, and the first row indicated by the first information includes rows 6, 7, 8, 9 and 10, wherein rows 6, 7 and 8 are a row group, rows 9 and 10 are a row group, the column weight of each column of the matrix area, subgraph or matrix formed by rows 1, 4 and 3 corresponding to rows 6, 7 and 8 is less than or equal to 2, and rows 6, 7 and 8 are associated with each other, the column weight of each column of the matrix area, subgraph or matrix formed by rows 2 and 5 corresponding to rows 9 and 10 is less than or equal to 2, and rows 9 and 10 are associated with each other.

[0204] The above-mentioned association relationship may include a first association relationship and / or a second association relationship. The first association relationship and the second association relationship are the relationship between two first rows. Among them, the two first rows with the first association relationship are orthogonal to each other, and the union of the column numbers of the columns where the non-zero elements of the two first rows are located contains the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located. The two first rows with the first association relationship mentioned here can be any two first rows with the first association relationship in a row group. The two first rows with the second association relationship have the same connecting edge at the first position, and the column number at the first position belongs to the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located. The two first rows with the second association relationship mentioned here can be any two first rows with the second association relationship in a row group.

[0205] Figure 8 This is a schematic diagram of the first association relationship.

[0206] Figure 8 The first and second rows in correspond to the second row, the column weight of each column of the matrix area (or matrix or subgraph) formed by the first and second rows is not greater than 2, the third and fourth rows correspond to the first row, and the first row and the third row are a row pair, the second row and the fourth row are a row pair, and the tenth and eleventh columns of each row correspond to the expansion nodes.

[0207] like Figure 8 As shown in (a), the 3rd row and the 4th row are orthogonal to each other, that is, the column weight of each column of the matrix area formed by the 3rd row and the 4th row is less than or equal to 1.

[0208] like Figure 8 As shown in (b), the set of column numbers of the columns where the non-zero elements of the first row excluding the expanded nodes are located is {1, 2, 3, 4, 5, 6}, and the set of column numbers of the columns where the non-zero elements of the third row excluding the expanded nodes are located is {2, 4, 6}. {1, 2, 3, 4, 5, 6} truly contains {2, 4, 6}, or in other words, {2, 4, 6} is a proper subset of {1, 2, 3, 4, 5, 6}.

[0209] like Figure 8 As shown in (c), the set of column numbers of the columns where the non-zero elements of the second row excluding the expanded nodes are located is {4, 5, 6, 7, 8, 9}, and the set of column numbers of the columns where the non-zero elements of the fourth row excluding the expanded nodes are located is {5, 7}. {4, 5, 6, 7, 8, 9} truly contains {5, 7}, or in other words, {5, 7} is a proper subset of {4, 5, 6, 7, 8, 9}.

[0210] like Figure 8 As shown in (d), the intersection of the set {1, 2, 3, 4, 5, 6} of the column numbers of the columns where the non-zero elements of the first row are located and the set {4, 5, 6, 7, 8, 9} of the column numbers of the columns where the non-zero elements of the second row are located is {4, 5, 6}, the union of the set {2, 4, 6, 10} of the column numbers of the columns where the non-zero elements of the third row are located and the set {5, 7, 11} of the column numbers of the columns where the non-zero elements of the fourth row are located is {2, 4, 5, 6, 7, 10, 11}, and {2, 4, 5, 6, 7, 10, 11} contains {4, 5, 6}. In this way, the third row and the fourth row have a first association relationship.

[0211] Fig. 9 This is a schematic diagram of the second association relationship.

[0212] Fig. 9The first and second rows in correspond to the second row, the column weight of each column of the matrix area (or matrix or subgraph) formed by the first and second rows is not greater than 2, the third and fourth rows correspond to the first row, and the first row and the third row are a row pair, the second row and the fourth row are a row pair, and the tenth and eleventh columns of each row correspond to the expansion nodes.

[0213] like Fig. 9 As shown in (b), the set of column numbers of the columns where the non-zero elements of the first row excluding the expanded nodes are located is {1, 2, 3, 4, 5, 6}, and the set of column numbers of the columns where the non-zero elements of the third row excluding the expanded nodes are located is {2, 4, 6}. {1, 2, 3, 4, 5, 6} truly contains {2, 4, 6}, or in other words, {2, 4, 6} is a proper subset of {1, 2, 3, 4, 5, 6}.

[0214] like Fig. 9 As shown in (c), the set of column numbers of the columns where the non-zero elements of the second row excluding the expanded nodes are located is {4, 5, 6, 7, 8, 9}, and the set of column numbers of the columns where the non-zero elements of the fourth row excluding the expanded nodes are located is {5, 7}. {4, 5, 6, 7, 8, 9} truly contains {5, 7}, or in other words, {5, 7} is a proper subset of {4, 5, 6, 7, 8, 9}.

[0215] like Fig. 9 As shown in (d), the intersection of the set {1, 2, 3, 4, 5, 6} of the column numbers of the columns where the non-zero elements of the first row are located and the set {4, 5, 6, 7, 8, 9} of the column numbers of the columns where the non-zero elements of the second row are located is {4, 5, 6}, that is, the first position is the 4th, 5th and 6th columns, the 4th, 5th and 6th columns of the 3rd row are the same as the 4th, 5th and 6th columns of the 4th row, so that the 3rd row and the 4th row have a second association relationship.

[0216] The generalized form of the first association relationship and the second association relationship is given below in combination with the sequence θ corresponding to the indication information.

[0217] Suppose for i≥1, if θ(i)>0, then there exists j≥1, satisfying the condition θ(j)>0, θ(i)≠θ(j), where i and j represent the row numbers of the child nodes, and θ(i) and θ(j) represent the row numbers of the parent node.

[0218] For the first relationship: and

[0219] For the second association relationship: [N(θ(j))∩N(θ(i))]∩N(i)=[N(θ(j))∩N(θ(i))]∩N(j). [N(θ(j))∩N(θ(i))]∩N(i)=[N(θ(j))∩N(θ(i))]∩N(j) can be simplified to N(θ(j))∩N(i)=N(θ(i))∩N(j).

[0220] Among them, N(i) represents the set consisting of the column numbers of the columns where the non-zero elements of the row with row number i are located, N(j) represents the set consisting of the column numbers of the columns where the non-zero elements of the row with row number j are located, N(j(i)) represents the set consisting of the column numbers of the columns where the non-zero elements of the row with row number θ(i) are located, and N(θ(j)) represents the set consisting of the column numbers of the columns where the non-zero elements of the row with row number θ(j) are located.

[0221] Based on the sequence θ, the concepts of parent nodes and child nodes are concretized above. In the above description, θ(i) and θ(j) are parent nodes that are grouped together, and their relevance is reflected in their child nodes i and j. Alternatively, it can also be described from the perspective of grouping of parent nodes, where nodes with child nodes having the first association relationship or the second association relationship belong to a group.

[0222] In an embodiment of the present application, in a row group consisting of at least two first rows, the first rows in the row group can form combinations in pairs, wherein each combination can have the first association relationship, or each combination can have the second association relationship, or some combinations can have the first association relationship and some combinations can have the second association relationship, without limitation.

[0223] In a possible implementation, in the pairwise combinations of the first rows of a row group, the number of combinations having the first association relationship and the number of combinations having the second association relationship are related to the number of first rows included in the row group.

[0224] As an example, for a row group including k first rows, the number of combinations with the first association relationship and the number of combinations with the second association relationship are distributed in a total of In this case, in the combination of the first two rows in the row group, The combination has the first association relationship. The combination has a second association relationship, represents the number of combinations of any two rows selected from ki rows, represents the number of combinations of selecting two rows from k rows, represents the number of combinations of any two rows selected from the i rows, Specifically, the allocation method of the number of combinations with the first association relationship and the number of combinations with the second association relationship may include: combinations have the first association and 0 combinations have the second association, The combination has the first association relationship. The combination has a second association relationship, The combination has the first association relationship. The combinations have a second association, …, The combination has the first association relationship. The combinations have a second association relationship.

[0225] For example, when k=2, the number of combinations with the first association relationship and the number of combinations with the second association relationship are allocated in a total of There is a situation where either the two first rows have a first association relationship or the two rows have a second association relationship.

[0226] For another example, when k=3, the number of combinations with the first association relationship and the number of combinations with the second association relationship are allocated in a total of Situations including The combination has a first association relationship and The combinations have a second association, and The combination has a first association relationship and The combinations have a second association relationship.

[0227] As another example, for a row group including k first rows, the number of combinations with the first association relationship and the number of combinations with the second association relationship are distributed in a total of In this case, in the combination of the first two rows in the row group, The combination has the first association relationship. The combination has a second association relationship, represents the number of combinations of selecting two rows from ki rows, represents the number of combinations of selecting two rows from k rows, represents the number of combinations of any two rows selected from the i rows, Indicates rounding up.

[0228] In this way, for each row group in the above-mentioned one or more row groups, since the first row in the row group has the above-mentioned first association relationship and / or second association relationship, after the splitting and expansion, the rows in the second LDPC base matrix corresponding to the first row in a row group and the rows in the second LDPC base matrix corresponding to the second row in the first row in the row group are re-divided and grouped, so as to achieve complete orthogonality between rows in the same group.

[0229] Step 703: The transmitting device sends the LDPC codeword sequence to the receiving device, or in other words, the receiving device receives the LDPC codeword sequence from the transmitting device.

[0230] It should be noted that, since the LDPC codeword sequence may introduce channel noise signals during the transmission process, the LDPC codeword sequence output or sent by the transmitting device may be different from the LDPC codeword sequence received by the receiving device.

[0231] Step 704: The receiving end device decodes the LDPC codeword sequence according to the first LDPC base matrix and the indication information.

[0232] The first LDCP base matrix and indication information used by the receiving device for decoding are the same as the first LDCP base matrix and indication information used by the transmitting device for encoding. Please refer to the description on the transmitting device side and will not be described in detail here.

[0233] In one possible implementation, the receiving device can obtain the second LDPC base matrix according to the first LDPC base matrix and the indication information, and decode the LDPC codeword sequence according to the second LDPC base matrix, wherein the row of the second LDPC base matrix corresponding to the first row is obtained by eliminating the second row in the same row pair by the first row.

[0234] It should be noted that the decoding matrix actually used by the receiving device and the encoding matrix actually used by the transmitting device may be the same or different. For example, the transmitting device may only read the corresponding rows from the first LDPC base matrix according to the indication information without splitting and expanding, and the receiving device may read the corresponding rows from the first LDPC base matrix according to the indication information and split and expand to obtain the second LDPC base matrix. In this case, the LDPC base matrices used by the transmitting device and the receiving device are different. For another example, the transmitting device obtains the second LDPC base matrix based on the first LDPC base matrix and the indication information and uses the second LDPC base matrix for encoding. The receiving device also obtains the second LDPC base matrix in the same way and uses the second LDPC base matrix for decoding. In this case, the decoding matrix actually used by the receiving device is the same as the encoding matrix actually used by the transmitting device.

[0235] It should be noted that, for each row group in the above-mentioned one or more row groups, the receiving device can perform row-parallel decoding on the rows in the second LDPC base matrix corresponding to the first row in a row group and the rows in the second LDPC base matrix corresponding to the second row in the row group that are divided into the same group.

[0236] In a possible implementation, the receiving end device may perform row-parallel decoding on the portion of the codeword sequence corresponding to the rows in the first row set, and perform row-parallel decoding on the portion of the codeword sequence corresponding to the rows in the second row set. The union of the first row set and the second row set includes the row corresponding to the first row in a row group in the second LDPC base matrix, and the row corresponding to the second row corresponding to the first row in the row group in the second LDPC base matrix. The first row set consists of the rows corresponding to the rows in the first subset in the second LDPC base matrix and / or the rows corresponding to the rows in the second subset in the second LDPC base matrix. The rows in the first subset are all first rows, and the first rows in the first subset have a first association relationship with each other, the rows in the second subset are all second rows, and the first row corresponding to the second row in the second subset has a second association relationship with the first row in the first subset. The second row set consists of the rows in the second LDPC base matrix corresponding to the rows in the third subset and / or the rows in the second LDPC base matrix corresponding to the rows in the fourth subset. The third subset consists of the second rows corresponding to the first row in the first subset, the fourth subset consists of the first rows corresponding to the second row in the second subset, and the first rows in the fourth subset have a first association relationship in pairs.

[0237] For example, a row group includes row C and row D, the second row corresponding to row C is row A, and the second row corresponding to row D is row B. Row C and row D have a first association relationship. Row A and row B can be divided into one group, and row C and row D can be divided into one group. In this case, the first subset includes row C and row D, the second subset is an empty set (that is, the first row set does not include the second subset), the third subset includes row A and row B, and the fourth subset is an empty set (that is, the second row set does not include the fourth subset). The receiving device can perform row-parallel decoding on the part of the LDPC codeword sequence corresponding to the rows corresponding to row A and row B in the second LDPC base matrix, and perform row-parallel decoding on the part of the LDPC codeword sequence corresponding to the rows corresponding to row C and row D in the second LDPC base matrix.

[0238] For example, a row group includes row C and row D, the second row corresponding to row C is row A, and the second row corresponding to row D is row B. Row C and row D have a second association relationship. Row A and row C can be divided into a group, and row B and row D can be divided into a group. In this case, the first subset includes row C, the second subset is row A, the third subset includes row D, and the fourth subset includes row B. The receiving device can perform row-parallel decoding on the part of the LDPC codeword sequence corresponding to the rows corresponding to row A and row C in the second LDPC base matrix, and perform row-parallel decoding on the part of the LDPC codeword sequence corresponding to the rows corresponding to row B and row D in the second LDPC base matrix.

[0239] For example, a row group includes row D, row E and row F, the second row corresponding to row D is row A, the row corresponding to row E is row B, and the row corresponding to row F is row C. Row D and row F have a first association relationship, row D and row E have a second association relationship, and row E and row F have a second association relationship. Row D, row F and row B can be divided into a group, and row A, row C and row E can be divided into a group. In this case, the first subset includes row D and row F, the second subset includes row B, the third subset includes row A and row C, and the fourth subset includes row E. The receiving device can perform row-parallel decoding on the part of the LDPC codeword sequence corresponding to the rows corresponding to row D, row F and row B in the second LDPC base matrix, and perform row-parallel decoding on the part of the LDPC codeword sequence corresponding to the rows corresponding to row A, row C and row E in the second LDPC base matrix.

[0240] It should be noted that the groups involved in the above-mentioned row parallel decoding may be stored in the receiving end device or may be predefined without limitation.

[0241] The technical solutions of the embodiments of the present application are described in detail below with reference to several specific examples.

[0242] Example 1

[0243] Fig.10 This is an example of the technical solution of the embodiment of the present application. In this example, k=2.

[0244] like Fig.10 As shown, the child node of node 1 is node 3, and the child node of node 2 is node 4.

[0245] If there is no correlation between node 3 and node 4, then node 1 and node 3 can only be divided into one group, and node 2 and node 4 can only be divided into one group. Both groups are quasi-orthogonal, that is, the expanded node part still has overlapping elements.

[0246] If the first association relationship is introduced between node 3 and node 4, that is, node 3 includes an extended node, and in addition to the extended node, the edges or non-zero elements contained in node 3 are a true subset of node 1, and node 4 includes an extended node, and in addition to the extended node, the edges or non-zero elements contained in node 4 are a true subset of node 2, nodes 3 and 4 are orthogonal to each other, and the union of the non-zero elements of nodes 3 and 4 contains the intersection of the non-zero elements of nodes 1 and 2, then a new grouping method can be generated, such as dividing nodes 1 and 2 into one group, and dividing nodes 3 and 4 into one group, so that the two groups obtained are completely orthogonal. For details of the first association relationship, please refer to Figure 8 .

[0247] In this example, multiple parent nodes (such as node 1 and node 2) are grouped into one group, multiple child nodes (such as node 3 and node 4) are grouped into one group, and the child nodes of the parent nodes in the same group have a first association relationship with each other. The transmitting end device can perform row-parallel decoding on multiple parent nodes (such as node 1 and node 2) and row-parallel decoding on multiple child nodes (such as node 3 and node 4).

[0248] Example 2

[0249] Fig.11 This is another example of the technical solution of the embodiment of the present application. In this example, k=2.

[0250] like Fig.11 As shown, the child node of node 1 is node 3, and the child node of node 2 is node 4.

[0251] If there is no correlation between node 3 and node 4, then node 1 and node 3 can only be divided into one group, and node 2 and node 4 can only be divided into one group. Both groups are quasi-orthogonal, that is, the expanded node part still has overlapping elements.

[0252] If a second association relationship is introduced between node 3 and node 4, that is, node 3 includes an extended node, and in addition to the extended node, the edges or non-zero elements contained in node 3 are a true subset of node 1, and node 4 includes an extended node, and in addition to the extended node, the edges or non-zero elements contained in node 4 are a true subset of node 2, and the edges of node 3 and node 4 at the intersection of node 1 and node 2 are exactly the same, then a new grouping method can be generated, such as dividing node 1 and node 4 into one group, and dividing node 2 and node 3 into one group, so that the two groups obtained are completely orthogonal. The second association relationship can be specifically referred to Fig. 9 .

[0253] In this example, nodes 1 and 4 are grouped together, nodes 2 and 3 are grouped together, and child nodes of parent nodes in the same group have a first association relationship with each other. The transmitting device can perform row-parallel decoding on nodes 1 and 4, and row-parallel decoding on nodes 2 and 3.

[0254] Fig.12 This is another example of the technical solution of the embodiment of the present application. In this example, k=3.

[0255] like Fig.12 As shown, the child node of node 1 is node 4, the child node of node 2 is node 5, and the child node of node 3 is node 6.

[0256] If there is no correlation between nodes 4, 5 and 6, then we can only group node 1 and node 4 into one group, group node 2 and node 5 into one group, and group node 3 and node 6 into one group. These three groups are quasi-orthogonal, that is, the expanded node part still has overlapping elements.

[0257] If the first association relationship is introduced between nodes 4, 5 and 6, that is, node 4 includes an extended node, and the edges or non-zero elements contained in node 4 except the extended node are a true subset of node 1, node 5 includes an extended node, and the edges or non-zero elements contained in node 5 except the extended node are a true subset of node 2, node 6 includes an extended node, and the edges or non-zero elements contained in node 6 except the extended node are a true subset of node 3, node 4 and node 5 are orthogonal to each other, and the union of the non-zero elements of node 4 and node 5 contains the intersection of the non-zero elements of node 1 and node 2. Set, node 4 and node 6 are mutually orthogonal, the union of the non-zero elements of node 4 and node 6 contains the intersection of the non-zero elements of node 1 and node 3, node 5 and node 6 are mutually orthogonal, the union of the non-zero elements of node 5 and node 6 contains the intersection of the non-zero elements of node 2 and node 3, and the column weight of each column of the matrix area composed of node 1, node 2 and node 3 is at most 2, then a new grouping method can be generated, such as dividing node 1, node 2 and node 3 into one group, and dividing node 4, node 5 and node 6 into one group, so that the two groups obtained are completely orthogonal. The first association relationship can be specifically referred to Figure 8 .

[0258] In this example, multiple parent nodes (such as node 1, node 2, and node 3) are grouped into one group, multiple child nodes (such as node 4, node 5, and node 6) are grouped into one group, and the child nodes of the parent nodes in the same group have a first association relationship with each other. The transmitting end device can perform row-parallel decoding on multiple parent nodes (such as node 1, node 2, and node 3), and perform row-parallel decoding on multiple child nodes (such as node 4, node 5, and node 6).

[0259] Fig.13 This is another example of the technical solution of the embodiment of the present application. In this example, k=3.

[0260] like Fig.13 As shown, the child node of node 1 is node 4, the child node of node 2 is node 5, and the child node of node 3 is node 6.

[0261] If there is no correlation between nodes 4, 5 and 6, then we can only group node 1 and node 4 into one group, group node 2 and node 5 into one group, and group node 3 and node 6 into one group. These three groups are quasi-orthogonal, that is, the expanded node part still has overlapping elements.

[0262] If the first association relationship and the second association relationship are introduced between nodes 4, 5 and 6, such as node 4 includes an extended node, and the edges or non-zero elements contained in node 4 except the extended node are a true subset of node 1, node 5 includes an extended node, and the edges or non-zero elements contained in node 5 except the extended node are a true subset of node 2, node 6 includes an extended node, and the edges or non-zero elements contained in node 6 except the extended node are a true subset of node 3, node 4 and node 6 are mutually orthogonal, the union of the non-zero elements of node 4 and node 6 contains the intersection of the non-zero elements of node 1 and node 3, the edges of node 4 and node 5 at the intersection of node 1 and node 2 are exactly the same, the edges of node 5 and node 6 at the intersection of node 2 and node 3 are exactly the same, and the column weight of each column of the matrix area composed of node 1, node 2 and node 3 is at most 2, then a new grouping method can be generated, such as dividing node 1, node 3 and node 5 into one group, and dividing node 2, node 4 and node 6 into one group, so that the two groups obtained are completely orthogonal. For details of the first association relationship, please refer to Figure 8 For details about the second relationship, please refer to Fig. 9 .

[0263] In this example, nodes 1, 3 and 5 are grouped together, and nodes 2, 4 and 6 are grouped together. The transmitting device can perform row-parallel decoding on nodes 1, 3 and 5, and row-parallel decoding on multiple nodes 2, 4 and 6.

[0264] The performance of the LDPC code of the embodiment of the present application is described below in conjunction with simulation results.

[0265] Fig.14 This is a simulation result of the difference between the SNR of the NR LDPC code at different code rates and the LDPC code of this application.

[0266] Fig.14 The simulation results of the difference between the SNR of the NR LDPC code and the LDPC code of the present application under the block error rate (BLER) @1e-2 are shown. The ordinate is the difference between the SNR of the NR LDPC code and the LDPC code of the present application under the BLER@1e-2, and the abscissa is the code rate. The difference in SNR greater than 0 indicates that the performance of the LDPC code of the present application is good, and the difference in SNR less than 0 indicates that the performance of the NR LDPC code is good. Fig.14 As shown, compared with BG1 of NR LDPC code, the LDPC code of the present application has gain in the code rate range of 0.4 and above, and the row orthogonality of the LDPC code of the present application is better than BG1 of NR LDPC code.

[0267] Fig.15This is the second simulation result of the difference between the SNR of the NR LDPC code at different code rates and the LDPC code of this application.

[0268] Fig.15 The simulation results of the difference between the SNR of the NR LDPC code and the LDPC code of the present application under BLER@1e-3 are shown. The ordinate is the difference between the SNR of the NR LDPC code and the LDPC code of the present application under BLER@1e-2, and the abscissa is the code rate. If the SNR difference is greater than 0, it means that the performance of the LDPC code of the present application is good, and if the SNR difference is less than 0, it means that the performance of the NR LDPC code is good. Fig.15 As shown, compared with BG1 of NR LDPC code, the LDPC code of the present application has gain in almost all code rate ranges. At the same time, the LDPC code of the present application has a slope gain of BLER-SNR, and the BLER1e-3 gain is larger than that of BLER1e-2.

[0269] Combination of the above Figures 7 to 15 , describes in detail the method embodiment provided by the present application, and will be combined with Figures 16 to 18 , describing an apparatus embodiment of the present application.

[0270] It can be understood that in order to realize the functions in the above embodiments, Figures 16 to 18 The device includes hardware structures and / or software modules corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, this application can be implemented in the form of hardware or a combination of hardware and computer software.

[0271] Fig.16 and Fig.17 The following is a schematic diagram of the structure of possible devices provided by the embodiments of the present application. These devices can be used to implement the functions of the sending end device or the receiving end device in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.

[0272] like Fig.16 As shown, the device 10 includes a transceiver unit 11 and a processing unit 12 .

[0273] When the apparatus 10 is used to implement the functions of the transmitting end device in the above-mentioned method embodiments, the transceiver unit 11 is used to execute the transmitting and receiving steps of the transmitting end device, such as step 703, and the processing unit 12 is used to execute the processing steps of the transmitting end device, such as steps 701 to 702. When the apparatus 10 is used to implement the functions of the receiving end device in the above-mentioned method embodiments, the transceiver unit 11 is used to execute the transmitting and receiving steps of the receiving end device, such as step 703, and the processing unit 12 is used to execute the processing steps of the receiving end device, such as step 704.

[0274] For a more detailed description of the transceiver unit 11 and the processing unit 12, reference may be made to the relevant description in the above method embodiment, which will not be described again here.

[0275] like Fig.17 As shown, the device 20 includes a processing circuit 21. The processing circuit 21 is coupled to a memory 23, and the memory 23 is used to store instructions. When the device 20 is used to implement the method described above, the processing circuit 21 is used to execute the instructions in the memory 23 to implement the functions of the processing unit 12 described above.

[0276] Optionally, the device 20 further includes a memory 23 .

[0277] Optionally, the device 20 further includes a transceiver circuit 22. The transceiver circuit may be referred to as a communication interface. The processing circuit 21 and the transceiver circuit 22 are coupled to each other. It is understood that the transceiver circuit 22 may be a transceiver or an input / output interface. When the device 20 is used to implement the method described above, the processing circuit 21 is used to execute instructions to implement the functions of the processing unit 12, and the transceiver circuit 22 is used to implement the functions of the transceiver unit 11.

[0278] Optionally, the apparatus 20 may be a transmitting end device or a receiving end device, and correspondingly, the transceiver circuit may be a transceiver.

[0279] Optionally, the apparatus 20 may be a chip applied to a transmitting end device or a receiving end device, and correspondingly, the transceiver circuit may be an input / output interface.

[0280] Exemplarily, when the device 20 is a chip applied to a transmitting device or a receiving device, the chip implements the functions of the transmitting device or the receiving device in the above method embodiment. The chip receives information from other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, and the information is sent to the transmitting device or the receiving device by other devices; or, the chip sends information to other modules (such as a radio frequency module or an antenna) in the transmitting device or the receiving device, and the information is sent to other devices by the transmitting device or the receiving device.

[0281] Fig.18 Schematic diagram of a chip system 30 provided in an embodiment of the present application. The chip system 30 (or also referred to as a processing system) includes a logic circuit 31 and an input / output interface 32.

[0282] Among them, the logic circuit 31 can be a processing circuit in the chip system 30. The logic circuit 31 can be coupled to the storage unit and call the instructions in the storage unit so that the chip system 30 can implement the methods and functions of each embodiment of the present application. The input / output interface 32 can be an input / output circuit in the chip system 30, outputting information processed by the chip system 30, or inputting data or signaling information to be processed into the chip system 30 for processing.

[0283] As a solution, the chip system 30 is used to implement the operations performed by the transmitting end device or the receiving end device in each of the above method embodiments.

[0284] For example, the logic circuit 31 is used to implement the processing-related operations performed by the sending device or the receiving device in the above method embodiments; the input / output interface 32 is used to implement the sending and / or receiving-related operations performed by the sending device or the receiving device in the above method embodiments.

[0285] The present application also provides a communication device, including a processing circuit, the processing circuit is coupled to a memory, the memory is used to store computer programs or instructions and / or data, and the processing circuit is used to execute the computer programs or instructions stored in the memory, or read the data stored in the memory to execute the methods in the above method embodiments. Optionally, the processing circuit is one or more. Optionally, the communication device includes a memory. Optionally, the memory is one or more. Optionally, the memory is integrated with the processing circuit, or is separately arranged.

[0286] The present application also provides a chip, including a processing circuit, the processing circuit and a memory are coupled, the memory is used to store computer programs or instructions, and the processing circuit is used to execute the computer programs or instructions stored in the memory to implement the methods executed by the transmitting end device or the receiving end device in the above-mentioned method embodiments. The memory can be located in the chip, or can be independent of the chip and located outside the chip, which is not limited here.

[0287] The present application also provides a computer-readable storage medium on which are stored computer instructions for implementing the methods executed by a transmitting end device or a receiving end device in the above-mentioned method embodiments.

[0288] The present application also provides a computer program product, comprising instructions, which, when executed by a computer, implement the methods performed by a transmitting device or a receiving device in the above-mentioned method embodiments.

[0289] The present application also provides a communication system, which includes at least one of the sending end device or the receiving end device in the above embodiments.

[0290] The explanation of the relevant contents and beneficial effects of any of the above-mentioned devices can be referred to the corresponding method embodiments provided above, which will not be repeated here.

[0291] It is understood that the processing circuit in the embodiments of the present application can be a processor or a circuit in a processor for performing processing operations, and the processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0292] The method steps in the embodiments of the present application can be implemented by hardware, or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, and the software modules can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, register, hard disk, mobile hard disk, compact disc read-only memory (CD-ROM) or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a transmitting end device or a receiving end device. Of course, the processor and the storage medium can also be present in a transmitting end device or a receiving end device as discrete components.

[0293] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is executed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device or other programmable device. The computer program or instruction may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instruction may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server, data center, etc. that integrates one or more available media. The available medium may be a magnetic medium, for example, a floppy disk, a hard disk, a tape; it may also be an optical medium, for example, a digital video disc; it may also be a semiconductor medium, for example, a solid-state hard disk.

[0294] In the various embodiments of the present application, unless otherwise specified or provided in a logical conflict, the terms and / or descriptions between the different embodiments are consistent and may be referenced to each other, and the technical features in the different embodiments may be combined to form new embodiments according to their inherent logical relationships.

[0295] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the present application. The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. It should be understood that the above is for illustration, and the examples above are only to help those skilled in the art understand the embodiments of the present application, rather than to limit the application embodiments to the specific numerical values ​​or specific scenarios illustrated. It is obvious that various equivalent modifications or changes can be made by those skilled in the art according to the examples given above, and such modifications and changes also fall within the scope of the embodiments of the present application.

Claims

1. A communication method based on low-density parity check (LDPC) codes, characterized in that: The method comprises: Obtaining an information bit sequence; According to the first LDPC base matrix and the indication information, the information bit sequence is LDPC encoded to obtain an LDPC codeword sequence; wherein the indication information includes first information, the first information is used to indicate a plurality of row pairs, each row pair in the plurality of row pairs includes a first row and a second row, a set consisting of column numbers of columns where non-zero elements in the first x elements of the first row in the row pair are located is a proper subset of a set consisting of column numbers of columns where non-zero elements in the first x elements of the second row in the row pair are located, and x is a positive integer; the plurality of first rows indicated by the first information form one or more row groups, each row group in the one or more row groups includes at least two first rows, the column weight of each column of a matrix region formed by the second rows corresponding to the at least two first rows is less than or equal to 2, and the at least two first rows are associated with each other; The LDPC codeword sequence is sent.

2. The method according to claim 1, characterized in that The step of performing LDPC encoding on the information bit sequence according to the first LDPC base matrix and the indication information to obtain an LDPC codeword sequence includes: Obtaining a second LDPC base matrix according to the first LDPC base matrix and the indication information; According to the second LDPC base matrix, LDPC encoding is performed on the information bit sequence to obtain an LDPC codeword sequence, wherein the row of the second LDPC base matrix corresponding to the first row is obtained by eliminating the second row in the same row pair by the first row.

3. The method according to claim 1 or 2, characterized in that: The association relationship includes a first association relationship and / or a second association relationship, wherein: The two first rows having the first association relationship are orthogonal to each other, and the union of the column numbers of the columns where the non-zero elements of the two first rows are located includes the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located; The two first rows having the second association relationship have the same connecting edge at the first position, and the column number at the first position belongs to the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located.

4. A communication method based on low-density parity check LDPC code, characterized in that: The method comprises: Receive an LDPC codeword sequence; The LDPC codeword sequence is decoded according to a first LDPC base matrix and indication information; wherein the indication information includes first information, the first information is used to indicate a plurality of row pairs, each row pair in the plurality of row pairs includes a first row and a second row, a set consisting of column numbers of columns where non-zero elements among the first x elements of the first row in the row pair are located is a proper subset of a set consisting of column numbers of columns where non-zero elements among the first x elements of the second row in the row pair are located, and x is a positive integer; the plurality of first rows indicated by the first information form one or more row groups, each row group in the one or more row groups includes at least two first rows, a column weight of each column of a matrix region formed by the second rows corresponding to the at least two first rows is less than or equal to 2, and the at least two first rows are associated with each other.

5. The method according to claim 4, characterized in that The step of decoding the LDPC codeword sequence according to the first LDPC base matrix and the indication information includes: Obtaining a second LDPC base matrix according to the first LDPC base matrix and the indication information; The LDPC codeword sequence is decoded according to the second LDPC base matrix, wherein the row of the second LDPC base matrix corresponding to the first row is obtained by eliminating the second row in the same row pair by the first row.

6. The method according to claim 4 or 5, characterized in that: The association relationship includes a first association relationship and / or a second association relationship, wherein: The two first rows having the first association relationship are orthogonal to each other, and the union of the column numbers of the columns where the non-zero elements of the two first rows are located includes the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located; The two first rows having the second association relationship have the same connecting edge at the first position, and the column number at the first position belongs to the intersection of the column numbers of the columns where the non-zero elements of the two second rows corresponding to the two first rows are located.

7. The method according to claim 6, characterized in that The step of decoding the LDPC codeword sequence according to the second LDPC base matrix includes: The portion of the LDPC codeword sequence corresponding to the rows in the first row set is subjected to row-parallel decoding, and the portion of the LDPC codeword sequence corresponding to the rows in the second row set is subjected to row-parallel decoding, wherein: The union of the first row set and the second row set includes rows in the second LDPC base matrix corresponding to the at least two first rows, and rows in the second LDPC base matrix corresponding to the second rows corresponding to the at least two first rows; The first row set is composed of rows in the second LDPC base matrix corresponding to rows in the first subset and / or rows in the second LDPC base matrix corresponding to rows in the second subset, the rows in the first subset are all the first rows and the first rows in the first subset have the first association relationship in pairs, the rows in the second subset are all the second rows and the first row corresponding to the second row in the second subset has the second association relationship with the first row in the first subset; The second row set consists of rows in the second LDPC base matrix corresponding to rows in the third subset and / or rows in the second LDPC base matrix corresponding to rows in the fourth subset, the third subset consists of the second rows corresponding to the first rows in the first subset, the fourth subset consists of the first rows corresponding to the second rows in the second subset, and the first rows in the fourth subset have the first association relationship in pairs.

8. The method according to claim 3, 6 or 7, characterized in that: In any two combinations of the at least two first rows, the number of combinations having the first association relationship and the number of combinations having the second association relationship are related to the number of the first rows included in the at least two first rows.

9. The method according to claim 8, characterized in that In any combination of at least two of the first rows, The combination has the first association relationship, combinations have the second association relationship, wherein k is the number of the first rows included in the at least two first rows, represents the number of combinations of any two rows selected from ki rows, represents the number of combinations of selecting two rows from k rows, represents the number of combinations of any two rows selected from the i rows, Indicates rounding down.

10. The method according to any one of claims 1 to 9, characterized in that Each row pair of the plurality of row pairs corresponds to two rows of the first LDPC base matrix; The indication information is in the form of a sequence, wherein the first information is a sequence consisting of the row number of the second row of each row pair in the one or more row pairs; In one of the row pairs, the row number of the second row is located at the same position as the row number of the first row in the sequence corresponding to the indication information, and the row number of the second row is located at a greater position than the row number of the first row in the sequence corresponding to the indication information.

11. The method according to claim 10, characterized in that The sequence corresponding to the first information includes one or more segments, and the row number in the t-th segment of the one or more segments is {1, 2, ..., 2 t-1 M-1,2 t-1 M}, where t and M are positive integers.

12. The method according to claim 10, characterized in that The indication information further includes second information, where the second information is used to indicate one or more third rows.

13. The method according to claim 12, characterized in that The second information includes one or more first characters, and positions of the one or more first characters in the sequence corresponding to the indication information correspond to row numbers of the one or more third rows.

14. The method according to claim 12 or 13, characterized in that The indication information further includes third information, and the third information is used to indicate one or more fourth rows.

15. The method according to claim 14, characterized in that The third information includes M second characters or M row numbers, and the M row numbers are 1, 2, ..., M-1, M in sequence, where M is a positive integer.

16. The method according to claim 15, characterized in that The first character and / or the second character is a value other than a row number of the first LDPC base matrix.

17. The method according to claim 15 or 16, characterized in that The sequence corresponding to the indication information includes a first segment, a second segment, a third segment, a fourth segment and a fifth segment in sequence, wherein the first segment is composed of the third information, the second segment is composed of the first part of the second information, the third segment is composed of the first part of the first information, the fourth segment is composed of the second part of the first information and the second part of the second information, and the fifth segment is composed of the third part of the second information.

18. The method according to claim 17, characterized in that The third segment includes one or more sub-segments, wherein the first r The row numbers in the segment are {1, 2, ..., 2 r-1 (M+T)-1,2 r-1 (M+T)}, wherein r is a positive integer and T is the number of characters in the first part of the second information.

19. A communication device, characterized in that: The method comprises a module or a unit for executing the method as claimed in any one of claims 1 to 18.

20. A communication device, characterized in that: It includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices outside the communication device and transmit them to the processor or send signals from the processor to other communication devices outside the communication device, and the processor is used to implement the method as described in any one of claims 1 to 18 through a logic circuit or executing code instructions.

21. The communication device according to claim 20, characterized in that: The communication device is a chip or a chip system.

22. A computer-readable storage medium, characterized in that: The storage medium stores a computer program or an instruction. When the computer program or the instruction is executed by the communication device, the method according to any one of claims 1 to 18 is implemented.

23. A computer program product, characterized in that The invention comprises a computer program which, when being executed, implements the method according to any one of claims 1 to 18.

24. A communication system, characterized in that: include: A sending end device for executing the method as claimed in any one of claims 1 to 3 and 8 to 18; A receiving device for executing the method as claimed in any one of claims 4 to 18.

Images