Asynchronous communication method based on FPGA

Abstract

The invention discloses an asynchronous communication method based on an FPGA (Field Programmable Gate Array), which is characterized in that a configuration module and a data verification and conversion module are expanded on the basis of a universal asynchronous transmission architecture, and the expanded architecture comprises three basic modules, namely a sending module, a receiving module and a control module, as well as the configuration module and the data verification and conversion module, and a corresponding frame header and a corresponding check code are added to the communication of the internal data packet. According to the invention, the problems of large resource consumption, complex design, poor applicability and no data verification in the existing asynchronous communication technology are solved.

Description

Technical Field

[0001] The invention belongs to the technical field of data communication, and in particular relates to an asynchronous communication method based on FPGA. Background Art

[0002] In modern digital systems, especially in FPGA design, data communication is often required between different modules or subsystems, which are likely to run in different clock domains, that is, their clock frequencies and phases may be different. Asynchronous communication technology is particularly important in this case because it can ensure reliable data transmission between different clock domains without being affected by clock synchronization issues.

[0003] Currently available asynchronous communications mainly include dual-port RAM, FIFO, handshake protocol, etc. Although the above methods have solved the problem of asynchronous communication to a certain extent, they still have shortcomings such as complex design and high resource consumption.

[0004] Patent [1] (CN118740113A) proposed digital filtering asynchronous communication, which reads data by comparing two-level thresholds. Although it can effectively read data signals, it does not detect the data in real time and cannot ensure the bit error rate during data transmission.

[0005] Patent [2] (CN118170707A) proposes a one-to-one or even one-to-many asynchronous communication method based on UART communication. Although data communication can be completed, the system communication is based on UART hardware circuit design and requires interface matching during the communication process. The applicability is poor, and the standard UART communication consumes more resources and has poor anti-infection performance. Summary of the invention

[0006] The purpose of the present invention is to provide an asynchronous communication method based on FPGA, which solves the problems of large resource consumption, complex design, poor applicability and no data verification in the existing asynchronous communication technology.

[0007] The technical solution adopted by the present invention is an asynchronous communication method based on FPGA. On the basis of a general asynchronous transmission architecture, a configuration module and a data verification and conversion module are expanded. The expanded architecture includes three basic modules: a sending module, a receiving module, and a control module, as well as a configuration module and a data verification and conversion module, and the communication of internal data packets adds corresponding frame headers and corresponding check codes.

[0008] The present invention is also characterized in that: The sending module performs data verification on the parallel data to be sent according to different check polynomials, generates a corresponding check code for each group of data, ensures the correctness of the data received by the subsequent receiving module, combines the parallel data and the corresponding check code inside the sending module, adds a data frame header to the combined new data stream, generates a new set of data stream structure, which has the original data information and the check data to be verified, and transmits the recombined data stream according to the communication clock in the communication system, ensures that the data stream is effectively sent within the corresponding clock cycle, and avoids data stream disorder or missing problems.

[0009] In terms of data reception, after receiving the serial data stream through the serial data line, the FPGA as the receiver judges the transmission frame header and data validity of the data. After ensuring that the frame header of the incoming data meets the internal settings of the system, the state machine running logic jumps inside the data receiving module to complete the serial-to-parallel conversion process of the serial data stream, divides the converted parallel data, and separates the transmitted data into three parts: frame header, data information, and check data value. At the same time, the converted data is checked and compared, and the check result is compared with the check result of the parallel data after the serial data is converted from the serial data to ensure the accuracy of the parallel data after the serial-to-parallel conversion, and the data that passes the check and comparison is transmitted to the storage module in the receiving module. The storage module is composed of FIFO. FIFO will give priority to the incoming stored data and send it out when needed for subsequent modules to read and calculate. If the current transmission data is recognized incorrectly or the check fails, the data will be automatically shielded and deleted so that the erroneous data information cannot enter the storage module, and a corresponding counting signal will be generated to locate and count errors in the transmission process.

[0010] For the sending module, a high-speed cache unit is used to cache the parallel data that needs to be transmitted. In addition, the cached data is packaged and processed through the state jump module, and the packaged data is passed to the data verification and conversion module to complete the data verification and generation of the corresponding frame header data for the receiving module to verify and identify the data. The configuration module completes the corresponding sending data packet configuration of the state jump module and the data verification and conversion module by receiving the instructions issued by the DSP, thereby realizing data stream transmission under different situations.

[0011] The conversion between parallel data and serial data is completed through the data verification and conversion module. This module completes the data conversion based on the counter synchronization method. The data packet sent by the superior is sent out bit by bit through the cyclic counting of the counter, and the corresponding flag signal is generated for system identification. When the write data enable signal wr_en is set to 1, the data on the transmit buffer tx_buff is valid and is written into the cache unit in the cache and transmit module. After the data is written, the write data enable signal wr_en is set to 0, and then the transmit data enable signal tx_en is set to 1, and the flag starts the data serial-to-parallel conversion.

[0012] For the receiving module, the transmitted data needs to be clock synchronized in the receiving module to ensure the accuracy of data sampling. After the receive preparation signal rx_rdy is set to 1, it represents that a new packet of data has been received. After the data is successfully received, the data read operation begins, the read data enable signal rd_en is set to 1, and the reading begins. The data receiving buffer unit rx_buff outputs data in the next clock cycle after the read data enable signal rd_en is set to 1.

[0013] For the clock synchronization of data, the corresponding signal acquisition is completed based on the duration of high and low levels, and the method of signal acquisition based on high and low levels is named half-half sampling method. The half-half sampling method is based on the Nyquist sampling theorem and is designed using multiple counters and multiplexers. The Nyquist sampling theorem requires that the sampling clock must be 2 times or more than the sampled data clock. The threshold of the corresponding counter is obtained by calculating the sending clock and the sampling clock, so as to complete the corresponding acquisition according to the threshold range. The internal reference clock of the system is used as the standard, and the sending clock and the sampling clock are counted respectively. The rising and falling edges of the sending clock and the sampling clock are used to ensure the threshold of the counter. The count value at the most stable moment of the data is obtained by proportional operation of the two threshold thresholds, and the sending and sampling are completed at this moment. The high and low levels of the transmission signal correspond to different counters. When the system is initially powered on, all threshold counts The counters are all 0. When the corresponding frame header data appears in the data, the system starts to judge the high and low levels of the data. When the data stream has a rising edge or a falling edge, the corresponding threshold counter starts counting. For the edge detection of the data stream, a method combining D flip-flops and logic gates is used to complete the edge detection. Through the cache of the 2-level D flip-flop, the occurrence of metastable states in asynchronous communication is reduced and it is used for subsequent edge detection. When a rising edge or a falling edge is detected, the corresponding counter starts counting, and the value at the middle moment of the counter is taken as the valid data. Each byte of the incoming data is used as a group to generate a corresponding flag signal for subsequent modules to check and transmit the data. The threshold of the counter is determined by the clock ratio of the sending module and the receiving module: suppose the sending module rate is n1 and the receiving module rate is n2, then the threshold of the counter is (n2 / n1)-1. When the counter meets the sampling condition, the signal is sampled.

[0014] For the data received by the receiving module, it is necessary to verify the received data to ensure that no erroneous data is transmitted into the system. The incoming data packet is verified in the data verification conversion module. The idea of ​​pipeline design is adopted in this module, and the state machine jump is used to complete the verification of each data in the data packet, and output the verification signal to ensure the correctness of the data. The correct data is written into the cache unit through the state jump logic in the data verification conversion module. In addition, the receiving module is the same as the sending module. The receiving parameters are configured by DSP and different receiving lengths are set to ensure the correct interaction with the sending module data.

[0015] The beneficial effects of the present invention are as follows: the FPGA-based asynchronous communication method enhances the applicability of the communication architecture through the setting of global variables, so that its rate can meet different requirements such as 10M, 20M, 40M, etc.; the existence of the internal verification module and the error module enhances the anti-interference and transmission stability of the communication architecture, and ensures the stability of cross-clock communication from multiple angles; with FPGA as the communication master control, the parallel processing capability of the system is enhanced, and the ns-level data errors occurring during the transmission process can be judged. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a traditional UART asynchronous communication architecture; Figure 2 It is a universal asynchronous transmission architecture of the asynchronous communication method based on FPGA of the present invention; Figure 3 It is the asynchronous communication sending module architecture in the asynchronous communication method based on FPGA of the present invention; Figure 4 It is the asynchronous communication receiving module architecture in the asynchronous communication method based on FPGA of the present invention; Figure 5 It is an asynchronous communication edge detection structure in the asynchronous communication method based on FPGA of the present invention; Figure 6 It is the asynchronous communication configuration module architecture in the FPGA-based asynchronous communication method of the present invention; Figure 7 It is a signal synchronization processing architecture in the asynchronous communication method based on FPGA of the present invention; Figure 8 It is the Manchester coding processing architecture in the asynchronous communication method based on FPGA of the present invention; Fig. 9 The invention relates to a double half sampling processing architecture in an asynchronous communication method based on FPGA. DETAILED DESCRIPTION

[0017] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] In order to improve the stability and applicability of asynchronous communication, the present invention abandons traditional design methods such as UART and handshake protocol, and proposes a universal full-duplex asynchronous transmission communication architecture. During the transmission process, the communication architecture can perform error checking on the transmitted data and convert serial data into parallel data, ensuring the correctness of written and transmitted data, and greatly improving the operating speed of the system. At the same time, its communication rate can be manually modified, which greatly enhances the applicability of the architecture.

[0019] like Figure 1As shown, it is a traditional UART asynchronous communication module, which is mainly composed of a sending module, a receiving module, and a control module, wherein the sending module and the receiving module are connected to the functional board, and the processed data stream is passed to the functional board for it to complete the corresponding data operation. Although this module is currently widely used, its communication usually uses a lower baud rate (such as 9600baud, 115200baud, etc.), which limits the rate of data transmission and UART communication does not support multi-point communication, and the application scenario is greatly limited; in addition, the standard UART protocol does not include error detection, such as parity check, CRC check, etc., which makes it difficult to detect and correct errors in the communication. The communication protocol in the present invention is different from the traditional UART communication protocol. It is based on the FT3 communication protocol and adopts its data packaging mechanism. The data transmission format is frame header + data packet + check code, but the overall resource consumption is lower, the transmission rate is faster, the applicability is stronger, and it is more suitable for high-speed data transmission in the power system.

[0020] Figure 2 To solve Figure 1 The present invention solves the problem of the scheme shown in the figure, and proposes a universal asynchronous transmission architecture. The present invention is based on the FPGA asynchronous communication method. On the basis of the universal asynchronous transmission architecture, the configuration module and the frame header recognition module for data transmission and reception, the data verification and conversion module are expanded. The expanded architecture includes three basic modules: the sending module, the receiving module, and the control module, as well as the frame header detection module. In addition, the data verification and conversion module is added inside the sending module and the receiving module to further ensure the stability of data transmission, and the communication of the internal data packet increases the corresponding frame header and the corresponding check code.

[0021] The sending module performs data verification on the parallel data to be sent according to different check polynomials, generates a corresponding check code for each group of data, ensures the correctness of the data received by the subsequent receiving module, combines the parallel data and the corresponding check code inside the sending module, adds a data frame header to the combined new data stream, generates a new set of data stream structure, which has the original data information and the check data to be verified, and transmits the recombined data stream according to the communication clock in the communication system, ensures that the data stream is effectively sent within the corresponding clock cycle, and avoids data stream disorder or missing problems.

[0022] In terms of data reception, after receiving the serial data stream through a serial data line such as an optical fiber, the FPGA as the receiver determines the transmission frame header and data validity of the data, ensuring that the frame header of the incoming data complies with the internal settings of the system. For example, when the frame header of the data stream of the sending module is 0xA1A1, when the frame header of the received serial data stream is determined, only when 0xA1A1 is received can the frame data be considered valid. By jumping the logic of the state machine operation inside the data receiving module, the serial data stream is converted into serial-to-parallel conversion, the converted parallel data is segmented, and the transmitted data is separated into three parts: frame header, data information, and check data value. At the same time, the converted data is checked and compared, and the check result is compared with the check result of the parallel data after the serial data is converted from the serial data to ensure the accuracy of the parallel data after the serial-to-parallel conversion, and the data that passes the check and comparison is transmitted to the storage module in the receiving module. The storage module is composed of FIFO. FIFO is similar to a queue in a data structure. FIFO will give priority to the stored data when needed, so that the subsequent modules can read and calculate it. If the current transmission data is recognized incorrectly or the check fails, the data will be automatically shielded and deleted, so that the erroneous data information cannot enter the storage module, and a corresponding counting signal is generated to locate and count errors in the transmission process.

[0023] For the sending module, the system architecture is as follows Figure 3 As shown. In data transmission, not all data is serial-to-serial data transmission. In most cases, it is the mutual conversion of parallel data and serial data. Therefore, a cache unit is used to cache the parallel data to be transmitted. In addition, the cached data is packaged and processed through the state jump module, and the packaged data is passed to the data verification and conversion module to complete the data verification and the generation of the corresponding frame header data, so that the receiving module can verify and identify the data. Considering that the data in data communication is not static, in order to enhance the scalability of the system, the configuration module completes the corresponding sending data packet configuration of the state jump module and the data verification and conversion module by receiving the instructions issued by the DSP, thereby realizing data stream transmission under different situations.

[0024] The conversion between parallel data and serial data is completed by the data verification and conversion module. This module completes the data conversion based on the counter synchronization method. The data packets sent by the superior are sent out bit by bit through the cycle counting of the counter, and the corresponding flag signal is generated for system recognition. The communication sending data timing is as follows Figure 4As shown, when the write data enable signal wr_en is set to 1, the data on the transmit buffer tx_buff is valid and is written into the cache and the cache unit in the transmit module. After the data is written, the write data enable signal wr_en is set to 0, and then the transmit data enable signal tx_en is set to 1, marking the start of data serial-to-parallel conversion.

[0025] For the receiving module, the system architecture is as follows Figure 5 As shown in the figure. In actual applications, different boards or systems have different clock sources, and not all communications have corresponding clock paths, so the receiving module needs to perform clock synchronization on the transmitted data to ensure the accuracy of data sampling. The communication receiving data timing is shown in the figure. Figure 6 As shown, after the receive ready signal rx_rdy is set to 1, it represents that a new packet of data has been received. After the data is received successfully, the data read operation starts, the read data enable signal rd_en is set to 1, and the reading starts. The data receiving buffer unit rx_buff outputs data in the next clock cycle after the read data enable signal rd_en is set to 1.

[0026] For the clock synchronization of data, the present invention completes the corresponding signal acquisition based on the duration of high and low levels, and the method for signal acquisition based on high and low levels in the present invention is named as half-half sampling method. The half-half sampling method is based on the Nyquist sampling theorem and is designed by using multiple counters and multiplexers. The Nyquist sampling theorem requires that the sampling clock must be 2 times or more than the sampled data clock. The threshold of the corresponding counter is obtained by calculating the sending clock and the sampling clock, so as to complete the corresponding acquisition according to the threshold range. The reference clock inside the system is used as the standard, and the sending clock and the sampling clock are counted respectively. The threshold of the counter is ensured by the jump of the rising and falling edges of the sending clock and the sampling clock. The count value at the most stable moment of the data is obtained by the proportional operation of the two threshold thresholds, and the sending and sampling are completed at this moment. The high and low levels of the transmission signal correspond to different counters. When the system is initially powered on, all threshold counters are 0. When the corresponding frame header data appears in the data, the system starts to judge the high and low levels of the data. When the data stream appears at a rising edge or a falling edge, the corresponding threshold counter starts counting. For edge detection of data stream, the present invention uses a method combining D flip-flop and logic gate to complete edge detection, which reduces resource consumption to the greatest extent. Figure 7As shown in the figure, through the cache of the 2-level D flip-flop, the occurrence of metastable state in asynchronous communication is reduced and it is also used for subsequent edge detection. When a rising edge or falling edge is detected, the corresponding counter starts counting, and the value of the counter at the middle moment is taken as the valid data, and each byte of the incoming data is used as a group to generate a corresponding flag signal for the subsequent module to check and transmit the data. The threshold of the counter is determined by the clock ratio of the sending module and the receiving module: if the sending module rate is n1 and the receiving module rate is n2, the threshold of the counter is (n2 / n1)-1, and when the counter meets the sampling condition, the signal is sampled.

[0027] For the data received by the receiving module, it is necessary to verify the data received from the cache unit to ensure that no erroneous data is transmitted into the system. The data packet received is verified in the data verification conversion module. Traditional data verification is time-consuming and has low processing efficiency. The present invention adopts the idea of ​​pipeline design in this module, and uses the jump of the state machine to complete the verification of each data in the data packet, and outputs a verification signal to ensure the correctness of the data. The correct data is written into the cache unit through the state jump logic in the data verification conversion module. In addition, the receiving module is the same as the sending module, and the receiving parameters are configured by DSP, and different receiving lengths are set to ensure the correct interaction with the sending module data.

[0028] Example 1 The present invention is based on an FPGA-based asynchronous communication method. On the basis of a general asynchronous transmission architecture, a configuration module and a data verification and conversion module are expanded. The expanded architecture includes three basic modules: a sending module, a receiving module, and a control module, as well as a configuration module and a data verification and conversion module. The communication of internal data packets is increased by corresponding frame headers and corresponding verification codes.

[0029] Example 2 The present invention is based on an FPGA-based asynchronous communication method. On the basis of a general asynchronous transmission architecture, a configuration module and a data verification and conversion module are expanded. The expanded architecture includes three basic modules: a sending module, a receiving module, and a control module, as well as a configuration module and a data verification and conversion module. The communication of internal data packets is increased by corresponding frame headers and corresponding verification codes.

[0030] The sending module performs data verification on the parallel data to be sent according to different check polynomials, generates a corresponding check code for each group of data, ensures the correctness of the data received by the subsequent receiving module, combines the parallel data and the corresponding check code inside the sending module, adds a data frame header to the combined new data stream, generates a new set of data stream structure, which has the original data information and the check data to be verified, and transmits the recombined data stream according to the communication clock in the communication system, ensures that the data stream is effectively sent within the corresponding clock cycle, and avoids data stream disorder or missing problems.

[0031] Example 3 The present invention is based on an FPGA-based asynchronous communication method. On the basis of a general asynchronous transmission architecture, a configuration module and a data verification and conversion module are expanded. The expanded architecture includes three basic modules: a sending module, a receiving module, and a control module, as well as a configuration module and a data verification and conversion module. The communication of internal data packets is increased by corresponding frame headers and corresponding verification codes.

[0032] The sending module performs data verification on the parallel data to be sent according to different check polynomials, generates a corresponding check code for each group of data, ensures the correctness of the data received by the subsequent receiving module, combines the parallel data and the corresponding check code inside the sending module, adds a data frame header to the combined new data stream, generates a new set of data stream structure, which has the original data information and the check data to be verified, and transmits the recombined data stream according to the communication clock in the communication system, ensures that the data stream is effectively sent within the corresponding clock cycle, and avoids data stream disorder or missing problems.

[0033] In terms of data reception, after receiving the serial data stream through a serial data line such as an optical fiber, the FPGA as the receiver determines the transmission frame header and data validity of the data, ensuring that the frame header of the incoming data complies with the internal settings of the system. For example, when the frame header of the data stream of the sending module is 0xA1A1, when the frame header of the received serial data stream is determined, only when 0xA1A1 is received can the frame data be considered valid. By jumping the logic of the state machine operation inside the data receiving module, the serial data stream is converted into serial-to-parallel conversion, the converted parallel data is segmented, and the transmitted data is separated into three parts: frame header, data information, and check data value. At the same time, the converted data is checked and compared, and the check result is compared with the check result of the parallel data after the serial data is converted from the serial data to ensure the accuracy of the parallel data after the serial-to-parallel conversion, and the data that passes the check and comparison is transmitted to the storage module in the receiving module. The storage module is composed of FIFO. FIFO is similar to a queue in a data structure. FIFO will give priority to the stored data when needed, so that the subsequent modules can read and calculate it. If the current transmission data is recognized incorrectly or the check fails, the data will be automatically shielded and deleted, so that the erroneous data information cannot enter the storage module, and a corresponding counting signal is generated to locate and count errors in the transmission process.

[0034] Example 4 The present invention is based on an FPGA-based asynchronous communication method. On the basis of a general asynchronous transmission architecture, a configuration module and a data verification and conversion module are expanded. The expanded architecture includes three basic modules: a sending module, a receiving module, and a control module, as well as a configuration module and a data verification and conversion module. The communication of internal data packets is increased by corresponding frame headers and corresponding verification codes.

[0035] The sending module performs data verification on the parallel data to be sent according to different check polynomials, generates a corresponding check code for each group of data, ensures the correctness of the data received by the subsequent receiving module, combines the parallel data and the corresponding check code inside the sending module, adds a data frame header to the combined new data stream, generates a new set of data stream structure, which has the original data information and the check data to be verified, and transmits the recombined data stream according to the communication clock in the communication system, ensures that the data stream is effectively sent within the corresponding clock cycle, and avoids data stream disorder or missing problems.

[0036] In terms of data reception, after receiving the serial data stream through a serial data line such as an optical fiber, the FPGA as the receiver determines the transmission frame header and data validity of the data, ensuring that the frame header of the incoming data complies with the internal settings of the system. For example, when the frame header of the data stream of the sending module is 0xA1A1, when the frame header of the received serial data stream is determined, only when 0xA1A1 is received can the frame data be considered valid. By jumping the logic of the state machine operation inside the data receiving module, the serial data stream is converted into serial-to-parallel conversion, the converted parallel data is segmented, and the transmitted data is separated into three parts: frame header, data information, and check data value. At the same time, the converted data is checked and compared, and the check result is compared with the check result of the parallel data after the serial data is converted from the serial data to ensure the accuracy of the parallel data after the serial-to-parallel conversion, and the data that passes the check and comparison is transmitted to the storage module in the receiving module. The storage module is composed of FIFO. FIFO is similar to a queue in a data structure. FIFO will give priority to the stored data when needed, so that the subsequent modules can read and calculate it. If the current transmission data is recognized incorrectly or the check fails, the data will be automatically shielded and deleted, so that the erroneous data information cannot enter the storage module, and a corresponding counting signal is generated to locate and count errors in the transmission process.

[0037] For the sending module, the system architecture is as follows Figure 3 As shown. In data transmission, not all data is serial-to-serial data transmission. In most cases, it is the mutual conversion of parallel data and serial data. Therefore, a cache unit is used to cache the parallel data to be transmitted. In addition, the cached data is packaged and processed through the state jump module, and the packaged data is passed to the data verification and conversion module to complete the data verification and the generation of the corresponding frame header data, so that the receiving module can verify and identify the data. Considering that the data in data communication is not static, in order to enhance the scalability of the system, the configuration module completes the corresponding sending data packet configuration of the state jump module and the data verification and conversion module by receiving the instructions issued by the DSP, thereby realizing data stream transmission under different situations.

[0038] Example 5 The present invention is based on an FPGA-based asynchronous communication method. On the basis of a general asynchronous transmission architecture, a configuration module and a data verification and conversion module are expanded. The expanded architecture includes three basic modules: a sending module, a receiving module, and a control module, as well as a configuration module and a data verification and conversion module. The communication of internal data packets is increased by corresponding frame headers and corresponding verification codes.

[0039] The sending module performs data verification on the parallel data to be sent according to different check polynomials, generates a corresponding check code for each group of data, ensures the correctness of the data received by the subsequent receiving module, combines the parallel data and the corresponding check code inside the sending module, adds a data frame header to the combined new data stream, generates a new set of data stream structure, which has the original data information and the check data to be verified, and transmits the recombined data stream according to the communication clock in the communication system, ensures that the data stream is effectively sent within the corresponding clock cycle, and avoids data stream disorder or missing problems.

[0040] In terms of data reception, after receiving the serial data stream through a serial data line such as an optical fiber, the FPGA as the receiver determines the transmission frame header and data validity of the data, ensuring that the frame header of the incoming data complies with the internal settings of the system. For example, when the frame header of the data stream of the sending module is 0xA1A1, when the frame header of the received serial data stream is determined, only when 0xA1A1 is received can the frame data be considered valid. By jumping the logic of the state machine operation inside the data receiving module, the serial data stream is converted into serial-to-parallel conversion, the converted parallel data is segmented, and the transmitted data is separated into three parts: frame header, data information, and check data value. At the same time, the converted data is checked and compared, and the check result is compared with the check result of the parallel data after the serial data is converted from the serial data to ensure the accuracy of the parallel data after the serial-to-parallel conversion, and the data that passes the check and comparison is transmitted to the storage module in the receiving module. The storage module is composed of FIFO. FIFO is similar to a queue in a data structure. FIFO will give priority to the stored data when needed, so that the subsequent modules can read and calculate it. If the current transmission data is recognized incorrectly or the check fails, the data will be automatically shielded and deleted, so that the erroneous data information cannot enter the storage module, and a corresponding counting signal is generated to locate and count errors in the transmission process.

[0041] For the sending module, the system architecture is as follows Figure 3As shown. In data transmission, not all data is serial-to-serial data transmission. In most cases, it is the mutual conversion of parallel data and serial data. Therefore, a cache unit is used to cache the parallel data to be transmitted. In addition, the cached data is packaged and processed through the state jump module, and the packaged data is passed to the data verification and conversion module to complete the data verification and the generation of the corresponding frame header data, so that the receiving module can verify and identify the data. Considering that the data in data communication is not static, in order to enhance the scalability of the system, the configuration module completes the corresponding sending data packet configuration of the state jump module and the data verification and conversion module by receiving the instructions issued by the DSP, thereby realizing data stream transmission under different situations.

[0042] The conversion between parallel data and serial data is completed by the data verification and conversion module. This module completes the data conversion based on the counter synchronization method. The data packets sent by the superior are sent out bit by bit through the cycle counting of the counter, and the corresponding flag signal is generated for system recognition. The communication sending data timing is as follows Figure 4 As shown, when the write data enable signal wr_en is set to 1, the data on the transmit buffer tx_buff is valid and is written into the cache and the cache unit in the transmit module. After the data is written, the write data enable signal wr_en is set to 0, and then the transmit data enable signal tx_en is set to 1, marking the start of data serial-to-parallel conversion.

[0043] For the receiving module, the system architecture is as follows Figure 5 As shown in the figure. In actual applications, different boards or systems have different clock sources, and not all communications have corresponding clock paths, so the receiving module needs to perform clock synchronization on the transmitted data to ensure the accuracy of data sampling. The communication receiving data timing is shown in the figure. Figure 6 As shown, after the receive ready signal rx_rdy is set to 1, it represents that a new packet of data has been received. After the data is received successfully, the data read operation starts, the read data enable signal rd_en is set to 1, and the reading starts. The data receiving buffer unit rx_buff outputs data in the next clock cycle after the read data enable signal rd_en is set to 1.

[0044] Example 6 The present invention is based on an FPGA-based asynchronous communication method. On the basis of a general asynchronous transmission architecture, a configuration module and a data verification and conversion module are expanded. The expanded architecture includes three basic modules: a sending module, a receiving module, and a control module, as well as a configuration module and a data verification and conversion module. The communication of internal data packets is increased by corresponding frame headers and corresponding verification codes.

[0045] The sending module performs data verification on the parallel data to be sent according to different check polynomials, generates a corresponding check code for each group of data, ensures the correctness of the data received by the subsequent receiving module, combines the parallel data and the corresponding check code inside the sending module, adds a data frame header to the combined new data stream, generates a new set of data stream structure, which has the original data information and the check data to be verified, and transmits the recombined data stream according to the communication clock in the communication system, ensures that the data stream is effectively sent within the corresponding clock cycle, and avoids data stream disorder or missing problems.

[0046] In terms of data reception, after receiving the serial data stream through a serial data line such as an optical fiber, the FPGA as the receiver determines the transmission frame header and data validity of the data, ensuring that the frame header of the incoming data complies with the internal settings of the system. For example, when the frame header of the data stream of the sending module is 0xA1A1, when the frame header of the received serial data stream is determined, only when 0xA1A1 is received can the frame data be considered valid. By jumping the logic of the state machine operation inside the data receiving module, the serial data stream is converted into serial-to-parallel conversion, the converted parallel data is segmented, and the transmitted data is separated into three parts: frame header, data information, and check data value. At the same time, the converted data is checked and compared, and the check result is compared with the check result of the parallel data after the serial data is converted from the serial data to ensure the accuracy of the parallel data after the serial-to-parallel conversion, and the data that passes the check and comparison is transmitted to the storage module in the receiving module. The storage module is composed of FIFO. FIFO is similar to a queue in a data structure. FIFO will give priority to the stored data when needed, so that the subsequent modules can read and calculate it. If the current transmission data is recognized incorrectly or the check fails, the data will be automatically shielded and deleted, so that the erroneous data information cannot enter the storage module, and a corresponding counting signal is generated to locate and count errors in the transmission process.

[0047] For the sending module, the system architecture is as follows Figure 3As shown. In data transmission, not all data is serial-to-serial data transmission. In most cases, it is the mutual conversion of parallel data and serial data. Therefore, a cache unit is used to cache the parallel data to be transmitted. In addition, the cached data is packaged and processed through the state jump module, and the packaged data is passed to the data verification and conversion module to complete the data verification and the generation of the corresponding frame header data, so that the receiving module can verify and identify the data. Considering that the data in data communication is not static, in order to enhance the scalability of the system, the configuration module completes the corresponding sending data packet configuration of the state jump module and the data verification and conversion module by receiving the instructions issued by the DSP, thereby realizing data stream transmission under different situations.

[0048] The conversion between parallel data and serial data is completed by the data verification and conversion module. This module completes the data conversion based on the counter synchronization method. The data packets sent by the superior are sent out bit by bit through the cycle counting of the counter, and the corresponding flag signal is generated for system recognition. The communication sending data timing is as follows Figure 4 As shown, when the write data enable signal wr_en is set to 1, the data on the transmit buffer tx_buff is valid and is written into the cache and the cache unit in the transmit module. After the data is written, the write data enable signal wr_en is set to 0, and then the transmit data enable signal tx_en is set to 1, marking the start of data serial-to-parallel conversion.

[0049] For the receiving module, the system architecture is as follows Figure 5 As shown in the figure. In actual applications, different boards or systems have different clock sources, and not all communications have corresponding clock paths, so the receiving module needs to perform clock synchronization on the transmitted data to ensure the accuracy of data sampling. The communication receiving data timing is shown in the figure. Figure 6 As shown, after the receive ready signal rx_rdy is set to 1, it represents that a new packet of data has been received. After the data is received successfully, the data read operation starts, the read data enable signal rd_en is set to 1, and the reading starts. The data receiving buffer unit rx_buff outputs data in the next clock cycle after the read data enable signal rd_en is set to 1.

[0050] For the clock synchronization of data, the present invention completes the corresponding signal acquisition based on the duration of high and low levels, and the method for signal acquisition based on high and low levels in the present invention is named as half-half sampling method. The half-half sampling method is based on the Nyquist sampling theorem and is designed by using multiple counters and multiplexers. The Nyquist sampling theorem requires that the sampling clock must be 2 times or more than the sampled data clock. The threshold of the corresponding counter is obtained by calculating the sending clock and the sampling clock, so as to complete the corresponding acquisition according to the threshold range. The reference clock inside the system is used as the standard, and the sending clock and the sampling clock are counted respectively. The threshold of the counter is ensured by the jump of the rising and falling edges of the sending clock and the sampling clock. The count value at the most stable moment of the data is obtained by the proportional operation of the two threshold thresholds, and the sending and sampling are completed at this moment. The high and low levels of the transmission signal correspond to different counters. When the system is initially powered on, all threshold counters are 0. When the corresponding frame header data appears in the data, the system starts to judge the high and low levels of the data. When the data stream appears at a rising edge or a falling edge, the corresponding threshold counter starts counting. For edge detection of data stream, the present invention uses a method combining D flip-flop and logic gate to complete edge detection, which reduces resource consumption to the greatest extent. Figure 7 As shown in the figure, through the cache of the 2-level D flip-flop, the occurrence of metastable state in asynchronous communication is reduced and it is also used for subsequent edge detection. When a rising edge or falling edge is detected, the corresponding counter starts counting, and the value of the counter at the middle moment is taken as the valid data, and each byte of the incoming data is used as a group to generate a corresponding flag signal for the subsequent module to check and transmit the data. The threshold of the counter is determined by the clock ratio of the sending module and the receiving module: if the sending module rate is n1 and the receiving module rate is n2, the threshold of the counter is (n2 / n1)-1, and when the counter meets the sampling condition, the signal is sampled.

[0051] It should be noted that although the present invention is based on FT3 communication, the overall communication rate and resource consumption rate are far superior to traditional FT3 communication. Since Manchester coding is used for data synchronization in traditional FT3 communication, its specific synchronization timing is as follows: Figure 8As shown, because Manchester encodes each data bit into two signal level changes, the transmission rate is half of the original data rate. For example, if the original data rate is 1Mbps, then its transmission rate is only 500kbps, which greatly reduces the transmission rate. In addition, the existence of the encoding and decoding module will lead to higher resource consumption and power consumption. This communication system abandons the data synchronization method of Manchester encoding and traditional edge sampling, and starts sampling from the data source to ensure the stability of the sampling level. In addition, the receiving module can automatically adjust the sampling threshold according to the change of the signal level and the change of the rate at both ends of the communication, so that the entire system has a certain self-synchronization ability, which can effectively reduce the bit error caused by clock deviation. The sampling timing is as follows Fig. 9 As shown, sampling is performed at the middle moment of data conversion, which greatly reduces the number of signal switching times of the receiving module, reduces the power consumption of the system, and the transmission rate is doubled compared with the traditional FT3 protocol.

Claims

1. An asynchronous communication method based on FPGA, characterized in that: On the basis of the general asynchronous transmission architecture, the configuration module and the data verification and conversion module are expanded. The expanded architecture includes three basic modules: the sending module, the receiving module, and the control module, as well as the configuration module and the data verification and conversion module. The communication of the internal data packet adds the corresponding frame header and the corresponding check code.

2. The FPGA-based asynchronous communication method according to claim 1, characterized in that: The sending module performs data verification on the parallel data to be sent according to different check polynomials, generates a corresponding check code for each group of data, ensures the correctness of the data received by the subsequent receiving module, combines the parallel data and the corresponding check code inside the sending module, adds a data frame header to the combined new data stream, generates a new set of data stream structure, which has the original data information and the check data to be verified, and transmits the recombined data stream according to the communication clock in the communication system, ensures that the data stream is effectively sent within the corresponding clock cycle, and avoids data stream disorder or missing problems.

3. The FPGA-based asynchronous communication method according to claim 2, characterized in that: In terms of data reception, after receiving the serial data stream through the serial data line, the FPGA as the receiver judges the transmission frame header and data validity of the data. After ensuring that the frame header of the incoming data meets the internal settings of the system, the state machine running logic jumps inside the data receiving module to complete the serial-to-parallel conversion process of the serial data stream, divides the converted parallel data, and separates the transmitted data into three parts: frame header, data information, and check data value. At the same time, the converted data is checked and compared, and the check result is compared with the check result of the parallel data after the serial data is converted from the serial data to ensure the accuracy of the parallel data after the serial-to-parallel conversion, and the data that passes the check and comparison is transmitted to the storage module in the receiving module. The storage module is composed of FIFO. FIFO will give priority to the incoming stored data and send it out when needed for subsequent modules to read and calculate. If the current transmission data is recognized incorrectly or the check fails, the data will be automatically shielded and deleted so that the erroneous data information cannot enter the storage module, and a corresponding counting signal will be generated to locate and count errors in the transmission process.

4. The FPGA-based asynchronous communication method according to claim 3, characterized in that: For the sending module, a high-speed cache unit is used to cache the parallel data that needs to be transmitted. In addition, the cached data is packaged and processed through the state jump module, and the packaged data is passed to the data verification and conversion module to complete the data verification and generation of the corresponding frame header data for the receiving module to verify and identify the data. The configuration module completes the corresponding sending data packet configuration of the state jump module and the data verification and conversion module by receiving the instructions issued by the DSP, thereby realizing data stream transmission under different situations.

5. The FPGA-based asynchronous communication method according to claim 4, characterized in that: The conversion between parallel data and serial data is completed through the data verification and conversion module. This module completes the data conversion based on the counter synchronization method. The data packet sent by the superior is sent out bit by bit through the cyclic counting of the counter, and the corresponding flag signal is generated for system identification. When the write data enable signal wr_en is set to 1, the data on the transmit buffer tx_buff is valid and is written into the cache unit in the cache and transmit module. After the data is written, the write data enable signal wr_en is set to 0, and then the transmit data enable signal tx_en is set to 1, and the flag starts the data serial-to-parallel conversion.

6. The FPGA-based asynchronous communication method according to claim 5, characterized in that: For the receiving module, the transmitted data needs to be clock synchronized in the receiving module to ensure the accuracy of data sampling. After the receive preparation signal rx_rdy is set to 1, it represents that a new packet of data has been received. After the data is successfully received, the data read operation begins, the read data enable signal rd_en is set to 1, and the reading begins. The data receiving buffer unit rx_buff outputs data in the next clock cycle after the read data enable signal rd_en is set to 1.

7. The FPGA-based asynchronous communication method according to claim 6, characterized in that: For the clock synchronization of data, the corresponding signal acquisition is completed based on the duration of high and low levels, and the method of signal acquisition based on high and low levels is named half-half sampling method. The half-half sampling method is based on the Nyquist sampling theorem and is designed using multiple counters and multiplexers. The Nyquist sampling theorem requires that the sampling clock must be 2 times or more than the sampled data clock. The threshold of the corresponding counter is obtained by calculating the sending clock and the sampling clock, so as to complete the corresponding acquisition according to the threshold range. The internal reference clock of the system is used as the standard, and the sending clock and the sampling clock are counted respectively. The rising and falling edges of the sending clock and the sampling clock are used to ensure the threshold of the counter. The count value at the most stable moment of the data is obtained by proportional operation of the two threshold thresholds, and the sending and sampling are completed at this moment. The high and low levels of the transmission signal correspond to different counters. When the system is initially powered on, all threshold counts The counters are all 0. When the corresponding frame header data appears in the data, the system starts to judge the high and low levels of the data. When the data stream has a rising edge or a falling edge, the corresponding threshold counter starts counting. For the edge detection of the data stream, a method combining D flip-flops and logic gates is used to complete the edge detection. Through the cache of the 2-level D flip-flop, the occurrence of metastable states in asynchronous communication is reduced and it is used for subsequent edge detection. When a rising edge or a falling edge is detected, the corresponding counter starts counting, and the value at the middle moment of the counter is taken as the valid data. Each byte of the incoming data is used as a group to generate a corresponding flag signal for subsequent modules to check and transmit the data. The threshold of the counter is determined by the clock ratio of the sending module and the receiving module: suppose the sending module rate is n1 and the receiving module rate is n2, then the threshold of the counter is (n2 / n1)-1. When the counter meets the sampling condition, the signal is sampled.

8. The FPGA-based asynchronous communication method according to claim 7, characterized in that: For the data received by the receiving module, it is necessary to verify the received data to ensure that no erroneous data is transmitted into the system. The incoming data packet is verified in the data verification conversion module. The idea of ​​pipeline design is adopted in this module, and the state machine jump is used to complete the verification of each data in the data packet, and output the verification signal to ensure the correctness of the data. The correct data is written into the cache unit through the state jump logic in the data verification conversion module. In addition, the receiving module is the same as the sending module. The receiving parameters are configured by DSP and different receiving lengths are set to ensure the correct interaction with the sending module data.

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