Memory cell, semiconductor structure and manufacturing method thereof

Abstract

The disclosed embodiments relate to the field of semiconductors and provide a memory cell, a semiconductor structure, and a method for manufacturing the same. The memory cell includes: a write word line, the write word line being divided into a first region and a second region spaced apart along a first direction; a first semiconductor layer, the first semiconductor layer facing the surface of the second region of the write word line; a write bit line, the write bit line being in contact with and connected to the first semiconductor layer; a conductive layer, the conductive layer being in contact with and connected to the first semiconductor layer, and the conductive layer being spaced apart from the write bit line along the first direction; a read word line, the read word line being in contact with and connected to the first region of the write word line, spaced apart from the conductive layer along the first direction, and located on a side of the conductive layer away from the write bit line along the first direction; and a second semiconductor layer, one end of the second semiconductor layer being in contact with and connected to the write bit line, the other end of the second semiconductor layer being in contact with and connected to the read word line, and also facing a portion of the surface of the conductive layer. This can improve the integration density of the memory cell.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a memory cell, a semiconductor structure, and a method for manufacturing the same. Background Art

[0002] Common dynamic random access memory (DRAM) is of the 1T1C (1Transistor-1Capacitor) type, where a transistor source or drain is electrically connected to a capacitor to form a storage unit. This structure uses capacitors to store data, but because reading consumes the capacitor's power and the capacitor itself leaks electricity, the charge in the capacitor needs to be constantly refreshed, resulting in high power consumption and unstable electrical performance. Furthermore, the large area occupied by the capacitor manufacturing process makes it difficult to scale down the size of the capacitor.

[0003] To overcome the problem caused by capacitance, a 2T0C type memory cell structure is used, that is, the source or drain of a transistor is electrically connected to the gate of another transistor to form a memory cell structure. Summary of the Invention

[0004] The embodiments of the present disclosure provide a memory cell, a semiconductor structure, and a method for manufacturing the same, which can at least improve the integration of the memory cell.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a storage unit, including a write word line, the write word line extending along a first direction, and the write word line is divided into a first region and a second region arranged at intervals along the first direction; a first semiconductor layer, the first semiconductor layer is opposite to the surface of the second region of the write word line; a write bit line, the write bit line is in contact with and connected to the first semiconductor layer; a conductive layer, the conductive layer is in contact with and connected to the first semiconductor layer, and the conductive layer and the write bit line are arranged at intervals along the first direction, a first transistor includes the write word line, the first semiconductor layer, the write bit line and the conductive layer; a read word line, the read word line is in contact with and connected to the first region of the write word line, is arranged at intervals with the conductive layer along the first direction, and the read word line is located on a side of the conductive layer away from the write bit line along the first direction; a second semiconductor layer, one end of the second semiconductor layer is in contact with and connected to the write bit line, the other end is in contact with and connected to the read word line, and is also opposite to a portion of the surface of the conductive layer, a second transistor includes: the conductive layer, the read word line and the second semiconductor layer.

[0006] In some embodiments, the second semiconductor layer covers a portion of a sidewall of the write bit line facing the read word line, and further covers a portion of a sidewall of the read word line facing the write bit line.

[0007] In some embodiments, in a second direction, a width of the first region of the write word line is smaller than a width of the second region of the write word line, and the second direction intersects the first direction.

[0008] In some embodiments, the method further includes: a first dielectric layer located between the write word line and the first semiconductor layer; and a second dielectric layer located between the second semiconductor layer and the conductive layer.

[0009] In some embodiments, the method further includes: a first isolation layer, wherein the first isolation layer is located between the first semiconductor layer and the second dielectric layer, and the first isolation layer is also located between the write word line and the second dielectric layer.

[0010] According to some embodiments of the present disclosure, another aspect of the present disclosure further provides a semiconductor structure, comprising a plurality of memory cells as described above, wherein the plurality of memory cells are arranged at intervals along the first direction and / or the third direction.

[0011] In some embodiments, the write word lines of the memory cells spaced apart along the first direction are in contact with each other.

[0012] In some embodiments, a conductive pillar is contact-connected to the write bit line, and the memory cells spaced apart along the third direction are contact-connected to the same conductive pillar.

[0013] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a stacking structure on the substrate, the stacking structure comprising a first insulating layer and a second insulating layer stacked along a third direction; etching the stacking structure to form a plurality of storage cells spaced apart along the first direction and / or the third direction, the storage cells comprising: a write word line, the write word line extending along the first direction, and the write word line being divided into a first region and a second region spaced apart along the first direction; a first semiconductor layer, the first semiconductor layer being opposite to a surface of the second region of the write word line; a write bit line, the write bit line being in contact and connected to the first semiconductor layer; a conductive layer, the A conductive layer is in contact with and connected to the first semiconductor layer, and the conductive layer and the write bit line are arranged at intervals along the first direction. The first transistor includes the write word line, the first semiconductor layer, the write bit line and the conductive layer; a read word line, the read word line is in contact with and connected to the first region of the write word line, and is arranged at intervals along the first direction with the conductive layer, and the read word line is located on a side of the conductive layer away from the write bit line along the first direction; a second semiconductor layer, one end of the second semiconductor layer is in contact with and connected to the write bit line, and the other end is in contact with and connected to the read word line, and is also opposite to a portion of the surface of the conductive layer. The second transistor includes: the conductive layer, the read word line and the second semiconductor layer.

[0014] In some embodiments, a method for forming write word lines and a first semiconductor layer in a plurality of the memory cells includes: etching a portion of the second insulating layer to form at least one first groove, the first groove extending along the first direction; forming a first semiconductor layer, the first semiconductor layer covering the surface of the second insulating layer exposed by the first groove; forming a write word line, the write word line being opposite to the first semiconductor layer and filling the first groove.

[0015] In some embodiments, the method for forming the write bit lines in the plurality of storage cells includes: etching the second insulating layer to form at least one second groove and at least two third grooves, the second groove exposing the surface of the first semiconductor layer, and the third groove exposing the surface of the first region of the write word line; forming a first isolation layer, the first isolation layer filling the second groove and the third groove; removing the remaining second insulating layer to form three fourth grooves spaced apart at least along the first direction, the three fourth grooves including two edge grooves and a middle groove located between the two edge grooves; forming the write bit line, the write bit line being located in one of the edge grooves.

[0016] In some embodiments, forming the write bit line also includes: forming a conductive layer, wherein the conductive layer is located in the middle groove; and forming a read word line, wherein the read word line is located in another edge groove.

[0017] In some embodiments, the method of forming the second semiconductor layer includes: etching the first isolation layer to form a fifth groove, wherein the fifth groove exposes the side wall of the write bit line, the two side walls of the conductive layer arranged along the first direction, and part of the side wall of the read word line; forming a second semiconductor layer, wherein the second semiconductor layer conformally covers the fifth groove.

[0018] In some embodiments, before forming the second semiconductor layer, the method further includes: forming a second initial dielectric layer, wherein the second initial dielectric layer conformally covers the inner wall of the fifth groove and the sidewall of the conductive layer arranged along the second direction, and the second semiconductor layer covers the surface of the second initial dielectric layer; after forming the second semiconductor layer, the method further includes: etching a portion of the read word line and the second initial dielectric layer covering the sidewall of this portion of the read word line to expose the sidewall of the second semiconductor layer, etching a portion of the write bit line and the second initial dielectric layer covering the sidewall of this portion of the write bit line to form a sixth groove, wherein the sixth groove exposes the sidewall of the second semiconductor layer, and the remaining second initial dielectric layer serves as the second dielectric layer; filling the sixth groove with a conductive material to form the read word line and the write bit line, respectively, which are in contact with the second semiconductor layer; and the first direction, the second direction, and the third direction intersect with each other.

[0019] In some embodiments, before forming the write word line, the method further includes: forming a first dielectric layer, where the first dielectric layer covers a surface of the first semiconductor layer.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: by setting a first transistor including a write word line, a first semiconductor layer, a write bit line and a conductive layer, the conduction of the first transistor is controlled by the write word line, and data information is provided to the write bit line, and when the first transistor is turned on, the data information is transmitted to the conductive layer through the first semiconductor layer; by setting a second transistor including: a conductive layer, a read word line and a second semiconductor layer, the conduction of the second transistor is controlled by the conductive layer, and the current between the second semiconductor layer and the read word line is detected to read whether there is charge stored in the first transistor; by setting the read word line and the write word line in contact connection, the second semiconductor layer and the read word line in contact connection, and by controlling the voltage signals of the write word line and the write bit line, the current between the second semiconductor layer and the read word line can be controlled, and by setting the read word line and the write word line in contact connection, the second semiconductor layer and the read word line in contact connection can further improve the integration of the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A circuit diagram of a storage unit provided in one embodiment of the present disclosure;

[0023] Figure 2 A schematic structural diagram of a storage unit provided in one embodiment of the present disclosure;

[0024] Figure 3 A schematic structural diagram of a first semiconductor structure provided in one embodiment of the present disclosure;

[0025] Figure 4 A schematic structural diagram of a second semiconductor structure provided in one embodiment of the present disclosure;

[0026] Figures 5 to 16 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] As can be seen from the background technology, in the current 2T0C type memory cell structure, only one end of the source and drain of the first transistor is connected to the gate of the other transistor between the first transistor and the second transistor, and the rest of the parts are spaced apart from each other. Therefore, it is necessary to fill an insulating structure to achieve spacing between other structures, which also results in the inability to improve the integration of the memory cell structure.

[0028] An embodiment of the present disclosure provides a storage unit, which includes a first transistor including a write word line, a first semiconductor layer, a write bit line and a conductive layer, so as to control the conduction of the first transistor through the write word line, provide data information to the write bit line, and transmit the data information to the conductive layer through the first semiconductor layer when the first transistor is turned on, and a second transistor including a conductive layer, a read word line and a second semiconductor layer, so as to control the conduction of the second transistor through the conductive layer, and detect the current between the second semiconductor layer and the read word line to read whether there is charge stored in the first transistor, and the read word line and the write word line are contacted and connected, the second semiconductor layer and the read word line are contacted and connected, and the voltage signals of the write word line and the write bit line are controlled, so that the current between the second semiconductor layer and the read word line can be controlled, and the read word line and the write word line are contacted and connected, and the second semiconductor layer and the read word line are contacted and connected, so that the integration of the storage unit can be further improved.

[0029] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0030] refer to Figure 1 and Figure 2 , Figure 1 A circuit diagram of a storage unit provided in an embodiment of the present disclosure is provided. Figure 2 A schematic structural diagram of a storage unit provided in one embodiment of the present disclosure.

[0031] In some embodiments, the memory cell includes a write word line 101 extending along a first direction X, and the write word line 101 is divided into a first region 111 and a second region 121 arranged at intervals along the first direction X.

[0032] The memory cell further includes a first semiconductor layer 102 , and the first semiconductor layer 102 faces a surface of the second region 121 of the write word line 101 .

[0033] The memory cell further includes a write bit line 103 , which is in contact with the first semiconductor layer 102 .

[0034] The memory cell further includes: a conductive layer 104 , the conductive layer 104 is in contact with the first semiconductor layer 102 , and the conductive layer 104 and the write bit line 103 are spaced apart along the first direction X. The first transistor 105 includes a write word line 101 , the first semiconductor layer 102 , the write bit line 103 and the conductive layer 104 .

[0035] The memory cell further includes a read word line 106 , which is in contact with the first region 111 of the write word line 101 and spaced apart from the conductive layer 104 along the first direction X. The read word line 106 is located on a side of the conductive layer 104 away from the write bit line 103 along the first direction X.

[0036] The storage unit also includes: a second semiconductor layer 107, one end of the second semiconductor layer 107 is in contact with the write bit line 103, the other end is in contact with the read word line 106, and is also opposite to a portion of the surface of the conductive layer 104. The second transistor 108 includes: a conductive layer 104, a read word line 106 and a second semiconductor layer 107.

[0037] In the embodiment of the present disclosure, the first transistor 105 is provided with a write word line 101, a first semiconductor layer 102, a write bit line 103 and a conductive layer 104, so as to control the conduction of the first transistor 105 through the write word line 101, and data information is provided to the write bit line 103. When the first transistor 105 is turned on, the data information is transmitted to the conductive layer 104 through the first semiconductor layer 102. The second transistor 108 is provided with a conductive layer 104, a read word line 106 and a second semiconductor layer 107, so as to control the conduction of the second transistor 108 through the conductive layer 104, and detect the first transistor 105. The current between the second semiconductor layer 107 and the read word line 106 is used to read out whether there is charge stored in the first transistor 105. By setting the read word line 106 and the write word line 101 in contact and connection, the second semiconductor layer 107 and the read word line 106 are in contact and connection, and by controlling the voltage signal of the write word line 101 and the write bit line 103, the current between the second semiconductor layer 107 and the read word line 106 can be controlled. By setting the read word line 106 and the write word line 101 in contact and connection, the second semiconductor layer 107 and the read word line 106 are in contact and connection, which can further improve the integration of the storage unit.

[0038] refer to Figure 1 When a write operation is required, you can Figure 1 The write word line 101 and the write bit line 103 are both supplied with voltage signals. For example, 2V is supplied to both the write word line 101 and the write bit line 103. The gate of the first transistor 105 receives the 2V signal, which controls the first transistor 105 to be turned on. The voltage signal of the write bit line 103 is transmitted to the second transistor 108. The gate of the second transistor 108 controls the second transistor to be turned on. Since the write word line 101 is connected to the source of the second transistor 108, the write bit line 103 is connected to the drain of the second transistor 108, and the voltage signal on the write word line 101 is equal to the voltage signal on the write bit line 103, no current can be read on the read word line 106. When no current can be read on the read word line 106, it can be considered that the write operation is completed.

[0039] When a read operation is required, a voltage of -2V can be applied to the write word line 101 and a voltage of 1V can be applied to the write bit line 103. Therefore, the gate of the first transistor 105 cannot control the conduction of the first transistor 105, and the voltage signal of the write bit line 103 cannot be transmitted to the gate of the second transistor 108. Therefore, the voltage signal on the gate of the second transistor 108 is 0V. Since the write word line 101 is connected to the source of the second transistor 108, the write bit line 103 is connected to the drain of the second transistor 108, and the voltage signal on the write bit line 103 is -2V, the voltage difference between the gate and source of the second transistor 108 is 2V, the second transistor 108 is turned on, and the source and drain of the second transistor 108 can be connected. Since the voltage on the source of the second transistor 108 is -2V and the voltage on the drain is 1V, current can be read on the read word line. When current can be read on the read word line, it is considered that the read operation is completed.

[0040] It should be noted that the voltage signals in the above-mentioned write and read operations are only examples for ease of understanding. Write and read operations can also be performed by passing voltages of other voltage values. In the embodiment of the present disclosure, the write word line 101 can serve as the gate of the first transistor 105, the write bit line 103 can serve as one of the source or drain of the first transistor 105, the conductive layer 104 can serve as the other of the source or drain of the first transistor 105, the first semiconductor layer 102 can serve as the channel of the first transistor 105, and the conductive layer 104 can also serve as the gate of the second transistor 108. The part of the second semiconductor layer 107 that is in contact with the write word line 101 serves as the source of the second transistor 108, and the remaining part can serve as the channel of the second transistor 108. The read word line 106 can serve as the drain of the second transistor 108.

[0041] In some embodiments, in the second direction Y, the width of the first region 111 of the write word line 101 is smaller than the width of the second region 121 of the write word line 101, and the second direction Y intersects the first direction X. In other words, the surface of the write word line 101 is not flat, but rather has a step, wherein the step with a smaller width is part of the first region 111, and the step with a larger width is part of the second region 121. By setting the width of the first region 111 of the write word line 101 to be smaller than the width of the second region 121 of the write word line 101, it is ensured that the read word line 106 can contact and connect with the write word line 101 when the read word line 106 is formed. It is also possible to plan the relative positions of the first semiconductor layer 102, the write bit line 103, the read word line 106, and the write word line 101 in advance, thereby facilitating the formation of the memory cell.

[0042] In some embodiments, the material of the write word line 101 can be a metal material, such as tungsten or cobalt. By setting the material of the write word line 101 to a metal material, the transmission rate of the write word line 101 can be increased, thereby improving the performance of the storage unit.

[0043] In some embodiments, a first dielectric layer 109 is further included, and the first dielectric layer 109 is located between the write word line 101 and the first semiconductor layer 102. The first dielectric layer 109 can prevent direct contact between the write word line 101 and the first semiconductor layer 102, thereby preventing carriers in the first semiconductor layer 102 from flowing directly to the write word line 101.

[0044] In some embodiments, the material of the first dielectric layer 109 may be a material with a high relative dielectric constant, such as hafnium oxide or zirconium oxide.

[0045] It should be noted that the relative dielectric constant is a physical parameter that characterizes the dielectric or polarization properties of a dielectric material. Its value is equal to the ratio of the capacitance of a capacitor made with a predetermined material to the capacitance of a capacitor of the same size made with a vacuum as the dielectric.

[0046] In some embodiments, the first semiconductor layer 102 may cover a surface of the first dielectric layer 109 away from the write word line 101 .

[0047] In some embodiments, the first dielectric layer 109 may surround the second region 121 of the write word line 101 , and the first semiconductor layer 102 may surround a surface of the first dielectric layer 109 .

[0048] In some embodiments, the material of the first semiconductor layer 102 may include indium gallium zinc oxide or zinc tin oxide. By setting the material of the oxide semiconductor layer to indium gallium zinc oxide or zinc tin oxide, the ion mobility of the first semiconductor layer 102 can be improved, thereby improving the subsequent performance of the first semiconductor layer 102 as a channel region. The material of the first semiconductor layer 102 may also be one or more of indium zinc oxide, indium gallium silicon oxide, indium tungsten oxide, indium oxide, tin oxide, titanium oxide, magnesium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide, or other similar materials.

[0049] In some embodiments, the material of the write bit line 103 may be the same as that of the write word line 101 , and may be a metal material, thereby increasing the transmission rate of the write bit line 103 and improving the performance of the memory cell.

[0050] In some embodiments, the write bit line 103 may be directly opposite the end of the second region 121 of the write word line 101 away from the first region 111 . That is, the position of the write bit line 103 may be defined by planning the first region 111 and the second region 121 .

[0051] In some embodiments, the conductive layer 104 may be directly opposite to the end of the second region 121 of the write word line 101 close to the first region 111 . That is, the position of the conductive layer 104 may be defined by planning the first region 111 and the second region 121 .

[0052] In some embodiments, the material of the conductive layer 104 may be the same as that of the write bit line 103 , and may be a metal material, thereby increasing the transmission rate of the conductive layer 104 and improving the performance of the memory cell.

[0053] For the first transistor 105 , when the write word line 101 receives a voltage signal and turns on, the first semiconductor layer 102 can be controlled to turn on, thereby controlling data transmission between the write bit line 103 and the conductive layer 104 .

[0054] In some embodiments, the material of the read word line 106 is the same as that of the write word line 101, which can be a metal material. On the one hand, the material difference between the read word line 106 and the write word line 101 can be reduced, thereby reducing the contact resistance between the read word line 106 and the write word line 101. On the other hand, the transmission rate of the read word line 106 can be improved.

[0055] In some embodiments, the memory cell may further include: a second dielectric layer 200, the second dielectric layer 200 being located between the second semiconductor layer 107 and the conductive layer 104. By providing the second dielectric layer 200, the second semiconductor layer 107 and the conductive layer 104 can be isolated, thereby preventing carriers in the second semiconductor layer 107 from flowing directly to the conductive layer 104.

[0056] In some embodiments, the material of the second dielectric layer 200 may be a material with a high relative dielectric constant, such as hafnium oxide or zirconium oxide.

[0057] In some embodiments, the memory cell may further include a first isolation layer 201, the first isolation layer 201 being located between the first semiconductor layer 102 and the second dielectric layer 200. The first isolation layer 201 is also located between the write word line 101 and the second dielectric layer 200. In other words, the first isolation layer 201 may cover the sidewalls of the first semiconductor layer 102 away from the write word line 101, and the second dielectric layer 200 may cover the sidewalls of the first isolation layer 201 away from the first semiconductor layer 102, thereby filling the space between the first semiconductor layer 102 and the second dielectric layer 200 and providing support.

[0058] In some embodiments, the first isolation layer 201 can be located between the write bit line 103 and the conductive layer 104, thereby isolating the write bit line 103 from the conductive layer 104, thereby avoiding direct contact between the write bit line 103 and the conductive layer 104; in some embodiments, the first isolation layer 201 can also be located between the read word line 106 and the conductive layer 104, thereby isolating the read word line 106 from the conductive layer 104, thereby avoiding direct contact between the read word line 106 and the conductive layer 104.

[0059] In some embodiments, the second dielectric layer 200 further covers the sidewall of the first isolation layer 201 away from the write word line 101 .

[0060] In some embodiments, the second semiconductor layer 107 covers a portion of the sidewall of the write bit line 103 facing the read word line 106, and also covers a portion of the sidewall of the read word line 106 facing the write bit line 103. By providing the second semiconductor layer 107 to cover a portion of the sidewall of the write bit line 103 facing the read word line 106, and also covering a portion of the sidewall of the read word line 106 facing the write bit line 103, the contact area between the second semiconductor layer 107 and the write bit line 103 and the read word line 106 can be increased, thereby reducing the contact resistance between the second semiconductor layer 107 and the write bit line 103 and the read word line 106.

[0061] In some embodiments, the semiconductor structure may further include a filling layer 302 . The filling layer 302 is in contact with the second semiconductor layer 107 . The filling layer 302 may fill the semiconductor structure to improve the appearance of the semiconductor structure and may also play a supporting role.

[0062] In the embodiment of the present disclosure, the first transistor 105 is provided with a write word line 101, a first semiconductor layer 102, a write bit line 103 and a conductive layer 104, so as to control the conduction of the first transistor 105 through the write word line 101, and data information is provided to the write bit line 103. When the first transistor 105 is turned on, the data information is transmitted to the conductive layer 104 through the first semiconductor layer 102. The second transistor 108 is provided with a conductive layer 104, a read word line 106 and a second semiconductor layer 107, so as to control the conduction of the second transistor 108 through the conductive layer 104, and detect the first transistor 105. The current between the second semiconductor layer 107 and the read word line 106 is used to read out whether there is charge stored in the first transistor 105. By setting the read word line 106 and the write word line 101 in contact and connection, the second semiconductor layer 107 and the read word line 106 are in contact and connection, and by controlling the voltage signal of the write word line 101 and the write bit line 103, the current between the second semiconductor layer 107 and the read word line 106 can be controlled. By setting the read word line 106 and the write word line 101 in contact and connection, the second semiconductor layer 107 and the read word line 106 are in contact and connection, which can further improve the integration of the storage unit.

[0063] Another embodiment of the present disclosure further provides a semiconductor structure, comprising a plurality of memory cells as in any of the above embodiments, and the plurality of memory cells are arranged at intervals along the first direction X and / or the third direction Z. The semiconductor structure provided by another embodiment of the present disclosure will be described below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as the above embodiments, reference may be made to the corresponding descriptions of the above embodiments, and will not be repeated below.

[0064] refer to Figure 3 and Figure 4 ,in Figure 3 is a schematic structural diagram of memory cells arranged along a first direction in a semiconductor structure, Figure 4 It is a structural diagram of memory cells in a semiconductor structure arranged along a first direction and a third direction.

[0065] In some embodiments, the write word lines 101 of the memory cells arranged at intervals along the first direction X are in contact with each other. In other words, the write word lines 101 of the memory cells arranged at intervals along the first direction X can be an integrated structure, that is, a single write word line 101 can control a plurality of memory cells arranged at intervals along the first direction X. Furthermore, by providing the write word lines 101 of the memory cells arranged at intervals along the first direction X in contact with each other, the reliability of the semiconductor structure can be increased.

[0066] In some embodiments, the write word lines 101 of the memory cells arranged at intervals along the first direction X may be spaced apart from each other, or the write word lines 101 may be isolated by an insulating material.

[0067] In some embodiments, the semiconductor structure may further include a conductive pillar 202, the conductive pillar 202 being in contact with and connected to the write bit line 103, and the memory cells arranged at intervals of Z along the third direction being in contact with and connected to the same conductive pillar 202. By providing the conductive pillar 202, a signal from the write bit line 103 can be extracted, thereby providing an electrical signal to the conductive pillar 202, and thereby providing an electrical signal to the write bit line 103. By providing the memory cells arranged at intervals of Z along the third direction to be in contact with and connected to the same conductive pillar 202, multiple memory cells arranged at intervals of Z along the third direction can be connected via one conductive pillar 202, thereby increasing the integration density of the semiconductor structure.

[0068] In some embodiments, the plurality of conductive pillars 202 may be arranged along the first direction X at intervals.

[0069] In some embodiments, the memory cells arranged at intervals along the third direction Z can be isolated by an insulating layer, so that the write word line 101, the first semiconductor layer 102, the conductive layer 104, the read word line 106 and the second semiconductor layer 107 of the memory cells arranged at intervals along the third direction Z can be isolated, thereby improving the reliability of the semiconductor structure.

[0070] In some embodiments, two adjacent memory cells along the third direction Z may be located on opposite sides of the conductive pillar 202 along the second direction, thereby increasing the distance between the two adjacent memory cells and improving the insulation between the two adjacent memory cells.

[0071] Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which can be used to manufacture the above-mentioned semiconductor structure. The method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that for the parts that are the same or corresponding to the above-mentioned embodiments, reference can be made to the corresponding description of the above-mentioned embodiments, and will not be repeated below.

[0072] refer to Figures 5 to 16 ,in Figures 5 to 16 This is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure, and it should be noted that for the sake of clarity, Figures 5 to 16 The method for forming a memory cell shown in FIG. 1 can be obtained by repeatedly performing the method for forming a memory cell.

[0073] In some embodiments, a method for manufacturing a semiconductor structure may include: providing a substrate 100 .

[0074] The method for manufacturing the semiconductor structure may further include: forming a stacked structure 204 on the substrate 100 , wherein the stacked structure 204 includes a first insulating layer 214 and a second insulating layer 224 stacked along a third direction Z.

[0075] The method for manufacturing the semiconductor structure may further include: etching the stacked structure 204 and forming a plurality of memory cells spaced apart along the first direction X and / or the third direction Z, the memory cells including: a write word line 101, the write word line 101 extending along the first direction X, and the write word line 101 being divided into a first region 111 and a second region 121 spaced apart along the first direction X; a first semiconductor layer 102, the first semiconductor layer 102 being directly opposite to a surface of the second region 121 of the write word line 101; a write bit line 103, the write bit line 103 being in contact with and connected to the first semiconductor layer 102; and a conductive layer 104, the conductive layer 104 being in contact with and connected to the first semiconductor layer 102, and the conductive layer 104 being in contact with and connected to the write bit line 103 along the first direction X. The first transistor 105 includes a write word line 101, a first semiconductor layer 102, a write bit line 103, and a conductive layer 104. The read word line 106 is arranged in a spaced-apart manner with respect to the first region 111 of the write word line 101 and is spaced-apart from the conductive layer 104 along the first direction X. The read word line 106 is located on a side of the conductive layer 104 away from the write bit line 103 along the first direction X. The second semiconductor layer 107 has one end in contact with the write bit line 103 and the other end in contact with the read word line 106, and is also opposite to a portion of the surface of the conductive layer 104. The second transistor 108 includes the conductive layer 104, the read word line 106, and the second semiconductor layer 107.

[0076] refer to Figures 5 to 8 In some embodiments, a method for forming the write word line 101 and the first semiconductor layer 102 in multiple memory cells includes: etching a portion of the second insulating layer 224 to form at least one first groove 205, the first groove 205 extending along the first direction X; forming the first semiconductor layer 102, the first semiconductor layer 102 covering the surface of the second insulating layer 224 exposed by the first groove 205; and forming the write word line 101, the write word line 101 facing the first semiconductor layer 102 and completely filling the first groove 205. Etching a portion of the second insulating layer 224 to form the first groove 205 provides a process foundation for the subsequent formation of the first semiconductor layer 102 and the write word line 101.

[0077] refer to Figure 5 , providing a substrate 100 and forming a stacked structure 204 .

[0078] The first insulating layer 214 and the second insulating layer 224 in the stacked structure 204 can have a high etching selectivity ratio, thereby avoiding affecting the first insulating layer 214 during the etching process of the second insulating layer 224. The first insulating layer 214 can also serve as an isolation layer for the storage cells arranged along the third direction Z, thereby avoiding electrical connection between the storage cells arranged along the third direction Z.

[0079] refer to Figure 6 and Figure 7 , forming a first groove 205.

[0080] refer to Figure 8 In some embodiments, before forming the write word line 101, a first dielectric layer 109 may be formed. The formed first dielectric layer 109 may cover the surface of the first semiconductor layer 102 away from the second insulating layer 224. The formed write word line 101 also covers the surface of the first dielectric layer 109 away from the first semiconductor layer 102.

[0081] refer to Figures 9 to 12 The method for forming the write bit lines 103 in the plurality of memory cells includes: etching the second insulating layer 224 to form at least one second groove 206 and at least two third grooves 207, wherein the second groove 206 exposes the surface of the first semiconductor layer 102, and the third groove 207 exposes the surface of the first region 121 of the write word line 101; forming a first isolation layer 201, wherein the first isolation layer 201 completely fills the second groove 206 and the third groove 207; removing the remaining second insulating layer 224 to form three fourth grooves 208 arranged at intervals along at least the first direction X, wherein the three fourth grooves 208 include two edge grooves 218 and a middle groove 228 located between the two edge grooves 218; and forming the write bit line 103, wherein the write bit line 103 is located within one of the edge grooves 218. The position of the fourth groove 208 can be defined by forming the second groove 206 and the third groove 207. The fourth groove 208 can be formed by forming the first isolation layer 201 and removing the second insulating layer 224. The formation of the fourth groove 208 can provide a basis for forming the write bit line 103, the conductive layer 104 and the read word line.

[0082] refer to Figure 9 , the second insulating layer 224 is etched to form at least one second groove 206 and at least two third grooves 207 , where the second groove 206 is directly opposite to the second region 121 of the write word line 101 .

[0083] In some embodiments, the process of etching the second insulating layer 224 to form the third groove 207 further includes: etching a portion of the first semiconductor layer 102 and the first dielectric layer 109, and etching a portion of the write word line 101 in the first region 111, so as to form a first region 111 of the write word line 101 along the second direction Y, where the width is smaller than the width of the second region 121.

[0084] In some embodiments, the two third grooves 207 are also connected to each other, that is, in the process of forming the third grooves 207, a portion of the second insulating layer 224 located between the two third grooves 207 is also laterally etched, and the write word line 101 of the first region 111 is etched so that along the second direction Y, the width of the first region 111 is smaller than the width of the second region 121 everywhere.

[0085] Etching part of the write word line 101 can also ensure that the side surface of the write word line 101 arranged along the second direction is exposed, thereby ensuring contact connection between the subsequently formed read word line 106 and the write word line 101.

[0086] refer to Figure 10 , forming a first isolation layer 201.

[0087] In some embodiments, during the process of forming the third groove 207 , a portion of the second insulating layer 224 between the two third grooves 207 is also laterally etched, and during the process of forming the first isolation layer 201 , the groove formed by the laterally etching portion is also filled.

[0088] refer to Figure 11 , remove the second insulating layer 224 to form a fourth groove 208. For forming a memory cell, there are three fourth grooves 208, one of which exposes the first region 111 of the write word line 101, and the other two expose the sidewalls of the first semiconductor layer 102. One of the fourth grooves 208 exposed on the sidewalls of the first semiconductor layer 102 is used to form the conductive layer 104, and the other is used to form the write bit line 103.

[0089] In some embodiments, during the process of forming the third groove 207, a portion of the second insulating layer 224 located between the two third grooves 207 is also laterally etched. During the process of forming the fourth groove 208 that exposes the first region 111 of the write word line 101, a portion of the first isolation layer 201 that is in contact with the second insulating layer 224 is also etched until the surface of the write word line 101 is exposed.

[0090] refer to Figure 12 , forming a write bit line 103.

[0091] In some embodiments, forming the write bit line 103 also includes forming a conductive layer 104, where the conductive layer 104 is located in the middle groove 228; and forming a read word line 106, where the read word line 106 is located in another edge groove 218. In other words, the write bit line 103, the conductive layer 104, and the read word line 106 are formed in the same process step. By forming the conductive layer 104 and the read word line 106 simultaneously with the write bit line 103, the number of process steps for the entire semiconductor structure can be reduced.

[0092] refer to Figure 13 and Figure 14 In some embodiments, the method of forming the second semiconductor layer 107 includes: etching the first isolation layer 201 to form a fifth recess 209, wherein the fifth recess 209 exposes the sidewalls of the write bit line 103, two sidewalls of the conductive layer 104 arranged along the first direction X, and a portion of the sidewall of the read word line 106; and forming the second semiconductor layer 107, wherein the second semiconductor layer 107 conformally covers the fifth recess 209. The formation of the fifth recess 209 provides a process foundation for forming the second semiconductor layer 107.

[0093] refer to Figure 13 , etching the first isolation layer 201.

[0094] In some embodiments, etching the first isolation layer 201 exposes a portion of the sidewall of the write bit line 103 , a portion of the surface of the conductive layer 104 , and a portion of the sidewall of the read word line 106 .

[0095] refer to Figure 14 Before forming the second semiconductor layer 107 , the method further includes: forming a second initial dielectric layer 210 , wherein the second initial dielectric layer 210 conformally covers the inner wall of the fifth groove 209 and the sidewall of the conductive layer 104 arranged along the second direction Y, and the second semiconductor layer 107 covers the surface of the second initial dielectric layer 210 .

[0096] More specifically, the second initial dielectric layer 210 covers the sidewalls of the write bit line 103 exposed by the fifth groove 209, covers the sidewalls of the remaining first isolation layer 201 arranged along the second direction Y, covers the surface of the conductive layer 104 exposed by the fifth groove 209, and also covers the sidewalls of the read word line 106 exposed by the fifth groove 209.

[0097] After forming the second initial dielectric layer 210 , the second semiconductor layer 107 is formed. The second semiconductor layer 107 covers the surface of the second initial dielectric layer 210 .

[0098] In some embodiments, a filling layer 302 is further formed after the second semiconductor layer 107 is formed, and the filling layer 302 fills the fifth groove 209 .

[0099] refer to Figure 15 and Figure 16 After forming the second semiconductor layer 107, the following steps further include: etching a portion of the read word line 106 and the second initial dielectric layer 210 covering the sidewalls of the read word line 106 to expose the sidewalls of the second semiconductor layer 107; etching a portion of the write bit line 103 and the second initial dielectric layer 210 covering the sidewalls of the write bit line 103 to form a sixth groove 301, wherein the sixth groove 301 exposes the sidewalls of the second semiconductor layer 107, and the remaining second initial dielectric layer 210 serves as the second dielectric layer 200; filling the sixth groove 301 with a conductive material to form the read word line 106 and the write bit line 103, respectively, which are in contact with the second semiconductor layer 107; and the first direction X, the second direction Y, and the third direction Z intersect with each other.

[0100] In other words, it is necessary to form a read word line 106 and a write bit line 103 that are in contact with the second semiconductor layer 107. However, a second initial dielectric layer 210 is formed in front to isolate the second semiconductor layer 107 from the read word line 106 and also isolate the second semiconductor layer 107 from the write bit line 103. Therefore, by first removing the portion of the read word line 106 that is in contact with the second initial dielectric layer 210, while etching the read word line 106, the second initial dielectric layer 210 that is in contact with the read word line 106 is removed to expose the surface of the second semiconductor layer 107, and then fill the second semiconductor layer 107 with the second initial dielectric layer 210. The conductive material is then filled in, and the newly formed conductive film layer is in contact with and connected to the second semiconductor layer 107 and the remaining read word lines 106. Similarly, in order to form the write bit line 103 in contact with the second semiconductor layer 107, the portion of the write bit line 103 in contact with the second initial dielectric layer 210 is first removed. While etching the write bit line 103, the portion of the second initial dielectric layer 210 in contact with the write bit line 103 is removed to expose the surface of the second semiconductor layer 107. The conductive material is then filled in, and the newly formed conductive film layer is in contact with and connected to the second semiconductor layer 107 and the remaining write bit line 103.

[0101] refer to Figure 16 In some embodiments, along the second direction Y, the length of the portion of the write bit line 103 in contact with the second semiconductor layer 107 is greater than the length of the portion of the write bit line 103 in contact with the first isolation layer 201; the length of the portion of the read word line 106 in contact with the second semiconductor layer 107 is greater than the length of the portion of the read word line 106 in contact with the first isolation layer 201, thereby ensuring that the first isolation layer 201 has a certain isolation effect while reducing the contact resistance between the write bit line 103 and the second semiconductor layer 107, and reducing the contact resistance between the read word line 106 and the second semiconductor layer 107.

[0102] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A storage unit, characterized in that: include: A write word line, the write word line extending along a first direction and divided into a first region and a second region arranged at intervals along the first direction; a first semiconductor layer, the first semiconductor layer facing a surface of the second region of the write word line; a write bit line, the write bit line being in contact with and connected to the first semiconductor layer; a conductive layer, the conductive layer being in contact with and connected to the first semiconductor layer, and the conductive layer and the write bit line being spaced apart along the first direction, the first transistor comprising the write word line, the first semiconductor layer, the write bit line, and the conductive layer; a read word line, the read word line being in contact with and connected to the first region of the write word line, being spaced apart from the conductive layer along the first direction, and being located on a side of the conductive layer away from the write bit line along the first direction; A second semiconductor layer, one end of the second semiconductor layer is in contact with the write bit line, the other end is in contact with the read word line, and is also opposite to a portion of the surface of the conductive layer. The second transistor includes: the conductive layer, the read word line and the second semiconductor layer.

2. The storage unit according to claim 1, wherein The second semiconductor layer covers a portion of a sidewall of the write bit line facing the read word line, and further covers a portion of a sidewall of the read word line facing the write bit line.

3. The storage unit according to claim 1, wherein In a second direction, a width of the first region of the write word line is smaller than a width of the second region of the write word line, and the second direction intersects the first direction.

4. The storage unit according to claim 1, wherein: Also includes: a first dielectric layer, wherein the first dielectric layer is located between the write word line and the first semiconductor layer; A second dielectric layer is located between the second semiconductor layer and the conductive layer.

5. The storage unit according to claim 4, wherein: Also includes: A first isolation layer is located between the first semiconductor layer and the second dielectric layer, and is also located between the write word line and the second dielectric layer.

6. A semiconductor structure, characterized in that The storage device comprises a plurality of storage units according to any one of claims 1 to 5, and the plurality of storage units are arranged at intervals along the first direction and / or the third direction.

7. The semiconductor structure according to claim 6, wherein: The write word lines of the memory cells arranged at intervals along the first direction are in contact with each other.

8. The semiconductor structure according to claim 6, wherein: Also includes: A conductive pillar is in contact with the write bit line, and the memory cells spaced apart along the third direction are in contact with the same conductive pillar.

9. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising a first insulating layer and a second insulating layer stacked along a third direction; The stacked structure is etched to form a plurality of memory cells spaced apart along the first direction and / or the third direction, wherein the memory cells include: a write word line, the write word line extending along the first direction and being divided into a first region and a second region spaced apart along the first direction; a first semiconductor layer, the first semiconductor layer facing a surface of the second region of the write word line; a write bit line, the write bit line being in contact with and connected to the first semiconductor layer; a conductive layer, the conductive layer being in contact with and connected to the first semiconductor layer, and the conductive layer and the write bit line being spaced apart along the first direction, and a first The transistor includes the write word line, the first semiconductor layer, the write bit line and the conductive layer; a read word line, the read word line is in contact with the first region of the write word line, and is spaced apart from the conductive layer along the first direction, and the read word line is located on the side of the conductive layer away from the write bit line along the first direction; a second semiconductor layer, one end of the second semiconductor layer is in contact with the write bit line, the other end is in contact with the read word line, and is also opposite to a portion of the surface of the conductive layer. The second transistor includes: the conductive layer, the read word line and the second semiconductor layer.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: The method of forming the write word lines and the first semiconductor layer in the plurality of memory cells includes: Etching a portion of the second insulating layer to form at least one first groove, wherein the first groove extends along the first direction; forming a first semiconductor layer, wherein the first semiconductor layer covers the surface of the second insulating layer exposed by the first groove; A write word line is formed, wherein the write word line is opposite to the first semiconductor layer and completely fills the first groove.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: The method of forming the write bit lines in the plurality of memory cells comprises: Etching the second insulating layer to form at least one second groove and at least two third grooves, wherein the second groove exposes the surface of the first semiconductor layer, and the third groove exposes the surface of the first region of the write word line; forming a first isolation layer, wherein the first isolation layer completely fills the second groove and the third groove; Removing the remaining second insulating layer to form three fourth grooves spaced apart at least along the first direction, wherein the three fourth grooves include two edge grooves and a middle groove located between the two edge grooves; The write bit line is formed, and the write bit line is located in one of the edge grooves.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein: The step of forming the write bit line also includes: forming a conductive layer, wherein the conductive layer is located in the middle groove; A read word line is formed, where the read word line is located in another edge groove.

13. The method for manufacturing a semiconductor structure according to claim 12, wherein: The method for forming the second semiconductor layer includes: etching the first isolation layer to form a fifth groove, wherein the fifth groove exposes a sidewall of the write bit line, two sidewalls of the conductive layer arranged along the first direction, and a portion of the sidewall of the read word line; A second semiconductor layer is formed, wherein the second semiconductor layer conformally covers the fifth groove.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein: Before forming the second semiconductor layer, the method further includes: forming a second initial dielectric layer, wherein the second initial dielectric layer conformally covers the inner wall of the fifth groove and the sidewall of the conductive layer arranged along the second direction, and the second semiconductor layer covers the surface of the second initial dielectric layer; After forming the second semiconductor layer, the method further includes: etching a portion of the read word line and the second initial dielectric layer covering the sidewalls of the read word line to expose the sidewalls of the second semiconductor layer, etching a portion of the write bit line and the second initial dielectric layer covering the sidewalls of the write bit line to form a sixth groove, wherein the sixth groove exposes the sidewalls of the second semiconductor layer, and the remaining second initial dielectric layer serves as the second dielectric layer; Filling the sixth groove with a conductive material to form the read word line and the write bit line respectively contacting the second semiconductor layer; The first direction, the second direction, and the third direction intersect with each other.

15. The method for manufacturing a semiconductor structure according to claim 10, wherein: Before forming the write word line, the method further includes forming a first dielectric layer, wherein the first dielectric layer covers the surface of the first semiconductor layer.

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