3D memory

Abstract

A 3D memory provided by the present invention comprises a substrate, semiconductor units, word lines and bit lines, each semiconductor unit extends along a first direction parallel to the substrate, and the plurality of semiconductor units are respectively distributed at intervals along a second direction and a third direction; each word line is connected with a column of semiconductor units which are distributed at intervals in the second direction, a first Pt metal layer is arranged between the word line and the semiconductor units, and a first Ti metal layer is arranged between the first Pt metal layer and the semiconductor units; each bit line is connected with a row of semiconductor units which are distributed at intervals in the third direction, a second Pt metal layer is arranged between the bit line and the semiconductor units, and a second Ti metal layer is arranged between the second Pt metal layer and the semiconductor units. According to the invention, the contact performance of the metal and the semiconductor unit can be effectively improved, the series resistance is reduced, and the overall working performance of the 3D memory is improved.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a 3D memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory. Multi-layer stacked 3D DRAM can effectively improve storage density. When the number of stacked layers is large enough, 3D DRAM can show obvious performance and cost advantages.

[0003] In the existing 3D DRAM structure, word lines and bit lines made of metal materials are usually used to contact and connect with semiconductor elements respectively. Since the metal material and the semiconductor element are made of different materials, the metal is easy to diffuse into the interior of the semiconductor element when the two are in contact, thereby easily generating a potential barrier and causing increased resistance. The increased resistance will cause the turn-on voltage to be too high, thereby generating heat, thereby damaging the performance of the 3D memory and causing the performance of the 3D memory to decline. Summary of the invention

[0004] The object of the present invention is to provide a 3D memory capable of solving the problem of poor performance of existing 3D memories.

[0005] The present invention provides a 3D memory, comprising a substrate, a plurality of long strip-shaped semiconductor units, a plurality of word lines made of metal material and a plurality of bit lines made of metal material, each of the semiconductor units extending along a first direction parallel to the substrate, and the plurality of semiconductor units are respectively spaced apart along a second direction parallel to the substrate and a third direction perpendicular to the substrate; each of the word lines is connected to a column of the semiconductor units spaced apart along the second direction, and a first Pt metal layer is provided between the word line and the semiconductor unit, and a first Ti metal layer is provided between the first Pt metal layer and the semiconductor unit; each of the bit lines is connected to a column of the semiconductor units spaced apart along the third direction, and a second Pt metal layer is provided between the bit line and the semiconductor unit, and a second Ti metal layer is provided between the second Pt metal layer and the semiconductor unit.

[0006] According to a 3D memory provided by the present invention, the first Ti metal layer is disposed around and in contact with the outer peripheral surface of the semiconductor unit.

[0007] According to a 3D memory provided by the present invention, the first Pt metal layer is arranged around and in contact with the outer peripheral surface of the first Ti metal layer.

[0008] According to a 3D memory provided by the present invention, the word line is arranged to surround and adhere to the outer peripheral surface of the first Pt metal layer.

[0009] According to a 3D memory provided by the present invention, the second Ti metal layer is disposed around and in contact with the outer peripheral surface of the semiconductor unit.

[0010] According to a 3D memory provided by the present invention, the second Pt metal layer is arranged around and in contact with the outer peripheral surface of the second Ti metal layer.

[0011] According to a 3D memory provided by the present invention, the bit line is arranged around and in contact with the outer peripheral surface of the second Pt metal layer.

[0012] According to a 3D memory provided by the present invention, the material of the word line is metal tungsten, and the material of the bit line is metal tungsten.

[0013] A 3D memory provided according to the present invention further includes a plurality of capacitors corresponding to the word lines one by one, each of the capacitors is connected to a column of the semiconductor units spaced apart along the second direction, and the capacitors are arranged around the outer circumference of the semiconductor unit.

[0014] A 3D memory provided according to the present invention further comprises two supporting bodies, wherein the two supporting bodies are arranged opposite to each other on the substrate, and two ends of each semiconductor unit are respectively inserted into the two supporting bodies.

[0015] The 3D memory provided by the present invention can effectively prevent the metal of the word line and the bit line from diffusing into the interior of the semiconductor unit by arranging a first Pt metal layer between the word line made of metal material and the semiconductor unit, and by arranging a second Pt metal layer between the bit line made of metal material and the semiconductor unit; and can be well adhered and fixed to the outer peripheral surface of the semiconductor unit by arranging a first Ti metal layer between the first Pt metal layer and the semiconductor unit, and by arranging a second Ti metal layer between the second Pt metal layer and the semiconductor unit, so that the contact performance between the metal and the semiconductor unit can be effectively increased, the series resistance can be reduced, and the overall working performance of the semi-3D memory can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1It is a main view cross-sectional view of the 3D memory of the present invention;

[0018] Figure 2 It is a top view cross-sectional view of the 3D memory of the present invention.

[0019] Description of reference numerals:

[0020] 1. Substrate; 2. Semiconductor unit; 3. Word line; 4. Bit line; 5. First Pt metal layer; 6. First Ti metal layer; 7. Second Pt metal layer; 8. Second Ti metal layer; 9. Capacitor; 10. First insulating layer; 11. Second insulating layer; 12. Support body. DETAILED DESCRIPTION

[0021] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0023] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. In addition, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0024] like Figure 1 and Figure 2As shown, the 3D memory of the embodiment of the present invention comprises a substrate 1, a plurality of long strip-shaped semiconductor units 2, a plurality of metal word lines 3 and a plurality of metal bit lines 4, each semiconductor unit 2 extends along a first direction A parallel to the substrate 1, and the plurality of semiconductor units 2 are spaced apart along a second direction B parallel to the substrate 1 and a third direction C perpendicular to the substrate 1. Each word line 3 is connected to a column of semiconductor units 2 spaced apart along the second direction B, and a first Pt metal layer 5 is provided between the word line 3 and the semiconductor unit 2, and a first Ti metal layer 6 is provided between the first Pt metal layer 5 and the semiconductor unit 2. Each bit line 4 is connected to a column of semiconductor units 2 spaced apart along the third direction C, and a second Pt metal layer 7 is provided between the bit line 4 and the semiconductor unit 2, and a second Ti metal layer 8 is provided between the second Pt metal layer 7 and the semiconductor unit 2.

[0025] Therefore, the 3D memory of the embodiment of the present invention can effectively prevent the metal of the word line 3 and the bit line 4 from diffusing into the interior of the semiconductor unit 2 by setting the first Pt metal layer 5 between the metal word line 3 and the semiconductor unit 2, and by setting the second Pt metal layer 7 between the metal bit line 4 and the semiconductor unit 2; by setting the first Ti metal layer 6 between the first Pt metal layer 5 and the semiconductor unit 2, and by setting the second Ti metal layer 8 between the second Pt metal layer 7 and the semiconductor unit 2, they can be well adhered and fixed to the outer peripheral surface of the semiconductor unit 2, thereby effectively increasing the contact performance between the metal and the semiconductor unit 2, reducing the series resistance, and further improving the overall working performance of the semi-3D memory.

[0026] Specifically, the material of the word line 3 is metal tungsten, and the material of the bit line 4 is metal tungsten.

[0027] In some embodiments of the present invention, the first Ti metal layer 6 is arranged around and in contact with the outer peripheral surface of the semiconductor unit 2. The first Pt metal layer 5 is arranged around and in contact with the outer peripheral surface of the first Ti metal layer 6. The word line 3 is arranged around and in contact with the outer peripheral surface of the first Pt metal layer 5. That is, each column of semiconductor units 2 spaced apart along the second direction passes through the corresponding word line 3, and the first Ti metal layer 6 and the first Pt metal layer 5 are arranged around the connection part between the semiconductor unit 2 and the word line 3 from the inside to the outside in sequence, thereby ensuring reliable connection between the word line 3 and the semiconductor unit 2 while also increasing the contact connection performance between the word line 3 and the semiconductor unit 2.

[0028] In some embodiments of the present invention, the second Ti metal layer 8 is arranged around and in contact with the outer peripheral surface of the semiconductor unit 2. The second Pt metal layer 7 is arranged around and in contact with the outer peripheral surface of the second Ti metal layer 8. The bit line 4 is arranged around and in contact with the outer peripheral surface of the second Pt metal layer 7. That is, each column of semiconductor units 2 spaced apart along the third direction passes through the corresponding bit line 4, and the second Ti metal layer 8 and the second Pt metal layer 7 are arranged around the connection part between the semiconductor unit 2 and the bit line 4 from the inside to the outside, thereby ensuring a reliable connection between the bit line 4 and the semiconductor unit 2, and also increasing the contact connection performance between the bit line 4 and the semiconductor unit 2.

[0029] Specifically, the substrate 1 can be made of semiconductor material, insulating material, conductive material or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure.

[0030] In some embodiments of the present invention, the 3D memory further includes a plurality of capacitors 9 corresponding to the word lines 3 one by one, each capacitor 9 is connected to a column of semiconductor units 2 spaced apart along the second direction, and the capacitors 9 are arranged around the outer circumference of the semiconductor unit 2. That is, the capacitors 9 arranged on the semiconductor units 2 arranged along the second direction B are sequentially connected to form an integrated structure for accessing the same reference potential.

[0031] A first insulating layer 10 is provided between two adjacent capacitors 9 along the third direction C to ensure insulation between the two adjacent capacitors 9 along the third direction C. The material of the first insulating layer 10 may be oxide, nitride, oxynitride or carbide, for example, the oxide may be silicon dioxide (SiO2), the nitride may be silicon nitride (SiN), the oxynitride may be silicon oxynitride (SiON), and the carbide may be silicon carbide.

[0032] Specifically, a second insulating layer 11 is provided between two adjacent word lines 3 along the third direction C to ensure insulation between the two adjacent word lines 3 along the third direction C. The second insulating layer 11 may be made of oxide, nitride, oxynitride or carbide. For example, the oxide may be silicon dioxide (SiO2), the nitride may be silicon nitride (SiN), the oxynitride may be silicon oxynitride (SiON), and the carbide may be silicon carbide.

[0033] In some embodiments of the present invention, the 3D memory further includes two support bodies 12, which are arranged on the substrate 1 in a relative manner, and the two ends of each semiconductor unit 2 are respectively inserted into the two support bodies 12. That is, by providing two support bodies 12 for supporting each semiconductor unit 2, a semiconductor unit array arranged in intervals along the second direction B and the third direction C can be formed on the substrate 1.

[0034] The material of the support structure 80 may be oxide, nitride, oxynitride or carbide. For example, the oxide may be silicon dioxide (SiO2), the nitride may be silicon nitride (SiN), the oxynitride may be silicon oxynitride (SiON), and the carbide may be silicon carbide.

[0035] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A 3D memory, comprising a substrate, a plurality of long strip-shaped semiconductor units, a plurality of metal word lines and a plurality of metal bit lines, characterized in that: Each of the semiconductor units extends along a first direction parallel to the substrate, and the plurality of semiconductor units are spaced apart along a second direction parallel to the substrate and a third direction perpendicular to the substrate, respectively; each of the word lines is connected to a column of the semiconductor units spaced apart along the second direction, and a first Pt metal layer is provided between the word line and the semiconductor unit, and a first Ti metal layer is provided between the first Pt metal layer and the semiconductor unit; each of the bit lines is connected to a column of the semiconductor units spaced apart along the third direction, and a second Pt metal layer is provided between the bit line and the semiconductor unit, and a second Ti metal layer is provided between the second Pt metal layer and the semiconductor unit.

2. The 3D memory according to claim 1, characterized in that: The first Ti metal layer is disposed around and in contact with the outer peripheral surface of the semiconductor unit.

3. The 3D memory according to claim 2, characterized in that: The first Pt metal layer is disposed around and in contact with the outer peripheral surface of the first Ti metal layer.

4. The 3D memory according to claim 3, characterized in that: The word line is disposed around and in contact with the outer peripheral surface of the first Pt metal layer.

5. The 3D memory according to claim 1, characterized in that: The second Ti metal layer is disposed around and in contact with the outer peripheral surface of the semiconductor unit.

6. The 3D memory according to claim 5, characterized in that: The second Pt metal layer is disposed around and in contact with the outer peripheral surface of the second Ti metal layer.

7. The 3D memory according to claim 6, characterized in that: The bit line is arranged around and in contact with the outer peripheral surface of the second Pt metal layer.

8. The 3D memory according to claim 1, characterized in that: The material of the word line is metal tungsten, and the material of the bit line is metal tungsten.

9. The 3D memory according to claim 1, characterized in that: It also includes a plurality of capacitors corresponding to the word lines one by one, each of the capacitors is connected to a column of the semiconductor units spaced apart along the second direction, and the capacitors are arranged around the outer peripheral surface of the semiconductor unit.

10. The 3D memory according to claim 1, characterized in that: It also includes two supporting bodies, which are arranged on the substrate opposite to each other, and two ends of each semiconductor unit are correspondingly inserted into the two supporting bodies.

Images