Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a preparation method of a semiconductor structure and the semiconductor structure, the semiconductor structure comprises a plurality of channel layers, and bit lines and capacitors can be electrically connected to source ends and drain ends at the two ends of the channel layers respectively. A single crystal material is arranged in the channel layer, so that the leakage problem caused by high scattering in a polycrystalline channel can be effectively reduced, and the conduction performance of the channel layer is ensured. Moreover, the plurality of channel layers are stacked in the first direction intersecting with the surface of the substrate, so that the space above the substrate can be more fully utilized, the channel layers are stacked in the direction intersecting with the surface of the substrate, and the stacking density of the channel layers is remarkably improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure thereof. Background Art

[0002] Traditional dynamic random access memory (DRAM) is usually a 1T1C structure, that is, a storage unit includes a transistor and a capacitor. In order to ensure the conduction performance of the transistor, the channel of the transistor is usually arranged in sequence along the surface of the substrate. This arrangement limits the further reduction of the device size and the further increase of the transistor density. Therefore, the density of semiconductor devices still needs to be further improved. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor structure to address the problems in the above-mentioned background technology, so as to further improve the density of semiconductor devices while ensuring the conduction performance of transistors.

[0004] According to some embodiments of the present disclosure, a method for preparing a semiconductor structure is provided, comprising:

[0005] Preparing a plurality of support layers and a plurality of precursor layers on a substrate, wherein the support layers and the precursor layers are alternately stacked along a first direction;

[0006] Performing an amorphization treatment on one side surface of the precursor layer to form an amorphous portion;

[0007] preparing a crystallization inducing layer in contact with the amorphous portion and performing a heat treatment so that the precursor layer is converted into a single crystal material and a channel layer is formed, wherein the channel layer has a source terminal and a drain terminal;

[0008] forming a bit line, wherein the bit line extends along a third direction;

[0009] forming a capacitor, wherein the bit line and the capacitor are electrically connected to the source terminal and the drain terminal respectively;

[0010] A word line is formed, the word line extending along the first direction, the word line being used to control the channel layer.

[0011] In some embodiments of the present disclosure, the precursor layer includes silicon element, and the material of the crystallization inducing layer includes silicon-nickel metal compound.

[0012] In some embodiments of the present disclosure, the precursor layer is polycrystalline silicon, and the precursor layer further includes a doping element, and the doping concentration of the doping element in the polycrystalline silicon is 10 16 cm -3 ~1019 cm -3 .

[0013] In some embodiments of the present disclosure, the step of preparing a crystallization inducing layer in contact with the amorphous portion includes: preparing a nickel metal material layer on the amorphous portion, and reacting the nickel metal material layer with the amorphous portion to form the crystallization inducing layer.

[0014] In some embodiments of the present disclosure, the step of amorphizing a surface of one side of the precursor layer includes: injecting ions into the surface of the precursor layer by ion implantation.

[0015] In some embodiments of the present disclosure, the precursor layer includes a plurality of spacers and a connecting portion connected to one end of the spacers in the second direction, the plurality of spacers are arranged in parallel and spaced relation along a third direction, and the first direction, the second direction and the third direction intersect each other;

[0016] Before amorphizing the surface of one side of the precursor layer, the method further includes the following steps: removing the connecting portion to form a bit line accommodating area, removing a portion of the spacer away from the connecting portion to form a capacitor accommodating area, and preparing a bit line sacrificial layer and a capacitor sacrificial layer in the bit line accommodating area and the capacitor accommodating area, respectively;

[0017] After forming the channel layer, the method further includes the following steps: removing the bit line sacrificial layer and the capacitor sacrificial layer, and preparing the bit line and the capacitor in the bit line accommodating area and the capacitor accommodating area, respectively.

[0018] Furthermore, an embodiment of the present disclosure also provides a semiconductor structure, which includes: a substrate, a channel layer, a bit line, a word line and a capacitor, wherein there are multiple channel layers, and the multiple channel layers are stacked along a first direction intersecting with the surface of the substrate, the channel layer includes a single crystal material, the channel layer has a source terminal and a drain terminal, the bit line and the capacitor are electrically connected to the source terminal and the drain terminal, respectively, and the word line is used to control the channel layer.

[0019] In some embodiments of the present disclosure, the capacitor is in the shape of a long strip and extends along a second direction. The capacitor includes an inner electrode, a dielectric layer and an outer electrode extending along a third direction. The dielectric layer is arranged between the inner electrode and the outer electrode, the dielectric layer is arranged around the inner electrode, the outer electrode is arranged around the dielectric layer, and the inner electrode or the outer electrode is electrically connected to the channel layer.

[0020] In some embodiments of the present disclosure, the protection layer is disposed between the bit line and the capacitor, and the protection layer is connected to the channel layer, the bit line and the capacitor.

[0021] In some embodiments of the present disclosure, the single crystal material is single crystal silicon.

[0022] The semiconductor structure disclosed in the present invention includes a plurality of channel layers, which can be used as the main functional part of the transistor, the bit line and the capacitor can be electrically connected to the source end and the drain end respectively, and the bit line, the capacitor and the channel layer can jointly participate in forming a storage unit. The channel layer is provided with a single crystal material, which can effectively reduce the leakage problem caused by high scattering in the polycrystalline channel and ensure the conduction performance of the channel layer. In addition, the plurality of channel layers are stacked in a first direction intersecting with the surface of the substrate, which can make more full use of the space above the substrate, thereby realizing the stacking of the channel layer in the direction intersecting with the surface of the substrate, and significantly improving the stacking density of the channel layer.

[0023] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1A It is a schematic structural diagram of a semiconductor structure in the present disclosure. Figure 1B It is a schematic diagram of the cross-sectional structure along AA' in FIG1, Figure 1C It is a schematic diagram of the cross-sectional structure along BB' in FIG. 1;

[0026] Figure 2A A schematic diagram of the structure of preparing a multi-layer support layer and a multi-layer precursor layer on a substrate. Figure 2B for Figure 2A Schematic diagram of the cross-sectional structure along AA'. Figure 2C for Figure 2A Schematic diagram of the cross-sectional structure along the middle line BB';

[0027] Figure 3A For Figure 2AA schematic diagram of a structure after a first groove is formed on the basis of the structure shown in FIG. Figure 3B for Figure 3A Schematic diagram of the cross-sectional structure along AA'. Figure 3C for Figure 3A Schematic diagram of the cross-sectional structure along the middle line BB';

[0028] Figure 4A For Figure 3A A schematic diagram of a structure for preparing a first isolation filling layer based on the structure shown in FIG. Figure 4B for Figure 4A Schematic diagram of the cross-sectional structure along AA'. Figure 4C for Figure 4A Schematic diagram of the cross-sectional structure along the middle line BB';

[0029] Figure 5A For Figure 4A A schematic diagram of a structure in which a bit line accommodating area and a capacitor accommodating area are formed on the basis of the structure shown in FIG. Figure 5B for Figure 5A Schematic diagram of the cross-sectional structure along AA'. Figure 5C for Figure 5A Schematic diagram of the cross-sectional structure along the middle line BB';

[0030] Fig. 6A For Figure 5A A schematic diagram of a structure for preparing a bit line sacrificial layer and a capacitor sacrificial layer based on the structure shown in FIG. Figure 6B for Fig. 6A Schematic diagram of the cross-sectional structure along AA'. Figure 6C for Fig. 6A Schematic diagram of the cross-sectional structure along the middle line BB';

[0031] Fig. 7A For Fig. 6A A schematic diagram of a structure in which a second trench is formed and ion implantation is performed on the basis of the structure shown in FIG. Figure 7B for Fig. 7A Schematic diagram of the cross-sectional structure along AA'. Figure 7C for Fig. 7A Schematic diagram of the cross-sectional structure along the middle line BB';

[0032] Fig. 8A For Fig. 7A A schematic diagram of a structure in which a nickel metal material layer is deposited on the basis of the structure shown. Figure 8B for Fig. 8A Schematic diagram of the cross-sectional structure along AA'. Figure 8C for Fig. 8A Schematic diagram of the cross-sectional structure along the middle line BB';

[0033] Fig.9A For Fig. 8A A schematic diagram of a structure in which a third groove is formed on the basis of the structure shown in FIG. 1 and the precursor layer is etched. Fig. 9B for Fig.9A Schematic diagram of the cross-sectional structure along AA'. Fig. 9C for Fig.9A Schematic diagram of the cross-sectional structure along the middle line BB';

[0034] Fig. 10A For Fig.9A Schematic diagram of the structure of preparing the protective layer based on the structure shown, Fig. 10B for Fig. 10A Schematic diagram of the cross-sectional structure along AA'. Fig. 10C for Fig. 10A Schematic diagram of the cross-sectional structure along the middle line BB';

[0035] Fig.11A For Fig. 10A A schematic diagram of a structure for removing a bit line sacrificial layer and preparing a word line hole based on the structure shown in FIG. Fig. 11B for Fig.11A Schematic diagram of the cross-sectional structure along AA'. Fig. 11C for Fig.11A Schematic diagram of the cross-sectional structure along the middle line BB';

[0036] Fig. 12A For Fig.11A A schematic diagram of the structure of preparing bit lines and word lines based on the structure shown in FIG. Fig. 12B for Fig. 12A Schematic diagram of the cross-sectional structure along AA'. Fig. 12C for Fig. 12A Schematic diagram of the cross-sectional structure along the middle line BB';

[0037] Fig.13A For Fig. 12A A schematic diagram of a structure in which the sacrificial layer of the capacitor is removed based on the structure shown. Fig. 13B for Fig.13A Schematic diagram of the cross-sectional structure along AA'. Fig. 13C for Fig.13A Schematic diagram of the cross-sectional structure along the middle line BB';

[0038] The reference numerals and their meanings are as follows:

[0039] 100, substrate; 110, channel layer; 120, bit line; 130, word line; 140, capacitor; 141, inner electrode; 142, dielectric layer; 143, outer electrode; 150, protective layer; 210, precursor layer; 211, connecting part; 212, spacer; 213, bit line sacrificial layer; 214, capacitor sacrificial layer; 215, nickel metal material layer; 2101, bit line accommodating area; 2102, capacitor accommodating area; 220, supporting layer; 310, first groove; 311, first isolation filling layer; 320, second groove; 321, second isolation filling layer; 330, third groove; 331, third isolation filling layer. DETAILED DESCRIPTION

[0040] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0041] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0042] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0043] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0044] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0045] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0046] Figure 1A It is a schematic structural diagram of a semiconductor structure in the present disclosure. Figure 1B It is a schematic diagram of the cross-sectional structure along AA' in FIG1, Figure 1C It is a schematic diagram of the cross-sectional structure along BB' in Figure 1. Figure 1A to Figure 1C As shown, the semiconductor structure in the present disclosure includes a substrate 100, a channel layer 110, a bit line 120, a word line 130, and a capacitor 140. There are multiple channel layers 110, and the multiple channel layers 110 are stacked along a first direction intersecting the substrate 100. The channel layer 110 includes a single crystal material, and the channel layer 110 has a source terminal and a drain terminal. The bit line 120 and the capacitor 140 are electrically connected to the source terminal and the drain terminal, respectively, and the word line 130 is used to control the channel layer.

[0047] The semiconductor structure disclosed in the present invention includes a plurality of channel layers 110, which can be used as the main functional part of the transistor, and the bit line 120 and the capacitor 140 can be electrically connected to the source end and the drain end respectively, and the bit line 120, the capacitor 140 and the channel layer 110 can jointly participate in forming a storage unit. The channel layer 110 is provided with a single crystal material, which can effectively reduce the leakage problem caused by high scattering in the polycrystalline channel and ensure the conduction performance of the channel layer 110. In addition, the plurality of channel layers 110 are stacked in a first direction intersecting with the surface of the substrate 100, which can make more full use of the space above the substrate 100, thereby realizing the stacking of the channel layer 110 in the direction intersecting with the surface of the substrate 100, and significantly improving the stacking density of the channel layer.

[0048] Reference Figure 1A to Figure 1C As shown in FIG. 1 , the surface of the substrate 100 refers to a side surface on which the channel layer 110 is disposed, and the first direction may obliquely intersect or perpendicularly intersect the surface of the substrate 100. In this embodiment, the first direction may perpendicularly intersect the surface of the substrate 100, and in this case, a plurality of channel layers 110 may be stacked in a direction perpendicular to the surface of the substrate 100. In this embodiment, the first direction may refer to FIG. Figure 1A The z direction shown in .

[0049] Reference Figure 1A to Figure 1C As shown, in some examples of this embodiment, the channel layer 110 in the semiconductor structure may be in the shape of a long strip, and the channel layer 110 may extend along a second direction intersecting the first direction, the source end and the drain end are respectively located at opposite ends of the channel layer 110 in the second direction, and the bit line 120 and the capacitor 140 are respectively arranged on both sides of the channel layer 110 in the second direction. In this embodiment, the second direction may refer to Figure 1AFurther, in some examples of this embodiment, the second direction may be perpendicular to the first direction.

[0050] Reference Figure 1A to Figure 1C As shown, in some examples of this embodiment, the capacitor 140 may also be in a strip shape, and the capacitor 140 may extend along the second direction.

[0051] Reference Figure 1B As shown, in some examples of this embodiment, the capacitor 140 may include an inner electrode 141, a dielectric layer 142, and an outer electrode 143 extending along the second direction, the dielectric layer 142 is disposed between the inner electrode 141 and the outer electrode 143, the dielectric layer 142 may be disposed around the inner electrode 141, and the outer electrode 143 may be disposed around the dielectric layer 142. The inner electrode 141 or the outer electrode 143 is electrically connected to the channel layer. By providing the inner electrode 141, the dielectric layer 142, and the capacitor 140 extending along the second direction, space in the third direction can be saved, and it is helpful to obtain a relatively large capacitor 140, thereby increasing the capacitance.

[0052] In some examples of this embodiment, the material of the inner electrode 141 may be the same as the material of the outer electrode 143 .

[0053] In some examples of this embodiment, the material of the inner electrode 141 may be selected from one or more of titanium and titanium nitride.

[0054] In some examples of this embodiment, the material of the external electrode 143 may be selected from one or more of titanium and titanium nitride.

[0055] In some examples of this embodiment, the material of the dielectric layer 142 may be selected from an insulating material. Further, the material of the dielectric layer 142 may be a high-K material, and the dielectric constant of the high-K material may be above 4. Further, the material of the dielectric layer 142 may be selected from hafnium dioxide (HfO2).

[0056] Reference Figure 1B As shown, in some examples of this embodiment, the outer electrode 143 in the capacitor 140 may be electrically connected to the channel layer 110 , and correspondingly, the inner electrode 141 may be electrically connected to an external circuit.

[0057] Reference Figure 1A to Figure 1C As shown, in some examples of this embodiment, a plurality of channel layers arranged in parallel in sequence along the first direction constitute a channel group, and the word line 130 can be used to control the plurality of channel layers in the channel group. Further, the word line 130 can be extended along the first direction to be arranged corresponding to the plurality of channel layers in the channel group.

[0058] Reference Figure 1A to Figure 1C As shown, in some examples of this embodiment, there may be multiple channel groups, there may be multiple channel groups, and multiple channel groups may be arranged in parallel in a third direction intersecting the first direction. The third direction may refer to the y direction shown in FIG. 1, and further, the first direction, the second direction, and the third direction may be perpendicular to each other, and the plane determined by the second direction and the third direction may be parallel to the surface of the substrate 100. It can be understood that in the multiple channel groups, there are multiple channel layers 110 arranged in parallel in the third direction. The bit line 120 may extend along the third direction, and the bit line 120 is electrically connected to the multiple channel layers 110 arranged in parallel in the third direction.

[0059] In some examples of this embodiment, the material of the bit line 120 may be a conductive material. Further, the material of the bit line 120 may be selected from one or more of titanium and titanium nitride, which have strong adhesion to the channel layer 110 and can improve the stability of the semiconductor structure.

[0060] Reference Figure 1C As shown, in some examples of this embodiment, the semiconductor structure may further include a protection layer 150, which may be disposed between the bit line 120 and the capacitor 140, and the protection layer 150 is connected to the channel layer 110, the bit line 120, and the capacitor 140. By providing the protection layer 150, not only the channel layer 110 located above can be better supported, but also the bonding strength between the channel layer 110, the bit line 120, and the capacitor 140 can be further enhanced, thereby ensuring the overall stability of the semiconductor structure.

[0061] Further, in some examples of this embodiment, the protection layer 150 may be disposed on one side of the channel layer 110 in the third direction.

[0062] In some examples of this embodiment, the material of the protective layer 150 may be an insulating material. For example, the material of the protective layer 150 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0063] Reference Figure 1A to Figure 1C As shown, in some examples of this embodiment, the channel layer 110 can be disposed between the word line 130 and the protective layer 150. By disposing the channel layer 110 between the word line 130 and the protective layer 150, the position of the channel layer 110 can be further fixed by means of the word line 130 and the protective layer 150, thereby ensuring the structural stability of the semiconductor structure. In this embodiment, the protective layer 150 and the word line 130 can be disposed on both sides of the channel layer 110 in the third direction, respectively.

[0064] In some examples of this embodiment, the word line 130 may include a gate and a gate dielectric layer, wherein the gate dielectric layer is disposed between the gate and the channel layer and insulates and separates the gate and the channel layer.

[0065] In some examples of this embodiment, the material of the gate dielectric layer may be an insulating material, for example, the material of the gate dielectric layer may be selected from silicon oxide.

[0066] In some examples of this embodiment, the material of the gate may be a conductive material. Further, the material of the gate may be the same as that of the bit line 120, which enables the gate and the bit line 120 to be prepared in the same preparation process, thus simplifying the actual preparation process.

[0067] Reference Figure 1A to Figure 1C As shown, in some examples of this embodiment, the semiconductor structure may further include a protective layer 150, which may be disposed between two adjacent channel layers 110 in the first direction, for insulating and spacing the two adjacent channel layers 110 and supporting the channel layer 110 located above.

[0068] Further, refer to Figure 1A to Figure 1C As shown, there may be multiple bit lines 120. Corresponding to the multiple channel layers 110, the multiple bit lines 120 may be stacked in sequence in the first direction. The protection layer 150 may also be disposed between two adjacent bit lines 120 to insulate and space the two adjacent bit lines 120 and support the bit line 120 located above.

[0069] Further, refer to Figure 1A to Figure 1C As shown, there may be a plurality of capacitors 140. Corresponding to the plurality of channel layers 110, the plurality of capacitors 140 may be stacked in sequence in the first direction. The protective layer 150 may also be disposed between two adjacent capacitors 140 to insulate and space the two adjacent capacitors 140 and support the capacitor 140 located above.

[0070] Reference Figure 1A to Figure 1C As shown, in some examples of this embodiment, the semiconductor structure may further include an isolation structure, which may be disposed between two adjacent channel groups and used to insulate the adjacent channel groups. Further, an isolation gap may be provided between two adjacent channel groups, and the isolation structure may be filled in the gap to maintain the stability of the semiconductor structure.

[0071] Reference Figure 1A to Figure 1C As shown, in some examples of this embodiment, a word line hole extending along the first direction may be provided in the isolation structure, and the word line 130 may be provided in the word line hole. In two channel groups adjacent to the isolation structure, the word line hole may be provided close to one of the channel groups and away from the other channel group to reduce interference of the word line 130 on the other channel group.

[0072] In some examples of this embodiment, the material of the single crystalline material in the channel layer 110 may be single crystalline silicon.

[0073] In conventional technology, the material of the channel is usually polycrystalline silicon. However, due to the large number of grain boundaries in polycrystalline silicon, the carriers are subject to more scattering, resulting in poor mobility and stability of the channel, and it is not suitable for preparing channels stacked in the height direction. The present disclosure uses single crystal silicon as the material of the channel layer, which can significantly reduce the scattering of carriers, thereby improving the mobility and stability of the channel and ensuring the quality of the semiconductor structure.

[0074] The present disclosure also provides a method for preparing a semiconductor structure, which includes steps S1 to S5, as follows.

[0075] Step S1 : preparing a plurality of support layers 220 and a plurality of precursor layers 210 on a substrate 100 , wherein the support layers 220 and the precursor layers 210 are alternately stacked along a first direction.

[0076] Figure 2A A schematic diagram of a structure for preparing a multi-layer support layer 220 and a multi-layer precursor layer 210 on a substrate 100. Figure 2B for Figure 2A Schematic diagram of the cross-sectional structure along AA'. Figure 2C for Figure 2A Schematic diagram of the cross-sectional structure along BB'. Figure 2A to Figure 2C As shown, a plurality of support layers 220 and a plurality of precursor layers 210 are alternately stacked on the substrate 100 in sequence.

[0077] In some examples of this embodiment, the material of the substrate 100 may be a semiconductor material, for example, the material of the substrate 100 may include one or more of silicon, germanium, a silicon-germanium alloy, and gallium nitride.

[0078] The precursor layer 210 can be used as a precursor of a single crystal material, and can be processed into a single crystal material through subsequent processing. It can be understood that the precursor layer 210 can contain elements in the single crystal material. In some examples of this embodiment, the precursor layer 210 contains silicon.

[0079] In some examples of this embodiment, the material of the precursor layer 210 may include polycrystalline silicon. Further, the precursor layer 210 may also include doping elements doped in the polycrystalline silicon. By pre-arranging the doping elements in the precursor layer 210, the single crystal material formed subsequently can also contain the doping elements, which can play a role in adjusting the voltage of the channel layer.

[0080] In some examples of this embodiment, the doping concentration in the polysilicon may be 10 -16 cm-3 ~10 -19 cm -3 By setting the doping concentration within this range, the quality of the single crystal material formed subsequently can be ensured to be better.

[0081] In some examples of this embodiment, the doping element in the precursor layer 210 may be a P-type doping element. Further, the P-type doping element may be selected from one or more of boron, aluminum, and gallium.

[0082] The support layer 220 is used to space adjacent precursor layers 210 and support the precursor layer 210 located thereon. In some examples of this embodiment, the material of the support layer 220 may include an insulating material. For example, the material of the support layer 220 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0083] In some examples of this embodiment, the precursor layer 210 may be prepared by chemical vapor deposition.

[0084] In some examples of this embodiment, the support layer 220 may be prepared by chemical vapor deposition.

[0085] In some examples of this embodiment, after preparing the multi-layer support layer 220 and the multi-layer precursor layer 210 , a step of forming a first groove 310 is further included. Figure 3A For Figure 2A A schematic diagram of a structure after a first groove 310 is formed on the basis of the structure shown in FIG. Figure 3B for Figure 3A Schematic diagram of the cross-sectional structure along AA'. Figure 3C for Figure 3A Schematic diagram of the cross-sectional structure along BB'. Figure 3A to Figure 3C As shown, the first groove 310 may penetrate the multi-layer support layer 220 and the multi-layer precursor layer 210 along the first direction. The first groove 310 may be formed by etching, and the etching method may be dry etching.

[0086] In some examples of this embodiment, the first groove 310 may also extend along the second direction. Further, there may be a plurality of first grooves 310, and the plurality of first grooves 310 are arranged in parallel.

[0087] 3 , in some examples of this embodiment, after forming the first trench 310, the precursor layer 210 may include a plurality of spacers 212 and a connection portion 211 connected to one end of the plurality of spacers 212 in the second direction, the connection portion 211 may extend along the third direction, and the first trench 310 may be located between two adjacent spacers 212. The spacers 212 may be used to prepare a channel layer in a subsequent process.

[0088] In some examples of this embodiment, after forming the first trench 310 , a step of filling a first isolation filling layer 311 in the first trench 310 may be further included. Figure 4A For Figure 3A A schematic diagram of a structure for preparing a first isolation filling layer 311 based on the structure shown in FIG. Figure 4B for Figure 4A Schematic diagram of the cross-sectional structure along AA'. Figure 4C for Figure 4A The cross-sectional structure diagram along the line BB' is shown in FIG. 3 , wherein the first isolation filling layer 311 is used for insulating the channel layer to be prepared subsequently.

[0089] Reference Figure 4A to Figure 4C As shown, the first isolation filling layer 311 can fill the first trench 310 and contact the two isolation parts on both sides. The material of the isolation part can include an insulating material. Further, the material of the first isolation filling layer 311 can be the same as that of the support layer 220.

[0090] In some examples of this embodiment, the material of the first isolation filling layer 311 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0091] Step S2 , performing an amorphization treatment on one side surface of the precursor layer 210 to form an amorphous portion.

[0092] In some examples of this embodiment, before amorphizing one side surface of the precursor layer 210, the following step is further included: removing the connection portion 211 in the precursor layer 210 to form a bit line accommodating area 2101. Further, in some examples of this embodiment, before amorphizing one side surface of the precursor layer 210, the following step is further included: removing a portion of the spacer 212 away from the connection portion 211 to form a capacitor accommodating area 2102. Figure 5A For Figure 4A A schematic diagram of a structure of a bit line accommodating area 2101 and a capacitor accommodating area 2102 formed on the basis of the structure shown in FIG. Figure 5B for Figure 5A Schematic diagram of the cross-sectional structure along AA'. Figure 5C for Figure 5A Schematic diagram of the cross-sectional structure along BB'. Figure 5A to Figure 5C As shown, the bit line accommodating area 2101 and the capacitor accommodating area 2102 can be arranged between two adjacent support layers 220. It can be understood that there can be a reserved part of the spacer 212 between the bit line accommodating area 2101 and the capacitor accommodating area 2102. The bit line accommodating area 2101 and the capacitor accommodating area 2102 can be used as the preparation area of ​​the bit line 120 and the capacitor 140.

[0093] In the step of forming the bit line accommodating area 2101 and the capacitor accommodating area 2102, the connection portion 211 and part of the spacer 212 may be removed by wet etching. Further, when removing the connection portion 211 and part of the spacer 212, the etching rate of the etchant on the precursor layer 210 may be controlled to be greater than the etching rate of the etchant on the support layer 220, so as to minimize the damage to the support layer 220. For example, the etching selectivity ratio of the etchant to the precursor layer 210 and the support layer 220 may be controlled to be (10-100):1.

[0094] In some examples of this embodiment, before the step of performing amorphization treatment and after forming the bit line accommodating area 2101 and the capacitor accommodating area 2102, the following steps are also included: preparing a bit line sacrificial layer 213 in the bit line accommodating area 2101 and preparing a capacitor sacrificial layer 214 in the capacitor accommodating area 2102. Fig. 6A For Figure 5A A schematic diagram of a structure for preparing a bit line sacrificial layer 213 and a capacitor sacrificial layer 214 based on the structure shown in FIG. Figure 6B for Fig. 6A Schematic diagram of the cross-sectional structure along AA'. Figure 6C for Fig. 6A Schematic diagram of the cross-sectional structure along BB'. Figure 6A to Figure 6C As shown, the bit line sacrificial layer 213 and the capacitor sacrificial layer 214 can fill the bit line accommodating area 2101 and the capacitor accommodating area 2102. The bit line sacrificial layer 213 and the capacitor sacrificial layer 214 can temporarily fill the vacancies in the bit line accommodating area 2101 and the capacitor accommodating area 2102 and protect the precursor layer 210 located therein.

[0095] In some examples of this embodiment, the material of the bit line sacrificial layer 213 and the capacitor sacrificial layer 214 may be the same.

[0096] In some examples of this embodiment, the material of the protective filling layer and the capacitor sacrificial layer 214 may be an insulating material. Further, the material of the protective filling layer and / or the capacitor sacrificial layer 214 may be different from the material of the first isolation filling layer 311, so that the two can be etched with different etchants respectively, and the mutual influence between the two during the etching process is reduced.

[0097] In some examples of this embodiment, the material of the bit line sacrificial layer 213 and the capacitor sacrificial layer 214 may include one or more of silicon oxide, silicon nitride and silicon oxynitride. In this embodiment, the material of the first isolation filling layer 311 may be silicon oxide, and the material of the protection filling layer may be silicon nitride.

[0098] In some examples of this embodiment, before the step of amorphizing one side surface of the precursor layer 210 , the following step may be further included: forming a second trench 320 exposing the precursor layer 210 in the first isolation filling layer 311 .

[0099] In some examples of this embodiment, the step of performing amorphization treatment on one side surface of the precursor layer 210 includes: injecting ions into the surface layer of the precursor layer 210 by ion implantation. Fig. 7A For Fig. 6A A schematic diagram of a structure in which a second trench 320 is formed and ion implantation is performed on the basis of the structure shown in FIG. Figure 7B for Fig. 7A Schematic diagram of the cross-sectional structure along AA'. Figure 7C for Fig. 7A Schematic diagram of the cross-sectional structure along BB'.

[0100] Reference Figure 7A to Figure 7C As shown, the second trench 320 may penetrate the first isolation filling layer 311 along the first direction, and the second trench 320 may be located on one side of the precursor layer 210 in the third direction, and expose the side surface of the precursor layer 210 in the third direction. Further, since the side surface of the precursor layer 210 is exposed from the second trench 320, ions can be directly implanted into the surface layer of the precursor layer 210. After the ions are implanted, the original lattice in the precursor layer 210 is destroyed, thereby forming an amorphous portion.

[0101] In some examples of this embodiment, the implanted element may be the same as the element in the precursor layer 210. For example, the precursor layer 210 may include silicon element, and the implanted element is also silicon element.

[0102] Step S3 , preparing a crystallization inducing layer in contact with the amorphous portion and performing a heat treatment, so that at least a portion of the precursor layer 210 is converted into a single crystal material and forms a channel layer.

[0103] In some examples of this embodiment, the precursor layer 210 includes silicon elements, and the material of the crystallization inducing layer includes silicon-nickel metal compounds. Further, the silicon-nickel metal compound may include nickel disilicide (NiSi2), and the lattice mismatch rate between nickel disilicide and single-crystalline silicon is only 0.4%, so the silicon atoms in amorphous silicon can be rearranged based on its surface and form single-crystalline silicon. Specifically, the silicon-nickel metal compound can be attached to the surface of the amorphous portion. When subjected to heat treatment, the atoms in the amorphous portion are first rearranged to form a single-crystalline material. Subsequently, the conversion process is gradually carried out toward the interior of the precursor layer 210 in a direction away from the amorphous inducing layer, and the atoms located inside are gradually rearranged and formed into a single-crystalline material, thereby eventually converting part or all of the precursor layer 210 into a single-crystalline material and forming the desired channel layer.

[0104] In some examples of this embodiment, the step of preparing a crystallization inducing layer in contact with the amorphous portion includes: preparing a nickel metal material layer 215 on the amorphous portion, and reacting the nickel metal material layer 215 with the amorphous portion to form the crystallization inducing layer. Fig. 8A For Fig. 7A A schematic diagram of a structure in which a nickel metal material layer 215 is deposited on the basis of the structure shown in FIG. Figure 8B for Fig. 8A Schematic diagram of the cross-sectional structure along AA'. Figure 8C for Fig. 8A Schematic diagram of the cross-sectional structure along BB'. Figure 8A to Figure 8C As shown, the nickel metal material layer 215 may be filled in the second trench 320 , and the nickel metal material layer 215 is located on one side of each precursor layer 210 in the third direction and directly contacts each precursor layer 210 .

[0105] In some examples of this embodiment, the nickel metal material layer 215 may be deposited in the second trench 320 by physical vapor deposition or chemical vapor deposition. After the nickel metal material layer 215 is deposited, the nickel metal material layer 215 and the precursor layer 210 may be heated to react the nickel metal material layer 215 with the amorphous portion and form a silicon-nickel metal compound as a crystallization inducing layer at the interface therebetween.

[0106] In some examples of this embodiment, in the step of heating the nickel metal material layer 215 and the precursor layer 210, the heating temperature can be controlled below 280°C to ensure the formation of nickel disilicide with a better lattice structure, thereby improving the quality of the single crystal silicon finally formed.

[0107] In some examples of this embodiment, after forming the crystallization inducing layer, a step of removing the nickel metal material layer 215 may be further included. The nickel metal material layer 215 may be removed by wet etching, which can selectively remove the nickel metal material layer 215 and retain the crystallization inducing layer.

[0108] In some examples of this embodiment, in the step of heat treating the crystallization inducing layer and the precursor layer 210, the temperature of the heat treatment can be controlled to be 400°C to 600°C to induce the precursor layer 210 to be converted into a single crystal material and ensure the quality of the single crystal material. Further, the temperature of the heat treatment can be controlled to be 400°C, 420°C, 450°C, 470°C, 500°C, 520°C, 550°C, 570°C or 600°C, or the temperature of the heat treatment can also be within the range between any two of the above temperatures.

[0109] In some examples of this embodiment, for the precursor layer 210 containing doping elements, the doping elements are doped into the single crystal material during the heat treatment process to obtain a channel layer with higher carrier mobility.

[0110] In some examples of this embodiment, after removing the nickel metal material layer 215 , a step of preparing a second isolation protection layer 150 in the second trench 320 may be further included, and the second isolation protection layer 150 may fill the second trench 320 .

[0111] In some examples of this embodiment, the material of the second isolation filling layer 321 may be the same as that of the first isolation filling layer 311 .

[0112] In some examples of this embodiment, the material of the second isolation filling layer 321 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the material of the second isolation filling layer 321 may be silicon oxide.

[0113] In the process of inducing the formation of a single crystal material through the crystallization inducing layer, since the transformation process is gradually carried out in the direction away from the crystallization inducing layer, and solid phase materials that hinder the transformation process may exist in the precursor layer 210, resulting in the precursor layer 210 not being completely transformed into a single crystal material. At this time, there may still be a part of the precursor layer 210 that has not been transformed on the side of the single crystal material away from the crystallization inducing layer, affecting the quality of the channel layer.

[0114] In order to improve the above problem, in some examples of this embodiment, after forming the single crystal material, the following steps may be further included: forming a third trench 330 on a side of the precursor layer 210 away from the second isolation filling layer 321, and etching the precursor layer 210 exposed from the third trench 330 to remove at least a portion of the precursor layer 210. The third trench 330 may be formed by etching at least a portion of the retained first isolation filling layer 311.

[0115] Fig.9A For Fig. 8A A schematic diagram of a structure in which a third trench 330 is formed on the basis of the structure shown in FIG. 1 and the precursor layer 210 is etched. Fig. 9B for Fig.9A Schematic diagram of the cross-sectional structure along AA'. Fig. 9C for Fig.9A Schematic diagram of the cross-sectional structure along BB'. Figures 9A to 9CAs shown, the surface of one side of the precursor layer 210 away from the second isolation filling layer 321 can be exposed from the third groove 330 and etched away during the etching process. In some examples of this embodiment, the method of etching the precursor layer 210 can be wet etching. It can be understood that due to the difference in crystal phase, the precursor layer 210 has a relatively high etching rate relative to the single crystal material, so the single crystal material can be retained during the etching process. Among them, after the precursor layer 210 is etched, a vacant area located between the bit line sacrificial layer 213 and the capacitor sacrificial layer 214 is generated.

[0116] In some examples of this embodiment, after etching the precursor layer 210 , a step of preparing a protection layer 150 in the vacant area may be further included. Fig. 10A For Fig.9A A schematic diagram of a structure for preparing a protective layer 150 based on the structure shown in FIG. Fig. 10B for Fig. 10A Schematic diagram of the cross-sectional structure along AA'. Fig. 10C for Fig. 10A The cross-sectional structure diagram along the middle line BB' is shown in FIG. The protection layer 150 may be located between the bit line sacrificial layer 213 and the capacitor sacrificial layer 214 and fill the vacant area. The protection layer 150 may also be connected to the bit line sacrificial layer 213, the capacitor sacrificial layer 214 and the channel layer 110 to protect the channel layer and enhance its structural stability.

[0117] Reference Figures 10A to 10C As shown, in some examples of this embodiment, after etching the precursor layer 210, a step of preparing a third isolation filling layer 331 in the third trench 330 may be further included. Further, the third isolation filling layer 331 may be located on a side of the protection layer 150 away from the channel layer.

[0118] In some examples of this embodiment, the material of the third isolation filling layer 331 may be the same as the material of the protection layer 150. Further, the third isolation filling layer 331 and the protection layer 150 may be prepared at the same time.

[0119] In some examples of this embodiment, the material of the third isolation filling layer 331 may be the same as that of the second isolation filling layer 321 .

[0120] In some examples of this embodiment, the material of the third isolation filling layer 331 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride. In this embodiment, the material of the third isolation filling layer 331 may be silicon oxide.

[0121] It can be understood that through steps S1 to S3 , in this embodiment, after forming the channel layer 110 , the steps of forming the bit line 120 , the word line 130 and the capacitor 140 may be further included.

[0122] Step S4 , preparing the bit lines 120 and the word lines 130 .

[0123] In this embodiment, the bit line 120 can be formed in the bit line accommodating area 2101 and contact the channel layer 110 , and the word line 130 can be formed on the side of the channel layer 110 in the third direction. Further, the word line 130 can be formed on the side of the channel layer 110 away from the protection layer 150 .

[0124] In some examples of this embodiment, the step of preparing the bit line 120 and the word line 130 may include: removing the bit line sacrificial layer 213, preparing a word line hole in the second isolation filling layer 321, and preparing the bit line 120 and the word line 130 in the bit line accommodating area 2101 and the word line hole, respectively.

[0125] Fig.11A For Fig. 10A A schematic diagram of a structure in which the bit line sacrificial layer 213 is removed and word line holes are prepared based on the structure shown in FIG. Fig. 11B for Fig.11A Schematic diagram of the cross-sectional structure along AA'. Fig. 11C for Fig.11A Schematic diagram of the cross-sectional structure along BB'. Figures 11A to 11C As shown, the bit line sacrificial layer 213 is removed to expose the bit line accommodating region 2101 , and the axial direction of the word line hole may be along the first direction, and the word line hole may penetrate the second isolation filling layer 321 in the first direction.

[0126] Fig. 12A For Fig.11A A schematic diagram of a structure of preparing a bit line 120 and a word line 130 based on the structure shown in FIG. Fig. 12B for Fig. 12A Schematic diagram of the cross-sectional structure along AA'. Fig. 12C for Fig. 12A Schematic diagram of the cross-sectional structure along BB'. Figures 12A to 12C As shown, the bit line 120 may be disposed in the bit line accommodating region 2101, and the bit line 120 may extend along the third direction, and the bit line 120 may be electrically connected to a plurality of parallel channel layers 110 located in the third direction. The word line 130 may be disposed in the word line hole, and the word line 130 may extend along the first direction, and the word line 130 may be electrically connected to a plurality of parallel channel layers 110 located in the first direction.

[0127] In some examples of this embodiment, the word line 130 includes a gate dielectric layer and a gate. The material of the gate can be the same as that of the bit line 120, so that the gate and the bit line 120 can be prepared and formed in the same process.

[0128] In some examples of this embodiment, the material of the bit line 120 may be selected from one or more of titanium and titanium nitride, and the material of the gate may also be selected from one or more of titanium and titanium nitride.

[0129] In some examples of this embodiment, the gate dielectric layer may be formed by deposition, or the gate dielectric layer may be formed by oxidizing the channel layer 110 .

[0130] Step S5, preparing the capacitor 140.

[0131] In this embodiment, the capacitor 140 may be fabricated in the capacitor accommodating region 2102 and contact the channel layer 110 .

[0132] In some examples of this embodiment, the step of preparing the capacitor 140 may include: removing the capacitor sacrificial layer 214 , and sequentially preparing an outer electrode 143 , a dielectric layer 142 , and an inner electrode 141 in the capacitor accommodating area 2102 .

[0133] Fig.13A For Fig. 12A A schematic diagram of a structure in which the capacitor sacrificial layer 214 is removed from the structure shown in FIG. Fig. 13B for Fig.13A Schematic diagram of the cross-sectional structure along AA'. Fig. 13C for Fig.13A Schematic diagram of the cross-sectional structure along BB'. Figures 13A to 13C As shown, the channel layer 110 has a capacitor accommodation region 2102 on one side away from the bit line 120 . The capacitor accommodation region 2102 is located between two adjacent support layers 220 , and the capacitor accommodation region 2102 is also located between the second isolation filling layer 321 and the third isolation filling layer 331 .

[0134] In some examples of this embodiment, the capacitor sacrificial layer 214 may be removed by dry etching or wet etching. It is understood that since the material of the capacitor sacrificial layer 214 is different from the material of the second isolation layer and the material of the third isolation layer, the capacitor sacrificial layer 214 may be removed more preferentially to obtain the hole-shaped capacitor accommodating area 2102.

[0135] The outer electrode 143, the dielectric layer 142 and the inner electrode 141 can be prepared in sequence in the capacitor accommodation area 2102. In some examples of this embodiment, the outer electrode 143, the dielectric layer 142 and the inner electrode 141 can be prepared by deposition. During the preparation process, the deposition time can be controlled so that the outer electrode 143 is attached to the hole wall of the capacitor accommodation area 2102, and the side of the outer electrode 143 away from the hole wall also has an inner hole. Further, the dielectric layer 142 can be attached to the hole wall of the inner hole of the outer electrode 143, the side of the dielectric layer 142 away from the outer electrode 143 also has an inner hole, and the inner electrode 141 can be filled in the inner hole of the dielectric layer 142.

[0136] It can be understood that after steps S1 to S5, the following can be prepared: Figure 1A to Figure 1C The semiconductor structure shown.

[0137] Conventional technology can usually only prepare polycrystalline materials, but due to the high scattering problem of polycrystalline materials, polycrystalline materials are not suitable for preparing multiple transistors stacked in the height direction. In the preparation method of the semiconductor structure disclosed in the present invention, a multi-layer support layer and a precursor layer are first prepared, the precursor layer is amorphized to form an amorphous portion, and then a crystallization inducing layer is used to convert the precursor layer into a single crystal material and form a channel layer. While preparing the channel layer stacked along the first direction, it is ensured that the channel layer includes a single crystal material, which can significantly improve the stacking density of the channel layer while ensuring the carrier mobility of the channel layer.

[0138] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0139] It should be understood that, unless otherwise specified herein, there is no strict order restriction for the execution of the steps, and the steps may be executed in other orders. Moreover, at least a portion of the steps in the preparation process may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0140] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0141] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Preparing a plurality of support layers and a plurality of precursor layers on a substrate, wherein the support layers and the precursor layers are alternately stacked along a first direction; Performing an amorphization treatment on one side surface of the precursor layer to form an amorphous portion; preparing a crystallization inducing layer in contact with the amorphous portion and performing a heat treatment so that the precursor layer is converted into a single crystal material and a channel layer is formed, wherein the channel layer has a source terminal and a drain terminal; forming a bit line, wherein the bit line extends along a third direction; forming a capacitor, wherein the bit line and the capacitor are electrically connected to the source terminal and the drain terminal respectively; A word line is formed, the word line extending along the first direction, the word line being used to control the channel layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The precursor layer includes silicon element, and the material of the crystallization inducing layer includes silicon-nickel metal compound.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The precursor layer is polycrystalline silicon, and the precursor layer also includes a doping element, and the doping concentration of the doping element in the polycrystalline silicon is 10 16 cm -3 ~10 19 cm -3 .

4. The method for preparing a semiconductor structure according to claim 2, characterized in that: The step of preparing a crystallization inducing layer in contact with the amorphous portion includes: preparing a nickel metal material layer on the amorphous portion, and reacting the nickel metal material layer with the amorphous portion to form the crystallization inducing layer.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The step of amorphizing one side surface of the precursor layer includes: injecting ions into the surface of the precursor layer by ion implantation.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The precursor layer includes a plurality of spacers and a connecting portion connected to one end of the spacers in the second direction, the plurality of spacers are arranged in parallel and spaced relation along the third direction, and the first direction, the second direction and the third direction intersect each other; Before amorphizing the surface of one side of the precursor layer, the method further includes the following steps: removing the connecting portion to form a bit line accommodating area, removing a portion of the spacer away from the connecting portion to form a capacitor accommodating area, and preparing a bit line sacrificial layer and a capacitor sacrificial layer in the bit line accommodating area and the capacitor accommodating area, respectively; After forming the channel layer, the method further includes the following steps: removing the bit line sacrificial layer and the capacitor sacrificial layer, and preparing the bit line and the capacitor in the bit line accommodating area and the capacitor accommodating area, respectively.

7. A semiconductor structure, formed by the preparation method according to any one of claims 1 to 6, characterized in that: It includes a substrate, a channel layer, a bit line, a word line and a capacitor. There are multiple channel layers, and the multiple channel layers are stacked along a first direction intersecting with the surface of the substrate. The channel layer includes a single crystal material, and the channel layer has a source terminal and a drain terminal. The bit line and the capacitor are electrically connected to the source terminal and the drain terminal respectively, and the word line is used to control the channel layer.

8. The semiconductor structure according to claim 7, characterized in that: The capacitor is in the shape of an elongated strip and extends along a second direction. The capacitor includes an inner electrode, a dielectric layer and an outer electrode extending along a third direction. The dielectric layer is arranged between the inner electrode and the outer electrode, the dielectric layer is arranged around the inner electrode, the outer electrode is arranged around the dielectric layer, and the inner electrode or the outer electrode is electrically connected to the channel layer.

9. The semiconductor structure according to claim 7, characterized in that: The invention also includes a protection layer, wherein the protection layer is disposed between the bit line and the capacitor, and the protection layer is connected to the channel layer, the bit line and the capacitor.

10. The semiconductor structure according to any one of claims 7 to 9, characterized in that: The single crystal material is single crystal silicon.

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