Depletion type gallium nitride HEMT device with composite gate dielectric and preparation method of depletion type gallium nitride HEMT device

Abstract

The invention discloses a depletion type gallium nitride HEMT (High Electron Mobility Transistor) device with a composite gate dielectric and a preparation method of the depletion type gallium nitride HEMT device, the device comprises a substrate, and a buffer layer, a channel GaN layer, an ALGaN layer and a composite gate dielectric structure layer which are sequentially stacked on the surface of the substrate along the longitudinal direction, and the composite gate dielectric structure layer comprises an oxide isolation layer which is arranged between the insit-SiN layer and the LPSiN layer. According to the invention, the composite gate dielectric structure layer is arranged, and the three-layer gate structure formed by the insite-SiN layer, the oxide isolation layer and the LPSiN layer in sequence is formed, so that the oxide isolation layer with a high potential barrier is inserted between the insite-SiN medium and the LPSiN medium, charge movement between the insite-SiN medium and the LPSiN medium is prevented, and the performance of the device is improved. And the stability of the threshold voltage (VTH) in the subsequent pressurization process is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a depletion-mode gallium nitride HEMT device with a composite gate dielectric and a preparation method thereof. Background Art

[0002] The basic structure of a depletion-type GaN HEMT structure consists of three electrodes, namely, a source (S electrode), a drain (N electrode) and a gate. In the prior art, the composite gate dielectric in the depletion-type GaN HEMT structure uses two dielectrics, insitu-SiN and LPSiN, with LPSiN stacked on insitu-SiN, and the two are in direct contact. However, the above structure will cause charge movement between the two dielectrics, generate interface traps (Trap), and further cause instability of the threshold voltage (VTH) during the pressurization process. Summary of the invention

[0003] In order to overcome the defects in the prior art, an embodiment of the present invention provides a depletion-mode gallium nitride HEMT device with a composite gate dielectric and a preparation method thereof, which are used to solve one or more of the above problems.

[0004] The embodiment of the present application discloses: a depletion-mode gallium nitride HEMT device with a composite gate dielectric, comprising a substrate, and a buffer layer, a channel GaN layer, an ALGaN layer and a composite gate dielectric structure layer stacked in sequence along the longitudinal direction on the surface of the substrate, wherein the composite gate dielectric structure layer comprises an oxide isolation layer arranged between an insitu-SiN layer and a LPSiN layer.

[0005] Further, the insitu-SiN layer is stacked on the ALGaN layer, the oxide isolation layer is stacked on the insitu-SiN layer, the LPSiN layer is stacked on the oxide isolation layer, and the oxide isolation layer is an AL2O3 layer or a SiO2 layer.

[0006] Furthermore, the lateral cross-sectional area of ​​the composite gate dielectric structure layer is smaller than that of the ALGaN layer, and two ends of the composite gate dielectric structure layer are respectively provided with a first S pole and a first N pole abutting against the ALGaN layer.

[0007] Furthermore, the surfaces of the first S-pole, the first N-pole and the LPSiN layer are covered with a PESiN layer, and the PESiN layer is provided with a first metal gate isolated from the first S-pole and the first N-pole.

[0008] Furthermore, the PESiN layer is provided with a first contact hole, a second contact hole and a third contact hole connected to the first S pole, the first N pole and the first metal gate from the outer surface to the inner part thereof, and the outer surface of the PESiN layer is provided with a second S pole, a second N pole and a second metal gate isolated from each other, wherein the second S pole is connected to the first contact hole, the second N pole is connected to the second contact hole, and the second metal gate is connected to the third contact hole.

[0009] The embodiment of the present application also provides a method for preparing a depletion-mode gallium nitride HEMT with a composite gate dielectric, comprising the following steps:

[0010] A substrate is provided; a buffer layer, a channel GaN layer and an ALGaN layer are sequentially deposited on the surface of the substrate along the longitudinal direction; a composite gate dielectric structure layer is deposited on the surface of the ALGaN layer; wherein, in the step of "depositing a composite gate dielectric structure layer on the surface of the ALGaN layer", specifically, an insitu-SiN layer as a first gate dielectric is deposited on the surface of the ALGaN layer; an oxide isolation layer as a second gate dielectric is deposited on the surface of the insitu-SiN layer; and an LPSiN layer as a third gate dielectric is deposited on the surface of the oxide isolation layer.

[0011] Furthermore, after the step of "depositing an LPSiN layer as a third gate dielectric on the surface of the oxide isolation layer", the following step is also included: performing ohmic contact opening etching on both ends of the composite gate dielectric structure layer to expose the ALGaN layer located at both ends of the composite gate dielectric structure layer.

[0012] Furthermore, after the step of “etching ohmic contact openings at both ends of the composite gate dielectric structure layer to expose the ALGaN layer at both ends of the composite gate dielectric structure layer”, the following steps are also included:

[0013] A first S pole and a first N pole abutting against the ALGaN layer are respectively deposited at two ends of the composite gate dielectric structure layer.

[0014] Furthermore, after the step of "respectively depositing a first S pole and a first N pole abutting the ALGaN layer at both ends of the composite gate dielectric structure layer", the following steps are also included: PESiN is deposited on the surface of the first S pole, the first N pole and the LPSiN layer to form a PESiN layer; the PESiN layer is etched twice, wherein the first etching is longitudinally etching from the outer surface of the PESiN layer to the LPSiN layer, and the second etching is transversely etching and connected to the portion after the first etching, and the upper surface after the second etching is isolated from the LPSiN layer; and a first metal gate and a metal field plate are deposited inside the etched PESiN layer.

[0015] Furthermore, after the step of "depositing a metal gate and a metal field plate inside the etched PESiN layer", the following steps are also included: performing dielectric deposition on the surface of the PESiN layer to cover the first S pole, the first N pole, the first metal gate and the metal field plate; performing contact hole opening etching on the surface of the PESiN layer to respectively open a first contact hole, a second contact hole and a third contact hole connected to the first S pole, the first N pole and the first metal gate from the outer surface to the inside of the PESiN layer; depositing a back-end metal on the outer surface of the PESiN layer to provide a second S pole, a second N pole and a second metal gate isolated from each other on the outer surface of the PESiN layer, wherein the second S pole is connected to the first contact hole, the second N pole is connected to the second contact hole, and the second metal gate is connected to the third contact hole.

[0016] The beneficial effects of the present invention are as follows:

[0017] By setting a composite gate dielectric structure layer and forming a three-layer gate structure formed by an insitu-SiN layer, an oxide isolation layer and an LPSiN layer in sequence, an oxide isolation layer with a high potential barrier is inserted between the insitu-SiN and LPSiN dielectrics, thereby preventing the movement of charges between the insitu-SiN and LPSiN dielectrics, thereby improving the stability of the threshold voltage (VTH) in the subsequent voltage application process.

[0018] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 It is a schematic structural diagram of a depletion-mode gallium nitride HEMT device with a composite gate dielectric in an embodiment of the present invention;

[0021] Figure 2 It is a schematic diagram of the preparation process of a depletion-mode gallium nitride HEMT device with a composite gate dielectric in an embodiment of the present invention;

[0022] Figure 3 It is a flow chart of a method for preparing a depletion-mode gallium nitride HEMT with a composite gate dielectric in an embodiment of the present invention;

[0023] The figure marks of the above drawings are: 1. substrate; 2. buffer layer; 3. channel GaN layer; 4. ALGaN layer; 5. composite gate dielectric structure layer; 51. insitu-SiN layer; 52. oxide isolation layer; 53. LPSiN layer; 6. first S pole; 7. first N pole; 8. PESiN layer; 9. first metal gate; 10. first contact hole; 11. second contact hole; 12. third contact hole; 13. second S pole; 14. second N pole; 15. second metal gate. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] like Figure 1 to Figure 2 As shown, a depletion-mode gallium nitride HEMT device with a composite gate dielectric in this embodiment includes a substrate 1, and a buffer layer 2 (Buffer layer), a channel GaN layer 3 (Channel GaN layer), an ALGaN layer 4 and a composite gate dielectric structure layer 5 stacked in sequence along the longitudinal direction on the surface of the substrate 1, wherein the composite gate dielectric structure layer 5 includes an oxide isolation layer 52 disposed between an insitu-SiN layer 51 and a LPSiN layer 53. In this embodiment, the substrate 1 is a silicon substrate 1 (Si Substrate). Of course, in other optional embodiments, the material of the substrate 1 can be adjusted according to actual needs. Preferably, the insitu-SiN layer 51 is stacked on the ALGaN layer 4, the oxide isolation layer 52 is stacked on the insitu-SiN layer 51, and the LPSiN layer 53 is stacked on the oxide isolation layer 52. Thus, the insitu-SiN layer 51, the oxide isolation layer 52 and the LPSiN layer 53 are stacked on the ALGaN layer 4 in sequence. The oxide isolation layer is an AL2O3 layer or a SiO2 layer. The AL2O3 layer or the SiO2 layer as an oxide isolation layer prevents the movement of charges between the insitu-SiN layer 51 and the LPSiN layer 53 by inserting a high barrier layer.

[0026] Embodiment 1: In this embodiment, the oxide isolation layer is an AL2O3 layer, and an insitu-SiN layer 51 is grown in a MOCVD machine as a first gate dielectric layer, and then an AL2O3 layer is grown on the insitu-SiN layer 51 in an ALD machine as a second gate dielectric layer, and then an LPSiN layer 53 is grown on the AL2O3 layer in a furnace tube as a third gate dielectric layer, that is, in this embodiment, the composite gate dielectric structure layer 5 is composed of a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer.

[0027] Embodiment 2: In this embodiment, the oxide isolation layer is a SiO2 layer, which is grown in an MOCVD machine to form an insitu-SiN layer 51 as the first gate dielectric layer, and then is introduced into an acid tank for pickling (HCL clean), and then introduced into a spin dryer for spin drying (spin dry), forming a water film on the surface, and then introduced into a furnace tube. The water film on the surface reacts with the SiCl2H2 in the furnace tube to form a SiO2 layer as the second gate dielectric layer, and then continues to react in the furnace tube to generate an LPSiN layer 53 as the third gate dielectric layer, that is, in this embodiment, the composite gate dielectric structure layer 5 is composed of a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer.

[0028] With the above structure, a composite gate dielectric structure layer 5 is provided, and a three-layer gate structure is formed in sequence consisting of an insitu-SiN layer 51, an oxide isolation layer 52, and an LPSiN layer 53, so that an oxide isolation layer with a high potential barrier is inserted between the insitu-SiN and LPSiN dielectrics, thereby preventing the movement of charges between the insitu-SiN and LPSiN dielectrics, thereby improving the stability of the threshold voltage (VTH) during the subsequent voltage application process.

[0029] Specifically, the lateral cross-sectional area of ​​the composite gate dielectric structure layer 5 is smaller than the lateral cross-sectional area of ​​the ALGaN layer 4, so that the ALGaN layer 4 exceeds the two ends of the composite gate dielectric structure layer 5 and is respectively used to carry the subsequent first S pole 6 and the first N pole 7. The two ends of the composite gate dielectric structure layer 5 are respectively provided with the first S pole 6 and the first N pole 7 abutting the ALGaN layer 4, wherein the S pole is the source and the N pole is the drain, the bottom ends of the first S pole 6 and the first N pole 7 are respectively abutted against the ALGaN layer 4 located at the two ends of the composite gate dielectric structure layer 5, and the sides of the first S pole 6 and the first N pole 7 are respectively abutted against the two ends of the composite gate dielectric structure layer 5, thereby achieving the effect of arranging the first S pole 6 and the first N pole 7 therein and isolating the first S pole 6 and the first N pole 7 from each other.

[0030] Specifically, the surfaces of the first S-pole 6, the first N-pole 7 and the LPSiN layer 53 are covered with a PESiN layer 8, wherein SiN is deposited by PECVD (plasma enhanced chemical vapor deposition), and the PESiN layer 8 is provided with a first metal gate 9 isolated from the first S-pole 6 and the first N-pole 7, thereby forming three electrodes in the basic structure of a depletion-type gallium nitride HEMT structure.

[0031] Specifically, the PESiN layer 8 is provided with a first contact hole 10, a second contact hole 11 and a third contact hole 12 connected with the first S pole 6, the first N pole 7 and the first metal gate 9 from the outer surface to the inner part thereof, wherein the first contact hole 10, the second contact hole 11 and the third contact hole 12 can all be formed by etching on the PESiN layer 8, and the outer surface of the PESiN layer 8 is provided with a second S pole 13, a second N pole 14 and a second metal gate 15 isolated from each other, wherein the second S pole 13 is connected with the first contact hole 10, the second N pole 14 is connected with the second contact hole 11, and the second metal gate 15 is connected with the third contact hole 12, so that the second S pole 13, the second N pole 14 and the second metal gate 15 together form a back-end structure.

[0032] like Figures 1 to 3 As shown, this embodiment also provides a method for preparing a depletion-mode gallium nitride HEMT with a composite gate dielectric, comprising the following steps:

[0033] A substrate 1 is provided. In the present embodiment, the substrate 1 is a silicon substrate 1 (Si Substrate). Of course, in other optional implementations, the material of the substrate 1 can be adjusted according to actual needs.

[0034] A buffer layer 2, a channel GaN layer 3 and an AlGaN layer 4 are sequentially deposited on the surface of the substrate 1 along the longitudinal direction.

[0035] A composite gate dielectric structure layer 5 is deposited on the surface of the ALGaN layer 4, wherein in the step of "depositing a composite gate dielectric structure layer 5 on the surface of the ALGaN layer 4", specifically, an insitu-SiN layer 51 as a first gate dielectric is deposited on the surface of the ALGaN layer 4, an oxide isolation layer 52 as a second gate dielectric is deposited on the surface of the insitu-SiN layer 51, and an LPSiN layer 53 as a third gate dielectric is deposited on the surface of the oxide isolation layer 52.

[0036] In this embodiment, an insitu-SiN layer 51 is grown in a MOCVD machine as a first gate dielectric layer, and then an oxide isolation layer 52 is grown on the insitu-SiN layer 51 in an ALD machine as a second gate dielectric layer, and then an LPSiN layer 53 is grown on the oxide isolation layer 52 in a furnace tube as a third gate dielectric layer, that is, in this embodiment, the composite gate dielectric structure layer 5 is composed of a first gate dielectric layer, a second gate dielectric layer and a third gate dielectric layer.

[0037] By means of the above method, a composite gate dielectric structure layer 5 is provided, and a three-layer gate structure is formed in sequence consisting of an insitu-SiN layer 51, an oxide isolation layer 52, and a LPSiN layer 53, so that an oxide isolation layer with a high potential barrier is inserted between the insitu-SiN and LPSiN dielectrics, thereby preventing the movement of charges between the insitu-SiN and LPSiN dielectrics, thereby improving the stability of the threshold voltage (VTH) during the subsequent voltage application process.

[0038] Specifically, after the step of “depositing the LPSiN layer 53 as the third gate dielectric layer on the surface of the oxide isolation layer 52”, the following steps are also included:

[0039] The two ends of the composite gate dielectric structure layer 5 are etched to form an ohmic contact opening to expose the ALGaN layer 4 located at the two ends of the composite gate dielectric structure layer 5. Thus, the ALGaN layer 4 exceeds the two ends of the composite gate dielectric structure layer 5 and is used to carry the subsequent first S pole 6 and the first N pole 7 respectively.

[0040] Specifically, after the step of “etching the two ends of the composite gate dielectric structure layer 5 for ohmic contact openings to expose the ALGaN layer 4 located at the two ends of the composite gate dielectric structure layer 5”, the following steps are also included:

[0041] A first S-pole 6 and a first N-pole 7 are deposited at both ends of the composite gate dielectric structure layer 5, respectively, and are in contact with the ALGaN layer 4. The bottom ends of the first S-pole 6 and the first N-pole 7 are respectively in contact with the ALGaN layer 4 located at both ends of the composite gate dielectric structure layer 5, and the sides of the first S-pole 6 and the first N-pole 7 are respectively in contact with both ends of the composite gate dielectric structure layer 5, thereby achieving the effect of arranging the first S-pole 6 and the first N-pole 7 therein and isolating the first S-pole 6 and the first N-pole 7 from each other.

[0042] Specifically, after the step of “respectively depositing a first S pole 6 and a first N pole 7 abutting against the ALGaN layer 4 at both ends of the composite gate dielectric structure layer 5”, the following steps are also included:

[0043] PESiN is deposited on the surfaces of the first S-pole 6, the first N-pole 7 and the LPSiN layer 53 to form a PESiN layer 8. Thus, the first S-pole 6, the first N-pole 7 and the LPSiN layer 53 are protected by the PESiN layer 8 as a dielectric layer.

[0044] The PESiN layer 8 is etched twice, wherein the first etching is longitudinally etching from the outer surface of the PESiN layer 8 to the LPSiN layer 53 , and the second etching is transversely etching and connected to the first etched portion, and the upper surface after the second etching is isolated from the LPSiN layer 53 .

[0045] A first metal gate 9 and a metal field plate are deposited inside the etched PESiN layer 8 , wherein the first metal gate 9 is used to form three electrodes together with the first S pole 6 and the first N pole 7 .

[0046] In this embodiment, the first etching is used to form a first groove for accommodating the first metal gate 9 in the vertical direction, and the second etching is used to form a second groove for accommodating the metal field plate in the horizontal direction, wherein the ends of the first groove and the second groove are connected, thereby making the first metal gate 9 and the metal field plate connected after deposition.

[0047] Specifically, after the step of “depositing a metal gate and a metal field plate inside the etched PESiN layer 8”, the following steps are also included:

[0048] Dielectric deposition is performed on the surface of the PESiN layer 8 to cover the first S pole 6, the first N pole 7, the first metal gate 9 and the metal field plate, thereby protecting the first S pole 6, the first N pole 7, the first metal gate 9 and the metal field plate.

[0049] Contact hole opening etching is performed on the surface of the PESiN layer 8 to open a first contact hole 10, a second contact hole 11 and a third contact hole 12 in the PESiN layer 8 from the outer surface to the inside thereof, respectively, which are connected to the first S pole 6, the first N pole 7 and the first metal gate 9.

[0050] A back-end metal is deposited on the outer surface of the PESiN layer 8, so that a second S-pole 13, a second N-pole 14 and a second metal gate 15 isolated from each other are provided on the outer surface of the PESiN layer 8, wherein the second S-pole 13 is connected to the first contact hole 10, the second N-pole 14 is connected to the second contact hole 11, and the second metal gate 15 is connected to the third contact hole 12. Thus, the second S-pole 13, the second N-pole 14 and the second metal gate 15 form a back-end structure together, and the second S-pole 13 is connected to the first S-pole 6 through the first contact hole 10, the second N-pole 14 is connected to the first N-pole 7 through the second contact hole 11, and the second metal gate 15 is connected to the first metal gate 9 through the third contact hole 12.

[0051] The present invention uses specific embodiments to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A depletion-mode gallium nitride HEMT device with a composite gate dielectric, characterized in that: The invention comprises a substrate, and a buffer layer, a channel GaN layer, an ALGaN layer and a composite gate dielectric structure layer which are sequentially stacked in the vertical direction on the surface of the substrate, wherein the composite gate dielectric structure layer comprises an oxide isolation layer arranged between an insitu-SiN layer and an LPSiN layer.

2. The depletion-mode gallium nitride HEMT device with a composite gate dielectric according to claim 1, characterized in that: The insitu-SiN layer is stacked on the ALGaN layer, the oxide isolation layer is stacked on the insitu-SiN layer, the LPSiN layer is stacked on the oxide isolation layer, and the oxide isolation layer is an AL2O3 layer or a SiO2 layer.

3. The depletion-mode gallium nitride HEMT device with a composite gate dielectric according to claim 1, characterized in that: The lateral cross-sectional area of ​​the composite gate dielectric structure layer is smaller than that of the ALGaN layer, and two ends of the composite gate dielectric structure layer are respectively provided with a first S pole and a first N pole abutting against the ALGaN layer.

4. The depletion-mode gallium nitride HEMT device with a composite gate dielectric according to claim 3, characterized in that: The surfaces of the first S-pole, the first N-pole and the LPSiN layer are covered with a PESiN layer, and the PESiN layer is provided with a first metal gate isolated from the first S-pole and the first N-pole.

5. The depletion-mode gallium nitride HEMT device with a composite gate dielectric according to claim 4, characterized in that: The PESiN layer is provided with a first contact hole, a second contact hole and a third contact hole connected to the first S pole, the first N pole and the first metal gate from the outer surface to the inner part thereof, respectively; the outer surface of the PESiN layer is provided with a second S pole, a second N pole and a second metal gate isolated from each other, wherein the second S pole is connected to the first contact hole, the second N pole is connected to the second contact hole, and the second metal gate is connected to the third contact hole.

6. A method for preparing a depletion-mode gallium nitride HEMT with a composite gate dielectric, characterized in that: The following steps are involved: providing a substrate; Depositing a buffer layer, a channel GaN layer and an AlGaN layer in sequence along the longitudinal direction on the surface of the substrate; Depositing a composite gate dielectric structure layer on the surface of the ALGaN layer; Wherein, in the step of "depositing a composite gate dielectric structure layer on the surface of the ALGaN layer", specifically, Depositing an insitu-SiN layer as a first gate dielectric on the surface of the ALGaN layer; Depositing an oxide isolation layer as a second gate dielectric on the surface of the insitu-SiN layer; A LPSiN layer as a third gate dielectric is deposited on the surface of the oxide isolation layer.

7. The method for preparing a depletion-mode gallium nitride HEMT with a composite gate dielectric according to claim 6, characterized in that: After the step of "depositing a LPSiN layer as a third gate dielectric layer on the surface of the oxide isolation layer", the following steps are also included: Ohmic contact opening etching is performed on both ends of the composite gate dielectric structure layer to expose the ALGaN layer located at both ends of the composite gate dielectric structure layer.

8. The method for preparing a depletion-mode gallium nitride HEMT with a composite gate dielectric according to claim 7, characterized in that: After the step of "etching ohmic contact openings at both ends of the composite gate dielectric structure layer to expose the ALGaN layer at both ends of the composite gate dielectric structure layer", the following steps are also included: A first S pole and a first N pole abutting against the ALGaN layer are respectively deposited at two ends of the composite gate dielectric structure layer.

9. The method for preparing a depletion-mode gallium nitride HEMT with a composite gate dielectric according to claim 8, characterized in that: After the step of "respectively depositing a first S pole and a first N pole abutting against the ALGaN layer at both ends of the composite gate dielectric structure layer", the following steps are also included: Depositing PESiN on the first S-pole, the first N-pole and the surface of the LPSiN layer to form a PESiN layer; Etching the PESiN layer twice, wherein the first etching is performed longitudinally from the outer surface of the PESiN layer to the LPSiN layer, and the second etching is performed transversely and connected to the first etched portion, and the upper surface after the second etching is isolated from the LPSiN layer; A first metal gate and a metal field plate are deposited inside the etched PESiN layer.

10. The method for preparing a depletion-mode gallium nitride HEMT with a composite gate dielectric according to claim 9, characterized in that: After the step of “depositing a metal gate and a metal field plate inside the etched PESiN layer”, the following steps are also included: Depositing a dielectric on the surface of the PESiN layer to cover the first S-pole, the first N-pole, the first metal gate and the metal field plate; Contact hole opening etching is performed on the surface of the PESiN layer, so as to respectively open a first contact hole, a second contact hole and a third contact hole connected with the first S pole, the first N pole and the first metal gate from the outer surface to the inner part of the PESiN layer; A back-end metal is deposited on the outer surface of the PESiN layer to provide a second S-pole, a second N-pole and a second metal gate isolated from each other on the outer surface of the PESiN layer, wherein the second S-pole is connected to the first contact hole, the second N-pole is connected to the second contact hole, and the second metal gate is connected to the third contact hole.

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