Trench gate silicon carbide MOSFET device integrated with FinFET structure and manufacturing method

Abstract

The invention provides a trench gate silicon carbide MOSFET device integrated with a FinFET structure and a manufacturing method. The device structurally comprises an N + substrate, an N-epitaxial layer, an N + buffer layer, a P-type well region, a carrier expansion layer (CSL layer), an N + source region, a P + shielding region, a polycrystalline silicon gate, a source trench, source metal and drain metal. According to the invention, the FinFET structure with the fin width less than 300nm is integrated into the gate trench of the trench gate silicon carbide MOSFET. The integrated FinFET increases the channel density of the device, meanwhile, the carrier distribution is more uniform due to the extremely narrow Fin-shaped table top, the influence of interface scattering on the carriers is weakened, and the channel mobility is increased. Therefore, after the FinFET structure is integrated, the specific on-resistance of the trench gate silicon carbide MOSFET is obviously reduced. Meanwhile, the device is provided with a source trench which is deep and is wrapped by a P + shielding region, and the P + shielding region prevents the oxide layer at the corner of the trench from being broken down in advance.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices, and in particular relates to a trench gate silicon carbide MOSFET device with an integrated FinFET structure and a manufacturing method thereof. Background Art

[0002] As more and more applications put forward higher requirements on the withstand voltage and power consumption of power devices, the performance of power devices is facing greater and greater challenges. Silicon carbide materials have the advantages of high thermal conductivity, wide bandgap, high critical breakdown voltage, etc. Semiconductor devices made of silicon carbide are becoming increasingly advantageous in high-voltage and high-power applications. Silicon carbide MOSFET has the characteristics of high breakdown voltage, low specific on-resistance, low switching loss, etc., and has advantages in various application scenarios such as new energy vehicles. However, due to the limitations of the gate oxide process, there are a large number of interface traps at the interface of silicon carbide MOSFET. These traps make silicon carbide MOSFET have lower channel mobility and increase the specific on-resistance of silicon carbide MOSFET.

[0003] In order to reduce the specific on-resistance of SiC MOSFET, trench SiC MOSFET was proposed. The channel of trench SiC MOSFET is generally located at (11 _ 20) or (1 _ 100) crystal plane, with smaller interface traps and thus higher interface mobility. However, in order to protect the gate oxide layer, trench-type SiC MOSFETs often introduce a P-type shielding region, which introduces JFET region resistance and increases the cell size, thus failing to achieve a smaller specific on-resistance. Trench-gate SiC MOSFET is a classic trench-gate SiC MOSFET structure, in which the channel is located at (112 _ 0) crystal plane. The structure has a gate trench and a source trench. The source trench is wrapped by P+, which prevents the oxide layer at the corner of the trench from breaking down prematurely. At the same time, the JFET resistance is introduced to limit the specific on-resistance of the device.

[0004] Japanese scholars proposed and manufactured silicon carbide FinFET devices. When the Fin width is narrow enough, the device forms a "body inversion layer" channel with a more uniform carrier distribution. The uniformly distributed channel carriers reduce interface scattering and increase interface mobility. At the same time, silicon carbide FinFET has a smaller cell size than silicon carbide trench gate MOSFET, so it has a larger channel density. The above mechanism makes silicon carbide FinFET have a much lower specific on-resistance than silicon carbide trench gate MOSFET. However, the gate oxide layer electric field of the above silicon carbide FinFET is high under high voltage, exceeding the safe working electric field strength of silicon dioxide 3MV / cm.

[0005] The present invention integrates the FinFET structure into the gate trench of the trench gate silicon carbide MOSFET, and the width of the Fin-shaped table is less than 300nm. The integrated FinFET structure sacrifices part of the channel located on the side wall of the trench and introduces a channel located inside the Fin-shaped table. The channel width inside the Fin-shaped table is greater than the channel width of the sacrificed trench side wall. Therefore, the overall channel density of the device is increased. At the same time, the extremely narrow Fin-shaped table has a "body inversion" layer with a more uniform carrier distribution inside, the carrier concentration away from the interface increases, the influence of interface scattering on channel carriers is weakened, and the channel mobility is increased. Therefore, after the FinFET structure is integrated, the specific on-resistance of the trench gate silicon carbide MOSFET is significantly reduced. The P-type shielding structure at the source trench of the conventional trench gate silicon carbide MOSFET can protect the gate oxide layer of the FinFET structure integrated inside the trench, so the gate oxygen reliability of the entire device is not weakened. Summary of the invention

[0006] The purpose of the present invention is to provide a trench gate silicon carbide MOSFET device with an integrated FinFET structure and a manufacturing method thereof. The device structure is based on a conventional double-trench silicon carbide MOSFET structure, wherein the channels are located on both sides of the gate trench, and a P+ shielding region is provided at the source trench. The present invention integrates a FinFET structure with a Fin-shaped mesa width of less than 300nm inside the gate trench to improve the device's specific on-resistance, while the P+ shielding region protects the gate oxide layer of the FinFET structure, so that the device has a low specific on-resistance and good gate oxide layer reliability.

[0007] In order to achieve the above-mentioned invention object, the present invention adopts the following technical solutions:

[0008] A trench gate silicon carbide MOSFET device with an integrated FinFET structure, comprising: an N+ substrate 3, an N+ buffer layer 2, an N-drift region 1 and a CSL layer 4 are sequentially arranged above the N+ substrate 3; a gate trench is arranged above the CSL layer 4, and a gate oxide layer 9 and a polysilicon gate 10 are arranged in the trench; and P-type well regions 7 and N+ source regions 8 are arranged on both sides of the gate trench to form a channel;

[0009] The gate trench integrates a FinFET structure consisting of a P-type well region 7, an N+ source region 8, a CSL layer 4, an N-drift region 1, a gate oxide layer 9 and a polysilicon gate 10, wherein the N-drift region 1 has a CSL layer 4, the P-type well region 7 is located on the CSL layer 4, the N+ source region 8 is located on the P-type well region 7, the polysilicon trench passes through the N+ source region 8 and the P-type well region 7 and ends in the CSL layer 4, and the polysilicon gate is located in the trench; There are P+ shielding area A5 and P+ shielding area B6 on the CSL layer 4, and the P+ shielding area A5 and P+ shielding area B6 wrap the source groove; the source groove contains a gate oxide layer 9 and polysilicon A11 and polysilicon B12 in the source groove; there are source metal A13 and source metal B14 above the P+ shielding area A5, P+ shielding area B6 and N+ source area 8, and the source metal forms an ohmic contact with the P+ shielding area A5, P+ shielding area B6 and N+ source area 8; a drain metal 15 is arranged at the bottom of the device to form an ohmic contact with the N+ substrate 3.

[0010] As a preferred embodiment, the FinFET structure integrated in the gate trench has a mesa width less than 300 nm.

[0011] The present invention also provides a method for manufacturing a trench gate silicon carbide MOSFET device with an integrated FinFET structure, comprising the following steps:

[0012] Step 1: Select silicon carbide material as the N+ substrate layer, and epitaxially grow an N+ buffer layer on the N+ substrate;

[0013] Step 2: epitaxially grow an N-drift region on the N+ buffer layer;

[0014] Step 3: epitaxially grow a CSL layer on the N-drift region;

[0015] Step 4: Form a P-type well region on the surface of the CSL layer by ion implantation of Al ions;

[0016] Step 5: Form an N+ source region by ion implantation of N ions on the surface of the P-type well region;

[0017] Step 6: Etching the CSL layer to form a gate trench;

[0018] Step 7: Etching the CSL layer to form a source trench;

[0019] Step 8: Form a P+ shielding region at the bottom and sidewalls of the source trench

[0020] Step 9: growing an oxide layer in the trench;

[0021] Step 10: deposit polysilicon in the trench, and then etch to leave the polysilicon in the gate and source trenches;

[0022] Step 11: depositing and etching polysilicon on the gate trenches to electrically connect the polysilicon in different gate trenches;

[0023] Step 12: Deposit a dielectric layer and etch a source contact hole.

[0024] Step 13: Form metal on the upper and lower surfaces of the device.

[0025] The present invention integrates a FinFET structure with a Fin-shaped table width less than 300nm on the basis of a traditional trench gate silicon carbide MOSFET device structure. The integrated FinFET structure sacrifices part of the channel located on the trench sidewall and introduces a channel located inside the Fin-shaped table. The channel width inside the Fin-shaped table is greater than the channel width of the sacrificed trench sidewall. Therefore, the overall channel density of the device is increased. At the same time, the extremely narrow Fin-shaped table has a "body inversion" layer with a more uniform carrier distribution inside, the carrier concentration away from the interface increases, the influence of interface scattering on channel carriers is weakened, and the channel mobility is increased. Therefore, after the FinFET structure is integrated, the specific on-resistance of the trench gate silicon carbide MOSFET is significantly reduced. In addition, the P-type shielding structure of the trench gate silicon carbide MOSFET structure protects the gate oxide layer, so that the oxide layer at the trench corner will not be broken down prematurely after the FinFET structure is introduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide a further understanding of the present invention and are used together with the embodiments of the present invention to explain the present invention, but do not constitute a limitation of the present invention:

[0027] Figure 1 The present invention is a trench gate silicon carbide device structure integrating a FinFET structure.

[0028] Figure 2 The present invention discloses a trench gate silicon carbide device with an integrated FinFET structure, which is a structure of polysilicon and metal.

[0029] Figure 3 A top view of a trench-gate SiC MOSFET with an integrated FinFET structure ignoring the metal, polysilicon and dielectric layers.

[0030] Figure 4 To consider the metal, polysilicon and dielectric Figure 2 The cross-sectional view along the AA' dashed line in the figure, the AA' dashed line is a dashed line pointing from one source trench to the other source trench and passing through the N+ source region and the polysilicon gate, and the BB' dashed line is a dashed line pointing from the gate trench to the adjacent gate trench and passing through the fin-shaped mesa.

[0031] Figure 5 After considering metal, polysilicon and dielectric Figure 2Cross-sectional view along the dotted line BB'.

[0032] Figure 6 It is a schematic diagram of the silicon carbide epitaxial wafer of the present invention.

[0033] Figure 7 It is a schematic diagram of the present invention of implanting a Pwell layer on an epitaxial wafer.

[0034] Figure 8 It is a schematic diagram of the present invention of injecting N+ region into the epitaxial layer.

[0035] Fig. 9 It is a schematic diagram of digging a gate trench and a source trench in the epitaxial layer according to the present invention.

[0036] Fig.10 It is a schematic diagram of the present invention of injecting a P+ shielding structure into a source trench.

[0037] Fig.11 The present invention forms an oxide layer and polysilicon in the gate trench, and forms metal contacts on the upper and lower surfaces of the device.

[0038] Among them, 1-N-drift region, 2-N+ buffer layer, 3-N+ substrate, 4-CSL layer, 5-P+ shielding region A, 6-P+ shielding region B, 7-P-type well region, 8-N+ source region, 9-gate oxide layer, 10-polysilicon gate, 11-polysilicon A in the source trench, 12-polysilicon B in the source trench, 13-source metal A, 14-source metal B, 15-drain metal. DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] like Figure 1 and Figure 2 As shown, a trench gate silicon carbide MOSFET device with an integrated FinFET structure comprises: an N+ substrate 3, an N+ buffer layer 2, an N-drift region 1 and a CSL layer 4 are sequentially arranged above the N+ substrate 3; a gate trench is arranged above the CSL layer 4, and a gate oxide layer 9 and a polysilicon gate 10 are arranged in the trench; and P-type well regions 7 and N+ source regions 8 are arranged on both sides of the gate trench to form a channel;

[0041] The gate trench integrates a FinFET structure consisting of a P-type well region 7, an N+ source region 8, a CSL layer 4, an N-drift region 1, a gate oxide layer 9 and a polysilicon gate 10, wherein the N-drift region 1 has a CSL layer 4, the P-type well region 7 is located on the CSL layer 4, the N+ source region 8 is located on the P-type well region 7, the polysilicon trench passes through the N+ source region 8 and the P-type well region 7 and ends in the CSL layer 4, and the polysilicon gate is located in the trench; There are P+ shielding area A5 and P+ shielding area B6 on the CSL layer 4, and the P+ shielding area A5 and P+ shielding area B6 wrap the source groove; the source groove contains a gate oxide layer 9 and polysilicon A11 and polysilicon B12 in the source groove; there are source metal A13 and source metal B14 above the P+ shielding area A5, P+ shielding area B6 and N+ source area 8, and the source metal forms an ohmic contact with the P+ shielding area A5, P+ shielding area B6 and N+ source area 8; a drain metal 15 is arranged at the bottom of the device to form an ohmic contact with the N+ substrate 3.

[0042] The FinFET structure integrated in the gate trench has a mesa width less than 300 nm.

[0043] Figure 3 A top view of a trench-gate SiC MOSFET with an integrated FinFET structure, ignoring metal, polysilicon, and dielectric layers, including a P+ shielding region, an N+ source region, a gate trench, and a gate oxide layer. The gate trenches are arranged alternately, and adjacent gate trenches form a FinFET structure with the N+ source region, the P-type well region, and the N-drift region.

[0044] Figure 4 To consider the metal, polysilicon and dielectric Figure 2 The cross-section along the AA' dashed line in the figure shows a double-trench SiC MOSFET structure, including a gate trench, with trenches on both sides of the trench. The source trench is wrapped by a P+ shielding structure, and the P+ shielding area protects the gate oxide layer under high electric fields. The AA' dashed line is a dashed line that points from one source trench to the other source trench and passes through the N+ source region and the polysilicon gate.

[0045] Figure 5 To consider the metal, polysilicon and dielectric Figure 2The cross-section along the BB' dashed line in the figure shows a FinFET structure integrated in the trench, which consists of adjacent gate trenches, N+ source region, Pwell region and N- drift region. When the Fin table width is less than 300nm, a "body inversion" layer appears, and the FinFET structure has a higher interface mobility. At the same time, after the FinFET structure is integrated, the channel density of the device increases. All of the above factors lead to a reduction in the on-resistance of the trench gate silicon carbide MOSFET with an integrated FinFET structure compared to the double trench silicon carbide MOSFET. The BB' dashed line is a dashed line pointing from the gate trench to the adjacent gate trench and passing through the fin-shaped table;

[0046] This embodiment also provides a method for manufacturing a trench gate silicon carbide MOSFET with an integrated FinFET structure, comprising the following steps:

[0047] Step 1: Select silicon carbide material as the N+ substrate layer and epitaxially grow an N+ buffer layer on the N+ substrate;

[0048] Step 2: epitaxially grow an N-drift region on the N+ buffer layer;

[0049] Step 3: epitaxially grow the CSL layer on the N-drift region, such as Figure 6 As shown;

[0050] Step 4: Form a P-type well region on the surface of the CSL layer by ion implantation of Al ions, such as Figure 7 As shown;

[0051] Step 5: Form an N+ source region by ion implantation of N ions on the surface of the P-type well region, such as Figure 8 As shown;

[0052] Step 6: Etching the CSL layer to form a gate trench;

[0053] Step 7: Etch the CSL layer to form a source trench, and finally form Fig. 9 The device shown;

[0054] Step 8: Form a P+ shielding region at the bottom and sidewalls of the source trench, such as Fig.10 As shown;

[0055] Step 9: growing an oxide layer in the trench;

[0056] Step 10: deposit polysilicon in the trench, and then etch to leave the polysilicon in the gate and source trenches;

[0057] Step 11: depositing and etching polysilicon on the gate trenches to electrically connect the polysilicon in different gate trenches;

[0058] Step 12: Deposit a dielectric layer and etch a source contact hole.

[0059] Step 13: Form metal on the upper and lower surfaces of the device, and finally form Fig.11 Device shown.

[0060] The specific concentration and thickness of the N-drift region 1 are determined according to the voltage level of the device.

[0061] The concentration and depth of P+ shielding region A5 and P+ shielding region B6 are determined according to the electric field strength and the on-state voltage drop of the gate oxide layer.

[0062] The working principle of the present invention is:

[0063] The present invention proposes a trench gate silicon carbide MOSFET device with an integrated FinFET structure, wherein the width of the Fin-shaped mesa is less than 300nm. The integrated FinFET structure sacrifices part of the channel located on the sidewall of the trench and introduces a channel located inside the Fin-shaped mesa. The channel width inside the Fin-shaped mesa is greater than the channel width of the sacrificed trench sidewall. Therefore, the overall channel density of the device is increased. At the same time, the extremely narrow Fin-shaped mesa has a "body inversion" layer with a more uniform carrier distribution, the carrier concentration away from the interface increases, the effect of interface scattering on channel carriers is weakened, and the channel mobility is increased. Therefore, after the FinFET structure is integrated, the specific on-resistance of the trench gate silicon carbide MOSFET is significantly reduced. Secondly, the P-type shielding region that wraps the source trench reduces the electric field strength of the gate oxide layer, so that the gate oxide layer of the device with the integrated FinFET structure is still protected.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A trench gate silicon carbide MOSFET device with an integrated FinFET structure, characterized in that: include: An N+ substrate (3), wherein an N+ buffer layer (2), an N-drift region (1) and a CSL layer (4) are sequentially arranged above the N+ substrate (3); a gate trench is arranged above the CSL layer (4), wherein a gate oxide layer (9) and a polysilicon gate (10) are arranged in the trench; and a P-type well region (7) and an N+ source region (8) are arranged on both sides of the gate trench, thereby forming a channel; The gate trench integrates a FinFET structure consisting of a P-type well region (7), an N+ source region (8), a CSL layer (4), an N-drift region (1), a gate oxide layer (9) and a polysilicon gate (10), wherein the N-drift region (1) has a CSL layer (4), the P-type well region (7) is located on the CSL layer (4), the N+ source region (8) is located on the P-type well region (7), the polysilicon trench passes through the N+ source region (8) and the P-type well region (7) and ends in the CSL layer (4), and the polysilicon gate is located in the trench; the CSL layer (4) has a P+ shielding region A (5) and a P+ shielding region B (6). Region B (6), the P+ shielding region A (5) and the P+ shielding region B (6) wrap the source trench; the source trench contains a gate oxide layer (9) and polysilicon A (11) in the source trench and polysilicon B (12) in the source trench; source metal A (13) and source metal B (14) are provided above the P+ shielding region A (5), the P+ shielding region B (6) and the N+ source region (8), and the source metal forms an ohmic contact with the P+ shielding region A (5), the P+ shielding region B (6) and the N+ source region (8); a drain metal (15) is provided at the bottom of the device to form an ohmic contact with the N+ substrate (3).

2. The trench gate silicon carbide MOSFET device with integrated FinFET structure according to claim 1, characterized in that: The FinFET structure integrated in the gate trench has a mesa width less than 300 nm.

3. A method for manufacturing a trench gate silicon carbide MOSFET device with an integrated FinFET structure as claimed in claim 1 or 2, characterized in that The following steps are involved: Step 1: Select silicon carbide material as the N+ substrate layer and epitaxially grow an N+ buffer layer on the N+ substrate; Step 2: epitaxially grow an N-drift region on the N+ buffer layer; Step 3: epitaxially grow a CSL layer on the N-drift region; Step 4: Form a P-type well region on the surface of the CSL layer by ion implantation of Al ions; Step 5: Form an N+ source region by ion implantation of N ions on the surface of the P-type well region; Step 6: Etching the CSL layer to form a gate trench; Step 7: Etching the CSL layer to form a source trench; Step 8: Form a P+ shielding region at the bottom and sidewalls of the source trench Step 9: growing an oxide layer in the trench; Step 10: deposit polysilicon in the trench, and then etch to leave the polysilicon in the gate and source trenches; Step 11: depositing and etching polysilicon on the gate trenches to electrically connect the polysilicon in different gate trenches; Step 12: Deposit a dielectric layer and etch a source contact hole. Step 13: Form metal on the upper and lower surfaces of the device.

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