Method and device for carrying out reverse conversion in RNS (Radio Network Server)

Abstract

The embodiment of the invention provides a method and a device for reverse conversion of an RNS (Radio Network Service). According to the proposed system, an RNS reverse conversion unit is used to implement multi-size support in matrix multiplication hardware acceleration. The proposed RNS inverse conversion unit reconstructs numbers of different size types from a control signal indicating one of the reconstructions of the results of the matrix multiplication and a kernel function. The result of the matrix multiplication is a single 128-bit result, two 64-bit results or four 32-bit results. The kernel function supports reconstruction of results of different size types using efficient hierarchical control accumulation. According to the architecture of the RNS reverse conversion unit provided by the invention, the end remodulo operation is replaced by subtraction and multiplexers, and binary numbers can be reconstructed in the whole dynamic range of the RNS. Thus, compared to known CRT-based multi-size type reverse conversion units, the proposed method and apparatus provide multi-size type RNS reverse conversion support for matrix multiplication with a smaller hardware area, less power consumption, and faster processing speed.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of residue number system (RNS), and more specifically, to a method and device for performing reverse conversion in RNS. Background Art

[0002] Dedicated matrix multiplication acceleration is widely used in the fields of high performance computing (HPC) and artificial intelligence (AI), but the two fields have different requirements for size types. Integer32 (int32) / integer64 (int64) are mainly used in HPC, while int8 / int16 are commonly used in AI. For hardware manufacturers, this provides two strategic directions, namely, creating dedicated accelerators for AI and HPC respectively, or minimizing development costs by creating accelerators suitable for both fields. A common approach to supporting different size types in hardware is to implement separate multiply accumulator (MAC) units for each data type. However, this approach reduces the competitiveness of the final product compared to matrix multiplication accelerators dedicated to specific fields because part of the hardware is not used and the power consumption is high. Hardware equipped with dedicated MACs for each size type is inefficient, especially when only large integer calculations or small integer calculations are required. Summary of the invention

[0003] The embodiment of the present invention provides a method and device for reverse conversion in RNS, which provides reconstructible multi-size support in the reverse conversion unit of RNS and has high hardware efficiency in reducing hardware cost, saving power consumption and processing time.

[0004] According to a first aspect, there is provided a method for performing reverse conversion in a residue number system (RNS), the method comprising:

[0005] receiving a control signal for indicating one of reconstruction of a single 128-bit result, reconstruction of two 64-bit results, and reconstruction of four 32-bit results, the indicated reconstruction being reconstruction of a result of a matrix multiplication;

[0006] The indicated reconstruction is performed on the result of the matrix multiplication according to a core function, wherein the core function is based on the RNS inverse conversion algorithm capable of implementing multi-size type support.

[0007] According to the present invention, RNS reverse conversion is performed according to a core function, which is based on an RNS reverse conversion algorithm capable of implementing multi-size type support. In addition, the proposed RNS reverse conversion algorithm replaces heavy modular operations with subtraction and multiplexers, and has high hardware efficiency in terms of reducing hardware cost, saving power consumption and processing time.

[0008] In one embodiment, the core function is a core function C(Z) of a binary number Z, which is defined as:

[0009]

[0010] Among them, C(Z) is the core function, w i is the corresponding m i The weight, m i The module set {m1,m2,m3,…,m n}, z i is the RNS representation of Z under RNS {z1,z2…,z i ,…,z n}, M is the dynamic range based on the module set, and the symbol Indicates rounding down.

[0011] In one embodiment, the binary number Z is determined according to the following equation:

[0012]

[0013] in, C M The calculation method is C M is chosen to be a power of 2, and

[0014] In one embodiment, the module set is module set g 64 , the module g 64 The modulus of is used to generate a single 128-bit number when the control signal indicates a first value, wherein g 64 ={m1,m2,m3,…,m 16},m1,m2,m3,…,m 16 are the 16 modules included in the module set;

[0015] Among them, the module and The modulus is used to generate two 64-bit numbers when the control signal indicates the second value, wherein,

[0016] or,

[0017] Wherein, when the control signal indicates the third value, the module The modulus generates four 32-bit numbers, where 1≤i≤4,

[0018]

[0019] The grouping of moduli must meet the following requirements:

[0020]

[0021] According to this embodiment, the proposed RNS inverse conversion based on the kernel function can reconstruct values ​​of different size types by appropriately grouping the modules.

[0022] In one embodiment, the output of the RNS reverse conversion It is calculated as follows:

[0023]

[0024] in,

[0025]

[0026] in, cm2=cm3=cm4=0 (when the control signal indicates the first value); cm3=cm4=0 (when the control signal indicates the second value); (when the control signal indicates the third value);

[0027]

[0028] in,

[0029]

[0030] in,

[0031]

[0032] According to this embodiment, the proposed RNS reverse conversion can use efficient hierarchical control accumulation to reconstruct numbers of different size types. Therefore, the proposed RNS reverse conversion can reconstruct a single 128-bit result, two 64-bit results, or four 32-bit results according to the control signal. The proposed RNS reverse conversion unit only needs a small additional area to support multiple size types in matrix multiplication hardware acceleration.

[0033] In one embodiment, the output is the result of matrix multiplication, and:

[0034] In the case where the control signal indicates the first value, the size type of the numbers in the input matrix is ​​64 bits, and the size type of the numbers in the output matrix is ​​128 bits;

[0035] In the case where the control signal indicates the second value, the size type of the numbers in the input matrix is ​​32 bits, and the size type of the numbers in the output matrix is ​​64 bits; or

[0036] In the case where the control signal indicates the third value, the size type of the numbers in the input matrix is ​​16 bits, and the size type of the numbers in the output matrix is ​​32 bits.

[0037] According to this embodiment, the proposed scheme supports reconstruction of the result of matrix multiplication whose elements are 64 bits, 32 bits or 16 bits.

[0038] According to a second aspect, a device for performing reverse conversion in a residue number system (RNS) is provided. The device has the function of implementing the method in the first aspect and any possible implementation of the first aspect. The function can be implemented by hardware. The hardware includes one or more circuits corresponding to the above functions.

[0039] According to a third aspect, a chip (or chip system) is provided. The chip may include a multiplexer, a multiplier, an adder, a subtractor, and a shifter. The chip has the function of implementing the method in any of the first aspect and the first embodiment. The function can be implemented by the above hardware structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] One or more embodiments are described exemplarily by corresponding drawings, and these exemplary descriptions and drawings do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are described as similar elements, and the scale of the drawings is not limited. In the drawings:

[0041] Figure 1 is a schematic block diagram of a method for RNS inverse conversion according to the present invention.

[0042] Figure 2 are examples of a module set and a group constituting the module set for reconstructing a binary number system (BNS) number according to the present invention.

[0043] Figure 3 is the architecture of a modular arithmetic (MAC) unit of a RNS according to the present invention.

[0044] Figure 4(a) , 4(b) 4(c) is an architectural diagram according to the present invention, showing a mechanism for the invention to reconstruct a single 64-bit binary value, two 32-bit binary values, and four 16-bit binary values ​​from a remainder using a core function that depends on a control signal.

[0045] Figure 5 It is an example of a schematic block diagram of the chip (or chip system) proposed by the present invention. DETAILED DESCRIPTION

[0046] In order to understand the features and technical contents of the embodiments of the present invention in more detail, the implementation of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, which are only used for reference and illustration and are not used to limit the embodiments of the present invention. In the following technical description, for ease of explanation, many details will be described to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be implemented without these details. In other cases, in order to simplify the drawings, well-known structures and devices may be simplified for display.

[0047] 1. Residue Number System (RNS)

[0048] RNS consists of n modules {m1,m2,…,m n} is called a module set. n modules are usually considered to be pairwise relatively prime, that is, GCD(m i ,m j )=1,i,j∈[1,n],i≠j. Let M be all m i : The product of , then an integer x in the range [0,M-1] is represented in RNS by its remainder x under Euclidean division of the modulus → {x1,x2,…,x n}; that is

[0049] One of the biggest features of RNS is that the addition and multiplication between corresponding remainder pairs are independent and can be performed in parallel. As mentioned in the background section, in many cases, it is necessary to support various integer size types in the RNS reverse unit. A common solution to support various integer size types is to add a dedicated MAC unit for each size type. The advantage of this solution is that calculations of various integer types and sizes can be performed in parallel. A reconfigurable low-power high-performance matrix multiplier design is proposed to implement 64-bit multiplication through 4×32-bit multiplication and 1×128-bit accumulator, as follows:

[0050]

[0051] A method and system for multi-precision computing has a similar idea to implement multi-precision support for floating point (FP) numbers, focusing on multiplication of mantissas of different sizes. The idea suggests using FP16 mantissa multiplication as the basis for creating FP32 and FP64 mantissa multiplication. Therefore, the idea requires 4×FP16 to implement a single FP32 mantissa multiplication, and 16×FP16 to implement a single FP16 mantissa multiplication.

[0052] In addition, there are other ways to Multipliers are used to construct D×D multipliers. Specifically, Booth multiplication or Vedic multiplication is used by The intermediate results of the multiplier are used to generate the final D×D multiplication result.

[0053] In view of this, the present invention proposes a method and apparatus for RNS reverse conversion. The main problem to be solved is to support reconstructable multi-size type RNS reverse conversion with smaller hardware area and lower power consumption compared with the above-mentioned known solutions. In addition, the present invention also supports data types such as int64, int32, int16 and int8.

[0054] The present invention reconstructs binary numbers over the entire dynamic range Z∈[0;M-1]. The scheme proposed by the present invention can be used in a matrix multiplication hardware accelerator to convert all multiplication and accumulation operations in BNS to RNS. Although the conversion operation from BNS to RNS requires additional forward conversion and reverse conversion costs, the number of conversion operations is one order of magnitude less than the number of multiplications and additions, so it can be ignored in matrix multiplication.

[0055] Figure 1 1 is a schematic block diagram of a method (200) for RNS reverse conversion according to the present invention. The method (200) can be applied to fields that need to support various data size types. For example, the method (200) can be applied to hardware matrix multiplication accelerators used in HPC and AI, and can reduce hardware costs and power consumption. The method (200) includes the following steps.

[0056] Step 210: Receive a control signal, wherein the control signal is used to indicate one of reconstruction of a single 128-bit result, reconstruction of two 64-bit results, and reconstruction of four 32-bit results, wherein the indicated reconstruction is reconstruction of the result of matrix multiplication.

[0057] In other words, the control signal indicates the operating mode, which may be reconstruction of a single 128-bit result, reconstruction of two 64-bit results, or reconstruction of four 32-bit results.

[0058] It should be understood that the RNS reverse conversion is to convert the result of the matrix multiplication of two numbers represented in RNS into the result of the matrix multiplication represented in BNS. Therefore, when the size type of the number in the input matrix is ​​64 bits, a single 128-bit result is reconstructed; when the size type of the number in the input matrix is ​​32 bits, two 64-bit results are reconstructed; when the size type of the number in the input matrix is ​​16 bits, four 32-bit results are reconstructed.

[0059] Step 220: Perform the indicated reconstruction on the result of the matrix multiplication according to a core function, wherein the core function is based on the RNS inverse conversion algorithm capable of implementing multi-size type support.

[0060] All relevant contents of the steps in the method (200) will be described in detail below in conjunction with the architecture of the proposed RNS reverse conversion unit.

[0061] In the present invention, the proposed RNS inverse conversion unit architecture replaces the terminal remodulus operation by subtraction and multiplexer.

[0062] The proposed RNS reverse conversion is based on hierarchical accumulation of intermediate values, where 64-bit size type values ​​need to be accumulated at all levels, 32-bit size type values ​​skip the last level accumulation, 16-bit size type values ​​skip the last two levels accumulation, and 8-bit size type values ​​bypass the reverse conversion.

[0063] Figure 2 is an example of a module set and a group constituting a module set for reconstructing a BNS number according to the present invention. It can be seen that the module set provided by the present invention is {m1,m2,…,m 16}, that is, the module set contains 16 modules. Specifically, {m1,m2,…,m 16} = {512,511,509,489,487,485,481,479,473,467,431,167,151,139,137,131}. In addition, the modules in the module set are grouped as follows:

[0064]

[0065] The above grouping of modules is for reference only, and other grouping methods can also be used. The general requirements that need to be met for module grouping include:

[0066]

[0067] Figure 3It is the architecture of the modular arithmetic (MAC) unit of the RNS according to the present invention. Specifically, the architecture shows a reconstruction mechanism for a single 128-bit binary value, two 64-bit binary values, and four 32-bit binary values, which is based on core functions and control signals. It can be seen that the architecture includes 16 RNS modular adders and multipliers, which are 9×9 and 8×8 adders and multipliers with modular subtraction, respectively. Since modular operations can be performed independently, no additional multi-size support is required in the RNS MAC unit except that the dedicated mode of 8-bit addition and multiplication needs to bypass modular subtraction. The RNS multipliers / adders implicitly form groups according to the operating mode that depends on the control signal (i.e., the CTRL signal). Specifically, the RNS multipliers / adders process a single 64-bit value, two 32-bit values, or four 16-bit values ​​according to the operating mode. Each modular multiplier performs Each adder performs Calculation.

[0068] Next, the core functions proposed by the present invention will be described in detail.

[0069] The mathematical description of the core function is based on the algorithm of the reverse conversion, that is, the conversion from RNS to BNS, which supports multiple size types. Consider the RNS representation of a BNS number Z {z1,z2…z n}, the core function is the core function of the BNS number Z and is defined as equation (1):

[0070]

[0071] Among them, C(Z) is the core function, w i is the corresponding m i The weight, m i The module set {m1,m2,m3,…,m n}, z i is the RNS representation of Z under RNS {z1,z2…,z i ,…,z n}, M is the dynamic range based on the module set, and the symbol Indicates rounding down.

[0072] Equation (1) can also be replaced by the following equation (2):

[0073]

[0074] in,

[0075] The RNS representation of the number Z can be used to calculate the C M is the core value of the modulus number Z, that is

[0076] Choose a number sh in such a way that C M =2 sh , A number sh that satisfies these conditions always exists. i ) does not depend on z i , can be used for all Pre-calculate.

[0077]

[0078] The number Z can be reconstructed by the following equation (4):

[0079]

[0080] Select C M Being a power of 2 is key to the invention as this greatly simplifies the calculation logic of the core value and also converts the final division into a bit shift operation.

[0081] To support different size types, the subsets of the module set for different size types are different, and the constant M for each subset of the module set is i ,w i ,B i However, in order to efficiently support multi-size type patterns through hierarchical accumulation, for all subsets of the module set, C M Must be the same.

[0082] Advantages of the present invention over the CRT-based approach include the need for only one multiplexer in the final modulo M operation (because ), and reconstruct all numbers from the entire dynamic range of [0; M-1] without error.

[0083] FIG4 is an architectural diagram showing a mechanism for reconstructing a single 64-bit binary number, two 32-bit binary numbers, and four 16-bit numbers from a remainder using a core function dependent on a control signal according to the present invention. The architectural diagram is shown in FIG4(a), FIG4(b), and FIG4(c), which is clear and concise.

[0084] As mentioned above, select C in this way M ,Right now

[0085] The input of the RNS reverse transformation unit is the remainder {z1,z2,…,z 16}:

[0086] In the case where the control signal indicates the first value, the group g is used 64 All remainders of the digits are used to generate a single 128-bit number;

[0087] In the case where the control signal indicates the second value, the The remainder of is used to generate the low 64 bits of the 128-bit number, from the group The remainder of is used to generate the first 64 bits of the 128-bit number; or

[0088] In the case where the control signal indicates a third value, the The remainders are used to generate the i-th 128-bit number. th 32-bit parts, where 1≤i≤4.

[0089] The output of the RNS reverse conversion unit also depends on the following control signal:

[0090] (1) If the control signal indicates the first value, a single 128-bit number is output, which is represented by A[127:0]. The single 128-bit number is also represented by

[0091] (2) If the control signal indicates the second value, two 64-bit numbers are output. The two 64-bit numbers are represented as {A[127:64], A[63:0]}. The two 64-bit numbers are also represented as {A[127:64], A[63:0]} in FIG. 4(c). and

[0092] (3) If the control signal indicates the third value, four 32-bit numbers are output. The four 32-bit numbers are represented as {A[127:96], A[95:64], A[63:32], A[31:0]}. The four 32-bit numbers are also represented as

[0093] Precomputed constants:

[0094]

[0095] If the control signal indicates a first value, the symbol “ctrl” is equal to 64; if the control signal indicates a second value, the symbol “ctrl” is equal to 32; and if the control signal indicates a third value, the symbol “ctrl” is equal to 16.

[0096] For example, if the first value is "0", the second value is "1", and the third value is "2", then the value of the symbol "ctrl" is determined according to the following equation:

[0097]

[0098] It should be noted that in FIG4(a), “×&” represents the operation Where "&" is a logical AND operation. Similarly, "+&" represents the operation The "&" is a logical AND operation.

[0099] Furthermore, in FIG4 , “MUX” denotes a multiplexer, “+” denotes an adder, “×” denotes a multiplier, “−” denotes a subtractor, and ″>>” denotes a shifter.

[0100] The hardware process is described below.

[0101] Step 1: Calculation core value.

[0102] Specifically, the core value is calculated according to equation (6):

[0103]

[0104] Initially, the values ​​of the above constants are selected according to the value of the control signal.

[0105]

[0106] in, In the above calculation.

[0107] Then use and To calculate and

[0108]

[0109] A modular exponentiation of 2 is performed according to the following equation (7) to calculate the core value:

[0110]

[0111] The output value is calculated as follows:

[0112]

[0113] in, is the output value.

[0114] Step 2: The multiplication operation.

[0115] If the control signal indicates a first value, then cm2=cm3=cm4=0; if the control signal indicates the second value, then cm3=cm4=0; or, if the control signal indicates a third value, then

[0116] Step 3: The sum is calculated in the same way as same.

[0117]

[0118] in, In the calculation of the third step above.

[0119] Step 4: Calculate the final output

[0120] Specifically, The calculation method is as follows:

[0121]

[0122] Here, the symbol “>>” represents a shift operation.

[0123] Final Output The output is as follows:

[0124] If the control signal indicates the first value, the final output The output is Represents a single 128-bit number, which is represented by A[127:0]; if the control signal indicates the second value, the final output The output is and Represents two 64-bit results of multiplying two 32-bit numbers, the two 64-bit numbers are represented as A[127:64], A[63:0]; if the control signal indicates a third value, the final output The output is and The four 32-bit numbers representing the result of multiplying two 16-bit numbers are represented as A[127:96], A[95:64], A[63:32], and A[31:0].

[0125] For example, if the first value, the second value, and the third value are "0", "1", and "2" respectively, the final output can be expressed as:

[0126]

[0127] It should be noted that the size of the numbers in the output matrix is ​​twice the size of the numbers in the input matrix, for example, the size of the numbers in the output matrix is ​​128 bits, which is the result of multiplying two numbers of size 64 bits. This method can be used to correctly handle overflow or implement numbers with fixed-point data types.

[0128] Specifically, when the control signal indicates a first value, the final output is the result of multiplying two 64-bit numbers; when the control signal indicates a second value, the final output is two results of multiplying two 32-bit numbers; when the control signal indicates a third value, the final output is four results of multiplying two 16-bit numbers.

[0129] The final set of multiplexers forms the correct final output based on the control signals, specifically, a single 128-bit number, two 64-bit numbers, or four 32-bit numbers, all of which provide a 128-bit output.

[0130] The present invention proposes to use the independent calculation characteristics of RNS to provide multi-size support for RNS reverse conversion. In the present invention, splitting 64-bit multiplication into 16 modular multiplications has a series of advantages. For example, the same group of modular multipliers and adders can be used to enable one 64-bit, two 32-bit, four 16-bit and eight (or sixteen) 8-bit MAC units through appropriate modular grouping. The number of 8-bit MAC units depends on the actual MAC implementation. Multiplication is performed first, and then the modulus is reduced, so that the multiplier can be used as an 8-bit BNS multiplier, thereby realizing a dedicated RNS-free mode of the 8-bit size type. Although this MAC implementation provides 16 8-bit MAC units, the overall hardware area and power consumption are higher than the efficient modular multiplier implementation that does not use a dedicated modular reduction step. In this case, the 8-bit MAC unit will use two MAC units, for a total of eight 8-bit MAC units.

[0131] Due to the complex carry propagation logic of the 64-bit adder and multiplier, sixteen 8 / 9-bit modular multipliers (needed to cover [0; 2 128 -1]) is less than the hardware area and power consumption of a single 64-bit multiplier.

[0132] The MAC unit does not require any dedicated multi-size support other than specializing in 8-bit integers, and simply bypasses the RNS operation to disable the modulo reduction. For converting between RNS and BNS, additional size type support is only required in the converter.

[0133] Compared with the CRT-based multi-size type reverse conversion unit, the proposed RNS reverse conversion unit supporting multi-size types can reduce hardware area by up to 21% and power consumption by 19%. In addition, the proposed scheme of the present invention is 16% faster than the CRT-based multi-size type reverse conversion unit.

[0134] In addition, the RNS inverse conversion algorithm based on the core function in the present invention correctly reconstructs binary numbers in the entire dynamic range of [0; M-1], while the approximate %M operation method based on CRT cannot guarantee the correct reconstruction of binary numbers in the entire dynamic range of RNS.

[0135] If the RNS inverse conversion unit based on the core function is extended, efficient hierarchical control accumulation can be used to reconstruct numbers of different size types. Therefore, the proposed RNS inverse conversion only requires a small additional area to support multiple size types.

[0136] The above is an introduction to the various embodiments of the method. The following is an explanation of the various embodiments of the device.

[0137] As an embodiment of the present invention, a chip (or chip system) is provided. The chip may include one or more circuits. The one or more circuits are used to implement the reverse conversion method proposed by the present invention. In other words, the one or more circuits as a whole have the function of implementing the method proposed by the present invention.

[0138] Figure 5 is an example of a schematic block diagram of a chip (or chip system) proposed by the present invention. Figure 5 As shown, the chip (or chip system) may include a multiplexer 11, a multiplier 12, an adder 13, a subtractor 14, and a shifter 15. Specifically, the devices included in the chip constitute one or more circuits for performing the RNS reverse conversion proposed by the present invention. The connection relationship between these devices and the operation of each of these devices can refer to the embodiment of FIG. 4 above, and will not be repeated here.

[0139] The above descriptions are only some specific implementations of the present invention and are not intended to limit the protection scope of the present invention. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for performing reverse conversion in a remainder system RNS, characterized in that include: receiving a control signal for indicating one of reconstruction of a single 128-bit result, reconstruction of two 64-bit results, and reconstruction of four 32-bit results, the indicated reconstruction being reconstruction of a result of a matrix multiplication; The indicated reconstruction is performed on the result of the matrix multiplication according to a core function, wherein the core function is based on the RNS inverse conversion algorithm capable of implementing multi-size type support.

2. The method according to claim 1, characterized in that: The core function is the core function C(Z) of the binary number Z, and the core function is defined as: Among them, C(Z) is the core function, w i is the corresponding m i The weight, m i The module set {m1,m2,m3,…,m n }, z i is the RNS representation of Z under RNS {z1,z2…,z i ,…,z n }, M is the dynamic range based on the module set, and the symbol Indicates rounding down.

3. The method according to claim 2, characterized in that The binary number Z is determined according to the following equation: in, C M The calculation method is C M is chosen to be a power of 2, and 4. The method according to claim 2 or 3, characterized in that: The module set is module set g 64 , the modulus of the modulus set is used to generate a single 128-bit number when the control signal indicates a first value, wherein g 64 ={m1,m2,m3,…,m 16 },m1,m2,m3,…,m 16 are the 16 modules included in the module set; Among them, the module and The modulus is used to generate two 64-bit numbers when the control signal indicates the second value, wherein, or, Wherein, when the control signal indicates the third value, the module The modulus generates four 32-bit numbers, where 1≤i≤4, The grouping of moduli must meet the following requirements:

5. The method according to claim 4, characterized in that RNS reverse conversion output It is calculated as follows: in, IN i =In i ctrl ; in, and cm2=cm3=cm4=0 (when the control signal indicates the first value); cm3=cm4=0 (when the control signal indicates the second value); (when the control signal indicates the third value); in in, 6. The method according to claim 5, characterized in that The output is the result of matrix multiplication, and: In the case where the control signal indicates the first value, the size type of the numbers in the input matrix is ​​64 bits, and the size type of the numbers in the output matrix is ​​128 bits; In the case where the control signal indicates the second value, the size type of the numbers in the input matrix is ​​32 bits, and the size type of the numbers in the output matrix is ​​64 bits; or In the case where the control signal indicates the third value, the size type of the numbers in the input matrix is ​​16 bits, and the size type of the numbers in the output matrix is ​​32 bits.

7. A device for performing reverse conversion in a remainder system RNS, characterized in that include: One or more circuits for: receiving a control signal for indicating one of reconstruction of a single 128-bit result, reconstruction of two 64-bit results, and reconstruction of four 32-bit results, the indicated reconstruction being reconstruction of a result of a matrix multiplication; The indicated reconstruction is performed on the result of the matrix multiplication according to a core function, wherein the core function is based on the RNS inverse conversion algorithm capable of implementing multi-size type support.

8. The device according to claim 7, characterized in that The core function is the core function C(Z) of the binary number Z, and the core function is defined as: Among them, C(Z) is the core function, w i is the corresponding m i The weight, m i The module set {m1,m2,m3,…,m n }, z i is the RNS representation of Z under RNS {z1,z2…,z i ,…,z n }, M is the dynamic range based on the module set, and the symbol Indicates rounding down.

9. The device according to claim 8, characterized in that The binary number Z is determined according to the following equation: in, C M The calculation method is C M is chosen to be a power of 2, and 10. The device according to claim 8 or 9, characterized in that The module set is module set g 64 , the module g 64 The modulus of is used to generate a single 128-bit number when the control signal indicates a first value, wherein g 64 ={m1,m2,m3,…,m 16 },m1,m2,m3,…,m 16 are the 16 modules included in the module set; Among them, the module and The modulus is used to generate two 64-bit numbers when the control signal indicates the second value, wherein, or, Wherein, when the control signal indicates the third value, the module The modulus generates four 32-bit numbers, where 1≤i≤4, The grouping of moduli must meet the following requirements:

11. The device according to claim 10, characterized in that The RNS reverse converts the output is calculated by the one or more circuits as follows: in, IN i =In i ctrl ; in, and cm2=cm3=cm4=0 (when the control signal indicates the first value); cm3=cm4=0 (when the control signal indicates the second value); (when the control signal indicates the third value); in in, 12. The device according to claim 9 or 10, characterized in that The output is the result of matrix multiplication, and: In the case where the control signal indicates the first value, the size type of the numbers in the input matrix is ​​64 bits, and the size type of the numbers in the output matrix is ​​128 bits; In the case where the control signal indicates the second value, the size type of the numbers in the input matrix is ​​32 bits, and the size type of the numbers in the output matrix is ​​64 bits; or In the case where the control signal indicates the third value, the size type of the numbers in the input matrix is ​​16 bits, and the size type of the numbers in the output matrix is ​​32 bits.

13. A chip or a chip system, characterized in that: The chip or chip system comprises the device according to any one of claims 7 to 12.

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