Input / output voltage control for data communication interface

Abstract

Aspects relate to techniques for controlling signal voltage levels across wired data links for data communication between devices. A first device may advertise a plurality of supported signal voltage levels to peer devices connected over a wired data link. The devices may implement the same signal voltage level or different signal voltage levels. Peer devices may compare and select compatible signal voltage levels for data communication. A first device may provide a signal voltage indicator signal configurable to a plurality of voltage levels corresponding to a plurality of signal voltages. At least one of the plurality of voltage levels may indicate that the first device may operate the data link at the plurality of signal voltages. In some examples, the wired data link may be a peripheral component interconnect express (PCIe) link.

Description

[0001] This patent application claims priority to pending U.S. non-provisional application No. 17 / 949,968, filed on September 21, 2022, and assigned to the assignee of the present application, and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0002] The techniques discussed below relate generally to data communication interfaces, and more particularly, to input and output voltage control of data communication interfaces. Background Art

[0003] High-speed data communication interfaces are often used between circuits and components of mobile wireless devices and other complex systems. For example, some devices may include processing, communication, storage and / or display devices that interact with each other through one or more high-speed interfaces. Some of these devices, including synchronous dynamic random access memory (SDRAM), can provide or consume data and control information at the processor clock rate. Other devices, such as display controllers, can use variable data volumes at relatively low video refresh rates.

[0004] The Peripheral Component Interconnect Express (PCIe) standard is an example of a high-speed data communication interface that supports high-speed links capable of sending data at multiple gigabits per second. The PCIe interface also has multiple standby modes for use when the link is inactive. Compared to parallel buses, PCIe provides lower latency and higher data transfer rates. PCIe is specified for communication between a variety of different devices. Typically, a device (e.g., a processor or a hub) acts as a host that communicates with multiple devices (called endpoints) over a PCIe link. Peripheral devices or components can include graphics adapter cards, network interface cards (NICs), storage accelerator devices, mass storage devices, input / output interfaces, and other high-performance peripherals.

[0005] The data communication connection between any two devices (e.g., PCIe devices) is called a link. PCIe links are built around bidirectional, serial (1-bit), differential, point-to-point connections called lanes. With PCIe, data is transmitted over two signal pairs: two lines (wires, circuit board traces, etc.) for transmission and two lines for reception. The transmit and receive pairs are separate differential pairs, with a total of four data lines per lane. A link contains a collection of lanes, and each lane is capable of simultaneously sending and receiving data packets between the host and the endpoint.

[0006] In some aspects, a PCIe link can have one or more separate lanes. For example, a PCIe link can have 1, 2, 4, 8, 12, or 16 lanes, which can be labeled x1, x2, x4, x8, x12, and x16, respectively, where the number is actually the number of lanes. In one example, a PCIe x1 implementation has four lanes to connect a pair of lanes in each direction, while a PCIe x16 implementation has 16 times the number for 16 lanes, or 64 lanes. Summary of the invention

[0007] A summary of one or more implementations is presented below in order to provide a basic understanding of such implementations. This summary is not an exhaustive overview of all contemplated implementations and is not intended to identify key or important elements of all implementations, nor is it intended to delineate the scope of any or all implementations. Its sole purpose is to introduce some concepts of one or more implementations in a simplified form as a prelude to a more detailed description that is subsequently presented.

[0008] Various aspects relate to techniques for controlling input and output voltages of a data communication interface. In some aspects, the data communication interface may be a wired data link, such as a peripheral component interconnect express (PCIe) interface. In some aspects, techniques for controlling signal voltage levels across a wired data link (e.g., a PCIe link) are provided. For example, a PCIe endpoint may notify a host of one or more supported sideband voltage levels. The host may implement the same or different sideband voltage levels. The host may compare and select a compatible sideband voltage level. Various aspects of the present disclosure provide backward compatible techniques for sideband voltage negotiation. These techniques allow a PCIe adapter and a PCIe platform to negotiate to reduce the sideband voltage.

[0009] In one aspect of the present disclosure, a device for data communication includes an interface circuit configured to provide an interface with a wired data link. The interface circuit is also configured to provide a voltage indication signal, the voltage indication signal can be configured as one of a plurality of voltage levels corresponding to a plurality of signal voltages, at least one of the plurality of voltage levels being capable of indicating two or more of the plurality of signal voltages. The device also includes a controller configured to operate the wired data link using the signal voltage indicated by the voltage indication signal.

[0010] In one aspect of the present disclosure, a method of operating a device for data communication includes: providing a voltage indication signal, the voltage indication signal being configurable as one of a plurality of voltage levels corresponding to a plurality of signal voltages, at least one of the plurality of voltage levels being capable of indicating two or more of the plurality of signal voltages. The method also includes operating a wired data link using the signal voltage indicated by the voltage indication signal.

[0011] In one aspect of the present disclosure, a device for data communication includes an interface circuit configured to provide an interface with a wired data link, the interface circuit configured to receive a voltage indication signal, the voltage indication signal configurable as one of a plurality of voltage levels corresponding to a plurality of signal voltages, at least one of the plurality of voltage levels being capable of indicating two or more of the plurality of signal voltages. The device also includes a controller configured to operate the wired data link using the signal voltage indicated by the voltage indication signal.

[0012] In one aspect of the present disclosure, a method of operating an apparatus for data communication includes: receiving a voltage indication signal, the voltage indication signal being configurable as one of a plurality of voltage levels corresponding to a plurality of signal voltages, at least one of the plurality of voltage levels being capable of indicating two or more of the plurality of signal voltages. The method further includes operating a wired data link using the signal voltage indicated by the voltage indication signal.

[0013] In one aspect of the present disclosure, a device for data communication includes an interface circuit, the interface circuit is configured to provide an interface with a wired data link, the interface circuit is further configured to provide a voltage indication signal, the voltage indication signal is configured to indicate a plurality of signal voltage levels of the interface circuit, the voltage indication signal can be configured as one of the following: a power supply voltage, a ground voltage, and one or more voltages between the power supply voltage and the ground voltage. The device also includes a controller, the controller is configured to operate the wired data link using the signal voltage level indicated by the voltage indication signal.

[0014] In one aspect of the present disclosure, a device for data communication includes an interface circuit, the interface circuit is configured to provide an interface with a wired data link, the interface circuit is configured to receive a voltage indication signal, the voltage indication signal is configured to indicate a plurality of signal voltage levels, the voltage indication signal can be configured as a power supply voltage, a ground voltage, and one or more voltages between the power supply voltage and the ground voltage. The device also includes a controller, the controller is configured to operate the wired data link using the signal voltage level indicated by the voltage indication signal.

[0015] To achieve the above and related purposes, one or more implementations include features fully described below and particularly indicated in the claims. The following description and drawings set forth in detail certain illustrative features of one or more implementations. However, these aspects indicate only a few of the various ways in which the principles of the various implementations can be employed, and the described implementations are intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a block diagram illustrating exemplary data communication connections according to some aspects of the present disclosure.

[0017] Figure 2 is a block diagram of a computing architecture with a Peripheral Component Interconnect Express (PCIe) interface suitable for use with aspects of the present disclosure.

[0018] Figure 3 is a block diagram of a system including a host system and an endpoint device system according to aspects of the present disclosure.

[0019] Figure 4 is a schematic diagram illustrating techniques for negotiating and controlling sideband voltages according to some aspects of the present disclosure.

[0020] Figure 5 is a schematic diagram illustrating a circuit configured for indicating and controlling PCIe sideband voltage according to some aspects of the present disclosure.

[0021] Figure 6 is a flow chart illustrating a process for communicating sideband voltage information between a PCIe adapter and a PCIe platform according to some aspects of the present disclosure.

[0022] Figure 7 is a flow chart illustrating a process for powering up a PCIe adapter according to some aspects of the present disclosure.

[0023] Figure 8 is a block diagram of a PCIe link interface processing circuit according to aspects of the present disclosure.

[0024] Fig. 9 is a flow chart illustrating a first method for communication interface voltage control according to aspects of the present disclosure.

[0025] Fig.10 is a flow chart illustrating a method for determining a sideband voltage at a PCIe adapter in accordance with aspects of the present disclosure.

[0026] Fig.11 is a flow chart illustrating a second method for communication interface voltage control according to aspects of the present disclosure.

[0027] Fig.12 is a flow chart illustrating a method for determining a sideband voltage at a PCIe platform according to aspects of the present disclosure.

[0028] Fig.13 is a flow chart illustrating a third method for communication interface voltage control according to aspects of the present disclosure.

[0029] Fig.14 is a flow chart illustrating a fourth method for communication interface voltage control according to aspects of the present disclosure. DETAILED DESCRIPTION

[0030] The specific embodiments described below in conjunction with the accompanying drawings are intended to be descriptions of various configurations, and are not intended to represent the only configurations that can practice the concepts described herein. For the purpose of providing a thorough understanding of various concepts, the specific embodiments include specific details. However, these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring such concepts.

[0031] Figure 1 1 is a block diagram illustrating an exemplary data communication connection 100 according to some aspects of the present disclosure. The data communication connection 100 can provide a data link between a first device 102 (device A) and a second device 104 (device B). The data communication connection 100 can include a high-speed data path 106 and a low-speed data path 108. In some aspects, the high-speed data path 106 can be used for data payload, and the low-speed data path 108 can be used for various control and / or signaling functions of the data communication connection 100. In some aspects, the data communication connection 100 can be a peripheral component interconnect express (PCIe) connection. In this example, the low-speed data path 108 can carry a PCIe sideband signal. The first device 102 and the second device 104 can each be provided with a PCIe interface to utilize the data communication connection 100 to perform data communication between devices. In the present disclosure, a device equipped with a PCIe interface can be referred to as a PCIe device.

[0032] Peripheral Component Interconnect Express (PCIe) devices may communicate using sideband signals, which may include, for example, interrupts, power management signals, and reset commands. Current PCIe standards may support either 1.8V or 3.3V sideband voltage levels. Typically, PCIe devices negotiate to a 3.3V sideband voltage level, which may require the use of space-consuming level shifters between PCIe devices operating at different sideband voltages.

[0033] Some aspects of the present disclosure relate to technologies for managing signal voltage levels across wired data links (e.g., PCIe links). In some aspects, a PCIe adapter (e.g., a PCIe endpoint) can notify a PCIe platform (e.g., a host) of one or more supported sideband voltage levels. The PCIe platform can implement the same sideband voltage or different sideband levels. In some aspects, the PCIe platform can compare and select compatible sideband voltage levels. The present disclosure is not limited to the examples described herein. The present disclosure can be used for future implementations of PCIe standards (e.g., GEN6 and higher versions). In addition, although the present disclosure is discussed in conjunction with the PCIe example, the basic principles of the disclosed system and method can be implemented in other types of wired data links (e.g., other physical serial interconnections) between a host and a client device.

[0034] Figure 2 2 is a block diagram of an exemplary computing architecture using a PCIe interface. The computing architecture 200 operates using multiple high-speed PCIe interface serial links. The PCIe interface can be characterized as an apparatus including a point-to-point topology, in which a separate serial link connects each device to a host, which can be referred to as a root complex 204. In the computing architecture 200, the root complex 204 couples the processor 202 to a memory device (e.g., a memory subsystem 208) and a PCIe switch circuit 206. In some instances, the PCIe switch circuit 206 includes a cascaded switch device. One or more PCIe endpoint devices 210 can be directly coupled to the root complex 204, while other PCIe endpoint devices 212-1, 212-2, ... 212-N can be coupled to the root complex 204 through the PCIe switch circuit 206. The root complex 204 can be coupled to the processor 202 using a proprietary local bus interface or a standard defined local bus interface. The root complex 204 may control configuration and data transactions over a PCIe interface and may generate transaction requests for the processor 202. In some examples, the root complex 204 is implemented in the same integrated circuit (IC) device that includes the processor 202. The root complex 204 may support multiple PCIe ports.

[0035] The root complex 204 can control communication between the processor 202 and a memory subsystem 208, which is one example of an endpoint. The root complex 204 also controls communication between the processor 202 and other PCIe endpoint devices 210, 212-1, 212-2, ... 212-N. The PCIe interface can support full-duplex communication between any two endpoints, with no inherent restrictions on concurrent access across multiple endpoints. Data packets can carry information over any PCIe link. In a multi-lane PCIe link, packet data can be striped across multiple lanes. The number of lanes in a multi-lane link can be negotiated during device initialization and can be different for different endpoints.

[0036] When one or both traffic directions of the lanes of a PCIe link are underutilized by low bandwidth applications that can be adequately served by fewer lanes, then the root complex 204 and endpoints may operate the link using more or fewer transmit and receive lines in one or both directions.

[0037] In some aspects, the computing architecture 200 can be implemented based on the PCI Express M.2 specification. The M.2 form factor can be used for mobile adapters. M.2 enables expansion, contraction, and higher integration of functionality into a single form factor module solution. For example, the above description of Figure 2 Any of the described PCIe endpoints may be implemented as an M.2 adapter, and the root complex 204 may be implemented as an M.2 platform.

[0038] Figure 3 305 is a block diagram of an exemplary PCIe system in which aspects of the present disclosure may be implemented. System 305 includes a host system 310 and an endpoint device system 350. For example, the host system 310 may be an M.2 platform and the endpoint device system 350 may be an M.2. adapter. The host system 310 may be integrated on a first chip (e.g., a system on a chip or SoC) and the endpoint device system 350 may be integrated on a second chip. Alternatively, the host system and / or the endpoint device system may be integrated in a first and second package, such as a SiP, a first system board having multiple chips and a second system board, or in other hardware or any combination. In this example, the host system 310 and the endpoint device system 350 are coupled via a PCIe link 385.

[0039] The host system 310 includes one or more host clients 314. Each of the one or more host clients 314 can be implemented on a processor executing software that performs the functions of the host client 314 discussed herein. For examples of more than one host client, the host clients can be implemented on the same processor or on different processors. The host system 310 also includes a host controller 312 that can perform root complex functions. The host controller 312 can be implemented on a processor executing software that performs the functions of the host controller 312 discussed herein.

[0040] The host system 310 includes a PCIe interface circuit 316, a system bus interface 315, and a host system memory 340. The system bus interface 315 can interface one or more host clients 314 with the host controller 312, and interface each of the one or more host clients 314 and the host controller 312 with the PCIe interface circuit 316 and the host system memory 340. The PCIe interface circuit 316 provides an interface to the PCIe link 385 to the host system 310. In this regard, the PCIe interface circuit 316 is configured to send data (e.g., from the host client 314) to the endpoint device system 350 via the PCIe link 385, and to receive data from the endpoint device system 350 via the PCIe link 385. The PCIe interface circuit 316 includes a PCIe controller 318, a physical interface 320 for a PCI Express (PIPE) interface, a physical (PHY) transmit (TX) block 322, a clock generator 324, and a PHY receive (RX) block 326. PIPE interface 320 provides a parallel interface between PCIe controller 318 and PHY TX block 322 and PHY RX block 326. PCIe controller 318 (which may be implemented in hardware) may be configured to perform transaction layer, data link layer, and control flow functions specified in the PCIe specification, as discussed further below.

[0041] The host system 310 also includes an oscillator (e.g., a crystal oscillator or "XO") 330 configured to generate a reference clock signal 332. In one example, the reference clock signal 332 may have a frequency of 19.2 MHz, but is not limited to such a frequency. The reference clock signal 332 is input to a clock generator 324, which generates a plurality of clock signals based on the reference clock signal 322. In this regard, the clock generator 324 may include a phase-locked loop (PLL) or a plurality of PLLs, each of which generates a respective one of the plurality of clock signals by multiplying the frequency of the reference clock signal 332 upward.

[0042] The endpoint device system 350 includes one or more device clients 354. Each device client 354 can be implemented on a processor executing software that performs the functions of the device client 354 discussed herein. For examples of more than one device client 354, the device clients 354 can be implemented on the same processor or on different processors. The endpoint device system 350 also includes a device controller 352. The device controller 352 can be configured to receive bandwidth requests from one or more device clients and determine whether to change the number of transmit lines or change the number of receive lines based on the bandwidth requests. The device controller 352 can be implemented on a processor executing software that performs the functions of the device controller.

[0043] The endpoint device system 350 includes a PCIe interface circuit 360, a system bus interface 356, and an endpoint system memory 374. The system bus interface 356 may interface one or more device clients 354 with a device controller 352, and interface each of the one or more device clients 354 and the device controller 352 with the PCIe interface circuit 360 and the endpoint system memory 374. The PCIe interface circuit 360 provides an interface to a PCIe link 385 to the endpoint device system 350. In this regard, the PCIe interface circuit 360 is configured to send data (e.g., from the device client 354) to a host system 310 (also referred to as a host device) via the PCIe link 385, and to receive data from the host system 310 via the PCIe link 385. The PCIe interface circuit 360 includes a PCIe controller 362, a PIPE interface 364, a PHY TX block 366, a PHY RX block 370, and a clock generator 368. PIPE interface 364 provides a parallel interface between PCIe controller 362 and PHY TX block 366 and PHY RX block 370. PCIe controller 362 (which may be implemented in hardware) may be configured to perform transaction layer, data link layer, and control flow functions.

[0044] Host system memory 340 and endpoint system memory 374 at the endpoint may be configured to contain registers for the status of each transmit and receive lane of PCIe link 385. The transmit lanes may be configured as differential transmit lane pairs and the receive lanes may be configured as differential receive lane pairs.

[0045] The endpoint device system 350 also includes an oscillator (eg, a crystal oscillator) 372 configured to generate a stable reference clock signal 373 for the endpoint system memory 374 and the clock generator 368. Figure 3In the example of FIG. 3 , the clock generator 324 at the host system 310 is configured to generate a stable EP reference clock signal, which is forwarded by the PHY RX block 326 to the endpoint device system 350 via the differential clock line 388. At the endpoint device system 350, the PHY RX block 370 receives the EP reference clock signal on the differential clock line 388 and forwards the EP reference clock signal to the clock generator 368. The EP reference clock signal may have a frequency of 100 MHz, but is not limited to such a frequency. The clock generator 368 is configured to generate a plurality of clock signals based on the EP reference clock signal from the differential clock line 388, as further discussed below. In this regard, the clock generator 368 may include a plurality of PLLs, each of which generates a respective one of the plurality of clock signals by multiplying up the frequency of the EP reference clock signal.

[0046] The system 305 also includes a power management integrated circuit (PMIC) 390, which is coupled to a power source 392, such as a mains voltage, a battery, or other power source. The PMIC 390 is configured to convert the voltage of the power source 392 to a plurality of power supply voltages (e.g., using a switching regulator, a linear regulator, or any combination thereof). In this example, the PMIC 390 generates a voltage 342 for the oscillator 330, a voltage 344 for the PCIe controller 318, and a voltage 346 for the PHY TX block 322, the PHY RX block 326, and the clock generator 324. The voltages 342, 344, and 346 may be programmable, where the PMIC 390 is configured to set the voltage levels (angles) of the voltages 342, 344, and 346 according to instructions (e.g., from the host controller 312).

[0047] The PMIC 390 also generates a voltage 380 for the oscillator 372, a voltage 378 for the PCIe controller 362, and a voltage 376 for the PHY TX block 366, the PHY RX block 370, and the clock generator 368. The voltages 380, 378, and 376 may be programmable, wherein the PMIC 390 is configured to set the voltage levels (angles) of the voltages 380, 378, and 376 according to instructions (e.g., from the device controller 352). The PMIC 390 may be implemented on one or more chips. Although in Figure 3 390 is shown as one PMIC, but it should be understood that PMIC 390 may be implemented by two or more PMICs. For example, PMIC 390 may include a first PMIC for generating voltages 342, 344, and 346 and a second PMIC for generating voltages 380, 378, and 376. In this example, the first and second PMICs may both be coupled to the same power supply 392 or to different power supplies.

[0048] In operation, PCIe interface circuitry 316 on host system 310 may send data from one or more host clients 314 to endpoint device system 350 via PCIe link 385. When the host controller negotiates bandwidth for the link, data from one or more host clients 314 may be directed to PCIe interface circuitry 316 according to a PCIe mapping established during initial configuration (sometimes referred to as link initialization) by host controller 312. At PCIe interface circuitry 316, PCIe controller 318 may perform transaction layer and data link layer functions on the data, e.g., packetizing the data, generating error correction codes to be sent with the data, etc.

[0049] The PCIe controller 318 outputs the processed data to the PHY TX block 322 via the PIPE interface 320. The processed data includes data from one or more host clients 314 and overhead data (e.g., packet headers, error correction codes, etc.). In one example, the clock generator 324 can generate a clock 334 for an appropriate data rate or transfer rate based on the reference clock signal 332, and input the clock 334 to the PCIe controller 318 to time the operation of the PCIe controller 318. In this example, the PIPE interface 320 can include a 22-bit parallel bus that transmits 22 bits of data in parallel to the PHY TX block during each cycle of the clock 334. At 250 MHz, this translates to a transfer rate of approximately 8 GT / s.

[0050] The PHY TX block 322 serializes the parallel data from the PCIe controller 318 and drives the PCIe link 385 with the serialized data. In this regard, the PHY TX block 322 may include one or more serializers and one or more drivers. The clock generator 324 may generate a high frequency clock for one or more serializers based on the reference clock signal 332.

[0051] At the endpoint device system 350, the PHY RX block 370 receives the serialized data via the PCIe link 385 and deserializes the received data into parallel data. In this regard, the PHY RX block 370 may include one or more receivers and one or more deserializers. The clock generator 368 may generate a high frequency clock for one or more deserializers based on the EP reference clock signal. The PHY RX block 370 transmits the deserialized data to the PCIe controller 362 via the PIPE interface 364. The PCIe controller 362 may recover the data from the one or more host clients 314 from the deserialized data and forward the recovered data to the one or more device clients 354.

[0052] On the endpoint device system 350, the PCIe interface circuit 360 can send data from one or more device clients 354 to the host system memory 340 via the PCIe link 385. At this point, the PCIe controller 362 at the PCIe interface circuit 360 can perform transaction layer and data link layer functions on the data, such as packetizing the data, generating error correction codes to be sent with the data, etc. The PCIe controller 362 outputs the processed data to the PHYTX block 366 via the PIPE interface 364. The processed data includes data from the one or more device clients 354 and overhead data (e.g., packet headers, error correction codes, etc.). In one example, the clock generator 368 can generate a clock based on the EP reference clock through the differential clock line 388 and input the clock to the PCIe controller 362 to control the timing operation of the PCIe controller 362.

[0053] The PHY TX block 366 serializes the parallel data from the PCIe controller 362 and drives the PCIe link 385 with the serialized data. In this regard, the PHY TX block 366 may include one or more serializers and one or more drivers. The clock generator 368 may generate a high frequency clock for one or more serializers based on the EP reference clock signal.

[0054] At the host system 310, the PHY RX block 326 receives the serialized data via the PCIe link 385 and deserializes the received data into parallel data. In this regard, the PHY RX block 326 may include one or more receivers and one or more deserializers. The clock generator 324 may generate a high frequency clock for one or more deserializers based on the reference clock signal 332. The PHY RX block 326 transmits the deserialized data to the PCIe controller 318 via the PIPE interface 320. The PCIe controller 318 may recover data from the one or more device clients 354 from the deserialized data and forward the recovered data to the one or more host clients 314.

[0055] Sideband Voltage Negotiation

[0056] Current PCIe standards (e.g., the M.2 standard) allow PCIe adapters and PCIe platforms to negotiate sideband voltage levels to either 1.8V or 3.3V. In some applications, if there is a sideband voltage level mismatch between a PCIe adapter and a PCIe platform, a voltage level converter (e.g., a voltage level shifter) may be used. For backward compatibility, current PCIe adapter implementations typically negotiate to a 3.3V sideband voltage level (worst case), which may require the use of space-consuming level shifters on the adapter and / or platform. Although PCIe adapters can support lower sideband voltages (e.g., 1.8V), there is currently no standardized way for PCIe adapters to communicate their sideband voltage capabilities to PCIe platforms. Various aspects of the present disclosure provide backward compatible techniques for sideband voltage negotiation that enable PCIe adapters and PCIe platforms to negotiate to a reduced sideband voltage. The technique may be implemented using voltage control pins that enable sideband communication without the need for voltage level shifters.

[0057] Figure 4 404 and 406. The PCIe adapter 402 and the PCIe platform 404 may be connected via a PCIe interface 406, which is similar to the PCIe interface 406 described above. Figure 2 and Figure 3 3. The PCIe interface described above. In some aspects, the PCIe adapter 402 may be implemented by the endpoint device system 350, and the PCIe platform may be implemented by the host system 310. The PCIe interface 406 may include a high-speed link 408 and a sideband link 410. The sideband link 410 may include various sideband signals, such as PCIe reset (PERST#), PCIe clock request (CLKREQ#), PCIe wakeup (PEWAKE#), power loss notification (PLN#), power loss acknowledgement (PLA#), etc.

[0058] In some aspects, the PCIe adapter 402 may be configured to support one or more sideband voltage levels (e.g., voltage levels 0.8V, 1.2V, 1.8V, and 3.3V). The PCIe adapter 402 may advertise or indicate one or more supported sideband voltage levels to the PCIe platform 404 before the PCIe adapter 402 is fully powered on (e.g., received 3.3V and input offset voltage (VIO)). For example, in order to fully power on the PCIe adapter 402, the PCIe platform 404 provides a 3.3V VIO voltage to the PCIe adapter in a predetermined order. In some aspects, the PCIe platform 404 may send an FCPO (full card power on) signal to indicate that the PCIe adapter 402 is powered on. The PCIe adapter 402 and the PCIe platform 404 may implement the same or different sideband voltage levels. Before fully powering up the PCIe adapter 402 or the high-speed link 408, the PCIe platform 404 can compare and select a compatible sideband voltage level based on the supported sideband voltages indicated by the PCIe adapter 402. If the PCIe platform 404 supports a compatible sideband voltage, the PCIe platform 404 can continue the process to fully enable the PCIe interface and power up the PCIe interface. Otherwise, if no compatible sideband voltage level is available, the PCIe platform 404 does not power up the PCIe adapter 402.

[0059] To fully power on the PCIe adapter 402, the PCIe platform 404 configures its sideband IO pads 412 to use a compatible sideband voltage level and applies 3.3V power to the PCIe adapter 402. The PCIe platform 404 can then provide a VIO voltage that matches the selected sideband voltage. The PCIe adapter 402 can use the VIO voltage to configure its sideband IO pads 414 so that it matches the sideband IO pad voltage of the PCIe platform 404. The PCIe platform 404 can then provide an "on" signal (e.g., FCPO) to power on the PCIe adapter 402, thereby locking the IO pad voltage.

[0060] In some aspects, the PCIe adapter 402 may use a VIO_CFG pin 415 (e.g., an input-output voltage configuration pin) to advertise or indicate the sideband voltage it supports or is compatible with. The PCIe platform 404 may detect or read the voltage at the VIO_CFG pin 415 to determine the sideband voltage level advertised by the PCIe adapter 402. In one aspect, the PCIe platform 404 may be provided with a VIO voltage detection circuit 420 that may detect the voltage level at the VIO CFG pin 415. In some aspects, the VIO voltage detection circuit 420 may be configured to convert the voltage (analog signal) detected at the VIO_CFG pin 415 into corresponding digital data based on a predetermined rule or mapping. In one example, the VIO voltage detection circuit 420 may include an analog-to-digital (A / D) converter that may convert the VIO_CFG voltage (sideband voltage indication signal) into a corresponding digital value.

[0061] Table 1 shows some non-limiting examples of VIO_CFG voltages and corresponding sideband voltage levels according to some aspects. In some aspects, the VIO_CFG voltage design can be backward compatible with the current PCIe M.2 specification. For example, setting the VIO_CFG voltage to 0V to signal 3.3V sideband support and setting it to 1.8V to signal 1.8V sideband support can be consistent with the current M.2 specification. In one example, the VIO_CFG voltage can have a voltage indicating a single compatible sideband voltage (e.g., 0V, 0.8V, 1.2V, or 1.8V). At least one VIO_CFG voltage can indicate two or more compatible sideband voltages. In one example, the VIO_CFG voltage can have a voltage indicating two or more compatible sideband voltages (e.g., 0.2V, 0.4V, or 0.6V). For example, the voltage can be an intermediate voltage between a power supply voltage (e.g., 1.8V) and ground. Since a single VIO_CFG voltage can signal multiple compatible sideband voltages (2 or more), it enables the PCIe adapter and PCIe platform to negotiate to lower the sideband voltage and avoid using a voltage level converter or defaulting to a higher voltage. In other aspects, the VIO_CFG voltage and the corresponding sideband voltage level can have other designs and are not limited to the designs shown in Table 1.

[0062] Table 1

[0063] Compatible sideband voltage VIO_CFG voltage 3.3V 0V or ground 3.3V and 1.8V 0.2V 1.8V 1.8V 1.8V vs 1.2V 0.4V 1.2V 1.2V 1.2V and 0.8V 0.6V 0.8V 0.8V reserve 1.5V or power supply voltage

[0064] In one example, when the PCIe adapter 402 advertises support for sideband voltages of 1.8V and 1.2V (e.g., the VIO_CFG voltage is set to 0.4V), the PCIe platform 404 does not power on the PCIe adapter 402 when the PCIe platform only supports a 3.3V sideband voltage. In one example, when the PCIe adapter 402 advertises support for sideband voltages of 1.8V and 1.2V (e.g., the VIO_CFG voltage is set to 0.4V) and the PCIe platform 404 can support 1.8V, the PCIe platform powers on the PCIe adapter 402 and sets the sideband voltage to 1.8V. In one example, when the PCIe adapter 402 advertises support for sideband voltages of 1.8 V and 1.2 V (e.g., the VIO_CFG voltage is set to 0.4 V) and the PCIe platform 404 can support 1.2 V, the PCIe platform 404 powers on the PCIe adapter 402 and sets the sideband voltage to 1.2 V. In one example, when the PCIe adapter 402 advertises support for sideband voltages of 0.8 V and 1.2 V (e.g., the VIO_CFG voltage is set to 0.6 V), the PCIe platform 404 does not power on the PCIe adapter 402 when the PCIe platform only supports a 1.8 V sideband voltage.

[0065] Figure 5 is a schematic diagram of a voltage indication circuit 500 configured to transmit and control PCIe sideband voltage according to some aspects of the present disclosure. In some aspects, the PCIe adapter 402 and the PCIe platform 504 can be connected to each other via a PCIe connector 502 on the PCIe platform. The PCIe connector 502 can be implemented in various form factors, such as an M.2 connector form factor. In one example, the PCIe connector 502 can be implemented by an edge connector having multiple pins (or pads) on the PCIe adapter and a mating connector on the PCIe platform. The PCIe platform can provide a power supply voltage, such as a DC voltage 505 (e.g., 1.8V), to the VIO_CFG pin via a first resistor (R1) 506, and the PCIe adapter can provide a second resistor (R2) 508 between the VIO_CFG pin and electrical ground (ground voltage). In this example, the first resistor 506 and the second resistor 508 form a voltage divider that outputs a VIO_CFG voltage based on the relative values ​​of the first resistor 506 and the second resistor 508. For example, the voltage of the VIO_CFG pin may be determined to be 1.8VX(R2 / (R1+R2)).

[0066] Table 2 below shows some exemplary values ​​of the first and second resistors (R1 and R2) for indicating various VIO_CFG voltages. Each of the VIO_CFG voltages can indicate one or more sideband voltages supported by the PCIe adapter. The resistor values ​​are only used to illustrate the concept and are not limiting. Other suitable resistor values ​​can be used in other examples and designs.

[0067] Table 2

[0068]

[0069] In one aspect, the PCIe platform may detect the VIO_CFG voltage level using an A / D converter 510. The A / D converter 510 converts the VIO_CFG voltage (analog signal) into a digital value or data representing the detected VIO_CFG voltage in the digital domain. The PCIe platform may have a voltage control circuit 512 that may perform various voltage control functions, including configuring the sideband voltage based on data received from the A / D converter 510. In one aspect, the voltage control circuit 512 may decode data from the A / D converter 510 to determine the sideband voltage advertised and supported by the PCIe adapter. In some aspects, the voltage control circuit 512 may include the A / D converter 510 as a component or provide the functionality of the A / D converter 510. The voltage control circuit 512 may control the 3.3V power supply 514 and the VIO power supply 516 based on the detected VIO_CFG voltage. In one example, the 3.3V power supply 514 may be a voltage regulator that provides 3.3V. In one example, the VIO power supply 516 can be a voltage regulator that provides a VIO voltage (e.g., 3.3V, 1.8V, 1.2V, or 0.8V) to the PCIe adapter. In one example, the voltage control circuit 512 can output a FCPO signal 518 to the PCIe adapter to indicate the 3.3V and VIO provided by the PCIe platform, and the PCIe adapter can set its sideband voltage based on the VIO voltage. Figure 5 The concept of voltage indication described in is not limited to PCIe sideband voltage control and can be applied to other data link examples.

[0070] Figure 6 4 is a flow chart illustrating a process 600 for communicating sideband voltage information between a PCIe adapter 402 and a PCIe platform 404, in accordance with some aspects of the present disclosure. However, in other examples, other PCIe devices may be used to perform the process 600.

[0071] At 602, the PCIe adapter may indicate or advertise one or more supported sideband voltage levels (e.g., 0.8V, 1.2V, 1.8V, and / or 3.3V) using a predetermined voltage (analog signal) at the VIO_CFG pin. In one aspect, the PCIe adapter may set the voltage at the VIO_CFG pin using a pull-down resistor (e.g., resistor 508) that forms a voltage divider circuit with a pull-up resistor (e.g., resistor 506) provided at the PCIe platform, as described above with respect to Figure 5 In one aspect, the VIO_CFG pin can be set to one of the VIO_CFG voltages in Table 1 and Table 2 to indicate a corresponding sideband voltage supported by the PCIe adapter.

[0072] At 604, the PCIe platform may detect the voltage at the VIO_CFG pin using, for example, the VIO voltage detection circuit 420. In some aspects, the VIO voltage detection circuit 420 may include an A / D converter 510 and / or a voltage control circuit 512 that may detect the voltage (analog signal) at the VIO_CFG pin and convert it to corresponding digital data representing the detected VIO_CFG voltage in the digital domain.

[0073] At 606, the PCIe platform may decode the VIO_CFG voltage to determine the sideband voltage supported by the PCIe adapter. In one aspect, the PCIe platform may use the voltage control circuit 512 to decode digital data (e.g., from the A / D converter 510) representing the voltage detected at the VIO_CFG pin. For example, the decoded digital data may correspond to one of the VIO_CFG voltages in Table 1 / 2 described above. The PCIe platform may then determine the sideband voltage supported by the PCIe adapter based on the decoded VIO_CFG voltage.

[0074] At 608, the PCIe platform may determine whether the PCIe platform can provide or operate with a sideband voltage that matches the sideband voltage supported by the PCIe adapter. For example, the voltage control circuit 512 may determine whether the PCIe platform can provide a sideband voltage that matches or is compatible with the sideband voltage indicated by the PCIe adapter at the VIO_CFG pin.

[0075] At 610 , if the PCIe platform cannot provide a compatible sideband voltage supported by the PCIe adapter, the PCIe platform will not perform a power-on procedure for the PCIe adapter.

[0076] At 612, if the PCIe platform determines that it can provide a sideband voltage that is compatible with or supported by the PCIe adapter, the PCIe platform sets the VIO voltage to the sideband voltage indicated by the PCIe adapter. For example, the PCIe platform can use the voltage control circuit 512 to set the VIO power supply 516 to the desired VIO voltage (e.g., 0.8V, 1.2V, 1.8V, or 3.3V). In some aspects, if the PCIe adapter indicates two or more sideband voltages that are supported by the PCIe platform, the PCIe platform can select one of the sideband voltages based on a predetermined rule (e.g., giving priority to a lower voltage for power conservation). During the power-on process, the PCIe platform provides 3.3V and VIO to the PCIe adapter in a predetermined order.

[0077] At 614, the PCIe platform may provide 3.3V and VIO in a predetermined order to power up the PCIe adapter. For example, the PCIe platform may use the voltage control circuit 512 to control the 3.3V power supply to provide 3.3V, and control the VIO power supply 516 to provide the VIO voltage. The PCIe platform may further provide an FCPO signal to the PCIe platform to indicate that the PCIe adapter is powered on and the VIO voltage is set.

[0078] Figure 7 700 is a flow chart illustrating a process 700 for powering up a PCIe adapter according to some aspects. For example, the process 700 can be performed at the PCIe adapter 402 after the PCIe platform 404 determines the sideband voltage supported by the PCIe adapter 402, as described above in Figure 6 At 702, the PCIe adapter 402 may receive 3.3V and VIO voltages from the PCIe platform 404. The PCIe adapter 402 may receive the 3.3V and VIO voltages in a predetermined sequence, for example, according to a sequence defined in the PCI Express M.2 specification. In one example, the PCIe platform may provide 3.3V to the PCIe adapter before providing the VIO voltage.

[0079] At 704, the PCIe adapter can configure its sideband interface 414 to a sideband voltage based on the VIO voltage provided by the PCIe platform. For example, the PCIe adapter can set the operating voltage of its sideband input / output (IO) pad 414 to be the same as or compatible with the VIO voltage (e.g., 0.8V, 1.2V, 1.8V, or 3.3V). At 706, the PCIe adapter can receive a power-on signal (e.g., FCPO signal) from the PCIe platform. The power-on signal indicates that the PCIe adapter can be in a fully powered-on state. In one aspect, the PCIe platform can set the power-on signal to a predetermined voltage level (e.g., 3.3V), which indicates that the PCIe adapter is fully powered (i.e., 3.3V and VIO voltage are connected). In this case, the PCIe adapter can fix its sideband I / O pad voltage to match the VIO voltage received from the PCIe platform.

[0080] Figure 8 800 is a block diagram of a link interface processing circuit according to some aspects. The link interface processing circuit 800 is a device that can be part of a host (e.g., a PCIe platform 404) or an endpoint (e.g., a PCIe adapter 402). The processing circuit can be coupled to a communication link 802 having multiple duplex channels, such as a PCIe link. The link 802 can be coupled to another PCIe device, such as a PCIe endpoint or a PCIe host at the opposite end. Data and control information transmitted as packets through the link 802 can be coupled to a link interface (e.g., a PCIe interface circuit 820), which can provide a PHY level interface to the link and convert baseband signals into packets (e.g., data packets and / or control packets). The data and control packets can be sent by the link interface circuit 820 to other components of the processing circuit 800 through the bus 810. The link interface circuit 820 can have a direct connection to the interface configuration circuit 818, which can provide configuration and control settings (e.g., sideband voltage settings) for the operation of the link interface circuit 820.

[0081] In some aspects, the link interface circuit 820 may include circuitry for communicating and controlling PCIe sideband voltages, such as Figure 5 In one example, when the link interface circuit 820 is included in a PCIe adapter (e.g., an endpoint), the link interface circuit 820 may include a PCIe adapter-side circuit (e.g., resistor 508). In one example, when the link interface circuit 820 is included in a PCIe platform (e.g., a host), the link interface circuit 820 may include a PCIe platform-side circuit (e.g., power supply 505 and resistor 506).

[0082] The processing circuit 800 may also include a timer circuit 812. The timer circuit 812 may be coupled to the bus 810 and provide timer functions, for example, to control various timings for delays, inactivity, confirmations, and / or PCIe power states. In one aspect, the timer circuit 812 may access a computer-readable storage medium 808 to access code and data for managing the timer 832. In some aspects, the storage medium is a non-transitory computer-readable medium. In some aspects, the timer circuit 812 may also access registers and data stored in the storage medium 808 or the memory 809.

[0083] In addition, within the processing circuit 800, a power management circuit 814 can manage the power and voltage used by various components of the processing circuit and the PCIe link. The power management circuit 814 can access code 840 for managing PCIe power and transmit line status registers 842 and receive line status registers 844 through the bus 810. These registers can be used to store status for each transmit line and each receive line, or for the transmit side of the link and the receive side of the link. The status can be determined using code 832 for managing timers, code 840 for managing PCIe power, or in another manner.

[0084] The interface configuration circuit 818 is coupled to the bus with the power management circuit 814 and the timer circuit 812 so that each of these blocks can communicate with each other, with the storage medium 808, and with the processor 806. The processor 806 can control the operation of other circuits and start the instance of each circuit according to the operation of the processing circuit 800. The interface configuration circuit 818 can also access the code 860 for configuring the PCIe interface. When executing the code, the interface configuration circuit 818 can read and write values ​​from various configuration registers. For example, these registers include a transmit control, state and capability register 862 and a receive control, state, and capability register 864. These registers can be accessed and read at the beginning of link initialization, and then updated with the results of the initialization. The registers can also be modified in response to power management and bandwidth negotiation or changing the state of one or more transmit lines or receive lines of the link 802. In some aspects, the interface configuration circuit 818 can read and write values ​​from one or more sideband VIO registers for configuring and controlling sideband communication. For example, interface configuration circuitry 818 and / or PCIe interface circuitry 820 may set the VIO voltage based on a VIO voltage sent to an endpoint or received from a host.

[0085] Processing circuit 800 may initialize link 802, manage power, and change the number of active lines of link 802. In operation, bandwidth requests may also be received from a host or an endpoint. The bandwidth request may result in bandwidth negotiation and then change the values ​​set for control, status, and capability registers.

[0086] like Figure 3 As shown in FIG, power management circuit 814 may change the voltage level of one or more of voltages 376, 378, and 380 by instructing PMIC 390 to set the voltage level of one or more of the voltages provided by PMIC 390. Thus, power according to the negotiated bandwidth may be managed by providing one or more voltages to the interface circuit of the link and by setting the level of the one or more voltages.

[0087] Fig. 9 1 is a flow chart of a method 900 for communication interface voltage control according to aspects of the present disclosure. In some aspects, the method 900 can be performed by the PCIe adapter 402 to implement sideband voltage level indication and configuration, for example, as described above with respect to Figure 4-7 The method 900 is not limited to PCIe applications. In other aspects, the method 900 can be used by an apparatus to indicate and control the signal voltage of a wired data link other than PCIe.

[0088] At 902, method 900 includes a process of providing a voltage indication signal, which can be configured as one of a plurality of voltage levels corresponding to a plurality of signal voltages. At least one of the plurality of voltage levels can indicate two or more of the plurality of signal voltages. For example, the voltage indication signal can be a sideband voltage indication signal (analog signal) that can be configured as a plurality of voltage levels corresponding to a plurality of sideband voltages. At least one of the plurality of voltage levels can indicate two or more of the plurality of signal voltages (e.g., sideband voltages 0.8V, 1.2V, 1.8V, and 3.3V for a PCIe link). In one aspect, the plurality of voltage levels can be the VIO_CFG voltages shown in Tables 1 and 2 described above. For example, voltages 0.2V, 0.4V, and 0.6V can each indicate two sideband voltages that can be compatible with a PCIe adapter 402. In one aspect, the PCIe interface circuit 820 can be a unit for providing a voltage indication signal (e.g., VIO_CFG). For example, the PCIe interface circuit 820 may include a resistor 508 , which may form a voltage divider with a resistor of the PCIe platform (eg, resistor 506 ) to provide the VIO_CFG voltage.

[0089] At 904, the method 900 includes a process for operating a wired data link (e.g., a PCIe link) using a signal voltage indicated by a voltage indication signal. In one example, the PCIe interface circuit 820 may provide a unit for operating a wired data link (e.g., a PCIe link) using a signal voltage indicated by a signal voltage indication (e.g., a sideband voltage indication, VIO_CFG). In one aspect, the PCIe interface circuit 820 may receive 3.3V, VIO, and FCPO signals from a PCIe platform, and the PCIe interface may set its sideband voltage based on the VIO voltage.

[0090] Fig.10 A flow chart of a method 1000 for setting a sideband voltage at a PCIe adapter according to aspects of the present disclosure is shown. In certain aspects, the method 1000 may be performed by the PCIe adapter 402 at block 904 of the method 900 to control a sideband (signal) voltage level of a sideband interface.

[0091] At 1002, method 1000 includes a process of receiving power and VIO from a PCIe platform. For example, a PCIe adapter may receive 3.3V and VIO in a predetermined order. At 1004, method 1000 includes a process of determining a voltage level of VIO. For example, the voltage level of VIO may be a sideband voltage (e.g., 0.8V, 1.2V, 1.8V, or 3.3V) advertised by a PCIe adapter. At 1006, method 1000 includes a process of setting the sideband voltage equal to the voltage of VIO. Thus, the PCIe platform may set the voltage of VIO to a sideband voltage supported by the PCIe adapter.

[0092] Fig.11 1 is a flow chart of a method 1100 for communication interface voltage control according to aspects of the present disclosure. In some aspects, the method 1100 can be performed by the PCIe platform 404 to implement sideband voltage level indication and configuration, for example, as described above with respect to Figure 4-7 The method 1100 is not limited to PCIe applications. In other aspects, the method 1100 can be used by an apparatus to indicate and control the signal voltage of a wired data link other than PCIe.

[0093] At 1102, method 1100 includes receiving a voltage indication signal (e.g., a PCIe sideband voltage indication signal from a PCIe adapter), the voltage indication signal being configurable as one of a plurality of voltage levels corresponding to a plurality of signal voltages. At least one of the plurality of voltage levels is capable of indicating two or more of the plurality of signal voltages (e.g., sideband voltages 0.8V, 1.2V, 1.8V, and 3.3V). In one aspect, the plurality of voltage levels may be the VIO_CFG voltages shown in Tables 1 and 2 described above. For example, voltages 0.2V, 0.4V, and 0.6V may each indicate two sideband voltages compatible with PCIe adapter 402. In one aspect, PCIe interface circuit 820 may be a unit for receiving a voltage indication signal (e.g., VIO_CFG). For example, PCIe interface circuit 820 may include power supply 505 and resistor 506, which may form a voltage divider with a resistor (e.g., resistor 508) of the PCIe adapter to provide VIO_CFG.

[0094] At 1104, method 1100 includes a process of operating a wired data link (e.g., a PCIe link having a PCIe adapter) using a signal voltage indicated by a voltage indication signal (e.g., VIO_CFG). In one example, PCIe interface circuit 820 may provide a unit for operating a PCIe link using a sideband voltage indicated by a sideband voltage indication. PCIe interface circuit 820 may provide 3.3V, VIO, and FCPO signals to a PCIe adapter, and the PCIe interface may set its sideband voltage based on the VIO voltage.

[0095] Fig.12 A flow chart of a method 1200 for determining a sideband voltage at a PCIe platform in accordance with aspects of the present disclosure is shown. In certain aspects, the method 1200 may be performed by the PCIe platform 404 at block 1104 of the method 1100 to control a sideband voltage level of a sideband interface.

[0096] At 1202, method 1200 includes a process of determining a voltage level (e.g., a sideband voltage indication) of VIO_CFG. The VIO_CFG signal (e.g., an analog signal) may indicate a sideband voltage supported by a PCIe adapter. In one aspect, the A / D converter 510 may provide a unit for determining a voltage level of VIO_CFG. At 1204, method 1200 includes a process of determining a sideband voltage indicated by VIO_CFG. In one aspect, the voltage control circuit 512 may provide a unit for determining a sideband voltage indicated by VIO_CFG, for example, based on a sideband voltage table 870 stored in memory 809. The sideband voltage table 870 may map various VIO_CFG voltages to compatible sideband voltages (e.g., Table 1 or Table 2).

[0097] At 1206, the method 1200 determines whether the sideband voltage indicated by VIO_CFG is supported by the PCIe platform. In one aspect, the voltage control circuit 512 may provide a unit for determining whether the sideband voltage indicated by VIO_CFG is supported by the PCIe platform. VIO_CFG may indicate that the PCIe adapter can support one or more sideband voltages (e.g., 0.8V, 1.2, 1.8V, and 3.3V). At 1208, if the PCIe platform can support at least one sideband voltage indicated by VIO_CFG, the PCIe platform may set the VIO voltage to the supported sideband voltage and supply power to the PCIe adapter (e.g., 3.3V and VIO). Otherwise, the PCIe platform does not power on the PCIe adapter.

[0098] Fig.13 1 is a flow chart of a method 1300 for communication interface voltage control according to aspects of the present disclosure. In some aspects, the method 1300 can be performed by the PCIe adapter 402 to implement sideband voltage level indication and configuration, for example, as described above with respect to Figure 5-8 The method 1300 is not limited to PCIe applications. In other aspects, the method 1300 can be used by an apparatus to indicate and control the signal voltage of a wired data link other than PCIe.

[0099] At 1302, method 1300 includes a process of providing a voltage indication signal, the voltage indication signal being configured to indicate a plurality of signal voltage levels of the interface circuit, the voltage indication signal being configurable to be one of a power supply voltage, a ground voltage, and one or more intermediate voltages between the power supply voltage and the ground voltage. For example, the power supply voltage (e.g., 3.3V or 1.8V) is higher than the ground voltage (e.g., 0V), and the one or more intermediate voltages are lower than the power supply voltage and higher than the ground voltage. At least one of the voltages may be configured to indicate a plurality of signal voltage levels (e.g., sideband voltages 0.8V, 1.2V, 1.8V, and / or 3.3V).

[0100] At 1304, method 1300 includes a process for operating a wired data link using a signal voltage level indicated by a voltage indication signal. In some aspects, the wired data link may be a PCIe link. In one example, PCIe interface circuitry 820 may provide a unit for operating a PCIe link (wired data link) using a sideband voltage indicated by a sideband voltage indication (e.g., VIO_CFG).

[0101] Fig.14 14 is a flow chart of a method 1400 for communication interface voltage control according to aspects of the present disclosure. In some aspects, the method 1400 can be performed by the PCIe platform 404 to implement sideband voltage level indication and configuration, for example, as described above with respect to Figure 5-8 The method 1400 is not limited to PCIe applications. In other aspects, the method 1400 can be used by an apparatus to indicate and control the signal voltage of a wired data link other than PCIe.

[0102] At 1402, method 1400 includes a process of receiving a voltage indication signal, the voltage indication signal being configured to indicate a plurality of signal voltage levels, the voltage indication signal being configurable as a power supply voltage, a ground voltage, and one or more intermediate voltages between the power supply voltage and the ground voltage. For example, the power supply voltage (e.g., 3.3V or 1.8V) is higher than the ground voltage (e.g., 0V), and the intermediate voltage is lower than the power supply voltage and higher than the ground voltage. At least one of the intermediate voltages may be configured to indicate a plurality of signal voltage levels (e.g., sideband voltages 0.8V, 1.2V, 1.8V, and / or 3.3V).

[0103] At 1404, the method 1400 also includes a process of operating a wired data link using the signal voltage level indicated by the voltage indication signal. In one example, the PCIe interface circuit 820 may provide a unit for operating a PCIe link (wired data link) using a sideband voltage indicated by a sideband voltage indication (e.g., VIO_CFG). The PCIe interface circuit 820 may receive 3.3V, VIO, and FCPO signals from a PCIe platform, and the PCIe interface may set its sideband voltage based on the VIO voltage.

[0104] The following provides an overview of examples of the present disclosure.

[0105] A first aspect of the present disclosure provides a device comprising: an interface circuit, the interface circuit being configured to provide an interface with a wired data link, the interface circuit being further configured to provide a voltage indication signal, the voltage indication signal being configurable as a plurality of voltage levels corresponding to a plurality of signal voltages, at least one voltage level of the plurality of voltage levels being capable of indicating two or more signal voltages of the plurality of signal voltages; and a controller, the controller being configured to operate the wired data link using the signal voltage indicated by the voltage indication signal.

[0106] A second aspect of the present disclosure, alone or in combination with the first aspect, wherein the multiple voltage levels include: a first voltage level indicating that the wired data link can operate at a first signal voltage; a second voltage level indicating that the wired data link can operate at a second signal voltage; and a third voltage level indicating that the wired data link can operate at the first signal voltage or the second signal voltage.

[0107] A third aspect of the present disclosure, alone or in combination with any one of the first to second aspects, wherein the plurality of signal voltages include 0.8V, 1.2V, 1.8V and 3.3V.

[0108] A fourth aspect of the present disclosure, alone or in combination with the first aspect, wherein the interface circuit is further configured to output a voltage indication signal at an input and output voltage configuration pin of the device.

[0109] A fifth aspect of the present disclosure, alone or in combination with any one of the first, second and fourth aspects, wherein the interface circuit is further configured to control a voltage level of a voltage indication signal in cooperation with a peripheral component interconnect express (PCIe) platform connected to the device.

[0110] A sixth aspect of the present disclosure, alone or in combination with the fifth aspect, wherein the interface circuit is further configured to control a voltage level of the voltage indication signal before the device receives power from the PCIe platform for operating the wired data link.

[0111] A seventh aspect of the present disclosure, alone or in combination with the fifth aspect, wherein the interface circuit includes a first resistor, the first resistor being configured to form a voltage divider with a second resistor in the PCIe platform, the output of the voltage divider corresponding to a voltage level of the voltage indication signal.

[0112] An eighth aspect of the present disclosure provides a method for operating a device for data communication, comprising: providing a voltage indication signal, the voltage indication signal being configurable as multiple voltage levels corresponding to multiple signal voltages, at least one voltage level of the multiple voltage levels being capable of indicating two or more signal voltages of the multiple signal voltages; and operating a wired data link using the signal voltage indicated by the voltage indication signal.

[0113] A ninth aspect of the present disclosure, alone or in combination with the eighth aspect, wherein the multiple voltage levels include: a first voltage level indicating that the wired data link can operate at a first signal voltage; a second voltage level indicating that the wired data link can operate at a second signal voltage; and a third voltage level indicating that the wired data link can operate at the first signal voltage or the second signal voltage.

[0114] A tenth aspect of the present disclosure, alone or in combination with any one of the eighth to ninth aspects, wherein the plurality of signal voltages include 0.8V, 1.2V, 1.8V and 3.3V.

[0115] According to an eleventh aspect of the present disclosure, either alone or in combination with the eighth aspect, providing a voltage indication signal comprises: outputting a voltage indication signal at an input and output voltage configuration pin of the device.

[0116] In a twelfth aspect of the present disclosure, alone or in combination with any one of the eighth, ninth and eleventh aspects, the method further comprises: controlling a voltage level of the voltage indication signal in cooperation with a peripheral component interconnect express (PCIe) platform connected to the device.

[0117] In a thirteenth aspect of the present disclosure, alone or in combination with the twelfth aspect, the method further comprises: controlling a voltage level of the voltage indication signal before receiving power for operating the data link from the PCIe platform.

[0118] A fourteenth aspect of the present disclosure, alone or in combination with the twelfth aspect, wherein controlling the voltage level of the voltage indication signal comprises: controlling the voltage level of the voltage indication signal using a first resistor, the first resistor being configured to form a voltage divider with a second resistor in the PCIe platform, the output of the voltage divider corresponding to the voltage level of the voltage indication signal.

[0119] A fifteenth aspect of the present disclosure provides a device for data communication, comprising: an interface circuit, the interface circuit being configured to provide an interface with a wired data link, the interface circuit being configured to receive a voltage indication signal, the voltage indication signal being configurable as a plurality of voltage levels corresponding to a plurality of signal voltages, at least one voltage level of the plurality of voltage levels being capable of indicating two or more signal voltages of the plurality of signal voltages; and a controller, the controller being configured to operate the wired data link using the signal voltage indicated by the voltage indication signal.

[0120] A sixteenth aspect of the present disclosure, alone or in combination with the fifteenth aspect, wherein the multiple voltage levels include: a first voltage level indicating that the wired data link can operate at a first signal voltage; a second voltage level indicating that the wired data link can operate at a second signal voltage; and a third voltage level indicating that the wired data link can operate at the first signal voltage or the second signal voltage.

[0121] A seventeenth aspect of the present disclosure, alone or in combination with any one of the fifteenth and sixteenth aspects, wherein the plurality of signal voltages include 0.8V, 1.2V, 1.8V and 3.3V.

[0122] An eighteenth aspect of the present disclosure, alone or in combination with any one of the fifteenth and sixteenth aspects, wherein the interface circuit is further configured to detect a voltage level of a voltage indication signal in cooperation with a peripheral component interconnect express (PCIe) adapter connected to the device.

[0123] A nineteenth aspect of the present disclosure, alone or in combination with the eighteenth aspect, wherein the interface circuit is further configured to detect a voltage level of the voltage indication signal before supplying power to the PCIe adapter to operate the data link.

[0124] The twentieth aspect of the present disclosure, alone or in combination with the eighteenth aspect, wherein the interface circuit includes a first resistor, the first resistor is configured to form a voltage divider circuit with a second resistor in the PCIe adapter, and the output of the voltage divider circuit corresponds to the voltage level of the voltage indication signal.

[0125] A twenty-first aspect of the present disclosure provides a method for operating a device for data communication, comprising: receiving a voltage indication signal, the voltage indication signal being configurable as multiple voltage levels corresponding to multiple signal voltages, at least one voltage level of the multiple voltage levels being capable of indicating two or more signal voltages of the multiple signal voltages; and operating a wired data link using the signal voltage indicated by the voltage indication signal.

[0126] The twenty-second aspect of the present disclosure, alone or in combination with the twenty-first aspect, wherein the multiple voltage levels include: a first voltage level indicating that the wired data link can operate at a first signal voltage; a second voltage level indicating that the wired data link can operate at a second signal voltage; and a third voltage level indicating that the wired data link can operate at the first signal voltage or the second signal voltage.

[0127] In a twenty-third aspect of the present disclosure, alone or in combination with any one of the twenty-first and twenty-second aspects, the plurality of signal voltages include 0.8V, 1.2V, 1.8V and 3.3V.

[0128] In the twenty-fourth aspect of the present disclosure, alone or in combination with any one of the twenty-first and twenty-second aspects, the method further includes: detecting a voltage level of the voltage indication signal in cooperation with a peripheral component interconnect express (PCIe) adapter connected to the device.

[0129] A twenty-fifth aspect of the present disclosure, alone or in combination with the twenty-fourth aspect, further includes: detecting a voltage level of a sideband voltage indication signal before powering the PCIe adapter to operate a data link.

[0130] In the twenty-sixth aspect of the present disclosure, alone or in combination with the twenty-fourth aspect, the method also includes: using a first resistor to detect the voltage level of the voltage indication signal, the first resistor is configured to form a voltage divider with a second resistor in the PCIe adapter, and the output of the voltage divider corresponds to the voltage level of the voltage indication signal.

[0131] The twenty-seventh aspect of the present disclosure provides a device for data communication, comprising: an interface circuit, the interface circuit being configured to provide an interface with a wired data link, the interface circuit being further configured to provide a voltage indication signal, the voltage indication signal being configured to indicate multiple signal voltage levels of the interface circuit, the voltage indication signal being configurable to be one of a power supply voltage, a ground voltage, and one or more intermediate voltages between the power supply voltage and the ground voltage; and a controller, the controller being configured to operate the wired data link using the signal voltage level indicated by the voltage indication signal.

[0132] A twenty-eighth aspect of the present disclosure, alone or in combination with the twenty-seventh aspect, wherein the voltage indication signal is configured to indicate at least one of the following: the interface circuit can operate at 3.3V and 1.8V; the interface circuit can operate at 1.8V and 1.2V; or the interface circuit can operate at 1.2V and 0.8V.

[0133] A twenty-ninth aspect of the present disclosure, alone or in combination with the twenty-seventh aspect, wherein the interface circuit is further configured to output a voltage indication signal at an input and output voltage configuration pin of the device.

[0134] The thirtieth aspect of the present disclosure, alone or in combination with any one of aspects twenty-seven to twenty-ninth, wherein the interface circuit is also configured to control the voltage level of the voltage indication signal in cooperation with a peripheral component interconnect express (PCIe) platform connected to the device.

[0135] The thirty-first aspect of the present disclosure, alone or in combination with the thirtieth aspect, wherein the interface circuit is further configured to control a voltage level of the voltage indication signal before the device receives power from the PCIe platform for operating a wired data link.

[0136] Aspect 32 of the present disclosure, alone or in combination with aspect 30, wherein the interface circuit includes a first resistor, the first resistor being configured to form a voltage divider with a second resistor in the PCIe platform, the output of the voltage divider corresponding to the voltage level of the voltage indication signal.

[0137] The thirty-third aspect of the present disclosure provides a device for data communication, comprising: an interface circuit, the interface circuit being configured to provide an interface with a wired data link, the interface circuit being configured to receive a voltage indication signal, the voltage indication signal being configured to indicate multiple signal voltage levels, the voltage indication signal being configurable as a power supply voltage, a ground voltage, and one or more intermediate voltages between the power supply voltage and the ground voltage; and a controller, the controller being configured to operate the wired data link using the signal voltage level indicated by the voltage indication signal.

[0138] A thirty-fourth aspect of the present disclosure, alone or in combination with the thirty-third aspect, wherein the voltage indication signal is configured to indicate at least one of the following: the interface circuit can operate at 3.3V and 1.8V; the interface circuit can operate at 1.8V and 1.2V; or the interface circuit can operate at 1.2V and 0.8V.

[0139] A thirty-fifth aspect of the present disclosure, alone or in combination with any one of the thirty-third and thirty-fourth aspects, wherein the interface circuit is also configured to detect the voltage level of the voltage indication signal in cooperation with a peripheral component interconnect express (PCIe) adapter connected to the device.

[0140] A thirty-sixth aspect of the present disclosure, alone or in combination with the thirty-fifth aspect, wherein the interface circuit is further configured to detect a voltage level of a voltage indication signal before supplying power to a PCIe adapter to operate a wired data link.

[0141] Aspect 37 of the present disclosure, alone or in combination with aspect 35, wherein the interface circuit includes a first resistor, the first resistor being configured to form a voltage divider circuit with a second resistor in the PCIe adapter, the output of the voltage divider circuit corresponding to the voltage level of the voltage indication signal.

[0142] It should be understood that the present disclosure is not limited to the exemplary terms used above to describe various aspects of the present disclosure. For example, bandwidth may also be referred to as throughput, data rate, or another term.

[0143] Although the example of the PCIe standard is used above to discuss aspects of the present disclosure, it should be understood that the present disclosure is not limited to this example and may be used with other standards.

[0144] The host client 314, host controller 312, device controller 352, and device client 354 discussed above can each be implemented using a controller or processor that is configured to perform the functions described herein by executing software including code for performing the functions. The software can be stored on a non-transitory computer-readable storage medium, such as RAM, ROM, EEPROM, optical disk, and / or magnetic disk, shown as host system memory 340, endpoint system memory 374, or another memory.

[0145] Any reference to an element using a name such as "first", "second" or the like in this article does not generally limit the quantity or order of these elements. Specifically, these names can be used as a convenient method to distinguish two or more elements or instances of elements in this article. Therefore, reference to the first and second elements does not mean that only two elements can be used, or that the first element must precede the second element.

[0146] Within the present disclosure, the word "exemplary" is used to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the present disclosure. Likewise, the word "aspect" does not require that all aspects of the present disclosure include the discussed feature, advantage, or mode of operation. The word "coupled" is used herein to refer to a direct or indirect electrical or other communication coupling between two structures. Additionally, the term "approximately" means within ten percent of the stated value.

[0147] The foregoing description of the present disclosure is provided to enable those skilled in the art to implement or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples described herein, but rather to be given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device for data communication, comprising: an interface circuit configured to provide an interface with a wired data link, the interface circuit further configured to provide a voltage indication signal, the voltage indication signal configurable as one voltage level of a plurality of voltage levels corresponding to a plurality of signal voltages, at least one voltage level of the plurality of voltage levels being capable of indicating two or more signal voltages of the plurality of signal voltages; as well as A controller is configured to operate the wired data link using the signal voltage indicated by the voltage indication signal.

2. The device according to claim 1, wherein: The plurality of voltage levels include: a first voltage level indicating that the wired data link is operable at a first signal voltage; a second voltage level indicating that the wired data link is operable at a second signal voltage; and A third voltage level indicates that the wired data link is operable at the first signal voltage and the second signal voltage.

3. The device according to claim 1, wherein: The plurality of signal voltages include 0.8V, 1.2V, 1.8V, and 3.3V.

4. The device according to claim 1, wherein: The interface circuit is further configured to output the voltage indication signal at an input and output voltage configuration pin of the device.

5. The device according to claim 1, wherein: The interface circuit is also configured to control a voltage level of the voltage indication signal in cooperation with a peripheral component interconnect express (PCIe) platform connected to the apparatus.

6. The device according to claim 5, wherein: The interface circuit is further configured to control the voltage level of the voltage indication signal before the device receives power from the PCIe platform for operating the wired data link.

7. The device according to claim 5, wherein: The interface circuit includes a first resistor configured to form a voltage divider with a second resistor in the PCIe platform, an output of the voltage divider corresponding to the voltage level of the voltage indication signal.

8. A method of operating an apparatus for data communication, comprising: providing a voltage indication signal, the voltage indication signal being configurable as one of a plurality of voltage levels corresponding to a plurality of signal voltages, at least one of the plurality of voltage levels being capable of indicating two or more of the plurality of signal voltages; as well as A wired data link is operated using a signal voltage indicated by the voltage indication signal.

9. The method according to claim 8, wherein: The plurality of voltage levels include: a first voltage level indicating that the wired data link is operable at a first signal voltage; a second voltage level indicating that the wired data link is operable at a second signal voltage; and A third voltage level indicates that the wired data link is operable at the first signal voltage or the second signal voltage.

10. The method according to claim 8, wherein: The plurality of signal voltages include 0.8V, 1.2V, 1.8V, and 3.3V.

11. The method according to claim 8, wherein: Providing the voltage indication signal includes: outputting the voltage indication signal at an input and output voltage configuration pin of the device.

12. The method according to claim 8, further comprising: A voltage level of the voltage indication signal is controlled in cooperation with a peripheral component interconnect express (PCIe) platform connected to the device.

13. The method according to claim 12, further comprising: The voltage level of the voltage indication signal is controlled before receiving power from the PCIe platform for operating the wired data link.

14. The method according to claim 12, wherein: Controlling the voltage level of the voltage indication signal comprises: The voltage level of the voltage indication signal is controlled using a first resistor, the first resistor being configured to form a voltage divider with a second resistor in the PCIe platform, the output of the voltage divider corresponding to the voltage level of the voltage indication signal.

15. An apparatus for data communication, comprising: an interface circuit configured to provide an interface with a wired data link, the interface circuit configured to receive a voltage indication signal, the voltage indication signal configurable as one voltage level of a plurality of voltage levels corresponding to a plurality of signal voltages, at least one voltage level of the plurality of voltage levels being capable of indicating two or more signal voltages of the plurality of signal voltages; as well as A controller is configured to operate the wired data link using the signal voltage indicated by the voltage indication signal.

16. The device according to claim 15, wherein: The plurality of voltage levels include: a first voltage level indicating that the wired data link is operable at a first signal voltage; a second voltage level indicating that the wired data link is operable at a second signal voltage; and A third voltage level indicates that the wired data link is operable at the first signal voltage or the second signal voltage.

17. The device according to claim 15, wherein: The plurality of signal voltages include 0.8V, 1.2V, 1.8V, and 3.3V.

18. The device according to claim 15, wherein: The interface circuit is further configured to detect a voltage level of the voltage indication signal in cooperation with a peripheral component interconnect express (PCIe) adapter connected to the apparatus.

19. The device according to claim 18, wherein: The interface circuit is further configured as: The voltage level of the voltage indication signal is detected before power for operating the wired data link is provided to the PCIe adapter.

20. The device according to claim 18, wherein The interface circuit includes a first resistor configured to form a voltage divider with a second resistor in the PCIe adapter, an output of the voltage divider corresponding to the voltage level of the voltage indication signal.

21. A method of operating an apparatus for data communication, comprising: receiving a voltage indication signal, the voltage indication signal being configurable as one of a plurality of voltage levels corresponding to a plurality of signal voltages, at least one of the plurality of voltage levels being capable of indicating two or more of the plurality of signal voltages; as well as A wired data link is operated using a signal voltage indicated by the voltage indication signal.

22. The method according to claim 21, wherein: The plurality of voltage levels include: a first voltage level indicating that the wired data link is operable at a first signal voltage; a second voltage level indicating that the wired data link is operable at a second signal voltage; and A third voltage level indicates that the wired data link is operable at the first signal voltage or the second signal voltage.

23. The method according to claim 21, wherein: The plurality of signal voltages include 0.8V, 1.2V, 1.8V, and 3.3V.

24. The method of claim 21, further comprising: A voltage level of the voltage indication signal is detected in cooperation with a peripheral component interconnect express (PCIe) adapter connected to the device.

25. The method according to claim 24, further comprising: The voltage level of the voltage indication signal is detected before power for operating the wired data link is provided to the PCIe adapter.

26. The method of claim 24, further comprising: The voltage level of the voltage indication signal is detected using a first resistor, the first resistor being configured to form a voltage divider with a second resistor in the PCIe adapter, the output of the voltage divider corresponding to the voltage level of the voltage indication signal.

27. An apparatus for data communication, comprising: an interface circuit configured to provide an interface with a wired data link, the interface circuit further configured to provide a voltage indication signal, the voltage indication signal configured to indicate a plurality of signal voltage levels of the interface circuit, the voltage indication signal configurable to be one of: a power supply voltage, a ground voltage, and one or more intermediate voltages between the power supply voltage and the ground voltage; and A controller is configured to operate the wired data link using the signal voltage level indicated by the voltage indication signal.

28. The device according to claim 27, wherein The voltage indication signal is configured to indicate at least one of the following: The interface circuit can operate at 3.3V and 1.8V; The interface circuit can operate at 1.8V and 1.2V; or The interface circuit can operate at 1.2V and 0.8V.

29. The device according to claim 27, wherein: The interface circuit is further configured to output the voltage indication signal at an input and output voltage configuration pin of the device.

30. The device according to claim 27, wherein: The interface circuit is also configured to control a voltage level of the voltage indication signal in cooperation with a peripheral component interconnect express (PCIe) platform connected to the apparatus.

31. The device according to claim 30, wherein The interface circuit is further configured to control the voltage level of the voltage indication signal before the device receives power from the PCIe platform for operating the wired data link.

32. The device according to claim 30, wherein: The interface circuit includes a first resistor configured to form a voltage divider with a second resistor in the PCIe platform, an output of the voltage divider corresponding to the voltage level of the voltage indication signal.

33. An apparatus for data communication, comprising: an interface circuit configured to provide an interface with a wired data link, the interface circuit configured to provide a voltage indication signal, the voltage indication signal configured to indicate a plurality of signal voltage levels, the voltage indication signal configurable to be a power supply voltage, a ground voltage, and one or more intermediate voltages between the power supply voltage and the ground voltage; as well as A controller is configured to operate the wired data link using the signal voltage level indicated by the voltage indication signal.

34. The device according to claim 33, wherein The voltage indication signal is configured to indicate at least one of the following: The interface circuit can operate at 3.3V and 1.8V; The interface circuit can operate at 1.8V and 1.2V; or The interface circuit can operate at 1.2V and 0.8V.

35. The device according to claim 33, wherein The interface circuit is further configured to detect a voltage level of the voltage indication signal in cooperation with a peripheral component interconnect express (PCIe) adapter connected to the apparatus.

36. The device according to claim 35, wherein The interface circuit is further configured as: The voltage level of the voltage indication signal is detected before power for operating the wired data link is provided to the PCIe adapter.

37. The device according to claim 35, wherein: The interface circuit includes a first resistor configured to form a voltage divider with a second resistor in the PCIe adapter, an output of the voltage divider corresponding to the voltage level of the voltage indication signal.

Images