Managing three-dimensional semiconductor devices

Abstract

Systems, apparatuses, and methods for managing three-dimensional semiconductor devices are provided. In one aspect, a method includes forming a plurality of memory cell strings in a first side of a semiconductor substrate having a semiconductor material, forming a plurality of alternating strips of semiconductor material and isolation material in a second opposite side of the semiconductor substrate, and forming bit lines in the second side of the semiconductor substrate. A layer of metal material may be deposited on alternating strips of semiconductor material and isolation material, and forming bit lines by forming a composite conductive material based on a metal material and a semiconductor material in a corresponding strip of the alternating strips of the semiconductor material to form each of the bit lines in the corresponding strip of the semiconductor material.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and manufacturing processes for semiconductor devices. Background Art

[0002] Semiconductor devices (e.g., memory devices) can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive because they can increase array density by stacking more layers within a similar footprint. 3D memory devices typically include a memory array of memory cells and peripheral circuits for facilitating the operation of the memory array. The memory cells may include vertical transistors. Summary of the invention

[0003] The present disclosure describes methods, devices, systems, and techniques for managing three-dimensional (3D) semiconductor devices, such as vertical transistors and bit lines that form a 3D memory device.

[0004] One aspect of the present disclosure features a method, comprising: forming a plurality of memory cell strings in a first side of a semiconductor substrate along a vertical direction, the semiconductor substrate comprising a semiconductor material; forming a plurality of alternating strips of semiconductor material and isolation material in a second side of the semiconductor substrate along a horizontal direction perpendicular to the vertical direction, the second side being opposite to the first side along the vertical direction; and forming a plurality of bit lines in the second side of the semiconductor substrate. Forming the plurality of bit lines comprises: depositing a metal material layer on the plurality of alternating strips of semiconductor material and isolation material; and forming each of the plurality of bit lines in a corresponding strip of semiconductor material of the plurality of alternating strips by forming a composite conductive material based on a metal material and a semiconductor material in the corresponding strip of the semiconductor material of the plurality of alternating strips.

[0005] In some embodiments, forming a composite conductive material based on a metal material and a semiconductor material in corresponding strips of semiconductor material includes annealing the metal material and the semiconductor material so that the metal material reacts with the semiconductor material to form the composite conductive material. There may be no reaction between the isolation material and the metal material deposited on the isolation material.

[0006] In some embodiments, the semiconductor material includes silicon, the isolation material includes oxide, and the composite conductive material includes silicide. In some examples, the metal material includes nickel (Ni).

[0007] In some embodiments, the method further comprises: after forming the plurality of bit lines in the second side of the semiconductor substrate, removing the residue of the metal material from the second side of the semiconductor substrate. In some embodiments, removing the residue of the metal material from the second side comprises: wet etching the residue of the metal material.

[0008] In some embodiments, forming a plurality of alternating strips of semiconductor material and isolation material in the second side of the semiconductor substrate includes: thinning the semiconductor substrate from the second side of the semiconductor substrate to expose the plurality of alternating strips of semiconductor material and isolation material. The method may also include: implanting ions into the second side of the semiconductor substrate. Forming a composite conductive material based on a metal material and a semiconductor material in corresponding strips of semiconductor material may include: forming a composite conductive material based on a metal material and a semiconductor material using implanted ions.

[0009] In some embodiments, implanting ions into the second side of the semiconductor substrate includes: implanting semiconductor ions into the second side of the semiconductor substrate; implanting N+ type ions into the second side of the semiconductor substrate; and activating the implanted N+ type ions with the implanted semiconductor ions at an activation temperature.

[0010] In some embodiments, the semiconductor material includes silicon, the semiconductor ions include germanium (Ge) ions, and the N+ type ions include arsenic (As) ions or phosphorus (P) ions.

[0011] In some embodiments, the activation temperature is lower than a nominal temperature for activating N+ type ions without implanting semiconductor ions. In some examples, the nominal temperature is about 900°C, and wherein the activation temperature is in a range of about 500°C to about 600°C.

[0012] In some embodiments, thinning the semiconductor substrate from the second side of the semiconductor substrate includes: etching semiconductor material in the second side of the semiconductor substrate; and polishing a top surface of the etched semiconductor material in the second side of the semiconductor substrate.

[0013] In some embodiments, each memory cell in the plurality of memory cell strings includes a vertical transistor along a vertical direction. Forming the plurality of memory cell strings includes: forming a gate terminal of the vertical transistor by depositing at least one metal layer on an inner surface of the trench along a vertical direction; forming a first terminal of the vertical transistor by implanting ions from a first side of the semiconductor substrate; and forming a second terminal of the vertical transistor by implanting ions into a second side of the semiconductor substrate. In some examples, the first terminal is a source terminal and the second terminal is a drain terminal.

[0014] In some implementations, each of the plurality of bit lines is formed on and coupled to the second terminal of the vertical transistor.

[0015] In some embodiments, each memory cell in the plurality of memory cell strings further includes a capacitor coupled to the vertical transistor. Forming the plurality of memory cell strings may include: forming the capacitor before forming the vertical transistor, the capacitor being located above the vertical transistor along a vertical direction.

[0016] In some embodiments, forming the plurality of memory cell strings includes forming gate terminals of a pair of independent vertical transistors in the same trench along a vertical direction, the gate terminals separated by an isolation material along a third direction perpendicular to the vertical and horizontal directions.

[0017] In some embodiments, the method further includes forming an isolation region between adjacent pairs of independent vertical transistors along a third direction.

[0018] In some embodiments, a plurality of memory cell strings and a plurality of bit lines are formed in the array die. The method further includes integrating the control die with the array die by bonding the first side of the semiconductor substrate to the front side of the control die and conductively coupling one or more conductive lines of the array die to control circuitry in the front side of the control die.

[0019] Another aspect of the disclosure features a semiconductor device including: a plurality of memory cell strings in a first side of a semiconductor substrate along a vertical direction, the semiconductor substrate including a semiconductor material; and a plurality of bit lines in a second side of the semiconductor substrate, the second side being opposite to the first side along the vertical direction, wherein adjacent bit lines of the plurality of bit lines are separated by an isolation material along a horizontal direction perpendicular to the vertical direction. The plurality of bit lines are made of a composite conductive material based on a semiconductor material, and the plurality of bit lines are located on a layer of the semiconductor material having ions implanted therein.

[0020] In some embodiments, the implanted ions include semiconductor ions and N+ ions. In some examples, the semiconductor material includes silicon, the semiconductor ions include germanium (Ge) ions, the N+ ions include arsenic (As) ions or phosphorus (P) ions, and the composite conductive material includes silicide.

[0021] In some embodiments, each memory cell in the plurality of memory cell strings includes a vertical transistor along a vertical direction, and a portion of the layer of semiconductor material having ion implantation is configured as a terminal of the vertical transistor and conductively coupled to a corresponding bit line.

[0022] In some embodiments, gate terminals of a pair of independent vertical transistors are in the same trench along the vertical direction and are separated by an isolation material along a third direction perpendicular to the vertical direction and the horizontal direction, and an isolation region is between adjacent pairs of independent vertical transistors along the third direction. In some examples, the isolation region includes an air cavity surrounded by the isolation material or a cavity filled with a metal material.

[0023] Another aspect of the disclosure features a system including a memory device and a controller coupled to the memory device and configured to control the memory device. The memory device includes: an array structure including a plurality of memory cell strings in a first side of a semiconductor substrate along a vertical direction, the semiconductor substrate including a semiconductor material; and a plurality of bit lines located in a second side of the semiconductor substrate, the second side being opposite to the first side along the vertical direction, wherein adjacent bit lines of the plurality of bit lines are separated by an isolation material along a horizontal direction perpendicular to the vertical direction, wherein the plurality of bit lines are made of a composite conductive material based on a semiconductor material, and wherein the plurality of bit lines are located on a layer of the semiconductor material having ions implanted therein.

[0024] Another aspect of the present disclosure is characterized by a method comprising: forming a plurality of memory cell strings in a first side of a semiconductor substrate along a vertical direction, the semiconductor substrate comprising a semiconductor material; thinning the semiconductor substrate from a second side of the semiconductor substrate along the vertical direction, the second side being opposite to the first side of the semiconductor substrate; and implanting semiconductor ions into the second side of the semiconductor substrate.

[0025] In some embodiments, the method further includes implanting N+ type ions into the second side of the semiconductor substrate, and activating the implanted N+ type ions at an activation temperature.

[0026] In some embodiments, the semiconductor material includes silicon, the semiconductor ions include germanium (Ge) ions, and the N+ type ions include arsenic (As) ions or phosphorus (P) ions.

[0027] In some embodiments, the activation temperature is lower than a nominal temperature for activating N+ type ions without implanting semiconductor ions.

[0028] In some embodiments, thinning the semiconductor substrate from the second side of the semiconductor substrate along a vertical direction includes thinning the semiconductor substrate to expose a plurality of alternating strips of semiconductor material and isolation material. The method also includes forming a plurality of bit lines in the second side of the semiconductor substrate based on the plurality of strips of semiconductor material of the plurality of alternating strips.

[0029] In some embodiments, forming a plurality of bit lines in the second side of the semiconductor substrate includes: depositing a metal material layer on a plurality of alternating strips of semiconductor material and isolation material; and forming each of the plurality of bit lines in a corresponding strip of the plurality of strips of semiconductor material by forming a composite conductive material based on the metal material and the semiconductor material in the corresponding strip. The metal material may include nickel (Ni).

[0030] In some embodiments, forming a composite conductive material based on a metal material and a semiconductor material in the corresponding strip includes annealing the metal material and the semiconductor material so that the metal material reacts with the semiconductor material to form the composite conductive material. There may be no reaction between the isolation material and the metal material deposited on the isolation material.

[0031] In some embodiments, forming the composite conductive material based on the metal material and the semiconductor material in the corresponding strips includes forming the composite conductive material based on the metal material and the semiconductor material using activated implanted N+ ions.

[0032] In some embodiments, each memory cell in the plurality of memory cell strings includes a vertical transistor along a vertical direction. Forming the plurality of memory cell strings includes: forming a gate terminal of the vertical transistor by depositing at least one metal layer on an inner surface of the trench along a vertical direction; forming a first terminal of the vertical transistor by implanting N+ type ions from a first side of the semiconductor substrate; and forming a second terminal of the vertical transistor by implanting N+ type ions into a second side of the semiconductor substrate. In some examples, the first terminal is a source terminal and the second terminal is a drain terminal.

[0033] Embodiments of the present disclosure may provide one or more of the following technical advantages and / or benefits. For example, the technology enables, for example, forming a self-aligned bit line through a strip of semiconductor material on the back side of a semiconductor substrate by forming a composite conductive material (e.g., metal silicide) based on a metal material (e.g., Ni) and a semiconductor material (e.g., Si). In addition, compared with the complex manufacturing process of forming a metal for a bit line, forming a self-aligned bit line enables the process window to be expanded, and the process steps to be simplified and / or minimized, for example, omitting Si groove and polysilicon groove processes, oxide stamping, and some other processes, which can reduce manufacturing costs and increase manufacturing speed.

[0034] In some embodiments, the first and second terminals (e.g., source terminal and drain terminal) of the vertical transistor are formed on opposite ends of the semiconductor body of the vertical transistor. The first terminal can be formed on the first end of the semiconductor body by injecting N+ type ions from the front side of the semiconductor substrate and activating the N+ type ions in the first end. The second terminal can be formed by injecting N+ type ions from the back side of the semiconductor substrate and activating the N+ type ions in the second end. In some cases, the activation temperature of the N+ type ions in the second end can be reduced by germanium (Ge) pre-amorphization implantation (Ge PAI), for example, from more than 900°C to a low thermal temperature, such as 500°C to 600°C, which can reduce the thermal budget of the process. In addition, the second terminal of the vertical transistor can be formed by directly injecting N+ type ions from the back side of the semiconductor substrate into the second end of the semiconductor body of the vertical transistor, which can expand the process window and reduce manufacturing costs.

[0035] The technology can also reduce the thickness requirement of performing chemical mechanical polishing (CMP) to thin the semiconductor substrate from the back side. In addition, the composite conductive material (e.g., silicide) can be formed using self-alignment for bit line metal connection, combined with forming the first terminal from the front side to reduce the off current Ioff and increase the on current Ion, and combined with forming the second terminal from the back side and forming an ohmic contact using N+ doped silicide to increase Ion, which can greatly improve the performance of the vertical transistor, the memory cell including the vertical transistor, and / or the 3D semiconductor device including the memory cell. The technology makes it possible to simplify or optimize the manufacturing process of the 3D semiconductor device and reduce the manufacturing cost.

[0036] The details of one or more implementations of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are incorporated herein and form a part of the present disclosure, illustrate various aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable one of ordinary skill in the relevant art to make and use the present disclosure.

[0038] Figure 1 A cross-sectional view of an example 3D semiconductor device is shown.

[0039] Figure 2 A perspective view of an example 3D semiconductor device is shown.

[0040] Figure 3A A cross-sectional view of an example 3D semiconductor device including vertical transistors and bit lines is shown.

[0041] Figure 3BShows Figure 3A 1. A top view of an example 3D semiconductor device.

[0042] Figure 4A An example structure is shown, showing the formation of the terminals of a vertical transistor by implanting N+ type ions from the front side of the semiconductor substrate.

[0043] Figure 4B Another example structure is shown, showing the formation of the terminals of a vertical transistor by implanting N+ type ions from the back side of the semiconductor substrate.

[0044] Figures 5A-5D Cross-sectional views showing the structure of a 3D semiconductor device at various stages of the manufacturing process.

[0045] Fig. 6A A cross-sectional view of an example structure before bit lines are formed is shown.

[0046] Figure 6B A cross-sectional view of the example structure after forming a bit line is shown.

[0047] Fig. 7A is a flow chart of an example process for forming a semiconductor device.

[0048] Figure 7B is a flow chart of another example process for forming a semiconductor device according to one or more embodiments of the present disclosure.

[0049] Figure 8 A block diagram of an example system having one or more semiconductor devices is shown.

[0050] Like reference numbers and designations in the various drawings indicate like elements.It should also be understood that the various exemplary embodiments shown in the drawings are merely illustrative representations and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0051] Figure 1 1 shows a side view of a cross section of an example 3D semiconductor device 100. The 3D semiconductor device 100 may be a 3D dynamic random access memory (DRAM). It should be understood that Figure 1 For illustrative purposes only, and may not necessarily reflect actual device structures (e.g., interconnections) in practice. In some embodiments, the 3D semiconductor device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 may be bonded at a bonding interface 106 therebetween.

[0052] like Figure 1As shown, the first semiconductor structure 102 may include a substrate 110, which may include silicon (e.g., single crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The first semiconductor structure 102 may include a peripheral circuit 112 on and / or in the substrate 110. In some embodiments, the peripheral circuit 112 includes a plurality of transistors 114 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of the transistors 114) may also be formed on or in the substrate 110. In some examples, the peripheral circuit 112 is formed using complementary metal oxide semiconductor (CMOS) technology, and the first semiconductor structure 102 may also be formed on a semiconductor die that may be referred to as a control die or a CMOS die 102.

[0053] In some embodiments, the first semiconductor structure 102 also includes an interconnect layer 116 above the peripheral circuit 112 to transmit electrical signals to and from the peripheral circuit 112. The interconnect layer 116 may include a plurality of interconnects (also referred to herein as "contacts"), including lateral interconnects and via contacts. The interconnect layer 116 may also include one or more interlayer dielectric (ILD) layers, in which interconnects and via contacts may be formed. That is, the interconnect layer 116 may include interconnects and via contacts in a plurality of ILD layers. In some embodiments, the peripheral circuits 112 are coupled to each other via the interconnects in the interconnect layer 116. The interconnects in the interconnect layer 116 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layer may be formed with a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0054] like Figure 1 As shown, the first semiconductor structure 102 has a front side and a back side, and the first semiconductor structure 102 may also include a bonding layer 118 at the back side at the bonding interface 106 and above the interconnect layer 116 and the peripheral circuit 112. The bonding layer 118 may include a plurality of bonding contacts 119 and a dielectric that electrically isolates the bonding contacts 119. The bonding contacts 119 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 118 may be formed with a dielectric material (e.g., silicon oxide). The bonding contacts 119 in the bonding layer 118 and the surrounding dielectric may be used for hybrid bonding. Similarly, as Figure 1As shown, the second semiconductor structure 104 may also include a bonding layer 120 at the bonding interface 106 and above the bonding layer 118 of the first semiconductor structure 102. The bonding layer 120 may include a plurality of bonding contacts 121 and a dielectric electrically isolating the bonding contacts 121. The bonding contacts 121 may include a conductive material, such as Cu. The remaining area of ​​the bonding layer 120 may be formed with a dielectric material (e.g., silicon oxide). The bonding contacts 121 and the surrounding dielectric in the bonding layer 120 may be used for hybrid bonding. The bonding contacts 121 may contact the bonding contacts 119 at the bonding interface 106. In some embodiments, the bonding layer 120 includes a dielectric layer opposite to a memory cell (e.g., a DRAM cell) 124, wherein a bit line 123 is located between the dielectric layer and the memory cell 124, as shown in FIG. Figure 1 The dielectric layer may include a bonding interface 106 having a bonding contact 121 .

[0055] The second semiconductor structure 104 can be bonded on top of the first semiconductor structure 102 in a face-to-face manner at a bonding interface 106. In some embodiments, the bonding interface 106 is disposed between the bonding layers 120 and 118 as a result of hybrid bonding (also referred to as "metal / dielectric hybrid bonding"), which is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer, such as solder or adhesive), and can simultaneously achieve metal-metal bonding and dielectric-dielectric bonding. In some embodiments, the bonding interface 106 is where the bonding layer 120 and the bonding layer 118 meet and bond. In some examples, the bonding interface 106 can be a layer having a certain thickness that includes a top surface of the bonding layer 118 of the first semiconductor structure 102 and a bottom surface of the bonding layer 120 of the second semiconductor structure 104.

[0056] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 122, which includes a bit line 123 above the bonding layer 120 to transmit electrical signals. The interconnect layer 122 may include multiple interconnects, such as middle-end process (MEOL) interconnects and back-end process (BEOL) interconnects. In some embodiments, the interconnects in the interconnect layer 122 also include local interconnects, such as bit lines 123 and word line contacts (not shown). The interconnect layer 122 may also include one or more ILD layers, in which interconnect lines and via contacts may be formed. The interconnects in the interconnect layer 122 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The ILD layer may be formed with a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0057] In some embodiments, peripheral circuit 112 includes a word line driver / row decoder, which is coupled to the word line contacts in interconnect layer 122 through bonding layer 120, bonding layer 118, bonding contacts 121 and bonding contacts 119, and interconnect layer 116. In some embodiments, peripheral circuit 112 includes a bit line driver / column decoder, which is coupled to bit line 123 and bit line contacts in interconnect layer 122 through bonding layer 120, bonding layer 118, bonding contacts 121 and bonding contacts 119, and interconnect layer 116. In some embodiments, bit line 123 is a metal bit line, as opposed to a semiconductor bit line (e.g., a doped silicon bit line). For example, bit line 123 can include W, Co, Cu, Al, or any other suitable metal having a higher conductivity than doped silicon. In some embodiments, the bit line contact is an ohmic contact rather than a Schottky contact.

[0058] In some embodiments, for example, as discussed in further detail below, the bit line 123 is made of a composite conductive material that can be based on a metal material (e.g., W, Co, Cu, Al) and a semiconductor material (e.g., Si). For example, the composite conductive material can include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon.

[0059] In some embodiments, the second semiconductor structure 104 includes a DRAM device in which memory cells are arranged in the form of an array of DRAM cells 124 over the interconnect layer 122 and the bonding layer 120. That is, the interconnect layer 122 including the bit lines 123 can be arranged between the bonding layer 120 and the array of DRAM cells 124. The bit lines 123 in the interconnect layer 122 can be coupled to the strings of DRAM cells 124. In some embodiments, the second semiconductor structure 104 is formed on a semiconductor die and can be referred to as an array die 104.

[0060] In some embodiments, the semiconductor device may include a plurality of array dies (e.g., array die 104) and a CMOS die (e.g., CMOS die 102). The plurality of array dies and CMOS dies may be stacked and bonded together. The CMOS die may be coupled to each of the plurality of array dies, respectively, and each of the plurality of array dies may be driven to operate in a manner similar to the semiconductor device, respectively. The semiconductor device may be any suitable device. In some examples, the semiconductor device includes at least a first wafer and a second wafer bonded face to face. The array die may be disposed on a first wafer together with other array dies, and the CMOS die may be disposed on a second wafer together with other CMOS dies. The first wafer and the second wafer may be bonded together, so that the array die on the first wafer may be bonded to the corresponding CMOS die on the second wafer. In some examples, the semiconductor device is a chip having at least an array die and a CMOS die bonded together. In an example, the chip is cut from the bonded wafer. In another example, the semiconductor device is a semiconductor package including one or more semiconductor chips assembled on a package substrate.

[0061] Each DRAM cell 124 may include a vertical transistor 126 and a capacitor 128 coupled to the vertical transistor 126. The DRAM cell 124 may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that the DRAM cell 124 may have any suitable structure, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 126 may be a MOSFET for switching the corresponding DRAM cell 124. In some embodiments, the vertical transistor 126 includes a semiconductor body 130 extending vertically (in the z-direction) (in which an active region of a channel may be formed), and a gate structure 136 contacting one side of the semiconductor body 130. In a single-gate vertical transistor, the semiconductor body 130 may have a rectangular parallelepiped shape or a cylindrical shape, and the gate structure 136 may be adjacent to a single side of the semiconductor body 130 in a plan view, for example, as shown in FIG. Figure 1 As shown. In some embodiments, the vertical transistor 126 has a structure including two or more gates, for example, a dual-gate structure, a triple-gate structure, or a full-all-around (GAA) structure. In some embodiments, the gate structure 136 includes a gate electrode 134 and a gate dielectric 132 laterally located between the gate electrode 134 and the semiconductor body 130 in a bit line direction (for example, in the x-direction). In some embodiments, the gate dielectric 132 abuts one side of the semiconductor body 130, and the gate electrode 134 abuts the gate dielectric 132.

[0062] like Figure 1As shown, in some embodiments, the semiconductor body 130 has two ends ( Figure 1 In some embodiments, the semiconductor body 130 has an upper end and a lower end in the z direction, and at least one end (e.g., the lower end) extends beyond the gate dielectric 132 into the ILD layer in the vertical direction (z direction). In some embodiments, one end (e.g., the upper end) of the semiconductor body 130 is flush with the corresponding end (e.g., the upper end) of the gate dielectric 132. In some embodiments, both ends (the upper end and the lower end) of the semiconductor body 130 extend beyond the gate electrode 134 into the ILD layer in the vertical direction (z direction). That is, the semiconductor body 130 may have a vertical dimension (e.g., in the z direction) that is larger than the vertical dimension (e.g., the depth) of the gate electrode 134, and neither the upper end nor the lower end of the semiconductor body 130 is flush with the corresponding end of the gate electrode 134. Therefore, a short circuit between the bit line 123 and the word line / gate electrode 134 or between the word line / gate electrode 134 and the capacitor 128 can be avoided. The vertical transistor 126 may further include a source and a drain (both referred to as 138 because their positions may be interchanged) disposed at two ends (upper end and lower end) of the semiconductor body 130 in the vertical direction (z direction), respectively. In some embodiments, one of the source and the drain 138 (e.g., at Figure 1 ) is coupled to capacitor 128, and the other of source and drain 138 (e.g., at Figure 1 That is, the vertical transistor 126 may have a first terminal in the positive z-direction and a second terminal opposite to the first terminal in the negative z-direction, such as Figure 1 shown.

[0063] In some embodiments, the semiconductor body 130 includes a semiconductor material such as single crystal silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 130 may include single crystal silicon. The source and drain 138 may be doped with an N+ type dopant (e.g., phosphorus (P) or arsenic (As)) or a P type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source / drain 138 of the vertical transistor 126 and the bit line 123 as a bit line contact, or between the source / drain 138 of the vertical transistor 126 and the first electrode of the capacitor 128 as a capacitor contact 142 to reduce contact resistance. In some embodiments, the gate dielectric 132 includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, the high-k dielectric including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 134 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 134 includes multiple conductive layers, such as a W layer on top of a TiN layer. In one example, the gate structure 136 can be a "gate oxide / gate polysilicon" gate, where the gate dielectric 132 includes silicon oxide and the gate electrode 134 includes doped polysilicon. In another example, the gate structure 136 can be HKMG, where the gate dielectric 132 includes a high-k dielectric and the gate electrode 134 includes a metal.

[0064] As described above, since the gate electrode 134 can be part of the word line or extend as a word line in the word line direction (e.g., the y direction), the second semiconductor structure 104 of the 3D semiconductor device 100 can also include multiple word lines, each word line extending in the word line direction (y direction). Each word line 134 can be coupled to a row of DRAM cells 124. That is, the bit lines 123 and the word lines 134 can extend in two perpendicular lateral directions, and the semiconductor body 130 of the vertical transistor 126 can extend in a perpendicular direction perpendicular to the two lateral directions in which the bit lines 123 and the word lines 134 extend. The word line 134 contacts a word line contact (not shown). In some embodiments, the word line 134 includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the word line 134 includes multiple conductive layers, such as a W layer on top of a TiN layer, such as Figure 1 shown.

[0065] In some embodiments, Figure 1As shown, the vertical transistor 126 extends vertically through and contacts the word line 134, and the source or drain 138 of the vertical transistor 126 contacts the bit line 123 (or contacts the bit line contact, if any) at its lower end. Therefore, due to the vertical arrangement of the vertical transistor 126, the word line 134 and the bit line 123 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 134 and the bit line 123. In some embodiments, the bit line 123 is vertically arranged between the bonding layer 120 and the word line 134, and the word line 134 is vertically arranged between the bit line 123 and the capacitor 128. The word line 134 can be coupled to the peripheral circuit 112 in the first semiconductor structure 102 through the word line contact (not shown) in the interconnect layer 122, the bonding contacts 121 and 119 in the bonding layers 120 and 118, and the interconnect in the interconnect layer 116. Similarly, the bit lines 123 in the interconnect layer 122 may be coupled to the peripheral circuits 112 in the first semiconductor structure 102 through the bonding contacts 121 and 119 in the bonding layers 120 and 118 and the interconnects in the interconnect layer 116 .

[0066] In some embodiments, vertical transistors 126 may be arranged in a mirror-symmetrical manner to increase the density of DRAM cells 124 in the bit line direction (x direction). Figure 1 As shown, two adjacent vertical transistors 126 in the bit line direction are mirror-symmetric to each other with respect to the trench isolation 160. That is, the second semiconductor structure 104 may include a plurality of trench isolations 160, each trench isolation 160 extending parallel to the word line 134 in the word line direction (y direction) and disposed between the semiconductor bodies 130 of two adjacent rows of vertical transistors 126. In some embodiments, the rows of vertical transistors 126 separated by the trench isolation 160 are mirror-symmetric to each other with respect to the trench isolation 160. The trench isolation 160 may be formed with a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. It should be understood that the trench isolation 160 may include air gaps, each of which is disposed laterally between adjacent semiconductor bodies 130. The air gaps may be formed due to the relatively small spacing of the vertical transistors 126 in the bit line direction (e.g., x direction). On the other hand, the relatively large dielectric constant of air in the air gap (e.g., about 4 times the dielectric constant of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the insulation effect between the vertical transistors 126 (and the rows of DRAM cells 124). Similarly, in some embodiments, air gaps are also formed laterally between the word lines / gate electrodes 134 in the bit line direction, depending on the spacing of the word lines / gate electrodes 134 in the bit line direction.

[0067] like Figure 1As shown, in some embodiments, capacitor 128 includes a first electrode 144 above the source or drain 138 of vertical transistor 126 (e.g., the upper end of semiconductor body 130) and coupled to the source or drain 138 of vertical transistor 126 via capacitor contact 142. In some embodiments, capacitor contact 142 is an ohmic contact, such as a metal silicide contact, as opposed to a Schottky contact. For example, capacitor contact 142 can include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a conductivity greater than that of doped silicon. Capacitor 128 can also include a capacitor dielectric above and in contact with first electrode 144, and a second electrode above and in contact with the capacitor dielectric. That is, capacitor 128 can be a vertical capacitor in which the electrodes and the capacitor dielectric are stacked vertically (in the z direction), and the capacitor dielectric can be sandwiched between the electrodes. In some embodiments, each first electrode is coupled to a source or drain 138 of a corresponding vertical transistor 126 in the same DRAM cell, and all second electrodes are coupled to a common plate 146, which is coupled to ground (e.g., a common ground). Capacitor 128 can have a first end in the negative z-direction and a second end opposite the first end in the positive z-direction, such as Figure 1 In some embodiments, the first end of capacitor 128 is coupled to the first terminal of vertical transistor 126 via an ohmic contact (eg, capacitor contact 142 made of a metal silicide material). Figure 1 As shown, the second semiconductor structure 104 may further include a capacitor contact 147 (e.g., a conductor) in contact with the common plate 146 for coupling the capacitor 128 to the peripheral circuit 112 or directly to the ground. In some embodiments, the capacitor contact 147 (e.g., a conductor) extends from the dielectric layer of the bonding layer 120 in the z direction to couple to the second end of the capacitor 128 via the common plate 146, as shown in FIG. Figure 1 In some embodiments, the ILD layer in which capacitor 128 is formed has the same dielectric material as the two ILD layers into which semiconductor body 130 extends, such as silicon oxide.

[0068] It should be understood that the structure and configuration of capacitor 128 is not limited to Figure 1, and may include any suitable structure and configuration, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-substrate capacitor. In some embodiments, the capacitor dielectric includes a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, the high-k dielectric including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, capacitor 128 can be a ferroelectric capacitor used in a FRAM cell, and the capacitor dielectric can be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, the electrode includes a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof.

[0069] like Figure 1 As shown, the vertical transistor 126 vertically extends through and contacts the word line 134, the source or drain 138 of the vertical transistor 126 contacts the bit line 123 at its lower end, and the source or drain 138 of the vertical transistor 126 is coupled to the capacitor 128 at its upper end. That is, due to the vertical arrangement of the vertical transistor 126, the bit line 123 and the capacitor 128 can be arranged in different planes in the vertical direction and coupled to opposite ends of the vertical transistor 126 of the DRAM cell 124 in the vertical direction. In some embodiments, the bit line 123 and the capacitor 128 are arranged on opposite sides of the vertical transistor 126 in the vertical direction, which simplifies the wiring of the bit line 123 and reduces the coupling capacitance between the bit line 123 and the capacitor 128 compared to a DRAM cell in which the bit line and the capacitor are arranged on the same side of a planar transistor.

[0070] like Figure 1 As shown, in some embodiments, the vertical transistor 126 is vertically disposed between the capacitor 128 and the bonding interface 106. That is, the vertical transistor 126 can be disposed closer to the peripheral circuit 112 of the first semiconductor structure 102 and the bonding interface 106 than the capacitor 128. Since the bit line 123 and the capacitor 128 are coupled to opposite ends of the vertical transistor 126, the bit line 123 (as part of the interconnect layer 122) is vertically disposed between the vertical transistor 126 and the bonding interface 106. As a result, the interconnect layer 122 including the bit line 123 can be disposed close to the bonding interface 106 to reduce the interconnect routing distance and complexity.

[0071] In some embodiments, the second semiconductor structure 104 also includes a substrate 148 disposed above the DRAM cell 124. As described below with respect to the manufacturing process, the substrate 148 can be part of a carrier wafer. It should be understood that in some examples, the substrate 148 may not be included in the second semiconductor structure 104.

[0072] like Figure 1 As shown, the second semiconductor structure 104 may further include a pad output interconnect layer 150 above the substrate 148 and the DRAM cell 124. The pad output interconnect layer 150 may include interconnects in one or more ILD layers, such as contact pads 154. The pad output interconnect layer 150 and the interconnect layer 122 may be formed on opposite sides of the DRAM cell 124. The capacitor 128 may be vertically disposed between the vertical transistor 126 and the pad output interconnect layer 150. In some embodiments, the interconnects in the pad output interconnect layer 150 may transmit electrical signals between the 3D semiconductor device 100 and an external circuit, for example, for pad output purposes.

[0073] In some embodiments, the second semiconductor structure 104 also includes one or more contacts 152 extending through the substrate 148 and a portion of the pad output interconnect layer 150 to couple the pad output interconnect layer 150 to the DRAM cell 124 and the interconnect layer 122. As a result, the peripheral circuit 112 can be coupled to the DRAM cell 124 through the interconnect layers 116 and 122 and the bonding layers 120 and 118, and the peripheral circuit 112 and the DRAM cell 124 can be coupled to an external circuit through the contacts 152 and the pad output interconnect layer 150. The contact pads 154 and the contacts 152 may include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In one example, the contact pads 154 may include Al, and the contacts 152 may include W. In some embodiments, the contacts 152 include vias surrounded by dielectric spacers (e.g., with silicon oxide) to electrically separate the vias from the substrate 148. Depending on the thickness of substrate 148 , contacts 152 may be ILVs with a depth of sub-micrometers (eg, between 10 nm and 1 μm) or TSVs with a depth of micrometers or tens of micrometers (eg, between 1 μm and 100 μm).

[0074] Although not shown, it should be understood that the pad output of the 3D memory device is not limited to the output from Figure 1 The second semiconductor structure 104 is shown with a DRAM cell 124 and may be from the first semiconductor structure 102 with the peripheral circuit 112. Although not shown, it is also understood that the air gaps between the word lines 134 and / or between the semiconductor bodies 130 may be partially or completely filled with a dielectric. Although not shown, it is also understood that arrays of more than one DRAM cell 124 may be stacked on top of each other to vertically scale up the number of DRAM cells 124.

[0075] Figure 22 shows a perspective view of an example 3D semiconductor device 200. The 3D semiconductor device 200 may be Figure 1 The 3D semiconductor device 100 or Figure 1 FIG. 1 is a diagram of an intermediate structure of a 3D semiconductor device 100 during a manufacturing process.

[0076] like Figure 2 As shown, the 3D semiconductor device 200 has a front side 201 and a back side 203 along a vertical direction (Z direction). The 3D semiconductor device 200 includes a plurality of bit lines 202 separated by an isolation material 204 (eg, oxide) on the back side 203. The bit lines 202 may be connected to Figure 1 The bit lines 202 may be similar or identical to the bit lines 123. The bit lines 202 may be separated along the Y direction and extend along the X direction. Figure 2 As shown, the bit line 202 has a depth along the vertical direction (Z direction). As discussed in further detail below, for example, in Figures 5A-5D In 6A-6B, the bit line 202 may be formed by depositing a metal material (e.g., Ni) layer on a plurality of alternating strips of a semiconductor material (e.g., Si) and an isolation material 204 (e.g., oxide), and forming a composite conductive material based on the metal material and the semiconductor material (e.g., silicide such as NiSi) in corresponding strips of the semiconductor material. Therefore, the bit line 202 may be self-aligned.

[0077] The 3D semiconductor device 200 may include a memory cell string on a front side 201. Each memory cell string may be coupled to a corresponding bit line 202. The memory cells may be connected to Figure 1 The memory cell may include a vertical transistor (e.g., Figure 1 The vertical transistor 126) and the capacitor coupled to the vertical transistor (eg, Figure 1 In some embodiments, the gate structures of the two vertical transistors 212, 214 (e.g., Figure 1 The gate structures 136 of the trench structures 210 may be formed in the trench structures 210 and separated by isolation materials 216 (eg, oxide) in the trench structures 210. Adjacent trench structures 210 (or adjacent vertical transistors in adjacent trench structures 210) may be separated in the X direction by isolation regions 220 (eg, Figure 1 The trench isolation 160) separates them.

[0078] Figure 3A A cross-sectional view (eg, in an XZ plane) of an example 3D semiconductor device 300 including vertical transistors and bit lines is shown. Figure 3B Shows Figure 3A 3D semiconductor device 300 is a top view (eg, in the XY plane) of an example 3D semiconductor device 300. 3D semiconductor device 300 may be Figure 2 The 3D semiconductor device 200 or Figure 1 The 3D semiconductor device 100 or Figure 1 The 3D semiconductor device 300 can be manufactured by Figure 4A-4B , 5A-5D, 6A-6B and / or 7A-7B are formed by the methods and / or processes further described in detail.

[0079] like Figure 3B As shown, the 3D semiconductor device 300 includes a plurality of bit lines 302 extending along the X direction and a plurality of word lines (WL1, W2, ..., WL8, ...) 304 extending along the Y direction. Adjacent bit lines 302 are separated along the Y direction by an isolation material (e.g., such as Figure 2 The bit lines 302 may be separated from the adjacent word lines 304 by an isolation region 306 along the X direction. Figure 1 The bit line 123 or Figure 2 The isolation region 306 may be similar or identical to the bit line 202. Figure 1 The trench isolation 160 or Figure 2 The isolation regions 306 may be similar or identical to the isolation regions 220 of the semiconductor bodies 314. The isolation regions 306 may be formed of dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. It should be understood that the isolation regions 306 may include air gaps laterally disposed between adjacent semiconductor bodies 314 (e.g., along the X direction).

[0080] The 3D semiconductor device 300 has a semiconductor substrate 301 including a semiconductor material (eg, silicon). Figure 1 An array of memory cells 124 of the embodiment of the present invention may be formed in a semiconductor substrate 301. Each memory cell may include a vertical transistor 310 (eg, Figure 1 The vertical transistor 126 or Figure 2 vertical transistor 212 or 214) and a capacitor coupled to vertical transistor 310 (e.g., Figure 1 The vertical transistor 310 may include a gate electrode (or gate terminal) 312, a semiconductor body 314, a first terminal 315 and a second terminal 316 formed on opposite ends of the semiconductor body 314 along a vertical direction (e.g., a Z direction). One of the first terminal 315 and the second terminal 316 may be a source terminal, and the other of the first terminal 315 and the second terminal 316 may be a drain terminal. The first terminal 315 and the second terminal 316 may be connected to Figure 1 The terminals 138 are similar or identical.

[0081] The semiconductor body 314 may be Figure 1 The semiconductor body 314 may be similar or identical to the semiconductor body 130 of the present invention. The semiconductor body 314 may include a semiconductor material, such as single crystal silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 314 may include single crystal silicon. As discussed in further detail below, each of the first terminal 315 and the second terminal 316 may be formed by implanting N+ type ions (e.g., P or As) or P type ions (e.g., B or Ga) into the end of the semiconductor body 314 at a desired doping level. In one example, the first terminal 315 represents a drain terminal (e.g., a lightly doped drain-LDD), and the second terminal 316 represents a source terminal. In another example, the first terminal 315 represents a source terminal, and the second terminal 316 represents a drain terminal.

[0082] The gate electrode 312 may include one or more conductive layers, such as a W layer 312a on a TiN layer 312b, such as Figure 3A The isolation material 311 may be formed as a gate dielectric (eg, Figure 1 The gate electrode 312 may be a part of the word line 304 or extend in the word line direction (eg, Y direction) as the word line 304. The gate electrode 312 and the gate dielectric may form a gate structure (eg, Figure 1 gate structure 136).

[0083] In some embodiments, the 3D semiconductor device 300 includes trench structures 308 (eg, Figure 2 The trench structure 210 of the embodiment of the present invention. A pair of gate electrodes 312 of the vertical transistors 310 may be formed in the trench structure 308 and separated by the isolation material 311. The bottom ends of the gate electrodes 312 of the vertical transistors 310 in the trench structure 308 may be separated by one or more isolation layers 307 (e.g., oxide), 317 (e.g., SiN), and 318 (e.g., oxide). The gate electrode 312 may be separated and isolated from the first terminal 315 and the second terminal 316, for example, by the isolation material 311. For example, as Figure 3A As shown, along the Z direction, the bottom of the gate electrode 312 is higher than the top surface of the second terminal 316 , and the bottom of the second terminal 316 may be higher than the bottom of the trench structure 308 .

[0084] The first terminal 315 of the vertical transistor 310 can be connected to the capacitor contact 322 (eg, Figure 1 The capacitor contact 142 of the embodiment is coupled to the first electrode 324 of the capacitor (e.g., Figure 1The capacitor contact 322 may include a via contact including a conductive material (e.g., polysilicon). The first electrode 324 may include one or more conductive layers, for example, a metal silicide 324a, an intermediate layer 324b (e.g., a TiN layer), and a metal layer 324c (e.g., a W layer) in contact with the capacitor contact 322. A dielectric layer 320 (e.g., including SiN) may be formed on top of the semiconductor substrate 301. The capacitor contact 322 may be at least partially formed in the dielectric layer 320 and may extend into the trench structure 308 to contact the first terminal 315 of the vertical transistor 310.

[0085] In some embodiments, the second terminal 316 of the vertical transistor 310 is coupled to the bit line 302, for example, through the intermediate region 313. The intermediate region 313 can be between the bottom of the second terminal 316 of the vertical transistor 310 and the bit line 302. The intermediate region 313 can also be between the bottom of the trench structure 308 and the bit line 302. As discussed in further detail below, for example Figure 5B-5C The middle region 313 may be formed by implanting N+ type ions (e.g., P or As) into the back side of the semiconductor substrate 301. The ions implanted into the semiconductor substrate 301 may be referred to as dopants. The middle region 313 may have a higher dopant concentration than the second terminal 316 of the vertical transistor 310.

[0086] As discussed in further detail below, for example Figure 5D and 6B , the bit line 302 can be formed by depositing a metal material (e.g., Ni) layer on the middle region 313 (e.g., alternating strips of semiconductor material (e.g., Si) with implanted dopants and isolation material (e.g., oxide)), and then forming a composite conductive material (e.g., NiSi) based on the metal material and the semiconductor material with implanted dopants in the corresponding strips of the semiconductor material. In contrast, the metal material does not react with the isolation material (e.g., oxide). Therefore, the metal material can be easily removed from the surface of the strip of isolation material during an etching process (e.g., wet etching), and the composite conductive material in the corresponding strip of semiconductor material can remain unchanged during the etching process, and a self-aligned bit line can be formed. The composite conductive material can be a silicide, such as a metal silicide.

[0087] Figure 4A An example structure 400 is shown, showing the terminals of a vertical transistor formed by implanting N+ type ions from the front side of a semiconductor substrate 401. The vertical transistor can be connected to Figure 1 The vertical transistor 126, Figure 2 The vertical transistors 212, 214 or Figure 3A The vertical transistors 310 are similar or identical.

[0088] The structure 400 includes a trench 420 for forming a gate structure of a vertical transistor. The gate structure may be Figure 1 The gate structure 136 is similar or identical to the gate structure 136. The gate structure includes a gate electrode (eg, Figure 1 The gate electrode 134 or Figure 3A The gate electrode 312 of the vertical transistor and the gate electrode and the semiconductor body 402 of the vertical transistor (eg, Figure 1 The semiconductor body 130 or Figure 3A The gate dielectric (eg, Figure 1 The structure 400 includes a dielectric layer 405 (e.g., oxide) on the inner surface of the trench 420, which can be used to form a gate dielectric of a gate structure of a vertical transistor. In addition, the dielectric layer 405 can protect the semiconductor body 402 from N+ type ions in a later process step of implanting N+ type ions from the opening of the trench 420 to the bottom of the trench 420.

[0089] The structure 400 may include an isolation region 410 between adjacent trenches 420 of a vertical transistor or between adjacent semiconductor bodies 402. The isolation region 410 may be Figure 1 Trench isolation 160, Figure 2 Isolation area 220 or Figure 3A The isolation regions 410 may be similar or identical to the isolation regions 306. The isolation regions 410 may be formed with a dielectric material 412 that surrounds an air gap 414 that is laterally disposed between adjacent semiconductor bodies 402 (eg, along the X-direction).

[0090] In structure 400, a first terminal 404 of a vertical transistor (eg, Figure 3A The first terminal 315 of the vertical transistor is formed on a first end (eg, top end) of the semiconductor body 402 at the front side of the semiconductor substrate 401, for example, by implanting N+ type ions from the front side of the semiconductor substrate 401 into the region of the first terminal 404. The first terminal 404 may be an LDD.

[0091] To form a second terminal 406 (eg, a bottom end) at a second end (eg, a bottom end) of the semiconductor body 402 of the vertical transistor, Figure 3A The second terminal 316 of Figure 4AAs shown, N+ type ions can be implanted from the opening of the trench 420 at the front side of the semiconductor substrate 401 to the bottom of the trench 420. The implanted ions can diffuse to the region of the second terminal 406 to form the second terminal 406 of the vertical transistor. One of the first terminal 404 and the second terminal 406 is a source terminal, and the other of the first terminal 404 and the second terminal 406 is a drain terminal. In one example, the width of the opening of the trench 420 is about tens of nm, for example, 40nm to 50nm.

[0092] Figure 4B Another example structure 430 is shown, showing the terminals of the vertical transistor formed by implanting N+ type ions from the back side of the semiconductor substrate 401. The vertical transistor can be connected to Figure 1 The vertical transistor 126, Figure 2 The vertical transistors 212, 214 or Figure 3A The vertical transistors 310 are similar or identical.

[0093] In forming the second terminal 436 of the vertical transistor (eg, Figure 3A Before forming the second terminal 316 of the vertical transistor, the first terminal 404 of the vertical transistor (eg, Figure 3A The first terminal 315 of the embodiment of the present invention) and / or the gate structure 432 (eg, Figure 1 The gate structure 432 may include a gate electrode 433 and a gate electrode 434 coupled to the gate electrode 433 (eg, Figure 1 The gate electrode 134 or Figure 3A The gate dielectric 434 (eg, Figure 1 Adjacent gate structures 432 in the same trench may be separated by an isolation material 431 (eg, Figure 2 Isolation material 216 or Figure 3A The gate structures 432 in the same trench may be isolated by the isolation material 311 of the present invention, and the gate structures 432 in the same trench may be covered by the isolation material 431. The gate structures 432 in the same trench may be separated by one or more isolation layers (eg, SiN layer 437 and oxide layer 438) on the bottom of the trench.

[0094] and Figure 4A In order to form the second terminal 436 of the vertical transistor (eg, Figure 3A The second terminal 316 of Figure 4BIn the embodiment, N+ type ions (e.g., P) are implanted from the back side of the semiconductor substrate 401. The structure 430 can be flipped over, and the semiconductor substrate 401 can be thinned from the back side (e.g., by chemical mechanical polishing - CMP) to a thickness of, for example, about 100 nm. Then, the N+ type ions can be implanted directly into the back side of the semiconductor substrate 401 to form a second terminal 436 at the bottom end of the semiconductor body 402, which can be more convenient than forming a second terminal 436. Figure 4A In addition, since the second terminal 436 is formed by direct implantation rather than diffusion, the second terminal 436 can have a larger diameter than the second terminal 406. Figure 4A In addition, since N+ type ions are implanted in the entire area of ​​the back side of the semiconductor substrate 401, the process window is much larger than Figure 4A The opening of the trench 420 for implantation from the front side of the semiconductor substrate 401 is shown.

[0095] In some embodiments, prior to implanting N+ type ions, germanium (Ge) pre-amorphization implantation (Ge PAI) is performed for low thermal activation. In some examples, semiconductor ions (e.g., Ge ions) are implanted at a certain depth (e.g., in the range of 20nm to 40nm), and then N+ type ions (e.g., P ions) are implanted, and the structure is activated at a low temperature (e.g., 500°C to 600°C) below the nominal temperature (e.g., 900°C).

[0096] Figures 5A-5D Cross-sectional views (in the XZ plane) of the structure of a 3D semiconductor device at various stages of the fabrication process are shown. Figure 6A-6B A cross-sectional view (in the YZ plane) of some structures of a 3D semiconductor device is shown to further illustrate the manufacturing process. A 3D semiconductor device may be Figure 3A-3B 3D semiconductor device 300, Figure 2 3D semiconductor device 200, Figure 1 The 3D semiconductor device 100 or Figure 1 FIG. 1 is a diagram of an intermediate structure of a 3D semiconductor device 100 during a manufacturing process.

[0097] The 3D semiconductor device includes a vertical transistor 510 (eg, Figure 1 The vertical transistor 126, Figure 2 The vertical transistors 212, 214 or Figure 3A The vertical transistor 510 extends along a vertical direction (eg, a Z direction). As described above, the vertical transistor 510 may include a semiconductor body 512 (eg, Figure 1 A semiconductor body 130, Figure 3A The semiconductor body 314 or Figure 4A or semiconductor body 402 of 4B), a first terminal 514 (eg, Figure 3A The first terminal 315 or Figure 4A or a first terminal 404 of 4B) and a second terminal 516 (eg, Figure 3A The second terminal 316 or Figure 4B ), a gate structure 518 coupled to the semiconductor body 512 (eg, Figure 1 The gate structure 136 or Figure 4B For the purpose of illustration, Figures 5A-5D , the components in the structure are simplified, and only one vertical transistor 510 is shown in detail.

[0098] In some embodiments, a 3D semiconductor device includes a trench structure 520 (eg, Figure 2 The trench structure 210 or Figure 3A In some embodiments, the trench structures 520 are separated by isolation regions 530 along a lateral direction (eg, X direction). In some embodiments, the isolation regions 530 include air gaps, for example, Figure 1 Isolation area 160, Figure 2 Isolation area 220, Figure 3A The isolated area 306 or Figure 4A 4B. In some embodiments, the isolation region 530 includes a conductive structure (e.g., including a metal material such as W). The conductive structure can be coupled to a low voltage (e.g., a negative voltage), which can reduce or eliminate back coupling effects or row hammer effects. In some cases, the conductive structure can contact at least one of the adjacent semiconductor bodies 512, which can reduce or eliminate floating body effects. The gate structures 518 of a pair of vertical transistors 510 can be formed in the trench structure 520 and separated by the isolation material 502 (e.g., oxide).

[0099] Figure 5A Shown with Figure 4B The structure 500a may be similar or identical to the structure 430. The structure 500a may include, for example, a first terminal 514 and a gate structure 518 formed from the front side of the semiconductor substrate 501. Figure 5A As shown, the back side of structure 500a faces upward for subsequent ion implantation, for example, to form second terminal 516 of vertical transistor 510. Thus, structure 500a may include an unfinished vertical transistor 510. Structure 500a may have a thinned semiconductor substrate on the back side, for example, with a thickness of about 100 nm.

[0100] Fig. 6A5 shows a cross-sectional view of the back side of structure 500a. Fig. 6A As shown, alternating strips of semiconductor material (e.g., Si) 602 and isolation material (e.g., oxide) 604 are formed along the Y direction. In some embodiments, the strips of isolation material 604 are formed by etching the semiconductor substrate 501 to form trenches and filling the trenches with isolation material 604 from the front side of the semiconductor substrate 501. The semiconductor substrate 501 can be thinned from the back side (e.g., by CMP) to expose the strips of semiconductor material 602 and isolation material 604. The strips of semiconductor material 602 and isolation material 604 can extend into the semiconductor substrate 501 with a thickness of, for example, about 100 nm.

[0101] Figure 5B The structure 500b is shown after N+ type ions (eg, P ions) are implanted into the semiconductor substrate 501 from the back side of the structure 500a. The region 540 of the semiconductor substrate having the implanted ions may be connected to the semiconductor substrate 501. Figure 3A The region 540 may be similar or identical to the middle region 313 of the semiconductor body 512. In some embodiments, the region 540 may extend to the end of the semiconductor body 512, for example, Figure 3A As shown. The second terminal 516 can be formed at the end of the semiconductor body 512. Note that Fig. 6A As shown, the back side of structure 500a includes alternating strips of semiconductor material 602 and isolation material 604. N+ type ions may be implanted into the strips of semiconductor material 602, but not into the strips of isolation material 604.

[0102] In some embodiments, semiconductor ions are first implanted before implanting N+ type ions, for example, using Ge pre-amorphization implantation (Ge PAI) for low thermal activation. In some examples, Ge ions are implanted at a certain depth (e.g., in the range of 20nm to 40nm), and then N+ type ions (e.g., P ions) are implanted, and then the structure 500b can be activated at a low temperature (e.g., in the range of 500°C to 600°C). The temperature can be lower than the nominal temperature (e.g., about 900°C) for activating N+ type ions without implanting Ge ions.

[0103] Figure 5C Structure 500c is shown after forming a metal layer 550 on the surface of the back side of structure 500b. Metal layer 550 may cover both the strips of semiconductor material 602 (eg, region 540) and the strips of isolation material 604. Metal layer 550 may include a metallic material, such as Ni.

[0104] Figure 5DStructure 500d is shown after an annealing process is performed on structure 500c. The metal material of metal layer 550 and the semiconductor material of semiconductor substrate 501 (e.g., the strip of semiconductor material 602) can react during the annealing process to form a composite conductive material 560, such as a silicide. In some examples, the metal material includes Ni, the semiconductor material includes Si, and the composite conductive material includes NiSi.

[0105] After the annealing process, the residue of the metal material of the metal layer 550 may be removed from the back side of the semiconductor substrate 501, for example, by etching (e.g., wet etching). Since the metal material of the metal layer 550 does not react with the strips of the isolation material 604, the metal material on the strips of the isolation material 604 may be removed, for example, Figure 6B Instead, layer 608 of composite conductive material 560 is formed as a bit line (e.g., Figure 1 The bit line 123, Figure 2 The bit line 202 or Figure 3A-3B A layer 608 of composite conductive material 560 may be formed on top of layer 606 of semiconductor material 602, with N+ type dopants implanted in region 540. In this way, a self-aligned bit line is formed on the back side of semiconductor substrate 501.

[0106] Fig. 7A is a flow chart of an example process 700 for forming a semiconductor device. The semiconductor device may be Figure 3A-3B 3D semiconductor device 300, Figure 2 3D semiconductor device 200, Figure 1 3D semiconductor device 100, Figure 1 A structure in an intermediate manufacturing process of the 3D semiconductor device 100, or Figure 5D The structure of 500d. Figures 5A-5D and Figure 6A-6B Process 700 is described. Process 700 includes operations (or steps) that may be performed in any suitable order and / or in any combination.

[0107] In operation 710, a plurality of memory cell strings are formed in a first side of a semiconductor substrate along a vertical direction. The semiconductor substrate includes a semiconductor material (eg, Si). The semiconductor substrate may be formed with Figure 1 a first semiconductor substrate 104, Figure 3A-3B A semiconductor substrate 301, Figure 4A-4B The semiconductor substrate 401 or Figure 5A The semiconductor substrate 501 is similar to or the same as the semiconductor substrate 502. The vertical direction may be the Z direction. The first side of the semiconductor substrate may be the front side of the semiconductor substrate. The memory cell may be Figure 1 A memory cell 124, for example, a DRAM memory cell.

[0108] The memory cell may include a vertical transistor (eg, Figure 1 The vertical transistor 126, Figure 2 The vertical transistors 212, 214, Figure 3A The vertical transistor 310 or Figures 5A-5D In some embodiments, for example, Figure 1 , 3A , 4B or 5A-5D, the vertical transistor includes a semiconductor body (eg, Figure 1 A semiconductor body 130, Figure 3A The semiconductor body 314, Figure 4B The semiconductor body 402 or Figures 5A-5D 512), a first terminal and a second terminal at opposite ends of the semiconductor body (eg, Figure 1 Terminal 138 of FIG. 3, terminals 315, 316, Figure 4B Terminals 404 and 436 or Figures 5B-5D 514, 516), and a gate structure coupled to the semiconductor body (eg, Figure 1 The gate structure 136, Figure 4B The gate structure 432 or Figures 5A-5D The gate structure may include a vertical gate electrode ( Figure 1 The gate electrode 134, Figure 3A The gate electrode 312 or Figure 4B A gate electrode 433) and a gate dielectric (eg, Figure 1 The gate dielectric 132, Figure 3A The gate dielectric 311 or Figure 4B of gate dielectric 434).

[0109] In some embodiments, forming a plurality of memory cell strings includes: forming a plurality of memory cell strings in a same trench (eg, Figure 4A The process 700 further comprises forming a gate terminal (e.g., a vertical gate electrode) of a pair of independent vertical transistors in the trench 420 of FIG. 4 . The gate terminals may be separated by an isolation material (e.g., an oxide) along a lateral direction (e.g., an X direction) perpendicular to the vertical direction. In some embodiments, the process 700 further comprises forming an isolation region between adjacent pairs of independent vertical transistors along the lateral direction. The isolation region may be Figure 1 Trench isolation 160, Figure 2 Isolation area 220, Figure 3A Isolation area 306, Figure 4Aor the isolation region 410 of 4B or Figures 5A-5D The isolation region 530 is similar or identical to the isolation region 530. In some examples, the isolation region includes an air cavity surrounded by an isolation material or a cavity filled with a metal material.

[0110] In operation 720, a semiconductor material and an isolation material (eg, a Y direction) are formed in a second side (eg, a back side) of the semiconductor substrate along a horizontal direction (eg, a Y direction) perpendicular to the vertical direction. Figure 6A-6B 602 and 604), the second side being opposite to the first side along a vertical direction.

[0111] In some embodiments, forming a plurality of alternating strips of semiconductor material and isolation material in the second side of the semiconductor substrate includes: thinning the semiconductor substrate from the second side of the semiconductor substrate to expose the plurality of alternating strips of semiconductor material and isolation material, e.g. Fig. 6A shown.

[0112] At operation 730, a plurality of bit lines are formed in the second side of the semiconductor substrate. The bit lines may be, for example, Figure 1 The bit line 123, Figure 2 The bit line 202 or Figure 3A-3B In some embodiments, the operation 730 of forming a plurality of bit lines includes: depositing a layer of metal material (eg, Figure 5C The metal layer 550)(732), for example, Figure 5C As shown, and by forming a composite conductive material based on a metal material and a semiconductor material in a corresponding strip of semiconductor material of a plurality of alternating strips, each bit line (734) of a plurality of bit lines is formed in the corresponding strip of semiconductor material, for example, as Figure 5D Or as shown in 6B.

[0113] In some embodiments, forming a composite conductive material based on a metal material and a semiconductor material in corresponding strips of semiconductor material includes: annealing the metal material and the semiconductor material so that the metal material reacts with the semiconductor material to form the composite conductive material. There may be no reaction between the isolation material and the metal material deposited on the isolation material. In some embodiments, the semiconductor material includes silicon, the isolation material includes an oxide, and the composite conductive material includes a silicide. In some examples, the metal material includes nickel (Ni).

[0114] In some embodiments, after forming the plurality of bit lines in the second side of the semiconductor substrate, process 700 further includes removing residues of the metal material from the second side of the semiconductor substrate, such as by wet etching the residues of the metal material. The residues of the metal material may include metal material on the strips of isolation material and remaining metal material on the bit lines.

[0115] In some embodiments, for example, Figure 5B As shown, process 700 includes implanting ions (eg, N+ type ions such as P ions) into the second side of the semiconductor substrate. A composite conductive material may be formed based on a metal material and a semiconductor material with implanted ions.

[0116] In some embodiments, implanting ions into the second side of the semiconductor substrate includes, for example, implanting semiconductor ions (e.g., Ge ions) into the second side of the semiconductor substrate using a Ge PAI technique, and implanting N+ ions into the second side of the semiconductor substrate, and activating the implanted N+ ions with the implanted semiconductor ions at an activation temperature. In some examples, the semiconductor material includes silicon, the semiconductor ions include germanium (Ge) ions, and the N+ ions include arsenic (As) ions or phosphorus (P) ions. The activation temperature may be lower than a nominal temperature for activating N+ ions without implanting semiconductor ions. In some examples, the nominal temperature is about 900°C, and the activation temperature is in the range of about 500°C to about 600°C.

[0117] In some embodiments, thinning the semiconductor substrate from the second side of the semiconductor substrate includes etching semiconductor material in the second side of the semiconductor substrate and polishing a top surface of the etched semiconductor material in the second side of the semiconductor substrate, such as by CMP.

[0118] In some embodiments, forming the plurality of memory cell strings includes: forming a first terminal of the vertical transistor by implanting ions from a first side of the semiconductor substrate, and forming a second terminal of the vertical transistor by implanting ions into a second side of the semiconductor substrate (e.g., Figure 4B In some embodiments, each of the plurality of bit lines is formed on and coupled to the second terminal of the vertical transistor, for example, as shown in FIG. Figure 1 Or as shown in 3A.

[0119] In some embodiments, each memory cell in the plurality of memory cell strings further includes a capacitor (eg, Figure 1 The capacitor 128 may be formed before forming the vertical transistor, and the capacitor may be located above the vertical transistor along a vertical direction (eg, Z direction).

[0120] In some embodiments, a plurality of memory cell strings and a plurality of bit lines are formed on an array die (eg, Figure 1Process 700 may also include bonding the control die (e.g., the array die) to the front side of the control die by bonding the first side of the semiconductor substrate to the front side of the control die and conductively coupling one or more conductive lines of the array die to the control circuit in the front side of the control die. Figure 1 A first semiconductor structure or control die 102) is integrated with the array die.

[0121] In some embodiments, for example, Figure 3A As shown, a plurality of bit lines are located on a semiconductor material layer having implanted ions. The implanted ions may include semiconductor ions and N+ type ions. In some examples, the semiconductor material includes silicon, the semiconductor ions include germanium (Ge) ions, the N+ type ions include arsenic (As) ions or phosphorus (P) ions, and the composite conductive material includes silicide.

[0122] In some embodiments, for example, Figure 3A As shown, a portion of the semiconductor material layer having implanted ions is configured as a terminal of a vertical transistor (eg, Figure 3A The second terminal 316, Figure 4B The second terminal 436 or Figures 5B-5D The second terminal 516 of the device is conductively coupled to the corresponding bit line.

[0123] Figure 7B is a flow chart of another example process 750 for forming a semiconductor device. The semiconductor device may be Fig. 7A Process 750 includes the following steps: Fig. 7A The operations may be similar or identical to the operations in process 700. The operations may be performed in any suitable order and / or in any combination.

[0124] In operation 752, with Fig. 7A Similar to or identical to operation 710, a plurality of memory cell strings are formed in a first side (eg, front side) of a semiconductor substrate along a vertical direction (eg, Z direction). The semiconductor substrate may include a semiconductor material (eg, Si).

[0125] At operation 754, the semiconductor substrate is thinned along a vertical direction from a second side (eg, a back side) of the semiconductor substrate. The second side is opposite to the first side of the semiconductor substrate. For example, Figure 4B or Figure 5A As shown, a first terminal (eg, Figure 3A The first terminal 315, Figure 4B The first terminal 404, Figure 5A The first terminal 514) and / or the gate structure (eg, Figure 4B The gate structure 432 or Figure 5AAfter the gate structure 518 is formed, the structure is flipped and the semiconductor substrate can be thinned from the second side, for example, by CMP. In some embodiments, the semiconductor substrate is thinned to expose multiple alternating strips of semiconductor material and isolation material, for example, Fig. 6A shown.

[0126] At operation 756, semiconductor ions are implanted into the second side of the semiconductor substrate. Process 750 may also include implanting N+ type ions into the second side of the semiconductor substrate, and activating the implanted N+ type ions at an activation temperature. In some examples, the semiconductor material includes silicon, the semiconductor ions include germanium (Ge) ions, and the N+ type ions include arsenic (As) ions or phosphorus (P) ions. Prior to implanting the N+ type ions, Ge pre-amorphization implantation (Ge PAI) is performed by implanting Ge ions into the second side of the semiconductor substrate for low thermal activation. Thus, the activation temperature may be lower than the nominal temperature for activating the N+ type ions without implanting semiconductor ions.

[0127] In some embodiments, process 750 also includes forming a plurality of bit lines in the second side of the semiconductor substrate based on the plurality of strips of semiconductor material in the plurality of alternating strips of semiconductor material and isolation material (eg, oxide), for example, Fig. 7A Operation 730. The bit lines may be formed by depositing a metal material layer on a plurality of alternating strips of semiconductor material and isolation material, and by forming a composite conductive material based on the metal material and the semiconductor material in a corresponding strip of the plurality of strips of semiconductor material, forming each of the plurality of bit lines in the corresponding strip. The metal material may include nickel (Ni).

[0128] The composite conductive material can be formed by annealing the metal material and the semiconductor material so that the metal material reacts with the semiconductor material to form the composite conductive material. There may be no reaction between the isolation material and the metal material deposited on the isolation material. In some embodiments, the composite conductive material is formed based on the metal material and the semiconductor material with activated implanted N+ ions.

[0129] In some embodiments, each memory cell in the plurality of memory cell strings includes a vertical transistor along a vertical direction. Forming the plurality of memory cell strings includes: forming a gate terminal of the vertical transistor by depositing at least one metal layer on an inner surface of the trench along a vertical direction; forming a first terminal of the vertical transistor by implanting N+ type ions from a first side of the semiconductor substrate; and forming a second terminal of the vertical transistor by implanting N+ type ions into a second side of the semiconductor substrate. In some examples, the first terminal is a source terminal and the second terminal is a drain terminal.

[0130] Figure 8A block diagram of a system 800 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure is shown. The system 800 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 8 As shown, the system 800 may include a host device 808 and a memory system 802 having one or more 3D memory devices 804 and a memory controller 806. The host device 808 may include a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host device 808 may be configured to send data to or receive data from the one or more 3D memory devices 804.

[0131] The 3D memory device 804 may be any 3D memory device disclosed herein, such as Figure 1-7B 3D memory device shown. In some embodiments, the 3D memory device 804 includes a NAND flash memory. A memory controller 806 (also referred to as a controller circuit) is coupled to the 3D memory device 804 and a host device 808. Consistent with embodiments of the present disclosure, the 3D memory device 804 may include a plurality of conductive interconnects that contact a conductive pad in a conductive pad layer through a cover layer, and the memory controller 806 may be coupled to the 3D memory device 804 through at least one of the plurality of conductive interconnects. The memory controller 806 is configured to control the 3D memory device 804. For example, the memory controller 806 may be configured to operate a plurality of channel structures via word lines. The memory controller 806 may manage data stored in the 3D memory device 804 and communicate with the host device 808.

[0132] In some embodiments, the memory controller 806 is designed / configured to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 806 is designed / configured to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which can be used as a data storage device and enterprise storage array for mobile devices such as smart phones, tablets, laptops, etc. The memory controller 806 can be configured to control the operation of the 3D memory device 804, such as read, erase and program operations. The memory controller 806 can also be configured to manage various functions related to data stored or to be stored in the 3D memory device 804, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the memory controller 806 is also configured to process error correction code (ECC) for data read from or written to the 3D memory device 804. Any other suitable functions may also be performed by the memory controller 806 , such as formatting the 3D memory device 804 .

[0133] The memory controller 806 may communicate with an external device (e.g., the host 808) according to a specific communication protocol. For example, the memory controller 806 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini interface (SCSI) protocol, an enhanced mini disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0134] The memory controller 806 and one or more 3D memory devices 804 can be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 802 can be implemented and packaged into different types of terminal electronic products. Figure 8In one example shown, a memory controller 806 and a single 3D memory device 804 may be integrated into a memory card 802. The memory card 802 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc.

[0135] The subject matter described in the present disclosure and the implementation of the actions and operations can be implemented in digital electronic circuits, in tangibly embodied computer software or firmware, in computer hardware, including the structures disclosed in the present disclosure and their structural equivalents, or a combination of one or more thereof. The implementation of the subject matter described in the present disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier, for execution by a data processing device or for controlling the operation of the data processing device. The carrier can be a tangible non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical, optical or electromagnetic signal, which is generated to encode information for transmission to an appropriate receiver device for execution by a data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them, or a part of a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination of one or more of them. The computer storage medium is not a propagation signal.

[0136] Note that references in this disclosure to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a person skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0137] Typically, a term can be understood at least in part from usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "one," "an," or "the" can also be understood to convey singular usage or to convey plural usage. In addition, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, but can allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least in part on the context.

[0138] It should be readily understood that the meaning of "on", "over", and "on" in the present disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween. Furthermore, "over" or "on" not only means "over something" or "on something", but also may include the meaning of "over something" or "on something" with no intervening features or layers therebetween (i.e., directly on something).

[0139] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or some) elements or features as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or process steps in addition to the orientation shown in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0140] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is usually where the semiconductor devices are formed, so unless otherwise specified, the semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, so the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0141] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. The layer can extend over the entire lower or upper structure, or can have a range less than the range of the lower or upper structure. In addition, the layer can be a region of a uniform or non-uniform continuous structure whose thickness is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes at or at the layer. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, wherein one or more layers can be included, and / or one or more layers can be provided on, above and / or below it. The layer can include multiple layers. For example, the interconnect layer can include one or more conductors and contact layers (wherein contacts, interconnect lines and / or vertical interconnect paths (vias) are formed) and one or more dielectric layers.

[0142] As used herein, the term "nominal / nominal" refers to an expected or target value for a characteristic or parameter of a component or process step set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. As used herein, a range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" refers to a value of a given quantity that may vary based on a particular technology node associated with the semiconductor device in question. Based on a particular technology node, the term "approximately" may refer to a value of a given quantity that varies, for example, within 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0143] In the present disclosure, the term "horizontal / horizontally / laterally / laterally" means nominally parallel to the lateral surface of the substrate, and the term "vertical" or "vertically" means nominally perpendicular to the lateral surface of the substrate. The terms "operation" and "step" can be used interchangeably to describe a process.

[0144] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "memory string", such as a NAND string) on ​​a laterally oriented substrate such that the memory string extends in a vertical direction relative to the substrate.

[0145] The present disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature may be in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0146] The foregoing description of specific embodiments can be readily modified and / or adapted for use in a variety of applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0147] Although the present disclosure contains many specific implementation details, these should not be interpreted as limitations on the scope of the protection claimed as defined by the claims themselves, but as descriptions of features that may be specific to a particular implementation. Certain features described in the present disclosure in the context of different implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any appropriate sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and claims may be directed to sub-combinations or variations of sub-combinations.

[0148] Similarly, although operations are shown in the drawings and described in a particular order in the claims, this should not be understood as requiring that the operations be performed in the particular order shown or in a sequential order, or that all of the operations shown be performed, to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0149] Specific implementations of the subject matter have been described. Other implementations are also within the scope of the appended claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes shown in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

[0150] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A method comprising: forming a plurality of memory cell strings in a first side of a semiconductor substrate along a vertical direction, the semiconductor substrate comprising a semiconductor material; forming a plurality of alternating strips of the semiconductor material and the isolation material in a second side of the semiconductor substrate along a horizontal direction perpendicular to the vertical direction, the second side being opposite to the first side along the vertical direction; as well as forming a plurality of bit lines in the second side of the semiconductor substrate, wherein forming the plurality of bit lines comprises: depositing a layer of metallic material over the plurality of alternating strips of the semiconductor material and the isolation material; and Each of the plurality of bit lines is formed in a corresponding strip of the semiconductor material of the plurality of alternating strips by forming a composite conductive material based on the metallic material and the semiconductor material in the corresponding strip of the semiconductor material.

2. The method according to claim 1, wherein: Forming the composite conductive material based on the metal material and the semiconductor material in the corresponding strips of the semiconductor material comprises: The metal material and the semiconductor material are annealed so that the metal material reacts with the semiconductor material to form the composite conductive material.

3. The method according to claim 1 or 2, wherein: The semiconductor material includes silicon, the isolation material includes oxide, and the composite conductive material includes silicide.

4. The method according to any one of claims 1 to 3, further comprising: After forming the plurality of bit lines in the second side of the semiconductor substrate, residues of the metal material are removed from the second side of the semiconductor substrate.

5. The method according to any one of claims 1 to 4, wherein: Forming the plurality of alternating strips of the semiconductor material and the isolation material in the second side of the semiconductor substrate comprises: thinning the semiconductor substrate from the second side of the semiconductor substrate to expose the plurality of alternating strips of the semiconductor material and the isolation material, Wherein, the method further comprises: implanting ions into the second side of the semiconductor substrate, and Wherein, forming the composite conductive material based on the metal material and the semiconductor material in the corresponding strip of the semiconductor material comprises: The composite conductive material based on the metal material and the semiconductor material is formed by implanting ions.

6. The method according to claim 5, wherein: Implanting the ions into the second side of the semiconductor substrate comprises: implanting semiconductor ions into the second side of the semiconductor substrate; implanting N+ type ions into the second side of the semiconductor substrate; and The implanted N+ type ions are activated with the implanted semiconductor ions at an activation temperature.

7. The method according to claim 6, wherein: The semiconductor material includes silicon, the semiconductor ions include germanium (Ge) ions, and the N+ type ions include arsenic (As) ions or phosphorus (P) ions.

8. The method according to claim 6 or 7, wherein: The activation temperature is lower than a nominal temperature for activating the N+ type ions without implanting the semiconductor ions.

9. The method according to any one of claims 5 to 8, wherein: Thinning the semiconductor substrate from the second side of the semiconductor substrate includes: etching the semiconductor material in the second side of the semiconductor substrate; and A top surface of the etched semiconductor material in the second side of the semiconductor substrate is polished.

10. The method according to any one of claims 5 to 9, wherein: Each memory cell in the plurality of memory cell strings includes a vertical transistor along the vertical direction, and Wherein, forming the plurality of memory cell strings comprises: forming a gate terminal of the vertical transistor by depositing at least one metal layer on an inner surface of the trench along the vertical direction; forming a first terminal of the vertical transistor by implanting the ions from the first side of the semiconductor substrate; and A second terminal of the vertical transistor is formed by implanting the ions into the second side of the semiconductor substrate.

11. The method according to claim 10, wherein: Each of the plurality of bit lines is formed on and coupled to the second terminal of the vertical transistor.

12. The method according to claim 10 or 11, wherein: Each memory cell in the plurality of memory cell strings further includes a capacitor coupled to the vertical transistor, and Wherein, forming the plurality of memory cell strings comprises: The capacitor is formed before forming the vertical transistor, and is located above the vertical transistor along the vertical direction.

13. The method according to any one of claims 10 to 12, wherein: Forming the plurality of memory cell strings comprises: A pair of gate terminals of independent vertical transistors are formed in the same trench along the vertical direction, and the gate terminals are separated by an isolation material along a third direction perpendicular to the vertical direction and the horizontal direction.

14. The method according to claim 13, further comprising: Isolation regions are formed between adjacent pairs of independent vertical transistors along the third direction.

15. The method according to any one of claims 1 to 14, wherein: The plurality of memory cell strings and the plurality of bit lines are formed in an array die, and Wherein, the method further comprises: The control die is integrated with the array die by bonding the first side of the semiconductor substrate to a front side of a control die and conductively coupling one or more conductive lines of the array die to control circuitry in the front side of the control die.

16. A semiconductor device comprising: a plurality of memory cell strings in a first side of a semiconductor substrate along a vertical direction, the semiconductor substrate comprising a semiconductor material; as well as a plurality of bit lines in a second side of the semiconductor substrate, the second side being opposite to the first side along the vertical direction, wherein adjacent bit lines of the plurality of bit lines are separated by an isolation material along a horizontal direction perpendicular to the vertical direction, The plurality of bit lines are made of a composite conductive material based on the semiconductor material, and the plurality of bit lines are located on a layer of the semiconductor material having implanted ions.

17. The semiconductor device according to claim 16, wherein: The implanted ions include semiconductor ions and N+ type ions.

18. The semiconductor device according to claim 16 or 17, wherein: Each memory cell in the plurality of memory cell strings includes a vertical transistor along the vertical direction, and wherein a portion of the layer of the semiconductor material having the implanted ions is configured as a terminal of the vertical transistor and is conductively coupled to a corresponding bit line.

19. The semiconductor device according to claim 18, wherein: The gate terminals of a pair of independent vertical transistors are in the same trench along the vertical direction and are separated by an isolation material along a third direction perpendicular to the vertical direction and the horizontal direction, and The isolation region is between adjacent independent vertical transistor pairs along the third direction.

20. A system comprising: A memory device, the memory device comprising: an array structure comprising a plurality of memory cell strings in a first side of a semiconductor substrate along a vertical direction, the semiconductor substrate comprising a semiconductor material; and a plurality of bit lines located in a second side of the semiconductor substrate, the second side being opposite to the first side along the vertical direction, wherein adjacent bit lines of the plurality of bit lines are separated by an isolation material along a horizontal direction perpendicular to the vertical direction, wherein the plurality of bit lines are made of a composite conductive material based on the semiconductor material, and wherein the plurality of bit lines are located on a layer of the semiconductor material having implanted ions; and A controller is coupled to the memory device and is configured to control the memory device.

21. A method comprising: forming a plurality of memory cell strings in a first side of a semiconductor substrate along a vertical direction, the semiconductor substrate comprising a semiconductor material; thinning the semiconductor substrate from a second side of the semiconductor substrate along the vertical direction, the second side being opposite to the first side of the semiconductor substrate; as well as Semiconductor ions are implanted into the second side of the semiconductor substrate.

22. The method according to claim 21, further comprising: implanting N+ type ions into the second side of the semiconductor substrate; as well as The implanted N+ ions are activated at an activation temperature.

23. The method according to claim 22, wherein: The semiconductor material includes silicon, the semiconductor ions include germanium (Ge) ions, and the N+ type ions include arsenic (As) ions or phosphorus (P) ions.

24. The method according to claim 22 or 23, wherein: The activation temperature is lower than a nominal temperature for activating the N+ type ions without implanting the semiconductor ions.

25. The method according to any one of claims 22 to 24, wherein: Thinning the semiconductor substrate from the second side of the semiconductor substrate along the vertical direction comprises: thinning the semiconductor substrate to expose the plurality of alternating strips of semiconductor material and isolation material, and Wherein, the method further comprises: A plurality of bit lines are formed in the second side of the semiconductor substrate based on the plurality of strips of the semiconductor material of the plurality of alternating strips.

26. The method according to claim 25, wherein: Forming the plurality of bit lines in the second side of the semiconductor substrate comprises: depositing a layer of metallic material over the plurality of alternating strips of the semiconductor material and the isolation material; and Each of the plurality of bit lines is formed in a corresponding strip of the plurality of strips of the semiconductor material by forming a composite conductive material based on the metal material and the semiconductor material in the corresponding strip.

27. The method according to claim 26, wherein: Forming the composite conductive material based on the metal material and the semiconductor material in the corresponding strips includes: The metal material and the semiconductor material are annealed so that the metal material reacts with the semiconductor material to form the composite conductive material.

28. The method according to claim 27, wherein: There is no reaction between the isolation material and the metallic material deposited on the isolation material.

29. The method according to any one of claims 26 to 28, wherein: Forming the composite conductive material based on the metal material and the semiconductor material in the corresponding strips includes: The composite conductive material based on the metal material and the semiconductor material is formed using the activated implanted N+ ions.

30. The method according to any one of claims 21 to 29, wherein: Each memory cell in the plurality of memory cell strings includes a vertical transistor along the vertical direction, and Wherein, forming the plurality of memory cell strings comprises: forming a gate terminal of the vertical transistor by depositing at least one metal layer on an inner surface of the trench along the vertical direction; forming a first terminal of the vertical transistor by implanting N+ type ions from the first side of the semiconductor substrate; and A second terminal of the vertical transistor is formed by implanting the N+ type ions into the second side of the semiconductor substrate.

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