A pressure chip with high resistance uniformity and a pressure sensor based on an epitaxial process

Abstract

The present invention discloses a pressure chip with high resistance uniformity based on an epitaxial process, which relates to the technical field of sensors and includes a single-crystalline silicon-based bottom layer, a conductive layer and a pad layer formed by epitaxial deposition growth; a high-resistance single-crystalline silicon layer is formed by epitaxial growth as the conductive layer, and a plurality of resistor bars are prepared by photolithography and etching processes to suppress the resistance value deviation of the resistors and improve the resistance uniformity; the plurality of resistor bars form two resistor groups and are symmetrically distributed in a double-M shape to form a Wheatstone bridge; wherein, a single resistor group and an internal connection solder joint form an M-shaped structure, which can increase the resistance path length of the resistor bars and the uniform stress distribution, and obtain a high piezoresistive coefficient and high sensitivity; and the double-M-shaped symmetrical structure can effectively cancel the resistance drift caused by temperature changes, thereby suppressing common-mode interference and improving the temperature stability and anti-interference ability of the sensor; it solves the problems of low resistance uniformity and insufficient measurement accuracy of existing pressure chips due to uneven etching thickness and doping fluctuations.

Description

Technical Field

[0001] The present invention relates to the technical field of sensors, and particularly relates to a pressure chip and a pressure sensor with high resistance uniformity based on an epitaxial process. Background Art

[0002] As a key component for measuring pressure, pressure sensors are widely used in industries, automobiles, aerospace, medical fields, etc.; among them, silicon-based semiconductor sensors have gradually become the mainstream products in the field of pressure sensing due to their significant piezoresistive effect and mature microelectromechanical system (MEMS) processing advantages.

[0003] Its working principle is to utilize the piezoresistive effect of single-crystalline silicon. When the silicon diaphragm is subjected to an external pressure, its resistivity will change, which will in turn cause a change in the output voltage of the Wheatstone bridge, thereby realizing the measurement of pressure.

[0004] In traditional pressure chip manufacturing processes, diffused resistors or ion implantation processes are usually used to form piezoresistors on silicon wafers. Although low-cost mass production can be achieved using the above two processes; however, there are still some problems with these processes:

[0005] First of all, factors such as process fluctuations and material inhomogeneity will cause large deviations in the resistance values of piezoresistors.

[0006] Secondly, the pre-etching thickness of the pressure chip is usually about 15 μm, and more than 90% of the silicon needs to be removed. However, the current etching process is difficult to maintain a high thickness uniformity, and the resistance changes greatly in different regions of the same pressure chip; due to process constraints, the thickness of the pressure chip is usually in the order of 12 - 20 μm; moreover, when the thickness of the pressure chip increases by only 2.54 μm, the resistance change will reach about 20%, resulting in a large deviation in the resistance value of the piezoresistor, which directly affects the measurement accuracy of the sensor.

[0007] In addition, traditional pressure chips also have some deficiencies in terms of sensitivity, linearity, temperature coefficient, zero drift, etc., and need to be improved by various methods.

[0008] In summary, it is found that the prior art has at least the following technical problems:

[0009] The technical problems that the existing pressure chips have low thickness uniformity and large resistance value deviations due to uneven etching thickness and doping fluctuations, which affect the measurement accuracy of the sensor. Summary of the Invention

[0010] The object of the present invention is to provide a pressure chip with high resistance uniformity and a pressure sensor based on an epitaxial process, so as to solve the technical problems that the existing pressure chip has low thickness uniformity and large resistance value deviation of the pressure chip due to uneven etching thickness and doping fluctuation, which affect the measurement accuracy of the sensor.

[0011] The preferred technical solutions among the many technical solutions provided by the present invention and the many technical effects that can be produced are described in detail below.

[0012] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0013] The present invention provides a pressure chip with high resistance uniformity based on an epitaxial process, including a base layer, a conductive layer, and a pad layer that are stacked in sequence from bottom to top to form the pressure chip with high resistance uniformity; multiple resistor bars are formed on the conductive layer, and the multiple resistor bars are divided into two resistor groups; the pad layer is provided with a plurality of internal connection solder joints and a plurality of external connection solder joints, and the internal connection solder joints are used for connecting between the two resistor bars of the same resistor group; the plurality of external connection solder joints are distributed between the two resistor groups, and the external connection solder joints are used for connecting to the resistor bars at the head and tail positions of the resistor group; a single resistor group and the internal connection solder joints form an M-shaped structure, and by forming the M-shaped structure, the resistance path length of the resistor bars is increased, and the resistor bars symmetrically distributed within the resistor group have uniform stress distribution, which is used to improve the conversion rate of the pressure chip with high resistance uniformity to convert mechanical stress into resistance change, obtain a high piezoresistive coefficient, and improve the sensitivity of the pressure chip with high resistance uniformity; the two resistor groups, the internal connection solder joints, and the external connection solder joints form a double M-shaped structure and form a Wheatstone bridge.

[0014] In one embodiment, the material of the base layer is single crystal silicon.

[0015] In one embodiment, the base layer is a P-type crystal-oriented single crystal silicon wafer with a thickness of 6 - 15 μm and a resistivity of 1 - 10 Ω·cm, or an N-type crystal-oriented single crystal silicon wafer with a thickness of 6 - 15 μm and a resistivity of 0.01 - 0.1 Ω·cm.

[0016] In one embodiment, the conductive layer is single crystal silicon epitaxially deposited and grown on the outer surface of the base layer.

[0017] In one embodiment, the thickness of the conductive layer is 1.5 - 5.5 μm and the resistivity is 0.04 - 0.06 Ω·cm.

[0018] In one embodiment, the conductive layer is uniformly epitaxially grown on the base layer by using a chemical vapor deposition process or a molecular beam epitaxy process.

[0019] In one embodiment, the resistive strip is the resistor body of a varistor directly formed on the conductive layer through photolithography and etching.

[0020] In one embodiment, both the pad layer and the electrodes of the varistor are formed by depositing metal using sputtering or evaporation processes, and based on the pad layer, the electrodes, the internal connection solder joints, and the external connection solder joints with corresponding patterns are formed through photolithography and etching processes. The internal connection solder joints and the external connection solder joints are connected to the electrodes of the varistor.

[0021] In one embodiment, the structural positions of the two resistor groups in the double-M structure are arranged symmetrically. The double-M structure uses the symmetrically distributed structural positions to offset the resistance drift caused by temperature changes and suppress common-mode interference.

[0022] In one embodiment, the two resistor groups are distributed on the left and right sides of the middle part of the conductive layer. Among them, the resistor group on the left includes the first to fifth resistive strips, and the resistor group on the right includes the sixth to tenth resistive strips. There are three external connection solder joints. One end of the first resistive strip and the sixth resistive strip is connected to the same external connection solder joint, and one end of the fifth resistive strip and the tenth resistive strip are respectively connected to one of the external connection solder joints individually.

[0023] In one embodiment, the internal connection solder joints include the first to sixth internal connection solder joints. Among them, the first to third internal connection solder joints are located within the resistor group on the left. The first internal connection solder joint is connected to the other end of the first resistive strip and one end of the second resistive strip. The second internal connection solder joint is connected to the other end of the second resistive strip, one end of the third resistive strip, and one end of the fourth resistive strip. The third internal connection solder joint is connected to the other end of the fourth resistive strip and the other end of the fifth resistive strip. The fourth to sixth internal connection solder joints are located within the resistor group on the right. The fourth internal connection solder joint is connected to the other end of the sixth resistive strip and one end of the seventh resistive strip. The fifth internal connection solder joint is connected to the other end of the seventh resistive strip, one end of the eighth resistive strip, and one end of the ninth resistive strip. The sixth internal connection solder joint is connected to the other end of the ninth resistive strip and the other end of the tenth resistive strip. The third resistive strip is only structurally connected to the second internal connection solder joint to fix and prevent the high-resistance uniformity pressure chip from cracking, and the eighth resistive strip is only structurally connected to the fifth internal connection solder joint to fix and prevent the high-resistance uniformity pressure chip from cracking.

[0024] In one embodiment, on the plane of the conductive layer, the first resistor bar and the sixth resistor bar, the second resistor bar and the seventh resistor bar, the third resistor bar and the eighth resistor bar, the fourth resistor bar and the ninth resistor bar, and the fifth resistor bar and the tenth resistor bar are all arranged horizontally and symmetrically in pairs.

[0025] In one embodiment, the shape vertices of the external connection solder joints are all rounded to prevent stress concentration at the vertices of the external connection solder joints after pressure application, and to avoid affecting the sensitivity and linearity of the high-resistance uniformity pressure chip.

[0026] In one embodiment, the shape vertices of the internal connection solder joints are all rounded to prevent stress concentration at the vertices of the internal connection solder joints after pressure application, and to avoid affecting the sensitivity and linearity of the high-resistance uniformity pressure chip.

[0027] The present invention also provides a pressure sensor, including a signal processing unit and the high-resistance uniformity pressure chip of any one of the above, and the signal processing unit is electrically connected to the high-resistance uniformity pressure chip.

[0028] In one embodiment, the pressure sensor includes a plurality of the high-resistance uniformity pressure chips, and the plurality of high-resistance uniformity pressure chips are arranged in the pressure sensor in a symmetric distribution, a uniform distribution or a matrix distribution manner.

[0029] The present invention also provides an epitaxial process for a high-resistance uniformity pressure chip, including the high-resistance uniformity pressure chip of any one of the above and the following steps:

[0030] S1. Select a single-crystal silicon wafer of corresponding specifications as the base layer of the high-resistance uniformity pressure chip;

[0031] S1.1. Select a P-type crystalline orientation single-crystal silicon wafer with a thickness of 6 - 15 μm and a resistivity of 1 - 10 Ω·cm as the base layer of the high-resistance uniformity pressure chip;

[0032] Or S1.2. Select an N-type crystalline orientation single-crystal silicon wafer with a thickness of 6 - 15 μm and a resistivity of 0.01 - 0.1 Ω·cm as the base layer of the high-resistance uniformity pressure chip;

[0033] S2. Adopt an epitaxial deposition process to grow a conductive layer on the base layer;

[0034] S2.1. Grow a P-type conductive layer with a thickness of 1.5 - 5.5 μm and a resistivity of 0.04 - 0.06 Ω·cm on the base layer using chemical vapor deposition. During the epitaxial deposition and growth of silicon crystals in the chemical vapor deposition process, control the growth temperature at 1100 °C, the pressure at 100 Torr, and the gas flow rate at 100 sccm;

[0035] Or S2.2. Grow an N-type conductive layer with a thickness of 2 - 4 μm and a resistivity of 0.04 - 0.06 Ω·cm on the base layer using molecular beam epitaxy. During the epitaxial deposition and growth of silicon crystals in the molecular beam epitaxy process, control the growth temperature at 800 °C and the pressure at 1×10 - 8 Torr;

[0036] S3. Directly form a resistor bar pattern on the conductive layer using photolithography and etching processes;

[0037] S3.1. Patterning: The patterning usually extends about 12 - 14 μm into the wafer from one side of the conductive layer;

[0038] S3.2. Grinding: Grind from an initial thickness of about 0.015 inches on the base layer side of the wafer to a thickness of about 100 μm;

[0039] S3.3. Coating: Coat the side of the conductive layer with a resist material;

[0040] S3.4. Etching: Use traditional etching techniques on the ground base layer side for chemical back etching until the pattern of the strain gauge is visible, and control the overall thickness of the ground base layer + conductive layer of the strain gauge to be 10 to 14 μm;

[0041] S3.5. Removal: Remove the resist material coated on the conductive layer using a conventional removal process;

[0042] S3.6. Form metallized electrical contacts on the conductive layer: Form metallized electrical contacts on the conductive layer part of the strain gauge;

[0043] S4. Fabricate metal electrodes;

[0044] S4.1. Form metal electrodes on the resistor bar;

[0045] S4.11. Form metal electrodes on the resistor bar using sputtering;

[0046] S4.12. Form metal electrodes on the resistor bar using evaporation;

[0047] S4.2. Perform photolithography on the conductive layer;

[0048] S4.3. Perform etching on the conductive layer;

[0049] S4.4. Form the required electrode pattern.

[0050] The beneficial effects of the present invention are as follows:

[0051] The present invention provides a pressure chip with high resistance uniformity based on an epitaxial process, and a pressure sensor with the pressure chip with high resistance uniformity as the sensing core; the pressure chip with high resistance uniformity includes: a base layer, a pad layer, and a conductive layer grown by epitaxial deposition; the pressure sensor includes: a signal processing unit and a pressure chip with high resistance uniformity.

[0052] Among them, on the pressure chip with high resistance uniformity: multiple resistor bars are formed on the conductive layer, and the resistor bars are piezoresistors directly formed on the conductive layer through photolithography and etching. The multiple resistor bars are divided into two resistor groups; the pad layer is provided with a plurality of internal connection solder joints and a plurality of external connection solder joints. The internal connection solder joints are used for connecting between the two resistor bars of the same resistor group; the plurality of external connection solder joints are distributed between the two resistor groups, and the external connection solder joints are used for connecting to the resistor bars at the head and tail positions of the resistor group; a single resistor group and the internal connection solder joints form an M-shaped structure. The M-shaped structure increases the resistance path length of the resistor bars and evenly distributes the stress of the resistor bars symmetrically distributed within the resistor group, so as to improve the conversion rate of the pressure chip with high resistance uniformity to convert mechanical stress into resistance change, obtain a high piezoresistive coefficient, and improve the sensitivity of the pressure chip with high resistance uniformity; the two resistor groups, the internal connection solder joints, and the external connection solder joints form a double M-shaped structure and are symmetrically distributed to form a Wheatstone bridge.

[0053] The present invention integrates at least one pressure chip with high resistance uniformity in a pressure sensor, and then electrically connects the pressure chip with high resistance uniformity integrated in the pressure sensor to the signal processing unit. The pressure chip with high resistance uniformity collects pressure and converts it into an electrical signal, and the signal processing unit processes the pressure signal and transmits the data externally, forming a complete pressure sensor with a pressure acquisition link, a pressure signal conversion link, a pressure signal processing link, and a link for transmitting pressure data externally.

[0054] Compared with the prior art

[0055] (1) The present invention improves the resistance uniformity of the pressure chip

[0056] The conductive layer with a high-resistance single-crystalline silicon layer is prepared on the base layer of single-crystalline silicon through an epitaxial growth process. By utilizing the atomic-level growth controllability and lattice consistency of the epitaxial silicon material, the doping concentration gradient defect of the traditional diffusion / ion implantation process is fundamentally eliminated, the resistance deviation of the varistor is controlled within ±1%, the resistance uniformity of the varistor is effectively improved, the output signals of the pressure chips are made more consistent, and the measurement accuracy and stability of the pressure sensor are improved. At the same time, the conductive layer formed by the epitaxial deposition growth technology has high thickness uniformity (the CV value of the present invention is <2%), which is significantly better than the traditional etching process (the CV value >10%), effectively suppressing the non-linear drift of the resistance caused by film thickness fluctuations, and ensuring that the resistance consistency of the pressure chips produced in batches is increased by more than 3 times.

[0057] (2) The present invention improves the temperature stability and anti-interference ability of the pressure sensor

[0058] By forming a symmetric resistor layout of the double M-shaped structure with two resistor groups having the M-shaped structure in a symmetric layout, the thermal stress difference caused by the temperature gradient is offset through a geometric self-compensation mechanism, the influence of temperature on the resistance of the resistor bars is reduced, the resistance drift caused by temperature changes is effectively offset, and the temperature coefficient of resistance (TCR) is reduced to below 0.05% / °C. The formed Wheatstone bridge structure further suppresses common-mode interference (such as power supply fluctuations). Combining with the stress balance design achieved by the symmetrically arranged resistor groups, the zero-temperature drift of the pressure sensor is less than 0.01%FS / °C, thereby improving the temperature stability and anti-interference ability of the pressure sensor.

[0059] (3) The present invention improves the piezoresistive efficiency and sensitivity of the pressure chip

[0060] The resistor group with the M-shaped structure extends the effective resistance path length to at least 3.2 times that of the traditional straight type through the meandering curve routing path of the M-shaped structure. Under the same strain generated by the pressure chip with high resistance uniformity under the same pressure, a higher resistance change rate (ΔR / R) can be generated. At the same time, the symmetric resistor layout of the double M-shaped structure enables the varistors to be distributed in the equivalent stress area of the strain field, further improving the utilization rate of the varistors, efficiently converting mechanical stress into resistance changes, thus obtaining a higher piezoresistive coefficient and further improving the sensitivity of the pressure chip.

[0061] (4) Process compatibility and cost advantages

[0062] By depositing silicon crystals through epitaxial growth and combining photolithography and direct writing etching processes, it is possible to be compatible with existing MEMS production lines without the need for additional doping or annealing steps, and the process cycle is shortened by 30%. The double M-shaped structure realizes pattern generation through single photolithography, avoiding multi-layer alignment errors, and the yield rate is increased to over 98%, further reducing the comprehensive manufacturing cost.

[0063] In summary, through the epitaxial technology and the symmetric resistor layout of the innovative double M-shaped structure, the present invention has significant advantages in improving resistor uniformity, optimizing stress distribution, enhancing temperature stability and anti-interference ability, can effectively improve the performance and reliability of silicon-based pressure sensors, and is applicable to the manufacture of high-precision and small-size pressure sensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the present invention, the drawings required for the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0065] Figure 1 It is an axonometric view structure diagram of a pressure chip with high resistor uniformity provided by an embodiment of the present invention;

[0066] Figure 2 It is a side view structure diagram of a pressure chip with high resistor uniformity provided by an embodiment of the present invention;

[0067] Figure 3 It is one of the top views of a pressure chip with high resistor uniformity provided by an embodiment of the present invention;

[0068] Figure 4 It is another top view of a pressure chip with high resistor uniformity provided by an embodiment of the present invention;

[0069] Figure 5 It is a third top view of a pressure chip with high resistor uniformity provided by an embodiment of the present invention;

[0070] Figure 6 It is a fourth top view of a pressure chip with high resistor uniformity provided by an embodiment of the present invention;

[0071] Figure 7 It is a fifth top view of a pressure chip with high resistor uniformity provided by an embodiment of the present invention;

[0072] Figure 8 It is a sixth top view of a pressure chip with high resistor uniformity provided by an embodiment of the present invention;

[0073] Figure 9It is one of the schematic diagrams of the assembly structure of the pressure sensor provided by the embodiment of the present invention;

[0074] Figure 10 It is the second schematic diagram of the assembly structure of the pressure sensor provided by the embodiment of the present invention;

[0075] Figure 11 It is the schematic diagram of the symmetrical distribution of the pressure chips with high resistance uniformity inside the pressure sensor provided by the embodiment of the present invention;

[0076] Figure 12 It is the schematic diagram of the uniform distribution of the pressure chips with high resistance uniformity inside the pressure sensor provided by the embodiment of the present invention;

[0077] Figure 13 It is the first schematic diagram of the matrix distribution of the pressure chips with high resistance uniformity inside the pressure sensor provided by the embodiment of the present invention;

[0078] Figure 14 It is the second schematic diagram of the matrix distribution of the pressure chips with high resistance uniformity inside the pressure sensor provided by the embodiment of the present invention.

[0079] Among them, the reference numerals are as follows:

[0080] 00, pressure chip with high resistance uniformity;

[0081] 1, base layer;

[0082] 2, conductive layer; 21, resistor group; 22, resistor strip; 220, first resistor strip; 221, second resistor strip; 222, third resistor strip; 223, fourth resistor strip; 224, fifth resistor strip; 225, sixth resistor strip; 226, seventh resistor strip; 227, eighth resistor strip; 228, ninth resistor strip; 229, tenth resistor strip;

[0083] 3, pad layer; 31, internal connection solder joints; 311, first internal connection solder joint; 312, second internal connection solder joint; 313, third internal connection solder joint; 314, fourth internal connection solder joint; 315, fifth internal connection solder joint; 316, sixth internal connection solder joint; 32, external connection solder joints; 321, first external connection solder joint; 322, second external connection solder joint; 323, third external connection solder joint; 33, rounded corner;

[0084] 4, M-shaped structure;

[0085] 5, double M-shaped structure;

[0086] 6, pressure sensor;

[0087] 7, signal processing unit;

[0088] 8, stress layer. Detailed implementation manners

[0089] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described below in conjunction with the drawings and embodiments. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings represent the same or similar structures, and thus the repeated description thereof will be omitted. The words expressing positions and directions described in the present invention are all illustrated by taking the drawings as examples, but can also be changed as needed, and all changes made are included in the protection scope of the present invention. The drawings of the present invention are only used to illustrate the relative position relationship and do not represent the true scale.

[0090] As a key component for measuring pressure, pressure sensors are widely used in industries, automobiles, aerospace, medical fields, etc.; among them, silicon-based semiconductor sensors have gradually become the mainstream products in the pressure sensing field due to their significant piezoresistive effect and mature microelectromechanical system (MEMS) processing advantages. Its working principle is to utilize the piezoresistive effect of single-crystal silicon. When the silicon diaphragm is subjected to an external pressure, its resistivity will change, which will in turn cause a change in the output voltage of the Wheatstone bridge, thereby realizing the measurement of pressure. In the traditional pressure chip manufacturing process, diffused resistors or ion implantation processes are usually used to form piezoresistors on silicon wafers. Although low-cost mass production can be achieved using these two processes; however, there are still some problems with these processes: First, factors such as process fluctuations and material inhomogeneity will cause large deviations in the resistance values of piezoresistors. Second, the pre-etching thickness of the pressure chip is usually about 15 μm, and more than 90% of the silicon needs to be removed. The current etching process is difficult to maintain a high thickness uniformity, and the resistance changes greatly in different regions of the same pressure chip; due to process constraints, the thickness of the pressure chip is usually in the order of 12 - 20 μm; moreover, when the thickness of the pressure chip only increases by a thickness value of 2.54 μm, the resistance change will reach about 20%, resulting in a large deviation in the resistance value of the piezoresistor, which directly affects the measurement accuracy of the sensor. In addition, traditional pressure chips also have some deficiencies in terms of sensitivity, linearity, temperature coefficient, zero drift, etc., and need to be improved by various methods.

[0091] In view of this, a pressure chip with high resistance uniformity based on epitaxial process is provided in the specific implementation manner of the present application. The pressure chip with high resistance uniformity includes a single-crystalline silicon base layer, a conductive layer and a pad layer deposited and grown epitaxially; a high-resistance single-crystalline silicon layer is formed as the conductive layer by epitaxial growth, and a plurality of resistor bars are prepared by photolithography and etching processes to suppress the resistance value deviation of the resistors and improve the resistance uniformity; the plurality of resistor bars form two resistor groups and are symmetrically distributed in a double-M shape to form a Wheatstone bridge; among them, a single resistor group and an internal connection solder joint form an M-shaped structure, which can increase the resistance path length of the resistor bars and the uniform stress distribution, and obtain a high pressure resistance coefficient and high sensitivity; and the double-M-shaped symmetrical structure can effectively cancel the resistance drift caused by temperature changes, thereby suppressing common-mode interference and improving the temperature stability and anti-interference ability of the sensor; effectively solving the technical problems of the existing pressure chip caused by uneven etching thickness and doping fluctuations, such as low thickness uniformity of the pressure chip, large deviation of the resistor value, and affecting the measurement accuracy of the sensor.

[0092] Figure 1 It is an axonometric perspective structural schematic diagram of the pressure chip with high resistance uniformity provided by the embodiment; Figure 2 It is a side view structural schematic diagram of the pressure chip with high resistance uniformity provided by the embodiment; Figure 3 It is one of the top view diagrams of the pressure chip with high resistance uniformity provided by the embodiment; Figure 4 It is another top view diagram of the pressure chip with high resistance uniformity provided by the embodiment; Figure 5 It is the third top view diagram of the pressure chip with high resistance uniformity provided by the embodiment; Figure 6 It is the fourth top view diagram of the pressure chip with high resistance uniformity provided by the embodiment; Figure 7 It is the fifth top view diagram of the pressure chip with high resistance uniformity provided by the embodiment.

[0093] The first embodiment of the pressure chip 00 with high resistance uniformity is as Figures 1 to 7As shown, it includes a base layer 1, a conductive layer 2, and a pad layer 3 that are stacked in sequence from bottom to top to form a pressure chip 00 with high resistance uniformity; multiple resistor bars 22 are formed on the conductive layer 2, and the multiple resistor bars 22 are divided into two resistor groups 21; the pad layer 3 is provided with multiple internal connection solder joints 31 and multiple external connection solder joints 32. The internal connection solder joints 31 are used for connecting between two resistor bars 22 of the same resistor group 21; the multiple external connection solder joints 32 are distributed between the two resistor groups 21, and the external connection solder joints 32 are used for connecting to the resistor bars 22 at the head and tail positions of the resistor group 21; a single resistor group 21 and the internal connection solder joints 31 form an M-shaped structure 4. By forming the M-shaped structure 4, the resistance path length of the resistor bars 22 is increased, and the stress of the resistor bars 22 symmetrically distributed within the resistor group 21 is evenly distributed, which is used to improve the conversion rate of the pressure chip 00 with high resistance uniformity to convert mechanical stress into resistance change, obtain a high piezoresistive coefficient, and improve the sensitivity of the pressure chip 00 with high resistance uniformity; the two resistor groups 21, the internal connection solder joints 31, and the external connection solder joints 32 form a double M-shaped structure 5 and form a Wheatstone bridge.

[0094] Among them, regarding the layout form of the above double M-shaped structure 5, such as Figure 3 and Figure 4 shown, the structural positions of the two resistor groups 21 in the double M-shaped structure 5 are set to be symmetrically distributed. The double M-shaped structure 5 uses the symmetrically distributed structural positions to offset the resistance drift caused by temperature changes and suppress common-mode interference.

[0095] Regarding the above, for the specific material of the base layer 1, such as Figure 1 and Figure 2 shown, the material of the base layer 1 is single-crystalline silicon; among them, since the base layer 1 uses single-crystalline silicon material, its crystal orientation and resistivity can be selected according to the specific application requirements of the pressure chip.

[0096] Specifically, regarding the crystal orientation of the above base layer 1, the base layer 1 can be selected as a P-type (100) crystal orientation single-crystalline silicon wafer or an N-type (111) crystal orientation single-crystalline silicon wafer.

[0097] Specifically, regarding the thickness parameter and resistivity parameter of the above base layer 1, the base layer 1 can be selected as a single-crystalline silicon wafer with a thickness of 6 - 15 μm and a resistivity of 1 - 10 Ω·cm or a resistivity of 0.01 - 0.1 Ω·cm.

[0098] Regarding the specific material and manufacturing process of the above conductive layer 2, such as Figure 1 and Figure 2 shown, the conductive layer 2 is single-crystalline silicon epitaxially deposited and grown on the outer surface of the base layer 1, and the conductive layer 2 can be formed by growing using any traditional epitaxial deposition technology.

[0099] Specifically, regarding the thickness parameter and resistivity parameter of the above-mentioned conductive layer 2, the conductive layer 2 can be selectively epitaxially deposited as an epitaxial layer with a thickness of 1.5 - 5.5 μm and a resistivity of 0.04 - 0.06 Ω·cm.

[0100] Regarding the formation process of the above-mentioned resistor strip 22 and the specific structure for forming electrical connection and structural connection, such as Figure 5 and Figure 6 As shown, the resistor strip 22 is the resistor body of the varistor directly formed on the conductive layer 2 through photolithography and etching.

[0101] Regarding the material of the above-mentioned pad layer 3, the pad layer 3 is a metal pad. The internal connection solder joint 31 and the external connection solder joint 32 of the pad layer 3 are both used to connect the resistor strip 22 to form an M-shaped structure 4, a double M-shaped structure 5, and build a Wheatstone bridge.

[0102] Among them, the external connection solder joint 32 is used to connect the internal resistor strip 22 and the external communication circuit connection. For example, a pressure chip 00 with high resistance uniformity is applied to form an electrical connection with the signal processing unit 7, thereby constructing a pressure sensor 6; while the internal connection solder joint 31 is only used for the connection between the internal resistor strips 22 to form an M-shaped structure 4.

[0103] The present invention manufactures a pressure chip with high resistance characteristics and high resistance uniformity characteristics through the use of an epitaxial process, forming an independent pressure chip 00 with high resistance uniformity and a pressure sensor 6 with the pressure chip 00 with high resistance uniformity as the sensing core; the pressure chip 00 with high resistance uniformity includes: a base layer 1, a pad layer 3, and a conductive layer 2 grown by epitaxial deposition; the pressure sensor 6 includes: a signal processing unit 7 and a pressure chip 00 with high resistance uniformity.

[0104] The present invention integrates at least one pressure chip 00 with high resistance uniformity into the pressure sensor 6, and then electrically connects the pressure chip 00 with high resistance uniformity integrated in the pressure sensor 6 to the signal processing unit 7. The pressure chip 00 with high resistance uniformity collects pressure and converts it into an electrical signal, and the signal processing unit 7 processes the pressure signal and transmits the data externally, forming a complete pressure sensor 6 with a pressure acquisition link, a pressure signal conversion link, a pressure signal processing link, and a link for transmitting pressure data externally.

[0105] Compared with the prior art

[0106] (1) The present invention improves the resistance uniformity of the pressure chip

[0107] A conductive layer 2 with a high-resistance single-crystalline silicon layer is prepared on the base layer 1 of single-crystalline silicon through an epitaxial growth process. By utilizing the atomic-level growth controllability and lattice consistency of the epitaxial silicon material, the doping concentration gradient defect of the traditional diffusion / ion implantation process is fundamentally eliminated, the resistance deviation of the varistor is controlled within ±1%, the resistance uniformity of the varistor is effectively improved, the output signals of the pressure chips are made more consistent, and the measurement accuracy and stability of the pressure sensor 6 are improved. At the same time, the conductive layer 2 formed by the epitaxial deposition growth technology has high thickness uniformity (CV value of the present invention <2%), which is significantly better than the traditional etching process (CV value >10%), effectively suppressing the non-linear drift of the resistance caused by film thickness fluctuations, and ensuring that the resistance consistency of the pressure chips produced in batches is increased by more than 3 times.

[0108] (2) The present invention improves the temperature stability of the pressure sensor 6 and enhances the anti-interference ability.

[0109] By forming a symmetric resistor layout of a double-M structure 5 with two resistor groups 21 having an M structure 4 in a symmetric layout, the thermal stress difference caused by the temperature gradient is offset through a geometric self-compensation mechanism, the influence of temperature on the resistance of the resistor bar 22 is reduced, the resistance drift caused by temperature change is effectively offset, and the temperature coefficient of resistance (TCR) is reduced to below 0.05% / °C. The formed Wheatstone bridge structure further suppresses common-mode interference (such as power supply fluctuations). Combining the stress balance design of the symmetric resistor group 21, the zero-temperature drift of the pressure sensor 6 is less than 0.01%FS / °C, thereby improving the temperature stability and anti-interference ability of the pressure sensor 6.

[0110] (3) The present invention improves the piezoresistive efficiency and sensitivity of the pressure chip.

[0111] The resistor group 21 of the M structure 4 extends the effective resistance path length to at least 3.2 times that of the traditional straight type through the meandering curve routing path of the M structure 4. Under the same strain generated by the same pressure on the pressure chip 00 with high resistance uniformity, a higher resistance change rate (ΔR / R) can be generated. At the same time, the symmetric resistor layout of the double-M structure 5 distributes the varistors in the equivalent stress area of the diaphragm strain field, further improving the utilization rate of the varistors, enabling the efficient conversion of mechanical stress into resistance changes, and thus obtaining a higher piezoresistive coefficient and further improving the sensitivity of the pressure chip.

[0112] (4) Process compatibility and cost advantages

[0113] By adapting to the epitaxial growth and deposition of silicon crystals and the direct laser writing process, it can be compatible with the existing MEMS production line without additional doping or annealing steps, shortening the process cycle by 30%. The double-M structure 5 realizes pattern generation through single lithography, avoiding multi-layer alignment errors, and increasing the yield rate to over 98%, further reducing the comprehensive manufacturing cost.

[0114] In summary, through the epitaxial technology and the symmetric resistance layout of the innovative double M-shaped structure 5, the present invention has significant advantages in improving resistance uniformity, optimizing stress distribution, enhancing temperature stability, and anti-interference ability. It can effectively improve the performance and reliability of the silicon-based pressure sensor 6 and is suitable for the manufacture of high-precision and small-size pressure sensors 6.

[0115] As an optional implementation

[0116] Figure 5 is the third top view of the pressure chip with high resistance uniformity provided by the embodiment; Figure 6 is the fourth top view of the pressure chip with high resistance uniformity provided by the embodiment.

[0117] Regarding the composition and distribution settings of the above-mentioned resistance bars 22, in this embodiment, for example Figure 5 and Figure 6 As shown, two groups of resistor groups 21 are distributed on the left and right sides of the middle part of the conductive layer 2; among them, the left resistor group 21 includes the first to fifth resistance bars 224, and the right resistor group 21 includes the sixth to tenth resistance bars 229.

[0118] During application, the left resistor group 21 includes the first resistance bar 220 to the fifth resistance bar 224, and the right resistor group 21 includes the sixth resistance bar 225 to the tenth resistance bar 229.

[0119] Specifically, the first resistance bar 220 to the fifth resistance bar 224 included in the left resistor group 21 are the first resistance bar 220, the second resistance bar 221, the third resistance bar 222, the fourth resistance bar 223, and the fifth resistance bar 224; the sixth resistance bar 225 to the tenth resistance bar 229 included in the right resistor group 21 are the sixth resistance bar 225, the seventh resistance bar 226, the eighth resistance bar 227, the ninth resistance bar 228, and the tenth resistance bar 229.

[0120] Figure 5 is the third top view of the pressure chip with high resistance uniformity provided by the embodiment; Figure 6 is the fourth top view of the pressure chip with high resistance uniformity provided by the embodiment; Figure 7 is the fifth top view of the pressure chip with high resistance uniformity provided by the embodiment.

[0121] Regarding the connection method between the above-mentioned resistance bar 22 and the external solder joint 32, in this embodiment, for example Figure 5 and Figure 6As shown, there are three external solder joints 32. One end of the first resistor bar 220 and the sixth resistor bar 225 is connected to the same external solder joint 32, and one end of the fifth resistor bar 224 and the tenth resistor bar 229 is separately connected to one of the external solder joints 32.

[0122] During application, one end of the first resistor bar 220 and the sixth resistor bar 225 is electrically and structurally connected to the same external solder joint 32, and one end of the fifth resistor bar 224 and the tenth resistor bar 229 is separately electrically and structurally connected to one of the external solder joints 32.

[0123] Among them, as Figure 6 and Figure 7 shown, the three external solder joints 32 provided are the first external solder joint 321, the second external solder joint 322, and the third external solder joint 323 respectively;

[0124] Furthermore, as Figure 6 and Figure 7 shown, one end of the first resistor bar 220 and the sixth resistor bar 225 is electrically and structurally connected to the first external solder joint 321, one end of the fifth resistor bar 224 is separately electrically and structurally connected to the second external solder joint 322, and one end of the tenth resistor bar 229 is separately electrically and structurally connected to the third external solder joint 323.

[0125] Figure 5 is the third top view of the pressure chip with high resistance uniformity provided by the embodiment; Figure 6 is the fourth top view of the pressure chip with high resistance uniformity provided by the embodiment; Figure 7 is the fifth top view of the pressure chip with high resistance uniformity provided by the embodiment.

[0126] Regarding the above internal solder joint 31, in this embodiment, as Figures 5 to 7As shown, the internal solder joints 31 include first to sixth internal solder joints 316. Among them, the first to third internal solder joints 313 are located in the resistor group 21 on the left side. The first internal solder joint 311 is connected to the other end of the first resistor bar 220 and one end of the second resistor bar 221. The second internal solder joint 312 is connected to the other end of the second resistor bar 221, one end of the third resistor bar 222, and one end of the fourth resistor bar 223. The third internal solder joint is connected to the other end of the fourth resistor bar 223 and the other end of the fifth resistor bar 224. The fourth to sixth internal solder joints 316 are located in the resistor group 21 on the right side. The fourth internal solder joint 314 is connected to the other end of the sixth resistor bar 225 and one end of the seventh resistor bar 226. The fifth internal solder joint 315 is connected to the other end of the seventh resistor bar 226, one end of the eighth resistor bar 227, and one end of the ninth resistor bar 228. The sixth internal solder joint is connected to the other end of the ninth resistor bar 228 and the other end of the tenth resistor bar 229. The third resistor bar 222 only forms a structural connection with the second internal solder joint to fix and prevent the high-resistance uniformity pressure chip 00 from cracking. The eighth resistor bar 227 only forms a structural connection with the fifth internal solder joint to fix and prevent the high-resistance uniformity pressure chip 00 from cracking.

[0127] Figure 6 is the fourth top view of the high-resistance uniformity pressure chip provided by the embodiment; Figure 7 is the fifth top view of the high-resistance uniformity pressure chip provided by the embodiment.

[0128] Specifically, as Figure 7 shown, the internal solder joints 31 include first to sixth internal solder joints 316, namely the first internal solder joint 311, the second internal solder joint 312, the third internal solder joint 313, the fourth internal solder joint 314, the fifth internal solder joint 315, and the sixth internal solder joint 316.

[0129] When in application, as Figure 6 and Figure 7 shown, the internal solder joints 31 have six internal solder joints including the first internal solder joint 311 to the sixth internal solder joint 316. Among them, the first internal solder joint 311 to the third internal solder joint 313 are located in the resistor group 21 on the left side. The first internal solder joint 311 is electrically and structurally connected to the other end of the first resistor bar 220 and one end of the second resistor bar 221. The second internal solder joint 312 is electrically and structurally connected to the other end of the second resistor bar 221, one end of the third resistor bar 222, and one end of the fourth resistor bar 223. The third internal solder joint is electrically and structurally connected to the other end of the fourth resistor bar 223 and the other end of the fifth resistor bar 224.

[0130] The fourth to sixth internal soldering points 314 to 316 are located within the resistor group 21 on the right side. The fourth internal soldering point 314 is electrically and structurally connected to the other end of the sixth resistor strip 225 and one end of the seventh resistor strip 226. The fifth internal soldering point 315 is electrically and structurally connected to the other end of the seventh resistor strip 226, one end of the eighth resistor strip 227, and one end of the ninth resistor strip 228. The sixth internal soldering point 316 is electrically and structurally connected to the other end of the ninth resistor strip 228 and the other end of the tenth resistor strip 229;

[0131] The third resistor strip 222 only forms a structural connection with the second internal soldering point 312 and has no electrical connection, so it is used for fixing and preventing the high-resistance uniformity pressure chip 00 from cracking. The eighth resistor strip 227 only forms a structural connection with the fifth internal soldering point 315 and has no electrical connection, so it is used for fixing and preventing the high-resistance uniformity pressure chip 00 from cracking. The third resistor strip 222 and the eighth resistor strip 227 do not participate in building the Wheatstone bridge and only play the role of fixing and preventing the pressure chip from breaking.

[0132] Figure 3 is one of the top views of the high-resistance uniformity pressure chip provided by the embodiment; Figure 4 is the second top view of the high-resistance uniformity pressure chip provided by the embodiment; Figure 5 is the third top view of the high-resistance uniformity pressure chip provided by the embodiment; Figure 6 is the fourth top view of the high-resistance uniformity pressure chip provided by the embodiment.

[0133] The second embodiment of the high-resistance uniformity pressure chip 00 is as Figure 5 and Figure 6 shown. The difference between this embodiment and the first embodiment of the high-resistance uniformity pressure chip 00 is that on the plane of the conductive layer 2, the first resistor strip and the sixth resistor strip 225, the second resistor strip 221 and the seventh resistor strip 226, the third resistor strip 222 and the eighth resistor strip 227, the fourth resistor strip 223 and the ninth resistor strip 228, and the fifth resistor strip 224 and the tenth resistor strip 229 are arranged horizontally and symmetrically in pairs.

[0134] When in application, as Figure 3 and Figure 4 、 Figure 5 and Figure 6As shown, in the resistor groups 21 on the left and right sides, the first resistor strip 220, the second resistor strip 221, the third resistor strip 222, the fourth resistor strip 223, and the fifth resistor strip 224 arranged from top to bottom; the sixth resistor strip 225, the seventh resistor strip 226, the eighth resistor strip 227, the ninth resistor strip 228, and the tenth resistor strip 229 are set in parallel one by one from start to end, ensuring that the M-shaped structure 4 constructed by the single-group resistor groups 21 on the left and right sides can be symmetrically distributed on the left and right sides with the positions where the first external solder joint 321, the second external solder joint 322, and the third external solder joint 323 converge as the center; and by arranging the resistor strips 22 in the two resistor groups 21 on the left and right sides horizontally, the length of the resistor strips 22 can be extended to form a high resistance value. At the same time, a pressure chip 00 with a double M-shaped structure 5 is constructed by the extended resistor strips 22, which can increase the area of the pressure chip, increase the area for applying pressure sensing, improve the sensing range, and thus improve the sensing sensitivity of the pressure chip 00 with high resistance uniformity in another aspect.

[0135] Figure 7 is the fifth top view of the pressure chip with high resistance uniformity provided by the embodiment; Figure 8 is the sixth top view of the pressure chip with high resistance uniformity provided by the embodiment.

[0136] The third embodiment of the pressure chip 00 with high resistance uniformity is as Figure 7 and Figure 8 shown. The difference between this embodiment and the first embodiment of the pressure chip 00 with high resistance uniformity is that the vertices of the shapes of the external solder joints 32 are all chamfered 33 to prevent stress concentration at the vertices of the external solder joints 32 after pressure application, avoiding affecting the sensitivity and linearity of the pressure chip 00 with high resistance uniformity.

[0137] And the vertices of the shapes of the internal solder joints 31 are all chamfered 33 to prevent stress concentration at the vertices of the internal solder joints 31 after pressure application, avoiding affecting the sensitivity and linearity of the pressure chip 00 with high resistance uniformity.

[0138] Figure 1 is the axonometric view structure schematic diagram of the pressure chip with high resistance uniformity provided by the embodiment; Figure 2 is the side view structure schematic diagram of the pressure chip with high resistance uniformity provided by the embodiment.

[0139] The fourth embodiment of the pressure chip 00 with high resistance uniformity is as Figure 1 and Figure 2 shown. The difference between this embodiment and the first embodiment of the pressure chip 00 with high resistance uniformity is that regarding the epitaxial deposition growth process of the above-mentioned conductive layer 2, the conductive layer 2 is uniformly epitaxially grown on the base layer 1 by using chemical vapor epitaxy process or molecular beam epitaxy process.

[0140] When applying, 1. Chemical Vapor Deposition (CVD) is a process for depositing a solid thin film on the surface of a wafer through a chemical reaction. It is one of the most widely used thin film processes in semiconductor manufacturing. The core of CVD is to generate and deposit the target thin film on the surface of the wafer through a chemical reaction of a gaseous or vapor precursor.

[0141] The basic process includes: Reaction source delivery: delivering reaction gas or vapor to the wafer surface.

[0142] Adsorption and reaction: Precursor molecules are adsorbed on the wafer surface and chemical reactions occur through heat, plasma, etc.

[0143] Thin film deposition: The solid generated by chemical reaction is deposited on the wafer surface to form the target thin film.

[0144] By-product discharge: Gaseous by-products generated during the reaction are discharged from the reactor through the gas flow.

[0145] This process can be figuratively likened to "planting trees": the reaction source is like a seed, adsorption is the seed taking root, the chemical reaction is the seed sprouting and growing, and finally the solid film covers the wafer surface like a tree, while the gaseous by-products are cleaned up.

[0146] 2. Molecular Beam Epitaxy (MBE) is an advanced technology for growing single crystal thin films. Its basic principle is to heat the elements that make up the thin film in their own molecular beam furnaces under ultra-high vacuum conditions into directional molecular beams that are incident on the heated substrate for thin film growth.

[0147] MBE technology has the following characteristics: High vacuum environment: MBE is carried out in an ultra-high vacuum environment, and the vacuum degree usually reaches 10^-8 to 10^-11 Torr. The extremely low gas pressure ensures that the collision of the molecular beam with the background gas during transmission is minimized, thereby ensuring the purity and accuracy of the deposition.

[0148] Precise control: MBE technology can achieve very precise thickness control and is suitable for making some devices that require highly precise control, such as quantum dot lasers or high mobility transistors (HEMT). By precisely controlling the molecular beam velocity and beam density, epitaxial growth of single crystal thin films can be achieved.

[0149] Low growth rate: The growth rate of MBE is relatively low, which helps to precisely control the thickness, composition and doping amount of the film at the atomic scale.

[0150] Real-time monitoring: MBE equipment is usually equipped with in-situ monitoring equipment, such as reflection high-energy electron diffraction (RHEED), which can monitor the crystal quality and growth kinetics of thin films in real time during the growth process.

[0151] Therefore, through chemical vapor epitaxy or molecular beam epitaxy processes, a conductive layer 2 with a high-resistance single-crystalline silicon layer is prepared on the base layer 1 of single-crystalline silicon. By utilizing the atomic-level growth controllability and lattice consistency of the epitaxial silicon material, the doping concentration gradient defects of the traditional diffusion / ion implantation processes are fundamentally eliminated, the resistance deviation of the varistor is controlled within ±1%, the resistance uniformity of the varistor is effectively improved, the output signals of the pressure chip are made more consistent, and the measurement accuracy and stability of the pressure sensor 6 are improved. At the same time, the conductive layer 2 formed by the epitaxial deposition growth technology has a high thickness uniformity, which can effectively suppress the non-linear drift of the resistance caused by film thickness fluctuations, ensuring that the pressure chips produced in batches have a high resistance consistency.

[0152] Figure 5 is the third top view of the pressure chip with high resistance uniformity provided by the embodiment; Figure 6 is the fourth top view of the pressure chip with high resistance uniformity provided by the embodiment; Figure 7 is the fifth top view of the pressure chip with high resistance uniformity provided by the embodiment.

[0153] The fifth embodiment of the pressure chip 00 with high resistance uniformity is as Figures 5 to 7 shown. The difference between this embodiment and the first embodiment of the pressure chip 00 with high resistance uniformity is that the pad layer 3 and the electrodes of the varistor are both formed by stacking metals using sputtering or evaporation processes, and corresponding pattern electrodes, internal connection solder joints, and external connection solder joints are formed based on the pad layer 3 through photolithography and etching processes. The internal connection solder joints 31 and the external connection solder joints 32 are connected to the electrodes of the varistor.

[0154] During application, the pad layer 3 is formed by stacking metals using sputtering or evaporation processes. The metals used can be: gold (Au), silver (Ag), aluminum (Al), copper (Cu).

[0155] Gold (Au) forms a metal electrode on the silicon wafer using sputtering or evaporation processes. Specifically:

[0156] Sputtering process: Magnetron sputtering can be used to deposit a gold thin film on the silicon wafer; this method can precisely control the thickness and uniformity of the gold film and is suitable for preparing high-quality gold electrodes.

[0157] Evaporation process: Thermal evaporation is also one of the commonly used methods for preparing gold thin films, including resistance evaporation and electron beam evaporation; by controlling evaporation conditions, such as evaporation rate and vacuum degree, etc., gold electrodes with good performance can be obtained.

[0158] Silver (Ag) forms a metal electrode on a silicon wafer using a sputtering or evaporation process. Specifically:

[0159] Sputtering process: The silver thin film can be deposited onto the silicon wafer by magnetron sputtering plasma sputtering; silver has good electrical conductivity and optical properties, and the sputtering process can prepare silver electrodes with specific thickness and structure.

[0160] Evaporation process: Thermal evaporation is also applicable to the preparation of silver thin films; during evaporation, silver atoms are vaporized from the evaporation source and deposited on the surface of the silicon wafer to form a uniform silver electrode layer.

[0161] Aluminum (Al) forms a metal electrode on a silicon wafer using a sputtering or evaporation process. Specifically:

[0162] Sputtering process: Aluminum is one of the commonly used sputtering materials. By bombarding the aluminum target with high-energy particles, its atoms are ejected onto the surface of the silicon wafer to form an aluminum thin film; this method can achieve uniform deposition of the aluminum film and is suitable for large-scale production.

[0163] Evaporation process: Aluminum can also form a metal electrode on the silicon wafer by means of resistance evaporation or electron beam evaporation, etc.; the evaporation process can precisely control the thickness and composition of the aluminum film to meet different application requirements.

[0164] Copper (Cu) forms a metal electrode on a silicon wafer using a sputtering or evaporation process. Specifically:

[0165] Sputtering process: The preparation of copper thin films can use processes such as magnetron sputtering; copper has excellent electrical conductivity and thermal conductivity, and copper electrodes prepared by sputtering have wide applications in electronic devices.

[0166] Evaporation process: Thermal evaporation is also an effective method for preparing copper thin films; by controlling the evaporation parameters, copper electrodes with stable performance can be obtained, which are suitable for the manufacture of various silicon-based devices.

[0167] In summary, metals with relatively high conductivity such as gold, silver, aluminum, and copper can all form metal electrodes on a silicon wafer using a sputtering or evaporation process. The specific choice of which process depends on factors such as actual production requirements, equipment conditions, and requirements for electrode performance.

[0168] Figure 9 is one of the schematic diagrams of the assembly structure of the pressure sensor provided by the embodiment; Figure 10 is the second schematic diagram of the assembly structure of the pressure sensor provided by the embodiment.

[0169] Based on the above embodiments of the high-resistance uniformity pressure chip 00 as Figure 9 shown, a pressure sensor 6 is provided, including a signal processing unit 7 and the high-resistance uniformity pressure chip 00 of any of the above embodiments. The signal processing unit 7 is electrically connected to the high-resistance uniformity pressure chip 00.

[0170] Among them, the pressure sensor 6 integrates (includes) at least one pressure chip 00 with high resistance uniformity.

[0171] During application, such as Figure 9 and Figure 10 As shown, on the front side (the side of the pad layer 3) of the pressure chip 00 with high resistance uniformity, it forms an electrical connection with the signal processing unit 7 through three external solder joints 32, constituting the connection between the sensing end and the processing circuit; in addition, in order to ensure that when the pressure chip 00 with high resistance uniformity, as the sensing end, measures pressure, the acting force received is uniform, so that when the resistance bars 22 of the resistor group 21 of the pressure chip 00 with high resistance uniformity are subjected to mechanical strain, the strain change is more uniform. It is necessary to set a stress layer 8 on the back side of the pressure chip 00 with high resistance uniformity, so that when sensing, the force transmitted to the pressure chip 00 with high resistance uniformity is uniform, and thus the mechanical strain received is also uniform. The electrical signal output from the pressure chip 00 with high resistance uniformity to the signal processing unit 7 is also uniform and stable, thereby improving the stability of the pressure sensor 6 in measuring pressure.

[0172] Figure 11 It is a schematic diagram of the symmetrical distribution of the pressure chips with high resistance uniformity in the pressure sensor provided by the embodiment; Figure 12 It is a schematic diagram of the uniform distribution of the pressure chips with high resistance uniformity in the pressure sensor provided by the embodiment; Figure 13 It is one of the schematic diagrams of the matrix distribution of the pressure chips with high resistance uniformity in the pressure sensor provided by the embodiment; Figure 14 It is the second schematic diagram of the matrix distribution of the pressure chips with high resistance uniformity in the pressure sensor provided by the embodiment.

[0173] The second embodiment of the pressure sensor 6 is as Figures 11 to 14 shown. The difference between this embodiment and the first embodiment of the pressure sensor 6 is that the pressure sensor 6 includes multiple pressure chips 00 with high resistance uniformity, and the multiple pressure chips 00 with high resistance uniformity are arranged in the pressure sensor 6 in a symmetrical distribution, uniform distribution or matrix distribution manner.

[0174] During application, according to the application scenario of the pressure sensor 6, when the pressure sensor 6 needs to detect a large area of pressure, the area required for the sensing side of the pressure sensor 6 is larger. In order to increase the detection range of the pressure sensor 6, the sensing side of the pressure sensor 6 can include multiple pressure chips 00 with high resistance uniformity.

[0175] When there are two pressure chips 00 with high resistance uniformity included in the sensing side of the pressure sensor 6, such as Figure 11As shown, two pressure chips 00 with high resistance uniformity can be symmetrically distributed, and then the two pressure chips 00 with high resistance uniformity are connected to the signal processing unit 7;

[0176] When the number of pressure chips 00 with high resistance uniformity included on the sensing side of the pressure sensor 6 is three or an odd number, as Figure 12 shown, three or an odd number of pressure chips 00 with high resistance uniformity can be arranged in a circular array around the same center, so as to be evenly distributed on the circumferential surface, and then the three or an odd number of pressure chips 00 with high resistance uniformity are connected to the signal processing unit 7;

[0177] When the number of pressure chips 00 with high resistance uniformity included on the sensing side of the pressure sensor 6 is an even number greater than two, as Figure 13 and Figure 14 shown, an even number greater than two of pressure chips 00 with high resistance uniformity can be arranged to form a rectangle or a square, so as to be matrix-distributed on the square surface, and then the even number greater than two of pressure chips 00 with high resistance uniformity are connected to the signal processing unit 7.

[0178] Based on the above embodiments of the pressure chip with high resistance uniformity, an epitaxial process for the pressure chip with high resistance uniformity is provided, including the following steps:

[0179] S1. Select a single crystal silicon wafer of corresponding specifications as the base layer of the pressure chip with high resistance uniformity;

[0180] S1.1. Select a P-type (100) crystal orientation single crystal silicon wafer with a thickness of 6 - 15 μm and a resistivity of 1 - 10 Ω·cm as the base layer (substrate) of the pressure chip with high resistance uniformity;

[0181] Or S1.2. Select an N (111) type crystal orientation single crystal silicon wafer with a thickness of 6 - 15 μm and a resistivity of 0.01 - 0.1 Ω·cm as the base layer (substrate) of the pressure chip with high resistance uniformity;

[0182] S2. Adopt an epitaxial deposition process to grow a conductive layer on the base layer;

[0183] S2.1. Adopt a chemical vapor deposition (CVD) process to grow a P-type conductive layer (epitaxial layer) with a thickness of 1.5 - 5.5 μm and a resistivity of 0.04 - 0.06 Ω·cm on the base layer (substrate). During the process of epitaxial deposition and growth of silicon crystals in the chemical vapor deposition (CVD) process, control the growth temperature at 1100 °C, the pressure at 100 Torr, and the gas flow rate at 100 sccm;

[0184] Or S2.2: Use molecular beam epitaxy (MBE) process to grow an N-type conductive layer (epitaxial layer) with a thickness of 2 - 4 μm, a resistivity of 1.5 - 5.5 μm, and a resistivity of 0.04 - 0.06 Ω·cm on the base layer (substrate). During the epitaxial deposition and growth of silicon crystals in the molecular beam epitaxy (MBE) process, control the growth temperature at 800 °C and the pressure at 1×10-8 Torr;

[0185] S3: Use photolithography and etching processes to directly form a resistor bar pattern on the conductive layer (epitaxial layer);

[0186] S3.1: Patterning: The patterning usually extends about 12 - 14 μm into the wafer from one side of the conductive layer (epitaxial layer);

[0187] S3.2: Grinding: Grind from the starting thickness of about 0.015 inches on the base layer side of the wafer to a thickness of about 100 μm;

[0188] S3.3: Coating: Coat the resist material on one side of the conductive layer;

[0189] S3.4: Etching: Use traditional etching techniques to perform chemical back etching on the ground base layer side until the pattern of the strain gauge is visible, and control the overall thickness of the ground base layer + conductive layer of the strain gauge to be 10 to 14 μm;

[0190] S3.5: Removal: Remove the resist material coated on the conductive layer using conventional removal processes;

[0191] S3.6: Form metallized electrical contacts on the conductive layer: Form metallized electrical contacts on the conductive layer (epitaxial layer) part of the strain gauge;

[0192] S4: Fabricate metal electrodes;

[0193] S4.1: Form metal electrodes on the resistor bar;

[0194] S4.11: Use sputtering process to form metal electrodes on the resistor bar;

[0195] S4.12: Use evaporation process to form metal electrodes on the resistor bar;

[0196] S4.2: Perform photolithography process on the conductive layer;

[0197] S4.3: Perform etching process on the conductive layer

[0198] S4.4: Form the required electrode pattern.

[0199] Experiment, test, analyze and summarize:

[0200] Experimental setup: High-resistance uniformity pressure chips fabricated through two embodiments of the epitaxial process, and traditional pressure chips fabricated using the traditional pressure chip manufacturing process.

[0201] Specifically, 16 groups of high-resistance uniformity pressure chips and traditional pressure chips were fabricated respectively using the first embodiment of the epitaxial process, the second embodiment of the epitaxial process, and the traditional pressure chip manufacturing process.

[0202] Among them, the first embodiment of fabricating high-resistance uniformity pressure chips using an epitaxial process for high-resistance uniformity pressure chips:

[0203] S1. Select a single-crystalline silicon wafer of corresponding specifications as the base layer of the high-resistance uniformity pressure chip;

[0204] S1.1. Select a P-type (100) crystal orientation single-crystalline silicon wafer with a thickness of 8 - 10 μm and a resistivity of 1 - 10 Ω·cm as the base layer (substrate);

[0205] S2. Use an epitaxial deposition process to grow a conductive layer on the base layer;

[0206] S2.1. Use a chemical vapor deposition (CVD) process to grow a P-type conductive layer (epitaxial layer) with a thickness of 1.5 - 5.5 μm and a resistivity of 0.04 - 0.06 Ω·cm on the base layer. During the process of epitaxial deposition and growth of silicon crystals in the chemical vapor deposition (CVD) process, control the growth temperature at 1100 °C, the pressure at 100 Torr, and the gas flow rate at 100 sccm;

[0207] S3. Use photolithography and etching processes to directly form a resistor bar pattern on the conductive layer (epitaxial layer);

[0208] S3.1. Patterning: The pattern typically extends about 12 - 14 μm from one side of the conductive layer (epitaxial layer) into the wafer;

[0209] S3.2. Grinding: Grind from an initial thickness of about 0.015 inches on one side of the wafer base layer to a thickness of about 100 μm;

[0210] S3.3. Coating: Coat a resist material on one side of the conductive layer;

[0211] S3.4. Etching: Use traditional etching techniques on one side of the ground base layer for chemical back-etching until the pattern of the strain gauge is visible, and control the overall strain gauge thickness of the ground base layer + conductive layer to be 10 to 14 μm;

[0212] S3.5. Removal: Remove the resist material coated on the conductive layer using a conventional removal process;

[0213] S3.6. Forming Metallized Electrical Contacts on the Conductive Layer: Form metallized electrical contacts on the conductive layer (epitaxial layer) portion of the strain gauge;

[0214] S4. Fabricating Aluminum Metal Electrodes;

[0215] S4.1. Forming Aluminum Metal Electrodes on the Resistance Bars;

[0216] S4.11. Forming Aluminum Metal Electrodes on the Resistance Bars by Sputtering Process;

[0217] S4.12. Forming Aluminum Metal Electrodes on the Resistance Bars by Evaporation Process;

[0218] S4.2. Performing Photolithography Process on the Conductive Layer;

[0219] S4.3. Performing Etching Process on the Conductive Layer

[0220] S4.4. Forming the Desired Aluminum Metal Electrode Pattern.

[0221] Among them, using an epitaxial process with a high-resistance uniformity pressure chip to fabricate the second embodiment of a high-resistance uniformity pressure chip:

[0222] S1. Select a single-crystalline silicon wafer of corresponding specifications as the base layer of the high-resistance uniformity pressure chip;

[0223] S1.2. Select an N-type (111) crystal orientation single-crystalline silicon wafer with a thickness of 8 - 10 μm and a resistivity of 0.01 - 0.1 Ω·cm as the base layer (substrate);

[0224] S2. Grow a conductive layer on the base layer by epitaxial deposition process;

[0225] S2.2. Grow an N-type conductive layer (epitaxial layer) with a thickness of 2 - 4 μm and a resistivity of 1.5 - 5.5 μm and a resistivity of 0.04 - 0.06 Ω·cm on the base layer by molecular beam epitaxy (MBE) process. During the epitaxial deposition and growth of silicon crystals in the molecular beam epitaxy (MBE) process, control the growth temperature at 800 °C and the pressure at 1×10-8 Torr;

[0226] S3. Directly form a resistance bar pattern on the conductive layer (epitaxial layer) by photolithography and etching processes;

[0227] S3.1. Patterning: The patterning usually extends about 12 - 14 μm into the wafer from one side of the conductive layer (epitaxial layer);

[0228] S3.2. Grinding: Grind from an initial thickness of about 0.015 inches on the base layer side of the wafer to a thickness of about 100 μm;

[0229] S3.3. Coating: Coat the anti-corrosion material on one side of the conductive layer;

[0230] S3.4. Etching: Use traditional etching technology on one side of the polished base layer for chemical back-etching until the pattern of the strain gauge is visible, and control the overall thickness of the strain gauge of the polished base layer + conductive layer to be 10 to 14 μm;

[0231] S3.5. Removal: Remove the anti-corrosion material coated on the conductive layer by using a conventional removal process;

[0232] S3.6. Forming metallized electrical contacts on the conductive layer: Form metallized electrical contacts on the conductive layer (epitaxial layer) part of the strain gauge;

[0233] S4. Fabricating aluminum metal electrodes;

[0234] S4.1. Forming aluminum metal electrodes on the resistance bars;

[0235] S4.11. Forming aluminum metal electrodes on the resistance bars by using the sputtering process;

[0236] S4.12. Forming aluminum metal electrodes on the resistance bars by using the evaporation process;

[0237] S4.2. Performing photolithography on the conductive layer;

[0238] S4.3. Performing etching on the conductive layer

[0239] S4.4. Forming the required aluminum metal electrode pattern.

[0240] Experimental data acquisition: Test the pressure chips fabricated by the first embodiment of the epitaxial process, the second embodiment of the epitaxial process, and the traditional pressure chip manufacturing process respectively, and obtain Test Table 1 and Test Table 2 respectively.

[0241] Among them, Test Table 1, Test Table 2, and Test Table 3 all list 16 groups of test data.

[0242] Test Table 1 shows the resistance values of the pressure chips of the first embodiment of the present invention, Test Table 2 shows the resistance values of the pressure chips of the second embodiment of the present invention, and Test Table 3 shows the resistance values of the traditional pressure chips.

[0243] Test data of the pressure chip with high resistance uniformity:

[0244] The pressure chip with high resistance uniformity of the first embodiment of the epitaxial process: The average resistance is about 2.7 kΩ, the maximum resistance is about 2.7 kΩ, and the minimum resistance is about 2.68 kΩ. The standard deviation is 0.015 kΩ, and the percentage of the standard deviation is 0.56%.

[0245] The second embodiment of the epitaxial process has a pressure chip with high resistance uniformity: the average resistance is about 2.7 kΩ, the maximum resistance is about 2.72 kΩ, and the minimum resistance is about 2.66 kΩ. The standard deviation is 0.014 kΩ, and the percentage of the standard deviation is 0.51%.

[0246] Test data of traditional pressure chips:

[0247] Compared with the two tests of the pressure chip with high resistance uniformity, the average resistance of the traditional pressure chip in Test Table 3 is about 4.30 kΩ, the maximum resistance is about 4.48 kΩ, and the minimum resistance is about 4.18 kΩ. The standard deviation is 0.08 kΩ, and the percentage of the standard deviation is 1.94%.

[0248] Comparative analysis: By summarizing the pressure chips with high resistance uniformity in the first embodiment and the second embodiment of the epitaxial process, and comparing with the pressure chips manufactured by using the traditional pressure chip manufacturing process, the test results show that the resistance value deviation of the resistance bars of the pressure chips with high resistance uniformity is controlled within ±1%.

[0249] Summary: Therefore, the output signal of the pressure chip with high resistance uniformity has good linearity and repeatability; compared with the smaller resistance value deviation of the traditional pressure chip, the output signal quality is better and more stable; for application scenarios with more stringent test environments and higher test accuracies, the performance of the pressure sensor made of the pressure chip with high resistance uniformity as the sensing core of the present invention is better, and it is more suitable for high-precision pressure test scenarios.

[0250] Test Table 1

[0251] Number Resistance value (kΩ) 1 2.69 2 2.68 3 2.68 4 2.69 5 2.69 6 2.71 7 2.7 8 2.72 9 2.72 10 2.71 11 2.72 12 2.7 13 2.68 14 2.68 15 2.7 16 2.71

[0252] Test Table 1: Shows the resistance values of the pressure chips in the first embodiment of the present invention.

[0253] Test Table 2

[0254] Number Resistance value (kΩ) 1 2.67 2 2.66 3 2.7 4 2.7 5 2.7 6 2.7 7 2.7 8 2.7 9 2.7 10 2.69 11 2.69 12 2.7 13 2.72 14 2.7 15 2.69 16 2.7

[0255] Test Table 2 shows the resistance values of the pressure chips in the second embodiment of the present invention.

[0256] Test Table 3

[0257] Number Resistance value (kΩ) 1 4.2 2 4.26 3 4.33 4 4.42 5 4.48 6 4.34 7 4.32 8 4.18 9 4.27 10 4.32 11 4.28 12 4.23 13 4.2 14 4.25 15 4.4 16 4.3

[0258] Test Table 3 shows the resistance values of traditional pressure chips.

[0259] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described.

Claims

1. A pressure chip with high resistance uniformity based on epitaxial process, characterized in that: The invention comprises a base layer, a conductive layer and a pad layer stacked in sequence from bottom to top to form a pressure chip with high resistance uniformity; A plurality of resistor strips are formed on the conductive layer, and the plurality of resistor strips are divided into two resistor groups; The pad layer is provided with a plurality of internal welding points and a plurality of external welding points, wherein the internal welding points are used to connect the two resistor bars of the same resistor group; the plurality of external welding points are distributed between the two resistor groups, and the external welding points are used to connect the resistor bars at the head and tail positions of the resistor group; The single resistor group and the internal solder joint form an M-shaped structure. By forming the M-shaped structure, the resistance path length of the resistor bar is increased, and the uniform stress distribution of the resistor bar symmetrically distributed in the resistor group is used to improve the conversion rate of the pressure chip with high resistance uniformity from mechanical stress to resistance change, obtain a high voltage resistance coefficient, and improve the sensitivity of the pressure chip with high resistance uniformity; The two groups of resistors, the internal solder joints and the external solder joints form a double M-shaped structure and a Wheatstone bridge; The structural positions of the two groups of the resistor groups in the double M-type structure are set to be symmetrically distributed, and the double M-type structure is used to offset the resistance drift caused by temperature change and suppress common mode interference through the symmetrically distributed structural positions; The two groups of resistor groups are distributed on the left and right sides of the middle part of the conductive layer; wherein the resistor group on the left side includes the first resistor bar to the fifth resistor bar, and the resistor group on the right side includes the sixth resistor bar to the tenth resistor bar; three external welding points are provided, one end of the first resistor bar and the sixth resistor bar is connected to the same external welding point, and one end of the fifth resistor bar and the tenth resistor bar is separately connected to one of the external welding points; The internal welding points include the first internal welding point to the sixth internal welding point; wherein, the first internal welding point to the third internal welding point are located in the resistor group on the left, the first internal welding point is connected to the other end of the first resistor bar and one end of the second resistor bar, the second internal welding point is connected to the other end of the second resistor bar, one end of the third resistor bar and one end of the fourth resistor bar, and the third internal welding point is connected to the other end of the fourth resistor bar and the other end of the fifth resistor bar; the fourth internal welding point to the sixth internal welding point are located in the resistor group on the right, and the fourth internal welding point The third resistor bar is connected to the other end of the sixth resistor bar and one end of the seventh resistor bar, the fifth internal welding point is connected to the other end of the seventh resistor bar, one end of the eighth resistor bar and one end of the ninth resistor bar, the sixth internal welding point is connected to the other end of the ninth resistor bar and the other end of the tenth resistor bar; the third resistor bar is structurally connected only to the second internal welding point for fixing and preventing the pressure chip with high resistance uniformity from cracking, and the eighth resistor bar is structurally connected only to the fifth internal welding point for fixing and preventing the pressure chip with high resistance uniformity from cracking; On the plane of the conductive layer, the first resistor bar and the sixth resistor bar, the second resistor bar and the seventh resistor bar, the third resistor bar and the eighth resistor bar, the fourth resistor bar and the ninth resistor bar, and the fifth resistor bar and the tenth resistor bar are arranged horizontally and symmetrically.

2. The pressure chip with high resistance uniformity according to claim 1, characterized in that: The material of the base layer is single crystal silicon.

3. The pressure chip with high resistance uniformity according to claim 2, characterized in that: The base layer is a P-type crystal-oriented single-crystalline silicon wafer with a thickness of 6-15 μm and a resistivity of 1-10 Ω·cm, or an N-type crystal-oriented single-crystalline silicon wafer with a thickness of 6-15 μm and a resistivity of 0.01-0.1 Ω·cm.

4. The pressure chip with high resistance uniformity according to claim 2, characterized in that: The conductive layer is single crystal silicon that is epitaxially deposited and grown on the outer surface of the base layer.

5. The pressure chip with high resistance uniformity according to claim 4, characterized in that: The thickness of the conductive layer is 1.5-5.5 μm, and the resistivity is 0.04-0.06 Ω·cm.

6. The pressure chip with high resistance uniformity according to claim 4, characterized in that: The conductive layer is formed by uniform epitaxial growth on the base layer by using a chemical vapor epitaxy process or a molecular beam epitaxy process.

7. The pressure chip with high resistance uniformity according to claim 4, characterized in that: The first to tenth resistor strips are resistor bodies of varistors formed directly on the conductive layer by photolithography and etching.

8. The pressure chip with high resistance uniformity according to claim 7, characterized in that: The pad layer and the electrodes of the varistor are formed by depositing metal using a sputtering or evaporation process, and the electrodes, the first to sixth internal solder joints and the external solder joints of corresponding patterns are formed based on the pad layer through photolithography and etching processes. The first to sixth internal solder joints and the external solder joints are connected to the electrodes of the varistor.

9. The pressure chip with high resistance uniformity according to claim 1, characterized in that: The vertices of the external solder joints are all rounded to prevent stress concentration at the vertices of the external solder joints after pressure is applied, thereby avoiding affecting the sensitivity and linearity of the pressure chip with high resistance uniformity.

10. The pressure chip with high resistance uniformity according to claim 1, characterized in that: The vertices of the internal solder joints are all rounded to prevent stress concentration at the vertices of the internal solder joints after pressure is applied, thereby avoiding affecting the sensitivity and linearity of the pressure chip with high resistance uniformity.

11. A pressure sensor, characterized in that: It comprises a signal processing unit and a pressure chip with high resistance uniformity according to any one of claims 1 to 10, wherein the signal processing unit is electrically connected to the pressure chip with high resistance uniformity.

12. The pressure sensor according to claim 11, characterized in that: The pressure sensor includes a plurality of pressure chips with high resistance uniformity, and the plurality of pressure chips with high resistance uniformity are arranged in the pressure sensor in a symmetrical distribution, uniform distribution or matrix distribution manner.

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