MEMS capacitive accelerometer wafer-level packaging structure and packaging method based on TSV

Abstract

The invention belongs to the technical field of sensors, and particularly relates to a TSV-based MEMS capacitive accelerometer wafer-level packaging structure and packaging method. A gold-silicon bonding and TSV (Through Silicon Via) combined technology is adopted, and a gold layer is used as a bonding medium and a sensor capacitor polar plate, so that the problem of integration of a polar plate structure and signal lead-out in an MEMS sensor is solved, the design that an independent electrode layer or an additional polar plate is needed in traditional packaging is avoided, and the packaging complexity is reduced. Meanwhile, the gold layer has low resistance and good conductivity, compared with a traditional electrode material, signals can be better transmitted, and the electrical performance of the MEMS sensor is improved. After the TSV technology is combined, short-path signal extraction can be realized in the wafer, signal attenuation and interference are reduced, and signal integrity and precision are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of sensors, and in particular relates to a TSV-based MEMS capacitive accelerometer wafer-level packaging structure and a packaging method. Background Art

[0002] Microelectromechanical system (MEMS) is a micro device or system that integrates micromechanical structure, microsensor, microactuator and electronic circuit at micron or nanometer scale. MEMS combines the advantages of mechanical engineering, electronics, material science and manufacturing technology, and can realize complex sensing, signal processing, control and execution functions in a very small size. MEMS devices are widely used in automobiles, military, aerospace, consumer electronics and other fields due to their remarkable features such as high precision, high reliability, low power consumption, low cost and miniaturization. Especially in automobiles and consumer electronics products, MEMS accelerometers play a vital role as key sensor components, such as vehicle airbag systems, electronic stability control systems, and motion sensing and posture detection in smartphones.

[0003] With the gradual development of MEMS technology, packaging technology must also innovate to meet the needs of miniaturization and integration of devices. Packaging not only needs to protect the precision mechanical structure of MEMS devices and prevent external physical damage, but also ensure the integrity and stability of electrical signals, and in some cases ensure that the devices can adapt to specific environmental conditions (such as vacuum, gas, pressure, etc.). In the past, the packaging of MEMS devices mainly relied on traditional single-chip packaging or multi-chip packaging methods, but with the increasing demand for miniaturization, wafer-level packaging has gradually become the mainstream of MEMS packaging technology.

[0004] Wafer-level packaging refers to the packaging process that is completed directly on the wafer during the MEMS chip processing stage, rather than packaging after the individual chips are produced. Through-silicon via (TSV) technology is a technology that introduces vertical electrical connections into silicon wafers, allowing electrical interconnection through the silicon layer, replacing traditional metal wire and solder ball connections. By adopting TSV technology, wafer-level packaging of MEMS devices can break through the limitations of traditional packaging technology, reduce the need for lateral electrical connections, greatly reduce the size of the device, and significantly improve the transmission speed and stability of signals.

[0005] However, the existing wafer-level packaging process is complex and the electrical signal transmission path is long, resulting in poor sensor sensitivity and signal quality.

[0006] In view of this, in order to improve the above problems, the present invention provides a TSV-based MEMS capacitive accelerometer wafer-level packaging structure and packaging method. Summary of the invention

[0007] The purpose of the present invention is to simplify the packaging structure and steps of a MEMS capacitive acceleration sensor and to improve its signal transmission quality and sensitivity.

[0008] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a TSV-based MEMS capacitive accelerometer wafer-level packaging structure, comprising: a cap layer, a substrate layer, and a sandwiched packaging structure layer located between the cap layer and the substrate layer; Wherein, the structural layer comprises an X / Y axis limit block, a Z axis limit block, a No. 1 support column, a No. 2 support column, and an X / Y axis acceleration sensing structure and a Z axis acceleration sensing structure respectively located on both sides of the No. 1 support column; the X / Y axis limit block, the Z axis limit block, the No. 1 support column, and the No. 2 support column are bonded and fixed to the upper surface of the substrate layer; the ends of the No. 1 support column and the No. 2 support column away from the substrate layer are respectively bonded and fixed to the bonding support columns provided on the lower surface of the cap layer; a bonding surface is formed at the bonding and fixing position of the cap layer, the substrate layer and the structural layer, and the cap layer, the structural layer and the substrate layer are electrically interconnected in sequence through the bonding surface, and the bonding surface is led out to the metal welding point at the outer bottom of the substrate layer through the TSV through hole provided on the substrate layer; A cavity for the X / Y axis acceleration sensing structure and the Z axis acceleration sensing structure to move is provided between the cap layer and the structural layer, and between the substrate layer and the structural layer.

[0009] Preferably, the X / Y-axis acceleration sensing structure includes orthogonally arranged X / Y-axis mass blocks and a center anchor structure No. 1 located at the center of the X / Y-axis mass block; the X / Y-axis mass block is bonded to the substrate layer through the center anchor structure No. 1; a comb-tooth electrode No. 1 and a comb-tooth electrode No. 2 are respectively arranged on both sides of the center anchor structure No. 1, and the comb-tooth electrode No. 1 and the comb-tooth electrode No. 2 change the electrode facing area as the X / Y-axis mass block moves to form a capacitance difference.

[0010] Preferably, the Z-axis acceleration sensing structure includes a Z-axis mass block and a No. 2 center anchor point structure located at the center of the Z-axis mass block; the Z-axis mass block is bonded to the substrate layer through the No. 2 center anchor point structure; and a No. 1 Au layer b is provided on the substrate layer below the Z-axis mass block for differential measurement of the Z-axis mass block.

[0011] Preferably, a plurality of No. 2 Au layers a are provided on the upper surface of the substrate layer; the plurality of No. 2 Au layers a are respectively bonded to the No. 1 central anchor structure, the No. 2 central anchor structure, the No. 1 comb-tooth electrode and the No. 2 comb-tooth electrode.

[0012] Preferably, the bonding method of the bonding surface is gold-silicon bonding.

[0013] Preferably, the bottom surface of the substrate layer except the metal welding points is covered with an insulating layer.

[0014] Preferably, a getter is prepared on the inner wall of the cavity on the cap layer.

[0015] Preferably, the cap layer, substrate layer and structural layer are made of single crystal silicon wafer.

[0016] In a second aspect, the present invention provides a packaging method for a MEMS capacitive accelerometer wafer-level packaging structure based on TSV, and the specific packaging steps are as follows: S1. Etch multiple blind holes on the substrate layer using TSV technology; S2. forming a silicon dioxide film on the upper surface of the blind hole and the entire substrate layer by thermal oxidation or chemical vapor deposition process; S3. Preparing a metal seed layer on the surface of the silicon dioxide film by physical vapor deposition or chemical vapor deposition process; S4. Filling the blind hole with Cu metal by electroplating process, and removing the excess Cu metal on the surface of the metal seed layer by CMP polishing; S5. Using a CMP copper exposure process to remove excess substrate material on the back of the substrate layer, so that the Cu layer is exposed on the lower surface of the substrate layer; S6. Using physical vapor deposition or chemical vapor deposition process, growing an insulating layer on the back of the substrate layer; S7. Patterning the metal seed layer in S3; S8. Preparing an Au layer on the metal seed layer patterned in S7 to form a first Au layer and a plurality of second Au layers; S9. Forming a layer of silicon dioxide film on the upper and lower surfaces of the structural layer by a thermal oxidation process, and patterning it so that the pattern of the patterned silicon oxide film matches the pattern in S7; S10. Using an etching process, a No. 1 support column, a No. 2 support column, an X / Y axis stop block, a Z axis stop block, a No. 1 center anchor structure and a No. 2 center anchor structure are first etched on the structural layer; S11. Using an etching process to remove the silicon dioxide film on the surface of the structural layer in S9, and then sequentially depositing a metal seed layer and an Au layer; S12. The metal seed layer and the Au layer in S11 are patterned to obtain a bonding area of ​​a No. 1 support column, a No. 2 support column, an X / Y axis stopper, a Z axis stopper, a No. 1 center anchor structure, and a No. 2 center anchor structure, which are sequentially covered with a metal seed layer and an Au layer on top; S13. eutectic bonding the upper surface of the substrate layer to the lower surface of the structural layer; S14. After bonding with the substrate layer, the structural layer is etched for the second time to etch out the X / Y axis mass block, the Z axis mass block, the first comb tooth electrode and the second comb tooth electrode for structural release; S15. A layer of silicon dioxide film is formed on the lower surface of the cap layer by a thermal oxidation process, and is patterned to form a silicon dioxide pattern consistent with the bonding region pattern of the structural layer in S9; S16. Using an etching process, etching a bonding support column on the lower surface of the cap layer; S17. removing the silicon dioxide film on the surface of the cap layer in S15 by an etching process, and then sequentially depositing a metal seed layer and an Au layer; S18. Patterning the metal seed layer and the Au layer in S17 to obtain a bonding support column with the metal seed layer and the Au layer sequentially covered on the top; S19. eutectic bonding the lower surface of the cap layer to the upper surface of the structural layer; S20. Patterning the insulating layer in S6 to expose the metal Cu by photolithography and etching processes; S21. Prepare a metal solder joint at one end of the metal Cu exposed in S20 by using a deposition process, thereby completing the packaging of the MEMS capacitive acceleration sensor.

[0017] The beneficial effects of the present invention are: 1. The present invention adopts the technology of combining gold-silicon bonding with TSV, and uses the gold layer as both a bonding medium and a sensor capacitor plate, which solves the integration problem of the plate structure and signal extraction in the MEMS sensor, avoids the design of a separate electrode layer or additional plate in traditional packaging, and reduces the complexity of packaging.

[0018] At the same time, the gold layer has lower resistance and good conductivity. Compared with traditional electrode materials, it can better transmit signals and improve the electrical performance of MEMS sensors. When combined with TSV technology, it can achieve short-path signal extraction inside the wafer, reduce signal attenuation and interference, and improve signal integrity and accuracy.

[0019] 2. In the present invention, the cavities between the cap layer and the structural layer and between the substrate layer and the structural layer can not only provide sufficient space for the activities of the X / Y-axis acceleration sensing structure and the Z-axis acceleration sensing structure to avoid interference from other structures and ensure their measurement sensitivity; they can also provide implementation conditions for preparing a getter in the cavity and realizing packaging with different vacuum degrees, that is, introducing an appropriate amount of getters such as titanium (Ti), zirconium (Zr), vanadium (V) and their alloys into the cavity, which can not only reduce the humidity in the cavity, but also optimize the damping characteristics of the MEMS sensor, ensuring that the device has the best dynamic response when working under specific vacuum and gas conditions, especially under high-frequency operation, appropriate damping can make the sensor system stabilize faster and avoid excessive oscillation. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the wafer-level packaging structure of a MEMS capacitive accelerometer based on TSV of the present invention; Figures 2a to 2i It is the processing flow chart of the substrate layer; Figure 3a to Figure 3d It is the processing flow chart of the structural layer; Figures 4a to 4d It is the processing flow chart of the capping layer; Figure 5a to Figure 5e It is a process flow chart of gold-silicon bonding of substrate layer, structural layer and cap layer in sequence; In the figure: 1, substrate layer; 2, structural layer; 3, cap layer; 4, 13, 17, 26, 29 are all metal seed layers; 5, 14, 28 are all metal layers; 6, X / Y axis acceleration sensing structure; 7, X / Y axis limit block; 8, No. 1 support column; 9, bonding support column; 10, 22 are all cavities; 11, Z axis limit block; 12, Z axis acceleration sensing structure; 15, No. 2 support column; 16, 32, 33 are all silicon dioxide films; 18, metal filling layer; 19, No. 1 comb electrode; 20, No. 1 center anchor structure; 21, No. 2 comb electrode; 23, insulating layer; 24, metal solder joint; 25, No. 2 center anchor structure; 27a, No. 2 Au layer; 27b, No. 1 Au layer; 30, photoresist; 31, blind hole. DETAILED DESCRIPTION

[0021] In order to deepen the understanding of the present invention, the present invention will be further described in detail below in conjunction with examples. The examples are only used to explain the present invention and do not constitute a limitation on the protection scope of the present invention.

[0022] Embodiment 1: like Figure 1As shown, the first embodiment provides a TSV-based MEMS capacitive accelerometer wafer-level packaging structure, including: a cap layer, a substrate layer, and a sandwiched packaging structure layer located between the cap layer and the substrate layer; Wherein, the structural layer comprises an X / Y axis limit block, a Z axis limit block, a No. 1 support column, a No. 2 support column, and an X / Y axis acceleration sensing structure and a Z axis acceleration sensing structure respectively located on both sides of the No. 1 support column; the X / Y axis limit block, the Z axis limit block, the No. 1 support column, and the No. 2 support column are bonded and fixed to the upper surface of the substrate layer; the ends of the No. 1 support column and the No. 2 support column away from the substrate layer are respectively bonded and fixed to the bonding support columns provided on the lower surface of the cap layer; a bonding surface is formed at the bonding and fixing position of the cap layer, the substrate layer and the structural layer, and the cap layer, the structural layer and the substrate layer are electrically interconnected in sequence through the bonding surface, and the bonding surface is led out to the metal welding point at the outer bottom of the substrate layer through the TSV through hole provided on the substrate layer; A cavity for the X / Y axis acceleration sensing structure and the Z axis acceleration sensing structure to move is provided between the cap layer and the structural layer, and between the substrate layer and the structural layer.

[0023] Preferably, the X / Y-axis acceleration sensing structure includes orthogonally arranged X / Y-axis mass blocks and a center anchor structure No. 1 located at the center of the X / Y-axis mass block; the X / Y-axis mass block is bonded to the substrate layer through the center anchor structure No. 1; a comb-tooth electrode No. 1 and a comb-tooth electrode No. 2 are respectively arranged on both sides of the center anchor structure No. 1, and the comb-tooth electrode No. 1 and the comb-tooth electrode No. 2 change the electrode facing area as the X / Y-axis mass block moves to form a capacitance difference.

[0024] Preferably, the Z-axis acceleration sensing structure includes a Z-axis mass block and a No. 2 center anchor point structure located at the center of the Z-axis mass block; the Z-axis mass block is bonded to the substrate layer through the No. 2 center anchor point structure; and a No. 1 Au layer b is provided on the substrate layer below the Z-axis mass block for differential measurement of the Z-axis mass block.

[0025] Preferably, a plurality of No. 2 Au layers a are provided on the upper surface of the substrate layer; the plurality of No. 2 Au layers a are respectively bonded to the No. 1 central anchor structure, the No. 2 central anchor structure, the No. 1 comb-tooth electrode and the No. 2 comb-tooth electrode.

[0026] Preferably, the bonding method of the bonding surface is gold-silicon bonding.

[0027] Preferably, the bottom surface of the substrate layer except the metal welding points is covered with an insulating layer.

[0028] Preferably, a getter is prepared on the inner wall of the cavity on the cap layer.

[0029] Preferably, the cap layer, substrate layer and structural layer are made of single crystal silicon wafer.

[0030] Using gold-silicon eutectic bonding technology, the substrate layer, structural layer and cap layer are bonded together in sequence to form a closed cavity structure, which allows the independent X / Y-axis mass block and Y-axis mass block in the MEMS capacitive three-axis acceleration sensor to move freely when subjected to force. The freely moving X / Y-axis mass block and Y-axis mass block will change the electrode facing area between the No. 1 comb-tooth electrode, the No. 2 comb-tooth electrode and the No. 1 Au layer, and then change the capacitance to form a differential capacitance, and reflect the change in acceleration through the change in the capacitance, thereby realizing the acceleration measurement in the X, Y, and Z three-axis directions.

[0031] Gold-silicon bonding provides good mechanical and electrical interconnection between the substrate layer and the structural layer. The electrical signal of the MEMS structural layer is vertically led out through the TSV through-holes of the substrate layer, and metal solder joints are prepared on the back of the substrate. The SMT process can be used to mount it on the transfer substrate to achieve integration with the signal processing circuit.

[0032] Compared with traditional packaging technology, this structure has a smaller package size, higher integration and better electrical performance, avoiding the problems of long signal transmission path and signal attenuation, and further improving the accuracy and response speed of MEMS sensors.

[0033] Embodiment 2: like Figures 2a to 5e This embodiment 2 provides a packaging method for a MEMS capacitive accelerometer wafer-level packaging structure based on TSV, and the specific steps are as follows: S1. Etch multiple blind holes on the substrate layer using TSV technology; S2. forming a silicon dioxide film on the upper surface of the blind hole and the entire substrate layer by thermal oxidation or chemical vapor deposition process; S3. Preparing a metal seed layer on the surface of the silicon dioxide film by physical vapor deposition or chemical vapor deposition process; S4. Filling the blind hole with Cu metal by electroplating process, and removing the excess Cu metal on the surface of the metal seed layer by CMP polishing; S5. Using a CMP copper exposure process to remove excess substrate material on the back of the substrate layer, so that the Cu layer is exposed on the lower surface of the substrate layer; S6. Using physical vapor deposition or chemical vapor deposition process, growing an insulating layer on the back of the substrate layer; S7. Patterning the metal seed layer in S3; S8. Preparing an Au layer on the metal seed layer patterned in S7 to form a first Au layer and a plurality of second Au layers; S9. Forming a layer of silicon dioxide film on the upper and lower surfaces of the structural layer by a thermal oxidation process, and patterning it so that the pattern of the patterned silicon oxide film matches the pattern in S7; S10. Using an etching process, a No. 1 support column, a No. 2 support column, an X / Y axis stop block, a Z axis stop block, a No. 1 center anchor structure and a No. 2 center anchor structure are first etched on the structural layer; S11. Using an etching process to remove the silicon dioxide film on the surface of the structural layer in S9, and then sequentially depositing a metal seed layer and an Au layer; S12. The metal seed layer and the Au layer in S11 are patterned to obtain a bonding area of ​​a No. 1 support column, a No. 2 support column, an X / Y axis stopper, a Z axis stopper, a No. 1 center anchor structure, and a No. 2 center anchor structure, which are sequentially covered with a metal seed layer and an Au layer on top; S13. bonding the upper surface of the substrate layer to the lower surface of the structural layer by gold-silicon eutectic bonding; S14. After bonding with the substrate layer, the structural layer is etched for the second time to etch out the X / Y axis mass block, the Z axis mass block, the first comb tooth electrode and the second comb tooth electrode for structural release; S15. A layer of silicon dioxide film is formed on the lower surface of the cap layer by a thermal oxidation process, and is patterned to form a silicon dioxide pattern consistent with the bonding region pattern of the structural layer in S9; S16. Using an etching process, etching a bonding support column on the lower surface of the cap layer; S17. removing the silicon dioxide film on the surface of the cap layer in S15 by an etching process, and then sequentially depositing a metal seed layer and an Au layer; S18. Patterning the metal seed layer and the Au layer in S17 to obtain a bonding support column with the metal seed layer and the Au layer sequentially covered on the top; S19. eutectic bonding the lower surface of the cap layer to the upper surface of the structural layer; S20. Patterning the insulating layer in S6 to expose the metal Cu by photolithography and etching processes; S21. Prepare a metal solder joint at one end of the metal Cu exposed in S20 by using a deposition process, thereby completing the packaging of the MEMS capacitive acceleration sensor.

[0034] Preparation of substrate layer 1: Adopt crystal orientation <100> The single crystal silicon wafer is used as the substrate layer 1, the thickness of which is 300 μm to 500 μm, and the resistivity is 0.01 Ω·cm to 1 Ω·cm. Figure 2aAs shown, a Piranha solution (the volume ratio of concentrated sulfuric acid to hydrogen peroxide is 3:7) is used to remove organic pollutants on the surface of the substrate layer 1, and after cleaning, it is rinsed with ultrapure deionized water, and dried by nitrogen or vacuum drying to ensure that there is no moisture remaining on the surface of the substrate layer; The substrate layer 1 is subjected to spin coating of photoresist 30, exposure and development to expose the area to be etched, such as Figure 2b As shown; The substrate layer 1 is etched to form a blind hole 31, and then the process of stripping and cleaning is performed. Figure 2c As shown; A uniform silicon dioxide film 16 is prepared on the upper surface of the substrate layer 1 and inside the blind hole 31 by thermal oxidation or chemical vapor deposition (CVD) process for electrical isolation. Figure 2d As shown; A metal seed layer 17 is prepared on the upper surface of the silicon dioxide film 15 by physical vapor deposition (PVD) or chemical vapor deposition (CVD) process. The material may be metal Ti or TiN / TiW alloy, such as Figure 2e As shown; The blind hole is filled with Cu metal as the metal filling layer 18 by electroplating process, and the excess metal Cu on the surface of the metal seed layer 17 is removed by CMP polishing. Figure 2f As shown; The back side of the substrate layer 1 is subjected to a CMP copper exposure process to remove excess substrate material, so that the Cu layer is exposed on the lower surface of the substrate layer 1. Then, a layer of insulating layer 23 is grown on the back side of the substrate layer 1 by a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process to prepare for subsequent electrical connection or packaging, such as Figure 2g As shown; The metal seed layer 17 on the upper surface of the substrate layer 1 is patterned by coating, exposing, developing, etching, degumming, cleaning and other processing steps. The formed metal seed layer 26 is used as an adhesion layer for preparing the first Au layer 27b in the Z-axis acceleration sensor structure 12. Figure 2h As shown; The upper surface of the substrate layer 1 is subjected to processes such as coating, exposure, development, Au layer deposition, and peeling to realize the preparation of the Au layer on the upper surface of the patterned metal seed layer 26, thereby obtaining the second Au layer 27a and the first Au layer 27b. Figure 2i As shown; Preparation of structural layer 2: A single crystal silicon wafer is used as the structural layer 2, and its thickness is between 10 μm and 100 μm. The structural layer 2 is subjected to a thermal oxidation process, and a silicon dioxide film 32 is formed on both the upper and lower surfaces of the structural layer 2. Figure 3a As shown; The silicon dioxide film 32 is etched and etched to form a silicon dioxide film pattern 32a that is consistent with the bonding area pattern of the substrate layer 1. Figure 3b As shown; The structural layer 2 is etched for the first time to etch out the first support column 8, the second support column 15, the X / Y axis limit block 7, the Z axis limit block 11, the first center anchor structure 20 and the second center anchor structure 25. Figure 3c As shown; The silicon dioxide film 32 is removed by etching, and then the bonding area of ​​the No. 1 support column 8, the No. 2 support column 15, the X / Y axis limit block 7, the Z axis limit block 11, the No. 1 center anchor structure 20 and the No. 2 center anchor structure 25, the No. 1 comb-tooth electrode 19 and the No. 2 comb-tooth electrode 21, which are sequentially covered with the metal seed layer 29 and the metal layer 28Au layer on the top, is obtained through processes such as glue coating, exposure, development, metal seed layer 29 deposition, Au metal layer 28 deposition, and stripping. The metal seed layer 29 material can be metal Ti or TiN / TiW alloy, such as Figure 3d As shown; Preparation of cap layer 3: A single crystal silicon wafer is used as the cap layer 3, and the thickness is between 100 μm and 500 μm; a thermal oxidation process is used for the cap layer 3, and a silicon dioxide film 33 is formed on the lower surface of the cap layer 3, such as Figure 4a As shown; The silicon dioxide film 33 is etched and etched to form a silicon dioxide pattern 33a that is consistent with the bonding area pattern of the structural layer 2. Figure 4b As shown; The cap layer 3 is etched to form bonding support columns 9a, 9b and 9c, wherein the structure 9b is used to separate the X / Y axis acceleration sensing structure 6 and the Z axis acceleration sensing structure 12. Figure 4c As shown; The silicon dioxide film 33 is removed, and processes such as coating, exposure, development, deposition of the metal seed layer 13, deposition of the metal layer 14Au layer, and stripping are performed on the etched surface of the cap layer 3 to achieve the patterning of the metal seed layer 13 and the metal layer 14Au layer, and obtain a bonding support column 9 with the metal seed layer 13 and the metal layer 14Au layer sequentially covered on the top. The metal seed layer material 13 can be metal Ti or TiN / TiW alloy, such as Figure 4d As shown; Bonding of substrate layer 1, structural layer 2 and capping layer 3: The substrate layer 1 and the structure layer 2 are bonded by gold-silicon eutectic bonding to form an internal cavity 22, such as Figure 5a As shown; The upper surface of the structural layer 2 is subjected to processes such as coating, exposure, development, deposition of the metal seed layer 4, deposition of the metal layer 5Au layer, and peeling to achieve the patterning of the metal seed layer 4 and the metal layer 5Au layer, and obtain the second support column 15 and the first support column 8 with the metal seed layer 4 and the metal layer 5 covered on the top in sequence. The material of the metal seed layer 4 can be metal Ti or TiN / TiW alloy, such as Figure 5b As shown; The structural layer 2 bonded to the substrate layer 1 is etched for the second time to etch out the X / Y axis mass block, the Z axis mass block, the first comb-tooth electrode 19 and the second comb-tooth electrode 21 for structural release, such as Figure 5c As shown; The structure layer 2 and the cap layer 3 are bonded by gold-silicon eutectic bonding to form an internal cavity 10, such as Figure 5d As shown; The insulating layer 23 is patterned by photolithography and etching to expose the metal Cu, and then the metal solder joint 24 is prepared by deposition process. The material of the solder joint can be metal Al / Au / Ti / Cu / Pd, and the wafer-level packaging of the MEMS capacitive acceleration sensor is completed. Figure 5e shown.

[0035] The preparation process of the metal seed layers 4, 13, 17, 26, and 29 is consistent, and the material can be metal Ti or TiN / TiW alloy, with a thickness of 50nm to 200nm. The preparation process of the first Au layer 27b and the second Au layer 27a is consistent with that of the metal layers 5, 14, and 28, and the material is metal Au with a thickness of 0.2μm to 2μm; The thickness of the silicon dioxide film is between 1 μm and 5 μm, and it is mainly used to isolate the metal layer from the silicon substrate, and its thickness is between 1 μm and 5 μm.

[0036] The above shows and describes the basic principles, main features and advantages of the present invention. It should be understood by those skilled in the art that the present invention is not limited to the above embodiments. The above embodiments and descriptions are only for explaining the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A TSV-based MEMS capacitive accelerometer wafer-level packaging structure, characterized in that: include: A cap layer (3), a substrate layer (1), and a structure layer (2) sandwiched and encapsulated between the cap layer (3) and the substrate layer (1); The structural layer (2) comprises an X / Y axis limit block (7), a Z axis limit block (11), a first support column (8), a second support column (15), and an X / Y axis acceleration sensing structure (6) and a Z axis acceleration sensing structure (12) respectively located on both sides of the first support column (8); the X / Y axis limit block (7), the Z axis limit block (11), the first support column (8), and the second support column (15) are bonded and fixed to the upper surface of the substrate layer (1); the first support column (8) and One end of the second support column (15) away from the substrate layer (1) is bonded and fixed to a bonding support column (9) provided on the lower surface of the cap layer (3); a bonding surface is formed at the bonding and fixing position of the cap layer (3), the substrate layer (1) and the structural layer (2); the cap layer (3), the structural layer (2) and the substrate layer (1) are electrically interconnected in sequence through the bonding surface, and the bonding surface is led out to a metal solder joint (24) at the outer bottom of the substrate layer (1) through a TSV through hole provided on the substrate layer (1); Cavities for the movement of the X / Y-axis acceleration sensing structure (6) and the Z-axis acceleration sensing structure (12) are provided between the cap layer (3) and the structural layer (2), and between the substrate layer (1) and the structural layer (2).

2. The TSV-based MEMS capacitive accelerometer wafer-level packaging structure according to claim 1, characterized in that: The X / Y-axis acceleration sensing structure (6) comprises orthogonally arranged X / Y-axis mass blocks and a first central anchor structure (20) located at the center of the X / Y-axis mass blocks; the X / Y-axis mass blocks are bonded to the substrate layer (1) via the first central anchor structure (20); a first comb-tooth electrode (19) and a second comb-tooth electrode (21) are respectively arranged on both sides of the first central anchor structure (20); the first comb-tooth electrode (19) and the second comb-tooth electrode (21) change the electrode facing area as the X / Y-axis mass block moves to form a capacitance difference.

3. The TSV-based MEMS capacitive accelerometer wafer-level packaging structure according to claim 1, characterized in that: The Z-axis acceleration sensing structure (12) comprises a Z-axis mass block and a second center anchor structure (25) located at the center of the Z-axis mass block; the Z-axis mass block is bonded to the substrate layer (1) via the second center anchor structure (25); and a first Au layer (27b) is provided on the substrate layer (1) below the Z-axis mass block for differential measurement of the Z-axis mass block.

4. The TSV-based MEMS capacitive accelerometer wafer-level packaging structure according to claim 2, characterized in that: A plurality of No. 2 Au layers (27a) are provided on the upper surface of the substrate layer (1); the plurality of No. 2 Au layers (27a) are respectively bonded to the No. 1 central anchor structure (20), the No. 2 central anchor structure (25), the No. 1 comb-tooth electrode (19) and the No. 2 comb-tooth electrode (21).

5. The TSV-based MEMS capacitive accelerometer wafer-level packaging structure according to claim 1, characterized in that: The bonding method of the bonding surface is gold-silicon bonding.

6. The TSV-based MEMS capacitive accelerometer wafer-level packaging structure according to claim 1, characterized in that: The bottom surface of the substrate layer (1) is covered with an insulating layer (23) except for the metal welding point (24).

7. The TSV-based MEMS capacitive accelerometer wafer-level packaging structure according to claim 1, characterized in that: The cavity is provided with a getter on the inner wall of the cap layer (3).

8. The TSV-based MEMS capacitive accelerometer wafer-level packaging structure according to claim 1, characterized in that: The cap layer (3), substrate layer (1) and structural layer (2) are made of single crystal silicon wafers.

9. A packaging method for a TSV-based MEMS capacitive accelerometer wafer-level packaging structure according to any one of claims 1 to 8, characterized in that: The specific packaging steps are as follows: S1. Etch multiple blind holes on the substrate layer using TSV technology; S2. forming a silicon dioxide film on the upper surface of the blind hole and the entire substrate layer by thermal oxidation or chemical vapor deposition process; S3. Preparing a metal seed layer on the surface of the silicon dioxide film by physical vapor deposition or chemical vapor deposition process; S4. Filling the blind hole with Cu metal by electroplating process, and removing the excess Cu metal on the surface of the metal seed layer by CMP polishing; S5. Using a CMP copper exposure process to remove excess substrate material on the back of the substrate layer, so that the Cu layer is exposed on the lower surface of the substrate layer; S6. Using physical vapor deposition or chemical vapor deposition process, growing an insulating layer on the back of the substrate layer; S7. Patterning the metal seed layer in S3; S8. Preparing an Au layer on the metal seed layer patterned in S7 to form a first Au layer and a plurality of second Au layers; S9. Forming a layer of silicon dioxide film on the upper and lower surfaces of the structural layer by a thermal oxidation process, and patterning it so that the pattern of the patterned silicon oxide film matches the pattern in S7; S10. Using an etching process, a No. 1 support column, a No. 2 support column, an X / Y axis stop block, a Z axis stop block, a No. 1 center anchor structure and a No. 2 center anchor structure are first etched on the structural layer; S11. Using an etching process to remove the silicon dioxide film on the surface of the structural layer in S9, and then sequentially depositing a metal seed layer and an Au layer; S12. The metal seed layer and the Au layer in S11 are patterned to obtain a bonding area of ​​a No. 1 support column, a No. 2 support column, an X / Y axis stopper, a Z axis stopper, a No. 1 center anchor structure, and a No. 2 center anchor structure, which are sequentially covered with a metal seed layer and an Au layer on top; S13. eutectic bonding the upper surface of the substrate layer to the lower surface of the structural layer; S14. After bonding with the substrate layer, the structural layer is etched for the second time to etch out the X / Y axis mass block, the Z axis mass block, the first comb tooth electrode and the second comb tooth electrode for structural release; S15. A layer of silicon dioxide film is formed on the lower surface of the cap layer by a thermal oxidation process, and is patterned to form a silicon dioxide pattern consistent with the bonding region pattern of the structural layer in S9; S16. Using an etching process, etching a bonding support column on the lower surface of the cap layer; S17. removing the silicon dioxide film on the surface of the cap layer in S15 by an etching process, and then sequentially depositing a metal seed layer and an Au layer; S18. Patterning the metal seed layer and the Au layer in S17 to obtain a bonding support column with the metal seed layer and the Au layer sequentially covered on the top; S19. eutectic bonding the lower surface of the cap layer to the upper surface of the structural layer; S20. Patterning the insulating layer in S6 to expose the metal Cu by photolithography and etching processes; S21. Prepare a metal solder joint at one end of the metal Cu exposed in S20 by using a deposition process, thereby completing the packaging of the MEMS capacitive acceleration sensor.

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