TSV-based MEMS capacitive accelerometer wafer level packaging structure and packaging method

Abstract

The application belongs to the technical field of sensors, and particularly relates to a TSV-based MEMS capacitive accelerometer wafer-level packaging structure and a packaging method. The technology of gold-silicon bonding combined with TSV is adopted, the gold layer is used as a bonding medium and a sensor capacitor plate, the integrated problem of the plate structure and signal extraction in the MEMS sensor is solved, the design of a separate electrode layer or an additional plate in the traditional packaging is avoided, and the complexity of the packaging is reduced. Meanwhile, the gold layer has low resistance and good electrical conductivity, compared with the traditional electrode material, the signal can be better transmitted, and the electrical performance of the MEMS sensor is improved. After the TSV technology is combined, short-path signal extraction can be realized in the wafer, signal attenuation and interference are reduced, and signal integrity and precision are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of sensors, and particularly relates to a TSV-based MEMS capacitive accelerometer wafer-level packaging structure and a packaging method. BACKGROUND

[0002] Micro-electro-mechanical system (MEMS) is a kind of micro device or system integrating micro mechanical structure, micro sensor, micro actuator and electronic circuit in micron or nanometer scale. MEMS combines the advantages of mechanical engineering, electronics, material science and manufacturing technology, and can realize complex sensing, signal processing, control and execution functions in a very small size. MEMS devices are widely used in automotive, military, aerospace, consumer electronics and other fields due to their high precision, high reliability, low power consumption, low cost and miniaturization. In particular, in automotive and consumer electronics, MEMS acceleration sensors play a crucial role as key sensor devices, such as vehicle airbag systems, electronic stability control systems and motion sensing and attitude detection in smartphones.

[0003] With the gradual development of MEMS technology, packaging technology must follow the innovation of device miniaturization and integration. Packaging not only needs to protect the precision mechanical structure of MEMS devices and prevent external physical damage, but also needs to ensure the integrity and stability of electrical signals, and in some cases ensure that the device can adapt to specific environmental conditions (such as vacuum, gas, pressure, etc.). In the past, the packaging of MEMS devices mainly relied on traditional single-chip packaging or multi-chip packaging methods, but with the increasing demand for miniaturization, wafer-level packaging has gradually become the mainstream of MEMS packaging technology.

[0004] Wafer-level packaging refers to completing packaging processes directly on a wafer during the MEMS chip processing stage, rather than after individual chip production. Through-hole silicon (TSV) technology is a technology that introduces vertical electrical connections into a silicon wafer, allowing electrical interconnection through the silicon layer, replacing traditional metal wire and solder ball connections. By using TSV technology, wafer-level packaging of MEMS devices can break through the limitations of traditional packaging technology, reduce the need for horizontal electrical connections, greatly reduce the size of the device, and significantly improve signal transmission speed and stability.

[0005] However, the existing wafer-level packaging process is complex, and the long electrical signal transmission path leads to poor sensitivity and signal quality of the sensor.

[0006] In view of this, in order to improve the above problems, the application provides a TSV-based MEMS capacitive accelerometer wafer-level packaging structure and a packaging method. SUMMARY

[0007] The purpose of the present application is to simplify the packaging structure and steps of the MEMS capacitive acceleration sensor and improve its signal transmission quality and sensitivity.

[0008] In order to achieve the above purpose, in the first aspect, the present application provides a TSV-based MEMS capacitive accelerometer wafer-level packaging structure, comprising: a cap layer, a substrate layer and a structure layer sandwiched and packaged between the cap layer and the substrate layer;

[0009] The structure layer comprises X / Y axis limiting blocks, Z axis limiting blocks, a first supporting column, a second supporting column, and X / Y axis acceleration sensing structures and Z axis acceleration sensing structures located on both sides of the first supporting column, respectively; the X / Y axis limiting blocks, the Z axis limiting blocks, the first supporting column and the second supporting column are fixedly bonded to the upper surface of the substrate layer; the ends of the first supporting column and the second supporting column away from the substrate layer are fixedly bonded to the bonding supporting columns provided on the lower surface of the cap layer; the bonding faces are formed at the bonding fixed positions of the cap layer, the substrate layer and the structure layer, and the cap layer, the structure layer and the substrate layer are electrically interconnected in sequence through the bonding faces; the bonding faces are led out to the metal welding points at the bottom of the substrate layer through the TSV through holes provided on the substrate layer.

[0010] The cavities for the movement of the X / Y axis acceleration sensing structures and the Z axis acceleration sensing structures are provided between the cap layer and the structure layer and between the substrate layer and the structure layer.

[0011] Preferably, the X / Y axis acceleration sensing structure comprises orthogonally arranged X / Y axis mass blocks and a first central anchor point structure located at the center of the X / Y axis mass blocks; the X / Y axis mass blocks are bonded to the substrate layer through the first central anchor point structure; a first comb electrode and a second comb electrode are arranged on both sides of the first central anchor point structure, respectively; the first comb electrode and the second comb electrode change the electrode facing area to form a capacitance difference with the movement of the X / Y axis mass blocks.

[0012] Preferably, the Z axis acceleration sensing structure comprises a Z axis mass block and a second central anchor point structure located at the center of the Z axis mass block; the Z axis mass block is bonded to the substrate layer through the second central anchor point structure; a first Au layer b is arranged on the substrate layer below the Z axis mass block for differential measurement of the Z axis mass block.

[0013] Preferably, a plurality of second Au layers a are arranged on the upper surface of the substrate layer; the plurality of second Au layers a are bonded to the first central anchor point structure, the second central anchor point structure, the first comb electrode and the second comb electrode, respectively.

[0014] Preferably, the bonding mode of the bonding face is gold-silicon bonding.

[0015] Preferably, the bottom surface of the substrate layer is covered with an insulating layer except for the metal soldering points.

[0016] Preferably, an air absorbent is prepared on the inner wall of the cap layer.

[0017] Preferably, the cap layer, the substrate layer and the structure layer are made of monocrystalline silicon wafer.

[0018] In the second aspect, the application provides a packaging method for a TSV-based MEMS capacitive accelerometer wafer-level packaging structure, and the specific packaging steps are as follows:

[0019] S1. A plurality of blind holes are etched on the substrate layer by using a TSV technology;

[0020] S2. A layer of silicon dioxide film is formed on the blind holes and the upper surface of the entire substrate layer by using a thermal oxidation or chemical vapor deposition process;

[0021] S3. A metal seed layer is prepared on the upper surface of the silicon dioxide film by using a physical vapor deposition or chemical vapor deposition process;

[0022] S4. Cu metal is filled in the blind holes by using an electroplating process, and the excess Cu metal on the upper surface of the metal seed layer is removed by CMP polishing;

[0023] S5. The excess substrate material on the back surface of the substrate layer is removed by using a CMP copper exposure process, so that the Cu layer is exposed on the lower surface of the substrate layer;

[0024] S6. An insulating layer is grown on the back surface of the substrate layer by using a physical vapor deposition or chemical vapor deposition process;

[0025] S7. The metal seed layer in S3 is patterned;

[0026] S8. An Au layer is prepared on the metal seed layer patterned in S7 to form a first Au layer and a plurality of second Au layers;

[0027] S9. A layer of silicon dioxide film is formed on the upper and lower surfaces of the structure layer by using a thermal oxidation process, and is patterned so that the pattern of the patterned silicon dioxide film corresponds to the pattern in S7;

[0028] S10. A first support column, a second support column, X / Y axis limit blocks, Z axis limit blocks, a first center anchor point structure and a second center anchor point structure are etched on the structure layer by using an etching process;

[0029] S11. The silicon dioxide film on the surface of the structure layer in S9 is removed by using an etching process, and then a metal seed layer and an Au layer are deposited in sequence;

[0030] S12. The metal seed layer and the Au layer in S11 are patterned to obtain a bonding area in which the one support column, the two support columns, the X / Y axis limiting block, the Z axis limiting block, the one center anchor point structure and the two center anchor point structures are sequentially covered by the metal seed layer and the Au layer from top to bottom;

[0031] S13. The upper surface of the substrate layer is bonded to the lower surface of the structure layer by gold silicon eutectic bonding;

[0032] S14. The structure layer after being bonded to the substrate layer is etched for a second time to release the structures of the X / Y axis mass block, the Z axis mass block, the one comb electrode and the two comb electrodes;

[0033] S15. A thin film of silicon dioxide is formed on the lower surface of the cap layer by a thermal oxidation process, and the thin film of silicon dioxide is patterned to form a silicon dioxide pattern consistent with the bonding area pattern of the structure layer in S9;

[0034] S16. The bonding support column is etched on the lower surface of the cap layer by an etching process;

[0035] S17. The thin film of silicon dioxide on the surface of the cap layer in S15 is removed by an etching process, and then the metal seed layer and the Au layer are sequentially deposited;

[0036] S18. The metal seed layer and the Au layer in S17 are patterned to obtain a bonding support column in which the metal seed layer and the Au layer are sequentially covered from top to bottom;

[0037] S19. The lower surface of the cap layer is bonded to the upper surface of the structure layer by gold silicon eutectic bonding;

[0038] S20. The insulating layer in S6 is patterned by a photolithography and etching process to expose the metal Cu;

[0039] S21. The metal solder joint is prepared at one end of the exposed metal Cu in S20 by a deposition process, thereby completing the packaging of the MEMS capacitive acceleration sensor.

[0040] The beneficial effects of the present application are:

[0041] 1. The present application combines the gold silicon bonding technology with the TSV technology, and uses the gold layer as the bonding medium and the sensor capacitor plate, thereby solving the integration problem of the plate structure and signal extraction in the MEMS sensor, avoiding the design of a separate electrode layer or an additional plate in the traditional packaging, and reducing the complexity of the packaging.

[0042] At the same time, the gold layer has lower resistance and good conductivity, compared with traditional electrode materials, can better transmit signals, and improve the electrical performance of the MEMS sensor. Combined with the TSV technology, short path signal leading-out can be realized inside the wafer, signal attenuation and interference are reduced, and signal integrity and precision are improved.

[0043] 2. The cavity between the cap layer and the structure layer, and the substrate layer and the structure layer in the application can not only provide sufficient space for the movement of the X / Y axis acceleration sensing structure and the Z axis acceleration sensing structure to avoid interference from other structures and ensure the measurement sensitivity, but also provide implementation conditions for preparing a getter in the cavity and realizing packaging with different vacuum degrees, that is, introducing an appropriate amount of metal such as titanium (Ti), zirconium (Zr), vanadium (V) and their alloys into the cavity as the getter, which can not only reduce the humidity in the cavity, but also optimize the damping characteristics of the MEMS sensor, so that the device has the optimal dynamic response when working under specific vacuum degree and gas conditions, especially under high frequency operation, appropriate damping can make the sensor system stabilize faster and avoid excessive oscillation. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 is a schematic diagram of a TSV-based wafer-level packaging structure of a MEMS capacitive accelerometer according to the application;

[0045] Figures 2a to 2i is a processing flowchart of the substrate layer;

[0046] Figures 3a to 3d is a processing flowchart of the structure layer;

[0047] Figures 4a to 4d is a processing flowchart of the cap layer;

[0048] Figures 5a to 5e is a processing flowchart of the substrate layer, the structure layer and the cap layer bonded in sequence;

[0049] In the figure: 1, substrate layer; 2, structure layer; 3, cap layer; 4, 13, 17, 26, 29, metal seed layer; 5, 14, 28, metal layer; 6, X / Y axis acceleration sensing structure; 7, X / Y axis limiting block; 8, No. 1 support column; 9, bonded support column; 10, 22, cavity; 11, Z axis limiting block; 12, Z axis acceleration sensing structure; 15, No. 2 support column; 16, 32, 33, silicon dioxide film; 18, metal filler layer; 19, No. 1 comb electrode; 20, No. 1 center anchor point structure; 21, No. 2 comb electrode; 23, insulating layer; 24, metal solder joint; 25, No. 2 center anchor point structure; 27a, No. 2 Au layer; 27b, No. 1 Au layer; 30, photoresist; 31, blind hole. DETAILED DESCRIPTION

[0050] To enhance understanding of the present invention, the present invention will be further described in detail below with reference to embodiments. These embodiments are only used to explain the present invention and do not constitute a limitation on the scope of protection of the present invention.

[0051] Example 1:

[0052] like Figure 1 As shown, this embodiment provides a wafer-level packaging structure for a TSV-based MEMS capacitive accelerometer, including: a cap layer, a substrate layer, and a structural layer sandwiched and packaged between the cap layer and the substrate layer;

[0053] The structural layer includes an X / Y axis limiting block, a Z axis limiting block, a first support pillar, a second support pillar, and X / Y axis acceleration sensing structures and Z axis acceleration sensing structures located on both sides of the first support pillar, respectively. The X / Y axis limiting block, Z axis limiting block, first support pillar, and second support pillar are bonded and fixed to the upper surface of the substrate layer. The ends of the first support pillar and the second support pillar away from the substrate layer are bonded and fixed to bonding support pillars formed on the lower surface of the capping layer. A bonding surface is formed at the bonding and fixing points of the capping layer, substrate layer, and structural layer, and the capping layer, structural layer, and substrate layer are electrically interconnected sequentially through the bonding surface. The bonding surface is led out through TSV vias formed on the substrate layer to metal solder joints at the bottom of the substrate layer.

[0054] Cavities are provided between the cap layer and the structural layer, and between the substrate layer and the structural layer, for the movement of the X / Y axis acceleration sensing structure and the Z axis acceleration sensing structure.

[0055] Preferably, the X / Y axis acceleration sensing structure includes orthogonally arranged X / Y axis mass blocks and a first central anchor point structure located at the center of the X / Y axis mass blocks; the X / Y axis mass blocks are bonded to the substrate layer through the first central anchor point structure; a first comb electrode and a second comb electrode are respectively disposed on both sides of the first central anchor point structure, and the first comb electrode and the second comb electrode change their facing area as the X / Y axis mass blocks move to form a capacitance difference.

[0056] Preferably, the Z-axis acceleration sensing structure includes a Z-axis mass block and a second central anchor point structure located at the center of the Z-axis mass block; the Z-axis mass block is bonded to the substrate layer through the second central anchor point structure; a first Au layer b is disposed on the substrate layer below the Z-axis mass block for differential measurement of the Z-axis mass block.

[0057] Preferably, a plurality of second Au layers a are disposed on the upper surface of the substrate layer; the plurality of second Au layers a are respectively bonded to the first central anchor structure, the second central anchor structure, the first comb electrode and the second comb electrode.

[0058] Preferably, the bonding mode of the bonding surface is gold-silicon bonding.

[0059] Preferably, the bottom surface of the substrate layer is covered with an insulating layer except for the metal solder joint.

[0060] Preferably, an adsorbent is prepared on the inner wall of the cap layer in the cavity.

[0061] Preferably, the materials for preparing the cap layer, substrate layer and structure layer are monocrystalline silicon wafers.

[0062] The substrate layer, structure layer and cap layer are bonded together in sequence by using gold-silicon eutectic bonding technology to form a closed cavity structure, which can provide free movement for the independent X / Y axis mass block, Y axis mass block in the MEMS capacitive three-axis acceleration sensor when under stress. The free movement of the X / Y axis mass block and Y axis mass block will change the electrode facing area between the first comb electrode, second comb electrode and first Au layer, thereby changing the capacitance to form a differential capacitance, and the change of the capacitance is used to reflect the change of acceleration, thereby realizing acceleration measurement in X, Y and Z three-axis directions.

[0063] Gold-silicon bonding provides good mechanical and electrical interconnection between the substrate layer and the structure layer. The electrical signal of the MEMS structure layer is vertically led out through the TSV through hole of the substrate layer, and a metal solder joint is prepared on the back of the substrate, which can be mounted on the conversion substrate by SMT process to realize integration with the signal processing circuit.

[0064] Compared with traditional packaging technology, the structure has smaller packaging size, higher integration and better electrical performance, avoids the problems of long signal transmission path and signal attenuation, and further improves the precision and response speed of the MEMS sensor.

[0065] Embodiment two:

[0066] As Figures 2a to 5e , the embodiment two provides a packaging method of a TSV-based MEMS capacitive accelerometer wafer-level packaging structure, and the specific steps are as follows:

[0067] S1. A plurality of blind holes are etched on the substrate layer by using TSV technology;

[0068] S2. A layer of silicon dioxide film is formed on the blind holes and the upper surface of the entire substrate layer by using thermal oxidation or chemical vapor deposition process;

[0069] S3. A metal seed layer is prepared on the upper surface of the silicon dioxide film by using physical vapor deposition or chemical vapor deposition process;

[0070] S4. Fill Cu metal in the blind hole by electroplating process, and remove the excess Cu on the surface of the metal seed layer by CMP polishing;

[0071] S5. Remove the excess substrate material on the back surface of the substrate layer by the CMP exposed copper process, so that the Cu layer is exposed on the lower surface of the substrate layer;

[0072] S6. Grow an insulating layer on the back surface of the substrate layer by physical vapor deposition or chemical vapor deposition process;

[0073] S7. Pattern the metal seed layer in S3;

[0074] S8. Prepare an Au layer on the metal seed layer patterned in S7 to form a first Au layer and a plurality of second Au layers;

[0075] S9. Form a layer of silicon dioxide film on the upper and lower surfaces of the structure layer by thermal oxidation process, and pattern it so that the patterned silicon dioxide film pattern matches the pattern in S7;

[0076] S10. Etch a first number of support columns, a second number of support columns, X / Y axis limit blocks, Z axis limit blocks, a first center anchor point structure and a second center anchor point structure on the structure layer by etching process;

[0077] S11. Remove the silicon dioxide film on the surface of the structure layer in S9 by etching process, and then deposit the metal seed layer and the Au layer in sequence;

[0078] S12. Pattern the metal seed layer and the Au layer in S11 to obtain a bonding area of a first number of support columns, a second number of support columns, X / Y axis limit blocks, Z axis limit blocks, a first center anchor point structure and a second center anchor point structure, which are sequentially covered with a metal seed layer and an Au layer on the top;

[0079] S13. Au-Si eutectic bonding of the upper surface of the substrate layer and the lower surface of the structure layer;

[0080] S14. Second etching of the structure layer after bonding with the substrate layer to etch out X / Y axis mass blocks, Z axis mass blocks, a first comb electrode and a second comb electrode for structure release;

[0081] S15. Form a layer of silicon dioxide film on the lower surface of the cap layer by thermal oxidation process, and pattern it to form a silicon dioxide pattern consistent with the bonding area pattern of the structure layer in S9;

[0082] S16. Etch a bonding support column on the lower surface of the cap layer by etching process;

[0083] S17. The silicon dioxide film on the surface of the capping layer in S15 is removed by etching process, and then the metal seed layer and Au layer are deposited in sequence.

[0084] S18. Graphicalize the metal seed layer and Au layer in S17 to obtain a bonded support pillar with the metal seed layer and Au layer sequentially covered on top.

[0085] S19. Bond the lower surface of the capping layer to the upper surface of the structural layer using a gold-silicon eutectic bond;

[0086] S20. The insulating layer in S6 is patterned using photolithography and etching processes to expose the metal Cu;

[0087] S21. A metal solder joint is prepared at one end of the exposed Cu metal in S20 using a deposition process, thereby completing the packaging of the MEMS capacitive accelerometer.

[0088] Fabrication of substrate layer 1:

[0089] Using crystal orientation <100> A single-crystal silicon wafer is used as substrate layer 1, with a thickness of 300μm to 500μm and a resistivity of 0.01Ω·cm to 1Ω·cm. Figure 2a As shown, Piranha solution (volume ratio of concentrated sulfuric acid to hydrogen peroxide is 3:7) was used to remove organic contaminants from the surface of substrate 1. After cleaning, it was rinsed with ultrapure deionized water and dried with nitrogen or vacuum to ensure that there was no moisture residue on the surface of the substrate.

[0090] Photoresist 30 is spin-coated onto substrate 1 and then exposed and developed to expose the area to be etched, such as... Figure 2b As shown;

[0091] The substrate layer 1 is etched to create blind vias 31, followed by processes such as resist removal and cleaning. Figure 2c As shown;

[0092] A uniform silicon dioxide thin film 16 is prepared on the upper surface of substrate layer 1 and inside blind via 31 using thermal oxidation or chemical vapor deposition (CVD) processes for electrical isolation, such as... Figure 2d As shown;

[0093] A metal seed layer 17 is prepared on the surface of the silicon dioxide thin film 15 using physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes. The material can be metallic Ti or a TiN / TiW alloy, such as... Figure 2e As shown;

[0094] Cu metal is used as a metal filler layer 18 to fill blind holes using an electroplating process, and excess Cu metal on the upper surface of the metal seed layer 17 is removed by CMP polishing. Figure 2f As shown;

[0095] A CMP (Chemical Vapor Processing) process is performed on the back side of substrate 1 to remove excess substrate material, exposing the Cu layer on the lower surface of substrate 1. Then, an insulating layer 23 is grown on the back side of substrate 1 using either physical vapor deposition (PVD) or chemical vapor deposition (CVD) to prepare for subsequent electrical connections or packaging. Figure 2g As shown;

[0096] The metal seed layer 17 on the upper surface of substrate 1 is patterned using processes such as resist coating, exposure, development, etching, resist removal, and cleaning. The resulting metal seed layer 26 serves as the adhesion layer for the first Au layer 27b in the Z-axis acceleration sensing structure 12. Figure 2h As shown;

[0097] A process involving coating, exposure, development, Au layer deposition, and lift-off is performed on the upper surface of substrate layer 1 to fabricate an Au layer on the patterned metal seed layer 26, resulting in Au layer 27a (second layer) and Au layer 27b (first layer). Figure 2i As shown;

[0098] Preparation of structural layer 2:

[0099] A single-crystal silicon wafer is used as structural layer 2, with a thickness between 10μm and 100μm. A thermal oxidation process is applied to structural layer 2, resulting in the formation of a silicon dioxide thin film 32 on both the upper and lower surfaces. Figure 3a As shown;

[0100] The silicon dioxide thin film 32 is formed using photolithography, etching, and other processes to create a silicon dioxide thin film pattern 32a that is consistent with the bonding region pattern of the substrate layer 1, such as... Figure 3b As shown;

[0101] The first etching is performed on structural layer 2, etching out support column 8, support column 15, X / Y axis limiting block 7, Z axis limiting block 11, center anchor structure 20, and center anchor structure 25, as follows. Figure 3c As shown;

[0102] The silicon dioxide film 32 is removed by etching, followed by processes such as resist coating, exposure, development, deposition of metal seed layer 29, deposition of Au metal layer 28, and stripping to obtain a bonding region consisting of a first support pillar 8, a second support pillar 15, an X / Y axis limiting block 7, a Z axis limiting block 11, a first center anchor structure 20, a second center anchor structure 25, a first comb electrode 19, and a second comb electrode 21, all sequentially covered with the metal seed layer 29 and the Au metal layer 28. The metal seed layer 29 can be made of metallic Ti or a TiN / TiW alloy, such as... Figure 3d As shown;

[0103] Preparation of cap layer 3:

[0104] A single-crystal silicon wafer is used as the capping layer 3, with a thickness between 100 μm and 500 μm. A thermal oxidation process is applied to the capping layer 3, thereby forming a silicon dioxide thin film 33 on the lower surface of the capping layer 3. Figure 4a As shown;

[0105] The silicon dioxide thin film 33 is subjected to photolithography, etching and other processes to form a silicon dioxide pattern 33a that is consistent with the bonding region pattern of the structural layer 2, such as... Figure 4b As shown;

[0106] The cap layer 3 is etched to create bonding support pillars 9a, 9b, and 9c. Structure 9b is used to separate the X / Y axis acceleration sensing structure 6 and the Z axis acceleration sensing structure 12. Figure 4c As shown;

[0107] After removing the silicon dioxide film 33, processes such as resist coating, exposure, development, deposition of metal seed layer 13, deposition of metal layer 14Au layer, and lift-off are performed on the etched surface of capping layer 3 to achieve patterning of metal seed layer 13 and metal layer 14Au layer, resulting in a bonding support pillar 9 with metal seed layer 13 and metal layer 14Au layer sequentially covered on top. The metal seed layer material 13 can be metallic Ti or TiN / TiW alloy, such as... Figure 4d As shown;

[0108] Bonding of substrate layer 1, structural layer 2 and capping layer 3:

[0109] The substrate layer 1 and the structural layer 2 are bonded together with gold-silicon eutectic bonding to form an internal cavity 22, such as... Figure 5a As shown;

[0110] The upper surface of structural layer 2 is subjected to processes such as coating, exposure, development, deposition of metal seed layer 4, deposition of metal layer 5 (Au layer), and stripping to achieve patterning of metal seed layer 4 and metal layer 5 (Au layer). This results in support pillar 15 (number two) and support pillar 8 (number one), with metal seed layer 4 and metal layer 5 sequentially covered on top. The material of metal seed layer 4 can be metallic Ti or a TiN / TiW alloy, such as... Figure 5b As shown;

[0111] A second etching is performed on the structural layer 2 after bonding with the substrate layer 1, etching out the X / Y axis mass block, the Z axis mass block, the first comb electrode 19, and the second comb electrode 21 to release the structure, as follows. Figure 5c As shown;

[0112] The structural layer 2 and the capping layer 3 are bonded together with gold-silicon eutectic bonding to form an internal cavity 10, such as... Figure 5d As shown;

[0113] The insulating layer 23 is patterned using photolithography and etching processes to expose the Cu metal. Then, metal solder joints 24 are fabricated using a deposition process. The solder joint material can be Al / Au / Ti / Cu / Pd, completing the wafer-level packaging of the MEMS capacitive accelerometer sensor. Figure 5e As shown.

[0114] The preparation process of metal seed layers 4, 13, 17, 26, and 29 is consistent, and the material can be metallic Ti or TiN / TiW alloy with a thickness of 50nm to 200nm. The preparation process of Au layer 27b and Au layer 27a is consistent with that of metal layers 5, 14, and 28, and the material is metallic Au with a thickness of 0.2μm to 2μm.

[0115] The thickness of the silicon dioxide film is between 1 μm and 5 μm, and it is mainly used to isolate the metal layer from the silicon substrate.

[0116] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A TSV-based MEMS capacitive accelerometer wafer level package structure, characterized in that, include: A capping layer (3), a substrate layer (1), and a structural layer (2) sandwiched and encapsulated between the capping layer (3) and the substrate layer (1); The structural layer (2) includes an X / Y axis limiting block (7), a Z axis limiting block (11), a first support column (8), a second support column (15), and X / Y axis acceleration sensing structures (6) and Z axis acceleration sensing structures (12) located on both sides of the first support column (8); the X / Y axis limiting block (7), Z axis limiting block (11), first support column (8), and second support column (15) are bonded and fixed to the upper surface of the substrate layer (1); the first support column (8) and The end of the second support post (15) away from the substrate layer (1) is bonded and fixed to the bonding support post (9) opened on the lower surface of the cap layer (3); the cap layer (3), the substrate layer (1) and the structural layer (2) are bonded and fixed with a bonding surface, and the cap layer (3), the structural layer (2) and the substrate layer (1) are electrically interconnected in sequence through the bonding surface. The bonding surface is led out through the TSV through-hole opened on the substrate layer (1) to the metal solder joint (24) at the bottom outside the substrate layer (1). Cavities are provided between the cap layer (3) and the structural layer (2), and between the substrate layer (1) and the structural layer (2) for the X / Y axis acceleration sensing structure (6) and the Z axis acceleration sensing structure (12) to move; The X / Y axis acceleration sensing structure (6) includes orthogonally arranged X / Y axis mass blocks and a first central anchor point structure (20) located at the center of the X / Y axis mass blocks; the X / Y axis mass blocks are bonded to the substrate layer (1) through the first central anchor point structure (20); a first comb tooth electrode (19) and a second comb tooth electrode (21) are respectively provided on both sides of the first central anchor point structure (20); the first comb tooth electrode (19) and the second comb tooth electrode (21) change their facing area as the X / Y axis mass blocks move to form a capacitance difference; The Z-axis acceleration sensing structure (12) includes a Z-axis mass block and a second center anchor point structure (25) located at the center of the Z-axis mass block; the Z-axis mass block is bonded to the substrate layer (1) through the second center anchor point structure (25); a first Au layer (27b) is disposed on the substrate layer (1) below the Z-axis mass block for differential measurement of the Z-axis mass block; The upper surface of the substrate layer (1) is provided with a plurality of second Au layers (27a); the plurality of second Au layers (27a) are respectively bonded to the first central anchor structure (20), the second central anchor structure (25), the first comb electrode (19) and the second comb electrode (21); The bonding method of the bonding surface is gold-silicon bonding.

2. The TSV-based MEMS capacitive accelerometer wafer level package structure of claim 1, wherein: The bottom surface of the substrate layer (1) is covered with an insulating layer (23) except for the metal solder joints (24).

3. The TSV-based MEMS capacitive accelerometer wafer level package structure of claim 1, wherein: The cavity has a getter prepared on the inner wall of the cap layer (3).

4. The TSV-based MEMS capacitive accelerometer wafer level package structure of claim 1, wherein: The capping layer (3), substrate layer (1) and structural layer (2) are made of single-crystal silicon wafers.

5. A method of packaging a TSV-based MEMS capacitive accelerometer wafer-level package structure as claimed in any one of claims 1 to 4, characterized in that, The specific packaging steps are as follows: S1. Adopting TSV technology to etch a plurality of blind holes on the substrate layer; S2. Adopting thermal oxidation or chemical vapor deposition process to form a layer of silicon dioxide film on the blind hole and the upper surface of the entire substrate layer; S3. Adopting physical vapor deposition or chemical vapor deposition process to prepare a metal seed layer on the upper surface of the silicon dioxide film; S4. Adopting electroplating process to fill Cu metal in the blind hole, and removing the excess metal Cu on the upper surface of the metal seed layer by CMP polishing; S5. Adopting CMP copper exposure process to remove the excess substrate material on the back surface of the substrate layer, so as to expose the Cu layer on the lower surface of the substrate layer; S6. Adopting physical vapor deposition or chemical vapor deposition process to grow an insulating layer on the back surface of the substrate layer; S7. Patterning the metal seed layer in S3; S8. Preparing an Au layer on the metal seed layer after patterning in S7 to form a first Au layer and a plurality of second Au layers; S9. Adopting thermal oxidation process to form a layer of silicon dioxide film on the upper and lower surfaces of the structure layer, and patterning the same, so that the pattern of the patterned silicon dioxide film matches the pattern in S7; S10. Adopting etching process to etch a first support column, a second support column, X / Y axis limit blocks, Z axis limit blocks, a first center anchor point structure and a second center anchor point structure on the upper surface of the structure layer; S11. Adopting etching process to remove the silicon dioxide film on the surface of the structure layer in S9, and then sequentially depositing a metal seed layer and an Au layer; S12. Patterning the metal seed layer and the Au layer in S11 to obtain a bonding area of the first support column, the second support column, the X / Y axis limit blocks, the Z axis limit blocks, the first center anchor point structure and the second center anchor point structure, which are sequentially covered with the metal seed layer and the Au layer on the top; S13. Bonding the upper surface of the substrate layer with the lower surface of the structure layer by gold silicon eutectic bonding; S14. Second etching the structure layer after bonding with the substrate layer to etch X / Y axis mass blocks, Z axis mass blocks, a first comb electrode and a second comb electrode for structure release; S15. Adopting thermal oxidation process to form a layer of silicon dioxide film on the lower surface of the cap layer, and patterning the same to form a silicon dioxide pattern consistent with the bonding area pattern of the structure layer in S9; S16. Adopting etching process to etch a bonding support column on the lower surface of the cap layer; S17. Adopting etching process to remove the silicon dioxide film on the surface of the cap layer in S15, and then sequentially depositing a metal seed layer and an Au layer; S18. Patterning the metal seed layer and the Au layer in S17 to obtain a bonding support column, which is sequentially covered with the metal seed layer and the Au layer on the top; S19. Bonding the lower surface of the cap layer with the upper surface of the structure layer by gold silicon eutectic bonding; S20. Adopting lithography and etching process to pattern the insulating layer in S6 to expose the metal Cu; S21. Adopting deposition process to prepare a metal solder on one end of the exposed metal Cu in S20, thereby completing the packaging of the MEMS capacitive acceleration sensor.

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