Chip testing system and method
By introducing a substrate management controller and multiple test units into the chip test system, multiple tests of the chip to be tested are realized and testing tasks are performed in parallel, which solves the problem of low chip testing efficiency in the existing technology and significantly improves the testing efficiency.
Patent Information
- Application Number
- CN202411908154.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-05-06
AI Technical Summary
In existing chip testing systems, the testing efficiency is low and it is difficult to meet user needs.
A chip testing system is designed, including a substrate management controller and multiple test units. Through the substrate management controller, the test instructions are sent to the target test unit, the placement orientation of the chip to be tested, the power supply to ground short circuit state and the FLASH test are realized, and a one-to-one test relationship between the test unit and the chip to be tested is established, allowing tests between channels to be executed in parallel.
By performing tests in parallel, the chip test efficiency is significantly improved, and the FLASH full-chip read and write test control can be efficiently completed according to the needs of different chips to be tested, solving the problem of low testing efficiency in the prior art.
Smart Images
Figure CN119936612A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip manufacturing technology, and in particular to a chip testing system and method. Background Art
[0002] Chips have made significant contributions to the development of modern society and have promoted productivity and cost reduction in analyzing and communicating information in various commercial, scientific, educational and entertainment applications. These chips usually need to be tested to ensure that the interface functions properly. In related technologies, chip testing is usually implemented through a test platform, connecting each interface of the chip to be tested to the same test chip, so that the test chip controls each channel to test the chip to be tested in turn; however, this test architecture is limited by the performance of the test chip and the number of interfaces, and it is necessary to control each channel to perform communication tests on the relevant interfaces in sequence. The test efficiency is low and it is difficult to meet user needs. Summary of the invention
[0003] The embodiments of the present application provide a chip testing system and method, which can at least solve the problem of low chip testing efficiency in related technologies.
[0004] In a first aspect, an embodiment of the present application provides a chip testing system, comprising: a baseboard management controller and a plurality of test units electrically connected to the baseboard management controller, each test unit being respectively configured with an interface for connecting to a chip to be tested; wherein:
[0005] The baseboard management controller is used to send a test instruction to the target test unit when receiving a feedback signal from the target test unit and determining that the current operating state of the chip test system and the ambient temperature conditions meet the test conditions; wherein the feedback signal is a signal confirming that the target test unit is in a connected state with the chip to be tested;
[0006] The target test unit is used to respond to the test instruction, test the placement orientation and the short-circuit state of the power supply to the ground of the chip under test, obtain a first test result and feed the first test result back to the baseboard management controller; if the first test result is a test pass, test the FLASH in the chip under test, obtain a second test result and feed the second test result back to the baseboard management controller.
[0007] A second aspect of the present application provides a chip testing method, which is applied to the chip testing system of the first aspect. The method includes:
[0008] When the baseboard management controller receives the feedback signal from the target test unit and determines that the current operating state of the chip test system and the ambient temperature conditions meet the test conditions, it sends a test instruction to the target test unit; wherein the feedback signal is a signal confirming that the target test unit is in a connected state with the chip to be tested;
[0009] The target test unit responds to the test instruction to test the placement direction of the chip to be tested and the short circuit state of the power supply to the ground, obtains a first test result and feeds the first test result back to the baseboard management controller;
[0010] If the first test result is that the test passes, the target test unit tests the FLASH in the chip to be tested, obtains a second test result, and feeds the second test result back to the baseboard management controller.
[0011] As can be seen from the above, according to the chip testing system and method provided by the scheme of the present application, the testing system includes a baseboard management controller and a plurality of testing units electrically connected to the baseboard management controller respectively; the baseboard management controller is used to send a test instruction to the target test unit when receiving a feedback signal from the target test unit and determining that the current operating status of the chip testing system and the ambient temperature conditions meet the test conditions; wherein the feedback signal is a signal confirming that the target test unit and the chip to be tested are in a connected state; the target test unit responds to the test instruction to test the placement orientation of the chip to be tested and the short-circuit state of the power supply to the ground, obtains a first test result and feeds back the first test result to the baseboard management controller; if the first test result is a test pass, the target test unit tests the FLASH in the chip to be tested, obtains a second test result and feeds back the second test result to the baseboard management controller. Through the implementation of the scheme of the present application, a one-to-one test relationship is established between the test unit and the chip to be tested, so that an independent test channel is formed between the test unit and the chip to be tested, so that the tests between the channels can be executed in parallel; each test channel is separately regulated by the baseboard management controller, so that the target test unit can efficiently complete the test control of the FLASH full-chip read, write and erase according to the required test scenarios of different chips to be tested when the system operating status meets the test conditions, thereby effectively improving the chip testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 A schematic diagram of the structure of a chip testing system provided in the first embodiment of the present application;
[0013] Figure 2 A schematic diagram of a circuit connection between an MCU and a DUT on a single test channel provided in the first embodiment of the present application;
[0014] Figure 3 A schematic diagram of a direction detection circuit according to the first embodiment of the present application;
[0015] Figure 4 A schematic diagram of the structure of a chip to be tested provided in the first embodiment of the present application;
[0016] Figure 5A basic flow chart of a chip testing method provided for the second embodiment of the present application. DETAILED DESCRIPTION
[0017] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.
[0018] In the description of the embodiments of the present application, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.
[0019] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.
[0020] In the embodiments of the present application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.
[0021] In the related art, the system-level test screening of the chip usually uses a system screening board with a chip fixture to perform system-level functional testing (including three-temperature and three-pressure testing) on the chip interface to test whether the chip interface function can remain normal under various conditions. Since the interface communication process is mostly bidirectional, other interface chips with normal communication capabilities with the DUT interface are generally set on the system screening board. This interface chip is a maturely designed interface chip that has been tested and proven to be able to be used normally in the current test environment.
[0022] Although some multi-channel sequential test architectures have emerged in related technologies, under these architectures, multi-channel DUTs are all connected to the same test chip, and the test chip needs to control each channel to test it in sequence. The test of DUTs in this type of architecture is limited by the performance and number of interfaces of the test chip, and each channel needs to be controlled to perform communication tests on related interfaces in sequence. When the single-channel test time is long, the total test time of a single board with multiple channels will increase as the number of channels increases, ultimately resulting in a very long total test time, low efficiency in testing and screening, and difficulty in meeting user needs.
[0023] In order to solve the problem of low chip testing efficiency in related technologies, such as Figure 1 As shown, the first embodiment of the present application provides a chip testing system, including: a baseboard management controller and a plurality of test units electrically connected to the baseboard management controller, each test unit is respectively configured with an interface for connecting to the chip to be tested; wherein, the baseboard management controller is used to send a test instruction to the target test unit when receiving a feedback signal from the target test unit and determining that the current operating state of the chip test system and the ambient temperature conditions meet the test conditions; wherein the feedback signal is a signal confirming that the target test unit and the chip to be tested are in a connected state; the target test unit is used to respond to the test instruction, test the placement orientation of the chip to be tested and the short-circuit state of the power supply to the ground, obtain a first test result and feed back the first test result to the baseboard management controller; if the first test result is a test pass, the FLASH in the chip to be tested is tested to obtain a second test result and feed back the second test result to the baseboard management controller.
[0024] Specifically, the chip to be tested in the present embodiment can be a DUT (Device Under Test) chip. The baseboard management controller of the present embodiment can be a BMC (Baseboard Management Controller) chip, which is an embedded controller for managing the power supply, temperature, network and other hardware states of the system, and controlling the working state of each test channel, and monitoring the running state of the whole board. The test unit in the present embodiment can be an MCU (Microcontroller Unit) chip, which is a monolithic integrated circuit integrated with components such as a microprocessor, a memory, and an input and output interface, which can execute complex control algorithms and process sensor data, and realize various automated test functions. The present embodiment establishes a one-to-one test channel between the test unit and the chip to be tested, so that the test between the channels can be executed in parallel, and the baseboard management controller is used to separately regulate each test channel, so that the test unit can efficiently complete the test control of the FLASH full-chip read, write and erase according to the demand test scenarios of different chips to be tested, thereby effectively improving the chip test efficiency. It should be noted that in some other embodiments, the baseboard management controller and the test unit can also be FPGA, CPLD, etc., which are not limited here. It should be understood that the target test unit of this embodiment refers to the test unit that is connected to the chip under test. The target test unit can refer to all test units or part of the test units. That is, the test channels corresponding to the test units in this embodiment can perform test work at the same time. Figure 1 As shown, the testing work can also be started at different times without affecting each other.
[0025] In some implementations of the present embodiment, it also includes a voltage sensor, a current sensor and multiple temperature sensors respectively connected to the baseboard management controller; the multiple temperature sensors are used to obtain temperature data of the baseboard management controller and the target test unit respectively; the baseboard management controller is specifically used to: combine the temperature data, the input voltage obtained by the voltage sensor, and the input current obtained by the current sensor to determine whether the operating status of the chip test system and the ambient temperature conditions meet the test conditions.
[0026] Specifically, in this embodiment, the BMC, as a board-level management controller, will first detect the voltage, current and temperature near the DUT test fixture of the 12V total input power supply input by the test system after the entire board is powered on. Only when all three are within the normal range can a test instruction be sent to the MCU of the corresponding channel to start the interface function test of the DUT. In some embodiments, appropriate voltage threshold intervals, current threshold intervals and temperature intervals can be pre-set respectively. After the BMC is powered on, it is determined whether the input voltage belongs to the preset voltage threshold interval, whether the input current belongs to the preset current threshold interval, and whether the detected temperature data belongs to the preset temperature interval. When all the above conditions are met, it is determined that the operating state of the chip test system and the ambient temperature conditions meet the test conditions, and the MCU can be powered on for subsequent testing.
[0027] In some implementations of the present embodiment, an isolation chip is also included. When the target test unit is connected to the chip to be tested, the isolation chip is connected between the target test unit and the chip to be tested to form a digital signal transmission channel; the digital signal transmission channel is used to realize the transmission of digital information between the target test unit and the chip to be tested during the test process (for example: during the process of the target test unit testing the FLASH), and the target test unit is also directly connected to the chip to be tested to form an analog signal transmission channel. The analog signal transmission channel is used to realize the transmission of current data and / or voltage data between the target test unit and the chip to be tested during the test process (for example: during the process of the target test unit testing the placement orientation of the chip to be tested and the short-circuit state of the power supply to the ground).
[0028] Specifically, Figure 2 As shown, the signals transmitted between MCU and DUT are divided into digital signals and analog signals. The digital signals are isolated by the isolation chip to avoid the MCU IO from leaking current to the DUT when the MCU is powered on but the DUT is not powered on, which will lead to adverse consequences. The analog signal consists of two parts: ADC and DAC. Since the digital isolation chip cannot be used, the MCU and DUT are directly connected, but a 0R resistor is reserved between the MCU and DUT for disconnection. Among the digital signals, UART1_TX, UART1_RX, and PF0~2 are used for communication between MCU and DUT, and the others are used for DUT startup mode control, working status control, and transmission of signals related to the interface under test.
[0029] Furthermore, in some implementations of the present embodiment, a first power supply module, a second power supply module and a load switch are also included, and the isolation chip includes a first side for connecting to a target test unit and a second side for connecting to a chip to be tested; the first power supply module is used to supply power to the target test unit and the first side, the load switch is used to realize conduction and disconnection between the second power supply module and the chip to be tested, and the second power supply module is used to supply power to the chip to be tested and the second side.
[0030] Specifically, Figure 2 As shown, the isolation chip is divided into two sides, A and B, and each side has a separate power supply to power the related IO. In the design, the side connected to the MCU is powered by the same power supply as the MCU (that is, the first power supply module), and the side connected to the DUT is powered by the DUT power supply (that is, the second power supply module). Therefore, when the DUT is not powered on, the isolation chip IO connected to the DUT is also not powered on, so no leakage current will be generated. The load switch is controlled by the MCU and can control whether to add voltage to the DUT power supply. The input power supply voltage of the load switch is monitored by the BMC. When the BMC recognizes that the voltage of the previous power supply is abnormal, it can send abnormal status information to the corresponding MCU to control whether to turn on or off the load switch.
[0031] In this embodiment, since the MCU works between the BMC and the DUT, the BMC interface is also needed. Figure 2 As shown, PG10 and PG11 are GPIOs connected between BMC and MCU, and UART3_TX and UART3_RX on MCU are serial ports for communication between MCU and BMC, which are mainly used to receive BMC instructions and report the test results of DUT interface to BMC. For example, BMC sends a "start test" instruction to MCU, MCU feeds back the second test result "test passed" or "test failed" to BMC, and if the placement direction of DUT or the power supply to ground short circuit state test fails before the test, the first test result fed back by MCU to BMC is "placement direction error" or "power supply short circuit" information.
[0032] Furthermore, in some implementations of the present embodiment, a DCDC chip connected to the baseboard management controller is also included, and the DCDC chip is also respectively connected to the target test unit and the first power supply module; the DCDC chip is used to convert the DC voltage of the first power supply module into a preset AC voltage after determining that the current operating status of the chip test system and the ambient temperature conditions meet the test conditions, and output the AC voltage to the target test unit.
[0033] Specifically, the DCDC chip can be used to implement a power management IC (Integrated Circuit) for buck or boost conversion, and adjust the output voltage to meet the needs of different loads. In this embodiment, the output voltage of the relevant power module can also be adjusted by the DCDC chip to power the baseboard management controller.
[0034] In some implementations of this embodiment, it also includes an orientation detection circuit connected to the target test unit, the orientation detection circuit is used to connect to the target IO of the chip to be tested, the target IO is the IO that is currently connected to the target test unit; the target test unit is specifically used to: when the placement orientation circuit is turned on by the target IO, read the voltage value of the target IO, and judge whether the placement orientation of the chip to be tested is correct according to the voltage value.
[0035] Specifically, in this embodiment, before testing the interface function of the chip to be tested, the placement orientation of the DUT in the fixture and the short-circuit state of the power supply to the ground must be tested first. Subsequent tests can only be performed when both parts of the test pass. Among them, when detecting the short-circuit state of the DUT power supply to the ground, it can be completed by electric meter detection, resistance testing, and short-circuit detection equipment, etc., which are not limited here. When detecting the placement orientation of the chip to be tested, it can be completed by visual observation, automatic detection circuit, etc., which are not limited here. In some embodiments, when the chip to be tested cannot be placed fool-proof in terms of physical structure, it is preferred to use the above-mentioned orientation detection circuit to determine whether the orientation is correct.
[0036] Further, in some preferred implementations of the present embodiment, the chip to be tested also includes a VDD power supply terminal, a VSS power supply terminal, a first diode and a second diode, the positive electrode of the first diode and the negative electrode of the second diode are respectively connected to the target IO, the VDD power supply terminal is connected to the negative electrode of the first diode, the VSS power supply terminal is connected to the positive electrode of the second diode, and the VSS power supply terminal is grounded; the direction detection circuit includes a pull-up resistor, a first switch unit and a second switch unit; one end of the first switch unit is connected to the target test unit, and the other end is used to be connected to the pull-up resistor; the end of the first switch unit connected to the target test unit is also used to be connected to the target IO; one end of the second switch unit is connected to the VDD power supply terminal, and the other end is used to be connected to a second power supply module outside the chip to be tested or to be grounded; the target test unit is also specifically used to: when the pull-up resistor and the target IO are connected and conducted through the first switch unit, and the VDD power supply terminal is grounded through the second switch unit; read the voltage value of the target IO, and judge whether the placement direction of the chip to be tested is correct according to the voltage value.
[0037] Specifically, the first switch unit and the second switch unit can both be single-pole double-throw switches, or circuits or integrated circuits having such a capability of controlling the conduction of circuit switches, which is not limited here. Figure 3 As shown, before the DUT is powered on, the MCU first controls the single-pole double-throw switch 1 (i.e., the first switch unit) and the single-pole double-throw switch 2 (i.e., the second switch unit) to switch to the circuit shown in the figure. At this time, the external circuit will pull up a target IO of the DUT to the power supply voltage (e.g., 3.3V) through a resistor, and at the same time, the VDD power supply of the DUT is grounded. Since, in the IO design of the DUT, there are two ESD diodes (i.e., the first diode and the second diode), which are respectively connected between the power supply and the target IO, and between the target IO and the VSS power supply ground; at this time, if the DUT is placed in the correct direction, the ESD diode between the power supply and the target IO will be forward-conducted, thereby causing the voltage of the target IO to drop from the power supply voltage to the forward conduction voltage of the ESD diode (e.g., 0.7V). At this time, the MCU uses the target IO with ADC function to read the voltage value of the target IO on the DUT. By distinguishing the voltage value, it can be determined whether the DUT is in place or placed correctly (for example, if the voltage of the target IO is between 0.1% and 3.3V, it is determined that the current placement direction is correct; otherwise, it is determined that the current placement direction is wrong). After the judgment is completed, the MCU controls the single-pole double-throw switch 1 and the single-pole double-throw switch 2 to switch back to the normal working circuit and executes the next step of the software design according to the result. It should be noted that if Figure 4 As shown, in the chip to be tested in this embodiment, the pin arrangement is centrally symmetrical. When the placement orientation is wrong, the chip to be tested can be rotated 90° and placed in the fixture to continue the placement orientation detection. If the detection finds that the placement orientation is still wrong, the chip to be tested can be rotated 90° and placed in the fixture to continue the placement orientation detection until it is determined that the placement orientation is correct.
[0038] In some implementations of this embodiment, the target test unit is further specifically used to output a level signal to the chip under test after being connected to the chip under test; the level signal is used to configure a pin voltage that meets the test requirements for the chip under test.
[0039] Specifically, the MCU works as the second level between the BMC and the DUT, and can control the power supply and configuration pin status of the DUT, that is, by connecting the IO of the MCU to the configuration pin of the DUT, and controlling the IO pin of the MCU to output a high or low level signal, the voltage state of the configuration pin of the DUT can be controlled. Specifically: the IO pin of the MCU can output a high or low level signal through program control; by controlling its voltage state, the working state or configuration of the DUT can be changed; the IO pin of the MCU is connected to the configuration pin of the DUT, and the high and low level signals output by the MCU are controlled as needed, so as to realize the control of the voltage state of the configuration pin of the DUT. In this way, the configuration state of the DUT can be indirectly controlled by controlling the output signal of the MCU without manually intervening in the hardware connection or external lines.
[0040] In some implementations of this embodiment, when testing the FLASH in the chip to be tested, the target test unit is also specifically used to: perform full address traversal data reading, data writing, and data erasing on the FLASH through the SPI interface.
[0041] The second embodiment of the present application provides a chip testing method, which is applied to the chip testing system of the first embodiment; Figure 5 The figure shows a basic flow chart of a chip testing method provided in this embodiment, and the chip testing method includes:
[0042] Step 501: When receiving a feedback signal from a target test unit and determining that the current operating state of the chip test system and the ambient temperature conditions meet the test conditions, the baseboard management controller sends a test instruction to the target test unit.
[0043] Specifically, the feedback signal is a signal confirming that the target test unit and the chip to be tested are in a connected state; after the target MCU detects that the chip to be tested is connected to the fixture, it can send a feedback signal to the BMC, and then the BMC can obtain parameters such as input voltage, input current, temperature data of the BMC itself, and temperature data of the target MCU. Combined with the above parameters, it determines whether the operating status of the chip test system and the ambient temperature conditions meet the test conditions. If the test conditions are met, a test instruction is sent to the target MCU.
[0044] Step 502: The target test unit responds to the test instruction to test the placement direction of the chip to be tested and the short-circuit state of the power supply to the ground, obtains a first test result and feeds the first test result back to the baseboard management controller.
[0045] Specifically, when detecting the short circuit state of the DUT power supply to the ground, it can be done by using an ammeter test, a resistance test, and a short circuit detection device, etc., without limitation. When detecting the placement orientation of the chip to be tested, it can be done by using visual observation, automatic detection circuits, etc., without limitation.
[0046] Step 503: If the first test result is that the test passes, the target test unit tests the FLASH in the chip to be tested, obtains a second test result, and feeds the second test result back to the baseboard management controller.
[0047] Specifically, the process of performing interface function test on the chip to be tested includes: performing full address traversal data reading, data writing, and data erasing on the FLASH through the SPI interface; and the MCU baseboard management controller reports the corresponding second test result.
[0048] In this embodiment, a one-to-one test relationship is established between the MCU and the chip to be tested, so that the test work between the test channels can be executed in parallel. The BMC chip can read the system temperature, voltage, and current values in real time, and judge whether the operating state of the system meets the test conditions based on these data. When the operating state of the system meets the test conditions, the test instructions are sent to the MCU and the test results are read. The test efficiency of the chip test system is significantly improved with the increase in the number of channels, and for test scenarios with long single-channel test time (such as FLASH full-chip read, write, and erase), the test time can be greatly reduced, effectively solving the time and resource waste problem caused by using one test chip to test multiple chips in sequence in the related technology.
[0049] In some implementations of the present embodiment, after the chip to be tested is connected to the target test unit, the target test unit sends a feedback signal to the baseboard management controller, and the baseboard management controller controls the power-on of the entire test system with 12V; the power supply module is controlled by the DCDC chip to output a 3.3V voltage to the baseboard management controller, so that the baseboard controller starts to work; the baseboard management controller determines whether the operating state of the chip test system and the ambient temperature conditions meet the test conditions based on the input voltage, input current, and various temperature data (ambient temperature); if the test conditions are met, the DCDC chip outputs a 3.3V voltage to the target test unit, and sends a "start test" test instruction to the target test unit, so that the target erase unit starts to power on; the target test unit first detects whether the placement direction of the chip to be tested in the fixture is correct and the power supply is short-circuited to the ground, and the MCU reports the corresponding first test result to the baseboard management controller; after both tests are passed, that is, when the first test result is a test pass, the MCU will open the load switch to power on the DUT, and after power-on, detect whether the DUT starts normally; the MCU performs subsequent interface function tests and feeds back the second test result to the baseboard management controller.
[0050] In the embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are only schematic, for example, the division of modules is only a logical function division, and there may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.
[0051] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0052] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.
[0053] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0054] The above is a description of the chip testing system and method provided in this application. For technicians in this field, according to the ideas of the embodiments of this application, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on this application.
Claims
1. A chip testing system, characterized in that: It includes a baseboard management controller and a plurality of test units electrically connected to the baseboard management controller, each of the test units is respectively configured with an interface for connecting to a chip to be tested; The baseboard management controller is used to send a test instruction to the target test unit when receiving a feedback signal from the target test unit and determining that the current operating state of the chip test system and the ambient temperature conditions meet the test conditions; wherein the feedback signal is a signal confirming that the target test unit is in a connected state with the chip to be tested; The target test unit is used to respond to the test instruction, test the placement orientation and the power supply to ground short-circuit state of the chip to be tested, obtain a first test result and feed the first test result back to the baseboard management controller; if the first test result is a test pass, test the FLASH in the chip to be tested, obtain a second test result and feed the second test result back to the baseboard management controller.
2. The chip testing system according to claim 1, characterized in that: It also includes an isolation chip, when the target test unit is connected to the chip to be tested, the isolation chip is connected between the target test unit and the chip to be tested to form a digital signal transmission channel; The digital signal transmission channel is used to realize the transmission of digital information between the target test unit and the chip under test during the test process; The target test unit is also directly connected to the chip under test to form an analog signal transmission channel; the analog signal transmission channel is used to realize the transmission of current data and / or voltage data between the target test unit and the chip under test during the test process.
3. The chip testing system according to claim 2, characterized in that: It also includes a first power supply module, a second power supply module and a load switch, and the isolation chip includes a first side for connecting to the target test unit and a second side for connecting to the chip to be tested; the first power supply module is used to supply power to the target test unit and the first side, and the load switch is used to achieve conduction and disconnection between the second power supply module and the chip to be tested, and the second power supply module is used to supply power to the chip to be tested and the second side.
4. The chip testing system according to claim 3, characterized in that: It also includes a DCDC chip connected to the baseboard management controller, and the DCDC chip is also connected to the target test unit and the first power supply module respectively; the DCDC chip is used to convert the DC voltage of the first power supply module into a preset AC voltage after determining that the current operating state of the chip test system and the ambient temperature conditions meet the test conditions, and output the AC voltage to the target test unit.
5. The chip testing system according to claim 1, characterized in that: It also includes a direction detection circuit connected to the target test unit, the direction detection circuit is used to connect to the target IO of the chip under test, the target IO is the IO currently connected to the target test unit; The target test unit is specifically used for: when the placement orientation circuit is connected to the target IO, reading the voltage value of the target IO, and judging whether the placement orientation of the chip to be tested is correct according to the voltage value.
6. The chip testing system according to claim 5, characterized in that: The chip under test further includes a VDD power supply terminal, a VSS power supply terminal, a first diode and a second diode, wherein an anode of the first diode and a cathode of the second diode are respectively connected to the target IO, the VDD power supply terminal is connected to the cathode of the first diode, the VSS power supply terminal is connected to the anode of the second diode, and the VSS power supply terminal is grounded; The direction detection circuit includes a pull-up resistor, a first switch unit and a second switch unit; one end of the first switch unit is connected to the target test unit, and the other end is used to connect to the pull-up resistor; the end of the first switch unit connected to the target test unit is also used to connect to the target IO; one end of the second switch unit is connected to the VDD power supply terminal, and the other end is used to connect to the second power supply module outside the chip under test or to be grounded; The target test unit is also specifically used for: when the pull-up resistor and the target IO are connected and conducted through the first switch unit, and the VDD power supply terminal is grounded through the second switch unit; reading the voltage value of the target IO, and judging whether the placement orientation of the chip to be tested is correct according to the voltage value.
7. The chip testing system according to claim 1, characterized in that: It also includes a voltage sensor, a current sensor and a plurality of temperature sensors respectively connected to the baseboard management controller; the plurality of temperature sensors are respectively used to obtain temperature data of the baseboard management controller and the target test unit; The baseboard management controller is specifically used to: combine the temperature data, the input voltage obtained by the voltage sensor, and the input current obtained by the current sensor to determine whether the operating status of the chip test system and the ambient temperature conditions meet the test conditions.
8. The chip testing system according to claim 1, characterized in that: The target test unit is further specifically used to output a level signal to the chip under test after being connected to the chip under test; the level signal is used to configure a pin voltage that meets the test requirements for the chip under test.
9. The chip testing system according to claim 1, characterized in that: When testing the FLASH, the target test unit is also specifically used to: perform full address traversal data reading, data writing, and data erasing on the FLASH through the SPI interface.
10. A chip testing method, characterized in that: Applicable to the chip testing system as claimed in any one of claims 1 to 9; the method comprises: The baseboard management controller sends a test instruction to the target test unit when receiving a feedback signal from the target test unit and determining that the current operating state of the chip test system and the ambient temperature conditions meet the test conditions; wherein the feedback signal is a signal confirming that the target test unit is in a connected state with the chip to be tested; The target test unit tests the placement direction of the chip to be tested and the short-circuit state of the power supply to the ground in response to the test instruction, obtains a first test result and feeds the first test result back to the baseboard management controller; If the first test result is that the test is passed, the target test unit tests the FLASH in the chip to be tested to obtain a second test result and feeds the second test result back to the baseboard management controller.