An LED chip defect detection method, device, equipment and storage medium

Abstract

The present invention relates to the technical field of defect detection, and in particular, to a method, device, equipment, and storage medium for detecting defects in LED chips. The method includes the following steps: obtaining the structural data of an LED chip sample; performing chip electrical connection on the LED chip based on the structural data of the LED chip sample to generate chip electrical connection data; confirming the critical levels of electrical connection for the chip electrical connection data, and performing three-dimensional reconstruction on the confirmed critical levels of electrical connection to obtain the three-dimensional structural data of the electrical connection metallization layer; dividing the three-dimensional structural data of the metallization layer into the external three-dimensional structural data of the metallization layer and the internal three-dimensional structural data of the metallization layer; performing temperature equilibrium defect detection on the external three-dimensional structural data of the metallization layer to generate surface defect detection data of the metallization layer. The present invention realizes automated three-dimensional structure reconstruction, comprehensive defect detection, intelligent prediction and evaluation, and improves the accuracy of detecting defects in the fine material levels inside the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of defect detection, and particularly to a method, device, equipment and storage medium for detecting defects of LED chips. Background Art

[0002] Initially, the defect detection of LED chips mainly relied on manual inspection. Although this method was simple, it had low efficiency and was easily affected by human factors, resulting in poor accuracy and consistency of the detection results. With the development of the LED industry, manual detection could not meet the requirements of high-precision and large-scale production, and gradually, automatic detection technologies based on vision emerged. After entering the 21st century, the introduction of computer vision technology and image processing algorithms enabled the defect detection of LED chips to gradually achieve automation. The initial detection systems used simple image acquisition and processing methods, which could detect common surface defects such as cracks, bubbles, scratches, etc., but had poor recognition ability for subtle defects. With the development of deep learning and artificial intelligence technologies, defect detection methods based on convolutional neural networks (CNNs) gradually became the mainstream. However, most traditional technologies focused on the detection of chip surface defects. For the detection of the internal metallization layer, due to its small size, concealment and complexity, it was difficult, resulting in many existing technologies not covering it or lacking sufficient processing capabilities. At the same time, the metallization layer is usually composed of a thin metal film with a small thickness and a smooth surface. Traditional detection methods such as surface scanning and optical detection are difficult to accurately identify the tiny defects in the metal layer, thus leading to low accuracy in the detection of chip subtle defects. Summary of the Invention

[0003] Based on this, it is necessary to provide a method, device, equipment and storage medium for detecting defects of LED chips to solve at least one of the above technical problems.

[0004] To achieve the above object, a method for detecting defects of LED chips, the method includes the following steps:

[0005] Step S1: Obtain the structural data of the LED chip sample; perform chip electrical connection on the LED chip based on the structural data of the LED chip sample to generate chip electrical connection data; confirm the key levels of electrical connection for the chip electrical connection data, and perform three-dimensional reconstruction on the confirmed key levels of electrical connection to obtain the three-dimensional structural data of the electrical connection metallization layer;

[0006] Step S2: dividing the three-dimensional structure data of the metallization layer into the external three-dimensional structure data of the metallization layer and the internal three-dimensional structure data of the metallization layer; performing temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer; performing particle group image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; integrating the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer;

[0007] Step S3: Model training is performed on the electrical connection metallization layer defect detection data to generate an LED chip electrical connection defect prediction model; the three-dimensional structure data of the electrical connection metallization layer is imported into the LED chip electrical connection defect prediction model to perform chip electrical connection defect prediction and generate electrical connection defect prediction data;

[0008] Step S4: Evaluate the chip circuit connection stability of the LED chip according to the electrical connection defect prediction data to generate chip circuit connection stability evaluation data; visualize the chip circuit connection stability evaluation data to generate an LED chip circuit defect detection report.

[0009] The present invention can accurately capture the metallization layer structure of the chip electrical connection by acquiring the structural data of the LED chip sample and performing three-dimensional reconstruction, ensuring the comprehensiveness and accuracy of the detection. This step provides reliable basic data for subsequent defect detection, especially when dealing with complex electrical connection metallization layers, the three-dimensional reconstruction technology improves the accuracy of detection. The three-dimensional structural data of the metallization layer is divided into external and internal structures, and different defect detection technologies (temperature balance and particle group image) are applied in a targeted manner to make the detection more targeted and accurate. External detection focuses on surface defects, while internal detection deals with hidden defects in the metallization layer to ensure all-round defect detection, especially to identify subtle internal problems. By training the defect detection data and generating a prediction model for the electrical connection defects of the LED chip, potential defects can be predicted automatically in actual detection. By combining the three-dimensional structural data with the prediction model, potential problems of the chip electrical connection can be identified in advance, which significantly improves the efficiency and accuracy of detection and reduces errors caused by human intervention. By evaluating the circuit connection stability of LED chips based on the electrical connection defect prediction data, the chip stability can be understood in real time, and a circuit defect detection report can be generated through data visualization to help engineers quickly identify problems and make adjustments. This step not only improves the efficiency of fault diagnosis, but also provides a scientific basis for chip quality control and promotes chip production and application optimization. Therefore, the present invention improves the accuracy of fine material level defect detection inside the chip through automated three-dimensional structure reconstruction, comprehensive defect detection, intelligent prediction and evaluation.

[0010] Preferably, step S1 includes the following steps:

[0011] Step S11: Obtain the structural data of the LED chip sample using an electron microscope;

[0012] Step S12: Perform chip electrical connection on the LED chip based on the structural data of the LED chip sample to generate chip electrical connection data;

[0013] Step S13: Use the chip electrical connection data to perform structural screening on the structural data of the LED chip sample to obtain the electrical connection structure data of the LED chip sample;

[0014] Step S14: Confirm the key levels of electrical connection for the electrical connection structure data of the LED chip sample, and perform three-dimensional reconstruction on the confirmed key levels of electrical connection to obtain the three-dimensional structure data of the electrical connection metallization layer.

[0015] The present invention obtains the structural data of the LED chip sample with high resolution through an electron microscope, ensuring detailed and accurate structural information at the microscopic level and laying a solid foundation for subsequent analysis. By performing electrical connection on the chip, the current flow inside the chip can be understood, ensuring that the electrical performance of the chip is within the expected range, which provides key data support for designing and optimizing the performance of the LED chip. Screening the electrical connection structure of the LED chip can exclude unqualified or unoptimized connection structures, ensure the maximization of the chip's performance, and improve the yield rate of the production process. Through three-dimensional reconstruction of the electrical connection metallization layer, the spatial distribution of the chip structure can be accurately presented, which helps in further designing, adjusting, and optimizing the chip. At the design level, this helps to improve the reliability, durability, and manufacturing precision of the LED chip.

[0016] Preferably, step S14 further includes:

[0017] Perform energy spectrum analysis on the electrical connection structure data of the LED chip sample to generate electrical connection energy spectrum data; use the electrical connection energy spectrum data to perform elemental composition analysis on the electrical connection structure data of the LED chip sample. When an elemental composition is analyzed, the corresponding structure is marked as the electrical connection metal layer;

[0018] Perform elemental distribution analysis on the electrical connection metal layer to generate electrical connection metal layer elemental distribution data; identify the key metal layer of the electrical connection metal layer based on the electrical connection metal layer elemental distribution data to obtain the electrical connection key metal layer;

[0019] Perform three-dimensional reconstruction on the electrical connection structure data of the LED chip sample based on the electrical connection key metal layer to generate the three-dimensional structure data of the metallization layer.

[0020] Through energy spectrum analysis of the electrical connection structure data of LED chip samples, the present invention can effectively obtain the energy distribution and chemical composition of each material within the chip, which provides an accurate physical basis for subsequent analysis, making the elemental composition analysis in different levels and regions more efficient and precise. Elemental composition analysis of the electrical connection structure of LED chips not only reveals the distribution of various elements in the chips, but also marks out the electrical connection metal layers. This provides key data support for subsequent design and fault diagnosis, and helps to improve the stability and reliability of the chips in terms of electrical performance. Analyzing the elemental distribution of the electrical connection metal layers can identify the uniformity and integrity of the metal layers, ensure the quality of the metallization layers, and avoid unstable electrical performance or premature chip failure caused by defects in the metallization layers. Through the identification of key metal layers, the metal layers crucial for the electrical connection of the chips can be accurately found, which helps to locate the weak links affecting the performance in the chip structure and provides a clear direction for the design optimization of the chips. Based on the identification of the key metal layers for electrical connection, three-dimensional reconstruction is carried out to generate three-dimensional structure data of the metallization layers, which can help engineers intuitively understand the internal and external structures of the chips, facilitate the optimization of the electrical connection design, and improve the performance and reliability of the chips.

[0021] Preferably, step S2 includes the following steps:

[0022] Step S21: Divide the three-dimensional structure data of the metallization layer into external three-dimensional structure data of the metallization layer and internal three-dimensional structure data of the metallization layer based on the thickness of the three-dimensional structure of the metallization layer;

[0023] Step S22: Use an infrared imaging sensor to analyze the surface temperature distribution of the chip metallization layer of the LED chip to generate surface temperature distribution data of the chip metallization layer; perform temperature equilibrium defect detection on the external three-dimensional structure data of the metallization layer according to the surface temperature distribution data of the chip metallization layer to generate surface defect detection data of the metallization layer;

[0024] Step S23: Use particle pulse technology to emit high-speed particles to the LED chip to obtain high-speed particle pulse data; perform particle swarm image defect detection on the internal three-dimensional structure data of the metallization layer through the high-speed particle pulse data to generate internal defect detection data of the metallization layer;

[0025] Step S24: Integrate the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer.

[0026] By dividing the three-dimensional structure data of the metallization layer into external and internal data according to the thickness, the present invention provides a more refined perspective for subsequent defect detection and analysis. This helps to accurately identify the structural characteristics of different levels, targetedly solve different problems of the external and internal parts, and improve the accuracy and efficiency of analysis. By using an infrared imaging sensor to analyze the surface temperature distribution of the chip metallization layer, temperature anomaly areas can be quickly detected. These anomalies indicate uniformity problems or other potential defects in the metallization layer. Combining with temperature balance defect detection can early identify areas that cause thermal damage or electrical performance instability, and improve the product quality control and thermal management capabilities. By using the high-speed particle pulse technology to emit on the chip, tiny defects inside the metallization layer, such as voids and cracks, can be effectively identified, which cannot be found by traditional methods. The particle pulse data provides a more accurate and non-destructive detection method, which helps to optimize the internal structure of the metallization layer and improve the long-term stability and reliability of the chip. By integrating the defect detection data of the surface and the inside of the metallization layer, comprehensive defect detection data of the electrical connection metallization layer is obtained. This comprehensive detection method can be analyzed from multiple dimensions and levels, providing a comprehensive view of fault detection, which helps to improve the yield rate in the chip manufacturing process and reduce potential performance problems.

[0027] Preferably, step S22 includes the following steps:

[0028] Step S221: Use an infrared imaging sensor to collect the surface temperature image of the chip metallization layer of the LED chip to obtain the surface temperature image of the metallization layer;

[0029] Step S222: Perform image preprocessing on the surface temperature image of the metallization layer to generate a standard surface temperature image of the metallization layer, where the image preprocessing includes image correction and image denoising; perform image data conversion on the standard surface temperature image of the metallization layer to generate temperature information data of the metallization layer;

[0030] Step S223: Map the temperature information data of the metallization layer to generate surface temperature distribution data of the chip metallization layer; calculate the temperature difference between adjacent pixels of the standard surface temperature image of the chip metallization layer according to the surface temperature distribution data of the chip metallization layer to obtain the temperature difference between each group of adjacent pixels;

[0031] Step S224: Analyze the uniformity of the surface temperature distribution data of the chip metallization layer through the temperature difference between each group of adjacent pixels to generate surface temperature uniformity data of the chip metallization layer; use the surface temperature uniformity data of the chip metallization layer to perform temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer.

[0032] The present invention collects surface temperature images of the chip metallization layer through an infrared imaging sensor, which can provide high-resolution temperature data. This precise temperature image collection provides high-quality basic data for subsequent defect detection, ensuring the accuracy and reliability of the analysis results. Image correction and denoising processing can eliminate errors caused by imaging devices, environmental interference, or data corruption, generating a standardized temperature image. This step ensures the consistency and clarity of the input data, providing accurate temperature information data for subsequent analysis. Through image data conversion and temperature distribution mapping, the temperature information of the chip metallization layer can be extracted, and detailed temperature distribution data can be generated. These data are crucial for evaluating the thermal management performance and uniformity of the metallization layer, providing a clear basis for defect detection. By calculating the temperature difference between adjacent pixels, uneven temperature regions on the surface of the chip metallization layer can be identified. Temperature differences are often potential indicators of defects in the metallization layer, such as weak areas, heat source concentration regions, or material non-uniformities. This process helps to detect and locate thermal management problems at an early stage. Through the analysis of temperature uniformity, the temperature distribution on the surface of the metallization layer can be comprehensively evaluated. The analysis of temperature uniformity can help identify irregular thermal patterns, thereby locating temperature equilibrium defect regions, which is of great significance for improving the thermal stability of LED chips and avoiding overheating problems. Temperature equilibrium defect detection can not only accurately locate surface defect regions but also provide data support for subsequent optimization design. By identifying surface defects in the metallization layer, it helps to improve the quality of the chip, extend its service life, and ensure its stable electrical performance.

[0033] Preferably, step S23 includes the following steps:

[0034] Step S231: Use particle pulse technology to perform high-speed particle emission on the LED chip to obtain high-speed particle pulse data;

[0035] Step S232: Identify the particle signal characteristics of the high-speed particle pulse data to generate particle signal characteristic data; analyze the particle propagation path of the high-speed particle pulse data according to the particle signal characteristic data to generate particle propagation path data;

[0036] Step S233: Perform structure mapping on the particle propagation path data and the internal three-dimensional structure data of the metallization layer to generate internal particle structure mapping data of the metallization layer; perform particle reflection and scattering analysis on the internal particle structure mapping data of the metallization layer respectively to generate metallization layer particle group image data;

[0037] Step S234: Quantify the uniformity of the particle pulse signal of the metallization layer particle group image data to generate a particle pulse signal uniformity value; perform internal particle defect detection on the internal three-dimensional structure data of the metallization layer based on the particle pulse signal uniformity value to generate internal defect detection data of the metallization layer.

[0038] The present invention uses high-speed particle emission through particle pulse technology to obtain data inside the chip metallization layer. This non-invasive method can penetrate deep into the material to detect tiny defects that cannot be discovered by traditional techniques. Through high-speed particle pulse data, higher-precision analysis of the internal structure of the chip can be achieved. The feature recognition of particle signals can help extract key information, thereby accurately analyzing the propagation path of the particles. The generation of particle propagation path data provides detailed particle flow trajectories for subsequent analysis, enabling researchers to deeply understand how particles propagate inside the chip and identify potential defect sources. By performing structural mapping of the particle propagation path data with the three-dimensional structure data inside the metallization layer, the propagation route of the particles can be accurately calibrated in the three-dimensional space inside the chip. This process provides visual support for subsequent particle reflection and scattering analysis, helping to reveal the physical properties and potential problem areas inside the chip. Particle reflection and scattering analysis can detect tiny defects inside the metallization layer, such as cracks, voids, or structural inhomogeneities. This process can reveal the heterogeneity inside the metallization layer, timely discover potential problems of material inhomogeneity or affecting electrical connections, and contribute to improving the long-term reliability and stability of the chip. The quantification of particle pulse signal uniformity can quantify the uniformity of particle propagation and analyze the influence of internal defect areas, which helps to accurately evaluate the quality and uniformity of the metallization layer and timely discover defects that lead to thermal runaway, electrical short circuits, or other performance problems. Defect detection inside the metallization layer based on the particle pulse signal uniformity value can accurately identify the defect areas that affect the performance inside the chip. This process provides strong data support for the quality control of the chip, helping to avoid defective products during the production process and improve the reliability of the product.

[0039] Preferably, step S3 includes the following steps:

[0040] Step S31: Extract defect features from the defect detection data of the electrical connection metallization layer to obtain metallization layer defect feature data; divide the metallization layer defect feature data into data sets to generate a model training set and a model test set;

[0041] Step S32: Use the support vector machine algorithm to train the model training set to generate a pre-model for predicting electrical connection defects of LED chips; use the model test set to optimize and iterate the pre-model for predicting electrical connection defects of LED chips to generate a prediction model for electrical connection defects of LED chips;

[0042] Step S33: Import the three-dimensional structure data of the electrical connection metallization layer into the prediction model for electrical connection defects of LED chips to predict electrical connection defects of the chip and generate electrical connection defect prediction data.

[0043] Through feature extraction from the defect detection data of the electrical connection metallization layer, the present invention can extract the most significant features for defect diagnosis from a large amount of data. This data processing method can effectively reduce noise and improve the accuracy of the prediction model. At the same time, by dividing the dataset (training set and test set), the generalization ability and reliability of the model are ensured, enabling the model to perform stably in different data environments. The support vector machine algorithm, with its excellent classification ability and strong performance in high-dimensional data spaces, can provide accurate predictions for the electrical connection defects of LED chips. During the model training stage, SVM can find the optimal classification hyperplane based on the feature data in the training set, thus effectively distinguishing normal and defective electrical connections. The optimization and iteration of the model further improve the prediction accuracy, making it adaptable to more complex defect patterns. By importing the three-dimensional structure data of the electrical connection metallization layer into the trained defect prediction model, real-time defect prediction can be carried out, which not only provides reliable support for troubleshooting during the production process but also enables potential problems to be detected in advance during the chip design stage, reducing the cost and time of later repairs. Through continuous iteration during the model optimization process, the algorithm can learn more accurate defect prediction patterns. This intelligent optimization not only improves the prediction accuracy but also enables the model to continuously adapt to new data and defect types, enhancing the adaptive ability and flexibility of the system. By predicting electrical connection defects in advance, defective products in the LED chip manufacturing process can be discovered and excluded at an early stage. This process greatly reduces the rework and scrap rates caused by defects, improves production efficiency and product quality, and ultimately reduces the manufacturing cost. Accurate defect prediction can avoid performance failures of the chip in actual applications and enhance its long-term reliability. Especially in high-demand application scenarios such as communication and lighting, avoiding electrical connection defects is crucial for ensuring the stable operation of the system.

[0044] In this specification, a defect detection device for an LED chip is provided for performing the above-mentioned LED chip defect detection method. The defect detection device for an LED chip includes:

[0045] A three-dimensional reconstruction module for obtaining the structure data of an LED chip sample; electrically connecting the LED chip based on the structure data of the LED chip sample to generate chip electrical connection data; confirming the key electrical connection levels for the chip electrical connection data and performing three-dimensional reconstruction on the confirmed key electrical connection levels to obtain the three-dimensional structure data of the electrical connection metallization layer;

[0046] A defect detection module, configured to divide the three-dimensional structure data of the metallization layer into the external three-dimensional structure data of the metallization layer and the internal three-dimensional structure data of the metallization layer; perform temperature equilibrium defect detection on the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer; perform particle swarm image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; integrate the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer;

[0047] A defect prediction module, configured to perform model training on the defect detection data of the electrical connection metallization layer to generate an LED chip electrical connection defect prediction model; import the three-dimensional structure data of the electrical connection metallization layer into the LED chip electrical connection defect prediction model to perform chip electrical connection defect prediction, and generate electrical connection defect prediction data;

[0048] A circuit stability evaluation module, configured to evaluate the chip circuit connection stability of the LED chip according to the electrical connection defect prediction data to generate chip circuit connection stability evaluation data; perform data visualization on the chip circuit connection stability evaluation data to generate an LED chip circuit defect detection report.

[0049] The present invention provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the above-mentioned LED chip defect detection method is implemented.

[0050] The present invention further provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned LED chip defect detection method is implemented.

[0051] The beneficial effects of the present invention are as follows: By accurately obtaining the structural data of the LED chip through the three-dimensional reconstruction module and further analyzing the electrical connection of the chip, it is possible to better understand the integrity of the internal electrical connection of the chip, providing solid data support for subsequent defect detection and stability evaluation. By dividing the metallization layer into external and internal data and performing temperature equilibrium defect detection and particle swarm defect detection respectively, potential defects on the surface and inside are effectively identified, improving the comprehensiveness and accuracy of defect detection and ensuring the early discovery of problems in the chip production process. Using a machine learning model to train the detection data to generate a prediction model for electrical connection defects of the LED chip enables the system not only to perform real-time defect detection but also to predict future electrical connection problems, thereby giving early warnings and making targeted optimizations. Through the prediction data of electrical connection defects, the stability of the circuit connection of the LED chip is evaluated, which can accurately reflect the risks existing in the circuit, predict the stability of the circuit in advance, and provide guarantee for the long-term stable operation of the chip. The system presents the evaluation results through data visualization, generating a detailed circuit defect detection report, helping engineers quickly understand the quality and stability of the chip and providing data support for subsequent improvements. Therefore, the present invention improves the accuracy of detecting subtle material-level defects inside the chip through automated three-dimensional structure reconstruction, comprehensive defect detection, intelligent prediction, and evaluation. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 FIG. is a schematic flow chart of the steps of a method for detecting defects of an LED chip;

[0053] Figure 2 is Figure 1 a detailed implementation step flow chart of step S2 in;

[0054] Figure 3 is Figure 1 a detailed implementation step flow chart of step S3 in;

[0055] The realization, functional features, and advantages of the object of the present invention will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0056] The technical method of the present invention for patents will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those skilled in the art within the scope of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0057] In addition, the attached drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor methods and / or microcontroller methods.

[0058] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed associated items.

[0059] To achieve the above object, please refer to Figures 1 to 3 , a method for detecting defects of LED chips, the method comprising the following steps:

[0060] Step S1: Obtain the structural data of the LED chip sample; perform chip electrical connection on the LED chip based on the structural data of the LED chip sample to generate chip electrical connection data; confirm the key levels of electrical connection for the chip electrical connection data, and perform three-dimensional reconstruction on the confirmed key levels of electrical connection to obtain the three-dimensional structural data of the electrical connection metallization layer;

[0061] Step S2: Divide the three-dimensional structural data of the metallization layer into the three-dimensional structural data outside the metallization layer and the three-dimensional structural data inside the metallization layer; perform temperature equilibrium defect detection on the three-dimensional structural data outside the metallization layer to generate surface defect detection data of the metallization layer; perform particle swarm image defect detection on the three-dimensional structural data inside the metallization layer to generate internal defect detection data of the metallization layer; integrate the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer;

[0062] Step S3: Perform model training on the defect detection data of the electrical connection metallization layer to generate a prediction model for electrical connection defects of the LED chip; import the three-dimensional structural data of the electrical connection metallization layer into the prediction model for electrical connection defects of the LED chip to predict electrical connection defects of the chip, and generate electrical connection defect prediction data;

[0063] Step S4: Evaluate the connection stability of the chip circuit of the LED chip based on the electrical connection defect prediction data to generate chip circuit connection stability evaluation data; visualize the chip circuit connection stability evaluation data to generate an LED chip circuit defect detection report.

[0064] Through obtaining the structural data of the LED chip samples and performing 3D reconstruction, the present invention can accurately capture the metallization layer structure of the chip electrical connection, ensuring the comprehensiveness and accuracy of the detection. This step provides reliable basic data for subsequent defect detection. Especially when dealing with complex electrical connection metallization layers, the 3D reconstruction technology improves the detection accuracy. Divide the 3D structure data of the metallization layer into external and internal structures, and apply different defect detection techniques (temperature equilibrium and particle swarm imaging) specifically, making the detection more targeted and precise. The external detection focuses on surface defects, while the internal detection deals with hidden defects within the metallization layer, ensuring comprehensive defect detection and especially being able to identify subtle internal problems. By training the defect detection data to generate an LED chip electrical connection defect prediction model, potential defects can be automatically predicted during actual detection. Combining the 3D structure data with the prediction model to identify potential problems in the chip electrical connection in advance significantly improves the detection efficiency and accuracy and reduces errors caused by human intervention. Evaluating the circuit connection stability of the LED chip according to the electrical connection defect prediction data can understand the stability of the chip in real time, and generate a circuit defect detection report through data visualization, helping engineers quickly identify problems and make adjustments. This step not only improves the efficiency of fault diagnosis but also provides a scientific basis for chip quality control, promoting the optimization of chip production and application. Therefore, the present invention improves the accuracy of detecting subtle material-level defects inside the chip through automated 3D structure reconstruction, comprehensive defect detection, intelligent prediction, and evaluation.

[0065] In the embodiment of the present invention, refer to Figure 1 As described, it is a schematic diagram of the step flow of a method for detecting defects in an LED chip according to the present invention. In this example, the method for detecting defects in an LED chip includes the following steps:

[0066] Step S1: Obtain the structural data of the LED chip samples; perform chip electrical connection on the LED chip based on the structural data of the LED chip samples to generate chip electrical connection data; confirm the key levels of electrical connection for the chip electrical connection data, and perform 3D reconstruction on the confirmed key levels of electrical connection to obtain the 3D structure data of the electrical connection metallization layer;

[0067] In the embodiments of the present invention, the physical structure data of the LED chip is obtained from an LED chip manufacturer or by using a scanning device. High-precision devices such as electron microscopes and scanning electron microscopes (SEM) can be used to obtain microscopic structure images of the chip. Through image processing techniques, these data are converted into a digital 3D structure model for subsequent analysis. According to the obtained 3D structure data, circuit design software (such as Cadence, Altium Designer, etc.) is used to simulate the electrical connections. By connecting elements such as the pins, pads, and wires of the chip, a virtual model of the electrical connection is formed. During the electrical connection process, it is necessary to ensure the correct connection of the power supply, signal pins, and ground wire of the chip to ensure the normal operation of the chip. Based on the simulation of the electrical connection of the chip, the connected data is extracted to form an electrical connection dataset, including current flow direction, voltage distribution, signal transmission path, etc. These data can be further converted into circuit board design data or directly used for electrical verification during the manufacturing process. In the electrical connection data, key layers such as the power layer, signal layer, and ground layer are identified, and their connection relationships and stabilities are confirmed. Each key layer is evaluated to ensure that it meets the electrical performance requirements, such as current-carrying capacity and signal integrity. Three-dimensional modeling software (such as SolidWorks, ANSYS, etc.) is used to perform three-dimensional reconstruction of the key layers according to the electrical connection data. In this step, it is ensured that the reconstructed three-dimensional structure model accurately reflects the actual situation of the electrical connection and takes into account factors such as current flow direction and thermal effects. Based on the data of the three-dimensional reconstruction, the geometric information of the metallization layer, including metal lines, solder joints, connection channels, etc., is extracted to generate the three-dimensional structure data of the final electrical connection metallization layer for further analysis or manufacturing process optimization.

[0068] Step S2: Divide the three-dimensional structure data of the metallization layer into the external three-dimensional structure data of the metallization layer and the internal three-dimensional structure data of the metallization layer; perform temperature equilibrium defect detection on the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer; perform particle swarm image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; integrate the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer;

[0069] In the embodiments of the present invention, the overall three-dimensional structure data of the metallization layer is divided by using three-dimensional modeling and data segmentation tools (such as CAD software, MeshLab, etc.). According to the design and physical structure of the chip, the external and internal regions of the metallization layer are distinguished. The external region is usually the surface of the metallization layer, mainly involving the contact surfaces for electrical connections. The internal region refers to the conductive lines and connection channels inside the metallization layer, which are related to the current path and signal transmission inside the chip. A thermal analysis tool (such as ANSYS Thermal, COMSOL, etc.) is used to simulate the thermal distribution to identify the regions with uneven temperature on the surface of the metallization layer. These regions are caused by poor connections or material defects, resulting in heat concentration, which affects the long-term reliability of the chip. Based on the thermal simulation results, the temperature uniformity difference is analyzed to detect the hot spot regions. Potential surface defects, such as microcracks, bubbles, short circuits, etc., are identified through abnormal patterns of temperature changes. The positions, sizes, properties, etc. of the detected surface defects are recorded to form the surface defect detection data of the metallization layer. The particle swarm optimization (PSO) algorithm is applied for internal defect detection. This method can identify tiny defects in the three-dimensional structure data by simulating the optimization behavior of the particle swarm in the search space. In the internal three-dimensional structure of the metallization layer, the particle swarm algorithm scans each region to identify potential defects, such as microcracks, voids, uneven thickness of the conductive layer, etc. Technologies such as CT scanning or X-ray imaging can be used to obtain the internal three-dimensional structure data to further verify the detection results. The spatial positions, sizes, shapes, etc. of all internal defects are recorded to generate the internal defect detection data of the metallization layer. The surface and internal defect detection data of the metallization layer are unified and integrated. Through data fusion techniques, such as weighted average, principal component analysis (PCA), etc., the detection results from different data sources are integrated into a unified defect dataset. According to the integrated defect data, the overall quality of the metallization layer is analyzed, including indicators such as the distribution, size, and quantity of surface and internal defects. This will help evaluate the reliability and durability of the electrical connections and generate complete defect detection data for the electrical connection metallization layer, including information on all surface and internal defects, for reference in subsequent optimization and manufacturing processes.

[0070] Step S3: Train a model with the defect detection data of the electrical connection metallization layer to generate a prediction model for electrical connection defects of the LED chip; import the three-dimensional structure data of the electrical connection metallization layer into the prediction model for electrical connection defects of the LED chip to predict the electrical connection defects of the chip and generate electrical connection defect prediction data;

[0071] In the embodiments of the present invention, by preprocessing the defect detection data of the electrical connection metallization layer, including data cleaning, standardization, and feature engineering, irrelevant features can be removed and missing values can be filled to ensure the integrity and consistency of the data. Important features are extracted from the defect detection data, such as the type, location, size, shape, depth, etc. of the defects. Feature selection techniques, such as correlation analysis, principal component analysis (PCA), etc., can be used to extract key features related to electrical connection defects. An appropriate machine learning or deep learning model is selected to train the defect prediction model. Commonly used models include: Support Vector Machine (SVM): suitable for smaller datasets and can effectively classify different types of defects. Decision trees and random forests can handle non-linear features, are suitable for larger datasets, and have good prediction accuracy. Neural networks, especially Convolutional Neural Networks (CNN), are suitable for processing structured data and image data and can capture complex patterns. The defect detection data of the electrical connection metallization layer is used to train the model, and cross-validation is performed to prevent overfitting. The optimal model is selected by comparing the performance of different models (such as accuracy, precision, recall, etc.). After training and validation, an LED chip electrical connection defect prediction model is generated. This model can predict the defects existing in the electrical connection based on the input metallization layer data. The three-dimensional structure data of the metallization layer is used as input and imported into the trained LED chip electrical connection defect prediction model. The data can be 3D mesh data, surface texture data, or other structured data. The model performs electrical connection defect prediction based on the input three-dimensional structure data and identifies potential defect areas and problems. The prediction results include the location, type, impact, etc. of the defects. According to the model output, electrical connection defect prediction data is generated. This data includes detailed information about each predicted defect, such as the predicted defect type, impact, risk level of electrical performance degradation, etc. The accuracy of the prediction results is verified through actual tests. The prediction results can be compared with the actual defects to evaluate the effectiveness and accuracy of the model. If necessary, the model can be further optimized. With the accumulation of more samples and data, the prediction model can be updated regularly to improve its prediction accuracy and robustness.

[0072] Step S4: Evaluate the chip circuit connection stability of the LED chip according to the electrical connection defect prediction data, and generate chip circuit connection stability evaluation data; visualize the chip circuit connection stability evaluation data to generate an LED chip circuit defect detection report.

[0073] In the embodiments of the present invention, the stability evaluation objective of the chip circuit connection is determined according to the electrical connection defect prediction data. The main objective of the evaluation is to determine whether the electrical connection meets the requirements of stable operation and avoid chip failure caused by connection defects. Based on the defect prediction data and the electrical connection model, a stability evaluation model is established. The stability of the connection can be evaluated by using engineering mechanics analysis, principles of materials science, and standards in electrical engineering. For example, evaluate the stability of the current path, the integrity of signal transmission, and the impact of thermal effects on the connection. During the evaluation process, finite element analysis (FEA) can be used to simulate the response of the chip circuit under different working conditions, including current load, thermal effects, mechanical stress, etc. Analyze whether there are overheated areas in the electrical connection and predict faults caused by overheating. Evaluate whether the connection part is affected by stress or vibration, resulting in poor contact or fracture. According to the integrity of the electrical connection, analyze whether the circuit can withstand long-term working conditions, such as current and voltage fluctuations. Based on the above model and evaluation indicators, the stability evaluation data of the chip circuit connection is generated. The data should include information such as the stability score of each connection point, the predicted failure probability, and the analysis of influencing factors. Select appropriate data visualization tools, such as MATLAB, Tableau, PowerBI, etc., to clearly display the stability evaluation data. Two-dimensional or three-dimensional visualization methods can be selected to present the stability information of the electrical connection. Allow users to interact with the data, such as viewing the detailed information of a specific area, or screening and comparing results according to different evaluation criteria. Based on the visualization results and the stability evaluation data, a defect detection report for the LED chip circuit is constructed.

[0074] Preferably, step S1 includes the following steps:

[0075] Step S11: Obtain the structural data of the LED chip sample by using an electron microscope;

[0076] Step S12: Perform chip electrical connection on the LED chip based on the structural data of the LED chip sample to generate chip electrical connection data;

[0077] Step S13: Use the chip electrical connection data to perform structural screening on the structural data of the LED chip sample to obtain the electrical connection structure data of the LED chip sample;

[0078] Step S14: Confirm the key electrical connection levels of the electrical connection structure data of the LED chip sample, and perform three-dimensional reconstruction on the confirmed key electrical connection levels to obtain the three-dimensional structure data of the electrical connection metallization layer.

[0079] In the embodiments of the present invention, by appropriately preprocessing the LED chip samples, including cleaning, cutting, etc., they are made suitable for electron microscope observation. A high-resolution electron microscope (such as a scanning electron microscope, SEM) is used to scan the LED chip samples to capture the microscopic structure images of the chip surface and inside. Based on the image data collected by the microscope, a detailed microstructure map of the LED chip is constructed, focusing on key structures such as metal layers, insulating layers, semiconductor layers, etc. The microscope images are analyzed to extract key information such as the size, shape, material composition, and layout of the chip, generating a structure data set. According to the physical structure data of the chip, electrical connection paths such as solder joints, electrodes, wires, etc. are identified. Using electrical principles and the geometric structure of the chip, a model of the chip's electrical connection is established. It can be verified through finite element analysis (FEA) or current flow models, etc. Electrical connection parameters including current paths, thicknesses of conductive layers, conductive materials, etc. are extracted from the modeling process to form an electrical connection data set. The electrical connection data is used to optimize the structural design of the chip, screening out structural parts crucial for electrical performance such as electrode contact surfaces, wire spacings, etc. Machine learning or optimization algorithms are applied to screen the structural data, and unnecessary parts are removed according to characteristics such as the stability and conductivity of electrical connections. The finally screened data reflects the optimal electrical connection layout of the chip, and this part of the data can be used as a reference for subsequent chip manufacturing and improvement. According to the electrical connection structure data, connection levels crucial for the electrical performance of the chip (such as metallization layers, conductive layers, etc.) are identified. Through electrical performance analysis, key metallization layers, contact layers, etc. are confirmed, and the specific positions and functions of each level are marked. Using the structural data and electrical connection level information, 3D modeling and reconstruction are carried out, especially in the construction of the metallization layer, to accurately position the hierarchical structures of each electrical connection. Through 3D reconstruction software (such as CAD or 3D modeling tools), detailed 3D structure data of the electrical connection metallization layer of the LED chip is generated, including layer thickness, material distribution, and electrical contact points, etc.

[0080] Preferably, step S14 further includes:

[0081] Performing energy spectrum analysis on the electrical connection structure data of the LED chip sample to generate electrical connection energy spectrum data; using the electrical connection energy spectrum data to perform elemental composition analysis on the electrical connection structure data of the LED chip sample, and when an elemental composition is analyzed, the corresponding structure is marked as an electrical connection metal layer;

[0082] Performing elemental distribution analysis on the electrical connection metal layer to generate electrical connection metal layer elemental distribution data; identifying the key metal layer of the electrical connection based on the electrical connection metal layer elemental distribution data to obtain the electrical connection key metal layer;

[0083] Perform three-dimensional reconstruction on the electrical connection structure data of the LED chip sample based on the key metal layer of the electrical connection to generate the three-dimensional structure data of the metallization layer.

[0084] In the embodiments of the present invention, by using energy spectrum analysis techniques such as X-ray energy spectrum (EDS) or electron probe microanalysis (EPMA), the LED chip samples are scanned and analyzed. These techniques can accurately analyze the elemental composition at different positions. By scanning the surface and internal structure of the chip, energy spectrum data of each region are obtained, which reflect the distribution and concentration of elements. This analysis mainly focuses on the electrical connection parts such as the metallization layer, electrode layer, and conduction path. According to the scanning results, the elemental composition and concentration information of each scanning point are extracted to generate electrical connection energy spectrum data, recording the distribution and intensity changes of different elements. The energy spectrum data obtained through energy spectrum analysis are processed to identify the elemental composition of each region, with particular attention paid to metal elements (such as copper, aluminum, gold, etc.) and semiconductor elements (such as nitrogen, gallium, etc.). In the energy spectrum data, based on the concentration and distribution of metal elements, the metallization layer regions of the electrical connection are marked. These regions are usually associated with the electrical conduction path and electrical connection layer, and the metallization layer is identified as a key part of the electrical connection. According to the analysis results, an elemental composition analysis report of the electrical connection structure data of the LED chip is generated, indicating the specific elemental composition of the metallization layer and other important regions. In the regions marked as the electrical connection metal layer, further elemental distribution analysis is carried out to analyze the uniformity and distribution law of metal elements (such as copper, silver, etc.) in this layer. Through scanning and data processing, elemental distribution data of the electrical connection metal layer are generated. These data will show the concentration distribution of different metal elements in the metallization layer and help evaluate the quality and stability of the connection layer. According to the elemental distribution data, regions with uneven elemental distribution are identified, and these regions will affect the electrical performance of the chip. Further optimization analysis can be carried out to improve the electrical connection structure. According to the elemental distribution data of the electrical connection metal layer, those metal layers that are crucial for electrical performance are identified. These layers usually include the electrical contact surface, solder joint area, and metallization layer of the conduction path. According to the elemental distribution and electrical connection requirements, "key metal layers" are defined. These layers have a decisive impact on the electrical conductivity and reliability of the LED chip. Through further structural analysis and experimental verification, the position, thickness, and elemental composition of the key metal layers are confirmed to ensure that they meet the requirements of electrical connection and conductive performance. Using the structural data and elemental distribution data of the electrical connection metal layer, three-dimensional modeling of the metallization layer of the electrical connection is carried out. Three-dimensional modeling software (such as CAD, 3DMax, SolidWorks, etc.) can be used for detailed modeling. According to the position and elemental distribution of the key metal layer, combined with electron microscope and energy spectrum analysis data, appropriate reconstruction algorithms (such as surface reconstruction, hierarchical analysis, etc.) are used to carry out three-dimensional modeling of the metallization layer. According to the modeling results, detailed three-dimensional structure data of the metallization layer are generated, including important parameters such as the thickness, shape, contact points, and connection methods of the metallization layer. Through simulation and experimental verification, the performance of the three-dimensional reconstructed metallization layer structure in terms of electrical performance, thermal stability, etc. is evaluated.If necessary, the structure can be further optimized to improve the reliability and performance of the chip.

[0085] As an example of the present invention, refer to Figure 2 As shown, in this example, step S2 includes:

[0086] Step S21: Divide the three-dimensional structure data of the metallization layer into external three-dimensional structure data of the metallization layer and internal three-dimensional structure data of the metallization layer based on the thickness of the three-dimensional structure of the metallization layer;

[0087] Step S22: Use an infrared imaging sensor to analyze the surface temperature distribution of the chip metallization layer of the LED chip to generate surface temperature distribution data of the chip metallization layer; perform temperature balance defect detection on the external three-dimensional structure data of the metallization layer according to the surface temperature distribution data of the chip metallization layer to generate surface defect detection data of the metallization layer;

[0088] Step S23: Use the particle pulse technology to emit high-speed particles to the LED chip to obtain high-speed particle pulse data; perform particle swarm image defect detection on the internal three-dimensional structure data of the metallization layer through the high-speed particle pulse data to generate internal defect detection data of the metallization layer;

[0089] Step S24: Integrate the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer.

[0090] In the embodiments of the present invention, through the aforementioned three-dimensional modeling technology or scanning technology (such as electron microscopy, X-ray CT scanning, etc.), the complete three-dimensional structure data of the metallization layer is obtained. This data should include the external and internal characteristics of the metallization layer (such as thickness, density, material distribution, etc.). Using the thickness data, the metallization layer is divided into external and internal regions. The external three-dimensional structure data generally refers to the layer close to the surface, while the internal three-dimensional structure data refers to the inner part of the metallization layer. A threshold value (for example, a thickness-based demarcation value) can be set to divide the different thicknesses of the metallization layer. Based on the thickness division principle, the external and internal regions of the metallization layer are marked out, forming two types of data sets - the external three-dimensional structure data of the metallization layer and the internal three-dimensional structure data of the metallization layer. This division is crucial for subsequent steps such as defect detection, thermal analysis, and particle pulse analysis. An infrared thermal imaging sensor (such as a FLIR camera) is used and aimed at the surface of the metallization layer of the LED chip to measure the temperature distribution. These sensors can measure the temperature at different positions on the chip surface and record it. The temperature distribution map is generated from the temperature data obtained through infrared imaging technology. These temperature data are usually presented in the form of a thermal map, and each point represents the temperature value at a certain position on the surface of the chip metallization layer. The infrared temperature data is post-processed to eliminate noise and optimize the visualization of the temperature distribution, ensuring the accuracy of the temperature distribution data for defect analysis in subsequent steps. By analyzing the temperature distribution data on the surface of the metallization layer, regions with uneven temperature are identified. These regions usually indicate potential defects or thermal imbalance problems, such as poor soldering, uneven heat conduction, inconsistent thickness of the metallization layer, etc. Based on the temperature balance analysis, a temperature deviation threshold (such as a certain temperature difference) is set to detect those regions that exceed the threshold. The generated defect detection data on the surface of the metallization layer will include information such as the location, size, and temperature deviation of these abnormal regions. Using the particle pulse flaw detection technology, a high-speed particle source (such as a proton or electron beam) is emitted into the interior of the metallization layer of the LED chip. These particles can penetrate the metallization layer and interact with the internal structure, generating measurable signals (such as backscattering, scattered particles, etc.). The backscattering signals are collected by a particle pulse detector, and the interaction information of the high-speed particles with internal defects (such as pores, cracks, voids, etc.) when passing through the metallization layer is recorded. These data provide a detailed view of the internal structure of the metallization layer. The collected particle pulse data is converted into a processable format (such as signal intensity, particle scattering angle, etc.), and particle pulse data related to the internal structure of the metallization layer is generated. By analyzing the particle pulse data, regions with abnormal particle scattering intensity are identified. These abnormalities usually indicate defects inside the metallization layer. Based on the particle pulse data, defect detection algorithms (such as image processing algorithms, pattern recognition algorithms) are applied to locate the defects (such as voids, cracks, material deficiencies, etc.) inside the metallization layer.Through detection and analysis, defect detection data of the metallization layer are generated, which include the location, size, and nature of internal defects. The surface defect detection data of the metallization layer are fused with the internal defect detection data of the metallization layer. Data fusion algorithms (such as weighted average, decision tree fusion, etc.) can be used to integrate the information of surface defects and internal defects. During the integration process, the impacts of surface defects and internal defects on the overall performance of the metallization layer are comprehensively considered. For example, surface defects affect electrical contact, while internal defects affect structural stability and conductivity. Based on the integrated data, defect detection data of the electrical connection metallization layer are generated. This data will provide a comprehensive defect analysis report of the metallization layer, including key information such as defect type (surface or internal), location, size, influencing factors, etc.

[0091] Preferably, step S22 includes the following steps:

[0092] Step S221: Use an infrared imaging sensor to collect the surface temperature image of the chip metallization layer of the LED chip to obtain the surface temperature image of the metallization layer;

[0093] Step S222: Perform image preprocessing on the surface temperature image of the metallization layer to generate a standard surface temperature image of the metallization layer, where the image preprocessing includes image correction and image denoising; perform image data conversion on the standard surface temperature image of the metallization layer to generate temperature information data of the metallization layer;

[0094] Step S223: Map the temperature information data of the metallization layer to generate surface temperature distribution data of the chip metallization layer; calculate the temperature difference between adjacent pixels of the standard surface temperature image of the chip metallization layer according to the surface temperature distribution data of the chip metallization layer to obtain the temperature difference of each group of adjacent pixels;

[0095] Step S224: Analyze the uniformity of the surface temperature distribution data of the chip metallization layer through the temperature difference of each group of adjacent pixels to generate surface temperature uniformity data of the chip metallization layer; use the surface temperature uniformity data of the chip metallization layer to detect temperature balance defects in the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer.

[0096] In the embodiments of the present invention, an infrared imaging sensor (such as a FLIR series thermal imager) is used to image the metallization layer of an LED chip. This sensor can measure and capture the temperature information on the chip surface, generating a high-resolution temperature image. Align the infrared imaging sensor with the surface of the metallization layer of the LED chip, perform temperature scans at different positions and different times, record the temperatures of each point on the chip surface, and these temperature information will be displayed in real time through the infrared imaging device and generate an image file containing temperature data. Each image reflects the distribution of the chip surface temperature, and the color or gray value of the image represents the temperature values of different regions. The finally output temperature image of the metallization layer surface will serve as the basic data for subsequent analysis. In the collected temperature images, there will be deviations caused by sensor errors, environmental factors, etc. Perform image correction. By adjusting the response curve of the infrared sensor and the image contrast, ensure the accuracy of the temperature data. Adjust the color mapping of the infrared image so that the correspondence between different temperature values and the colors of the image is accurate. Correct the geometric distortion in the image (for example, the distortion caused by the imaging angle) to ensure that the image is consistent with the actual physical shape. Since infrared imaging is affected by background noise, device noise, or external interference, perform image denoising. Common denoising methods include: using a Gaussian filter to remove high-frequency noise and smooth the temperature fluctuations in the image, using a median filter to remove noise pixels and retain the overall trend of the temperature data. After image correction and denoising, a standardized temperature image of the metallization layer surface is obtained. This image will provide a reliable basis for subsequent temperature information extraction and data analysis. Convert the standardized image into a temperature information data format (such as CSV, JSON, or other data table formats), and these data will contain the temperature values of each pixel position as the input for subsequent analysis. Map the temperature values of each pixel in the standard temperature image of the metallization layer surface. Using the pixel coordinates and temperature values in the temperature information data, visualize the temperature data in the form of a heat map for subsequent analysis. Based on the temperature information data, generate a temperature distribution map of the chip metallization layer surface. This map shows the temperature gradient of the entire chip metallization layer surface and the temperature fluctuations in different regions. Regions with higher or lower temperatures are usually associated with structural defects or performance problems in the metallization layer. For easy analysis, mark the hot spots or abnormal regions in the temperature distribution map. The temperatures in these regions are significantly higher or lower than the surrounding regions, indicating potential defect locations. For each group of adjacent pixels (such as the four directions: up, down, left, right) in the standard temperature image of the metallization layer surface, calculate the temperature difference between each group of adjacent pixels, which can help evaluate the uniformity of the temperature distribution. For two adjacent pixels p1(x1, y1) and p2(x2, y2), the temperature difference ΔT can be calculated by the formula: ΔT = ∣T(p1)−T(p2)∣; where T(p1) and T(p2) represent the temperature values of pixels p1 and p2 respectively, and ΔT represents the temperature difference.Analyze the temperature uniformity of the chip metallization layer surface based on the temperature difference between each group of adjacent pixels. If the temperature difference between adjacent pixels is large, it indicates non-uniform temperature, and there are problems such as poor heat conduction, uneven thickness of the metallization layer, or local material defects. The calculated temperature difference data is used to evaluate the temperature uniformity of the metallization layer surface. The generated temperature uniformity data of the chip metallization layer surface will quantify the uniformity of the temperature distribution and be represented in numerical form (such as uniformity index, standard deviation, etc.). Based on the temperature uniformity data, identify the regions with large temperature differences and mark them as potential defect regions. These regions usually correspond to non-uniform temperature or overheating of the chip metallization layer and are related to poor electrical connection or thermal expansion problems. By performing threshold analysis on the temperature uniformity data, locate the regions where the temperature difference exceeds the preset range. These regions can be marked using thermal icons to help engineers further diagnose and analyze the problems. According to the detection results, generate defect detection data for the metallization layer surface, including information such as the location, size, and temperature difference of the defect regions. This data can be used for subsequent quality control and chip optimization.

[0097] Preferably, step S23 includes the following steps:

[0098] Step S231: Use particle pulse technology to perform high-speed particle emission on the LED chip to obtain high-speed particle pulse data;

[0099] Step S232: Identify the particle signal characteristics of the high-speed particle pulse data to generate particle signal characteristic data; analyze the particle propagation path of the high-speed particle pulse data based on the particle signal characteristic data to generate particle propagation path data;

[0100] Step S233: Perform structure mapping on the particle propagation path data and the internal three-dimensional structure data of the metallization layer to generate internal particle structure mapping data of the metallization layer; perform particle reflection and scattering analysis on the internal particle structure mapping data of the metallization layer respectively to generate metallization layer particle group image data;

[0101] Step S234: Quantify the uniformity of the particle pulse signal of the metallization layer particle group image data to generate a particle pulse signal uniformity value; perform internal particle defect detection on the internal three-dimensional structure data of the metallization layer based on the particle pulse signal uniformity value to generate internal defect detection data of the metallization layer.

[0102] In the embodiments of the present invention, high-speed particle emission is performed on an LED chip by using particle pulse technology (e.g., proton or electron pulse emission). This technology can reveal defects or non-uniformities in the internal structure of the metallization layer through the interaction of high-speed particles with atoms inside the material. A particle source (such as a particle accelerator) emits particle pulses to the LED chip. The particles will penetrate the metallization layer of the chip and interact with different parts of the internal material of the chip according to different paths and scattering degrees. During the process of particles penetrating the material, certain pulse signals will be generated. The interaction information between particles and matter is recorded in real time by sensors (such as particle detectors or time-of-flight detectors) to obtain high-speed particle pulse data, which includes information such as the incident time, energy loss, and propagation path of the particles. The basic signal characteristics of the particles are extracted from the obtained high-speed particle pulse data, and these characteristics include the energy loss, flight time, propagation direction, attenuation rate, etc. of the particles. Signal processing techniques, such as Fourier transform, wavelet analysis, etc., can be used to extract the signal characteristics. Pattern recognition algorithms (such as support vector machine (SVM) or neural network) are applied to classify the particle pulse signals to identify signal patterns related to internal defects in the material. For example, if some particle signals show abnormal energy loss or scattering patterns, they correspond to internal defect regions. Through feature extraction and recognition, particle signal feature data is generated, including the basic information of each particle signal and its classification result, and this data can provide a basis for subsequent particle propagation path analysis and defect detection. According to the particle signal feature data, the propagation path of the particles from the source to the detector is analyzed, and this analysis takes into account various physical phenomena during the propagation of the particles inside the metallization layer, such as scattering, absorption, and reflection. Based on the particle signal feature data, simulation software (such as Monte Carlo method or other particle tracking algorithms) is used to simulate the propagation path of the particles inside the metallization layer. By detailed simulation of the space and interaction regions passed by the particles, the propagation path data of the particles inside the metallization layer is obtained. The particle propagation path data is compared and mapped with the internal three-dimensional structure data of the metallization layer. Using three-dimensional data visualization technology, the particle paths are corresponded to the specific structure of the metallization layer (such as lattice, grain boundary, void, etc.) to form the internal particle structure mapping data of the metallization layer, which provides the spatial relationship between particles and the structure for subsequent analysis. According to the propagation path of the particles, the reflection and scattering behaviors of the particles when encountering different substances inside the metallization layer are analyzed. Usually, the propagation of particles in the metallization layer will scatter or reflect when encountering substances such as metal particles, defects, voids, etc. Through the combination of the particle propagation path and the structure mapping data, the scattering and reflection phenomena can be quantitatively evaluated. Through the analysis of particle reflection and scattering, the distribution images of the particle group inside the metallization layer are obtained, and these images show the aggregation of the particle group in different regions, as well as the propagation and scattering effects inside the metallization layer. This data is called the particle group image data of the metallization layer.Perform uniformity analysis on the particle swarm image data, that is, analyze whether the distribution of particles in the metallization layer is uniform. If the particle distribution is uneven, it indicates the existence of non-uniformity or defect areas in the metallization layer. Use statistical methods to calculate the uniformity indicators of the particle swarm image, such as standard deviation, uniformity index, etc. These indicators can quantify the degree of uniformity of the particle swarm distribution and reflect the quality and internal defects of the metallization layer. According to the uniformity analysis results, generate the uniformity value of the particle pulse signal. The lower this value, the more uniform the particle distribution; conversely, the higher the value, the greater the non-uniformity or defects inside the metallization layer. Use the uniformity value of the particle pulse signal to detect the defect areas inside the metallization layer. If the uniformity value of the particle pulse signal exceeds the preset threshold, it indicates that there are defects in some areas of the metallization layer, and these defects are manifested as local voids, cracks, thermal deformations, etc. By comparing with the three-dimensional structure data inside the metallization layer, locate the defect areas. The areas with deviations, reflections, or abnormal scattering in the particle propagation path often correspond to the positions of the structural defects. Based on the uniformity value of the particle pulse signal and the defect location results, generate the defect detection data inside the metallization layer. This data includes the type, location, size, and impact of the defects.

[0103] As an example of the present invention, refer to Figure 3 As shown, in this example, step S3 includes:

[0104] Step S31: Extract defect features from the defect detection data of the electrical connection metallization layer to obtain the metallization layer defect feature data; divide the metallization layer defect feature data into data sets to generate a model training set and a model test set;

[0105] Step S32: Use the support vector machine algorithm to train the model training set to generate a pre-model for predicting electrical connection defects of the LED chip; use the model test set to optimize and iterate the pre-model for predicting electrical connection defects of the LED chip to generate a prediction model for electrical connection defects of the LED chip;

[0106] Step S33: Import the three-dimensional structure data of the electrical connection metallization layer into the prediction model for electrical connection defects of the LED chip to predict the electrical connection defects of the chip and generate the prediction data for electrical connection defects.

[0107] In the embodiments of the present invention, by preprocessing the defect detection data of the metallization layer, the consistency and reliability of the data are ensured. This includes noise removal, missing data supplementation, and outlier processing. Statistical analysis methods are used to extract key information of the metallization layer defects, such as defect types (cracks, holes, melting, fractures, etc.), defect locations, defect sizes, shapes, boundary features, defect distribution densities, etc. These features can be extracted through image processing techniques, signal processing methods, or machine learning algorithms. The extracted defect feature data of the metallization layer is divided into a model training set and a model test set in proportion. For example, 70% is used as the training set and 30% as the test set. This division ensures that overfitting does not occur during the model training process and can effectively evaluate the generalization ability of the model. The training set is used to train the Support Vector Machine (SVM) algorithm, and the model learns how to identify different types of defects from this data. The test set is used to verify and evaluate the performance of the trained model, detecting its accuracy, recall rate, precision, etc. According to the characteristics of the data, an appropriate SVM kernel function (such as linear kernel, polynomial kernel, Radial Basis Function (RBF) kernel, etc.) is selected. If the data has a high degree of non-linear relationship, the Radial Basis Function kernel is usually selected. The defect feature data of the training set is input into the SVM algorithm for training. The SVM learns how to distinguish different types of defects (such as whether there are cracks or other defects) by optimizing the boundary classification hyperplane. The SVM model forms a classification model by maximizing the classification boundary, learning the support vectors of each sample, and establishing a decision function for each defect category. The cross-validation method is used to optimize the model to ensure the stability and accuracy of the model. By dividing the training set and the test set multiple times, the performance of the model on different data is evaluated. The hyperparameters of the SVM (such as the penalty parameter C, kernel function parameters, etc.) are optimized through Grid Search or Random Search to improve the accuracy and generalization ability of the model. After the SVM model is trained, a preliminary electrical connection defect prediction model is obtained. This model can classify and predict different metallization layer defects and give the probability distribution of each defect type. The test set is input into the prediction model to evaluate the prediction performance of the model and detect whether the predicted defect types are consistent with the actual situation. By calculating indicators such as accuracy, recall rate, and F1-score, the classification effect of the model is evaluated, especially for different types of defect detections, to ensure the balanced performance of the model on all defect types. Based on the performance of the model on the test set, necessary model optimizations are carried out. If the performance of the model is not good, the model parameters need to be readjusted or more features need to be introduced. During the optimization process, more training samples can be added, especially for the defect types with weak model prediction performance, and more samples are collected and learned. After multiple rounds of optimization and verification, a reliable LED chip electrical connection defect prediction model is finally obtained. This model can accurately predict potential defects on the electrical connection metallization layer of the chip.Import the three-dimensional structure data of the electrical connection metallization layer of the LED chip into the finally trained LED chip electrical connection defect prediction model. The three-dimensional structure data includes the shape, size, defect location, etc. of the metallization layer on the chip surface. Use the trained SVM model to predict the defects in the three-dimensional data of the metallization layer and determine whether there are defects in the electrical connection layer. By comparing the three-dimensional structure of the chip with the defect patterns in the model, predict the types of defects (such as cracks, overheating, non-connection, etc.). According to the prediction results of the model, generate electrical connection defect prediction data, including the location, type, size of the predicted defect and its impact on the chip performance.

[0108] In this specification, a LED chip defect detection device is provided for performing the above-mentioned LED chip defect detection method. The LED chip defect detection device includes:

[0109] A three-dimensional reconstruction module for obtaining the structure data of the LED chip sample; performing chip electrical connection on the LED chip based on the structure data of the LED chip sample to generate chip electrical connection data; confirming the key electrical connection levels for the chip electrical connection data and performing three-dimensional reconstruction on the confirmed key electrical connection levels to obtain the three-dimensional structure data of the electrical connection metallization layer;

[0110] A defect detection module for dividing the three-dimensional structure data of the metallization layer into the external three-dimensional structure data of the metallization layer and the internal three-dimensional structure data of the metallization layer; performing temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer; performing particle swarm image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; integrating the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain the defect detection data of the electrical connection metallization layer;

[0111] A defect prediction module for training a model on the defect detection data of the electrical connection metallization layer to generate a LED chip electrical connection defect prediction model; importing the three-dimensional structure data of the electrical connection metallization layer into the LED chip electrical connection defect prediction model to perform chip electrical connection defect prediction and generate electrical connection defect prediction data;

[0112] A circuit stability evaluation module for evaluating the chip circuit connection stability of the LED chip according to the electrical connection defect prediction data to generate chip circuit connection stability evaluation data; visualizing the chip circuit connection stability evaluation data to generate a LED chip circuit defect detection report.

[0113] The present invention provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the above-mentioned LED chip defect detection method is implemented.

[0114] The present invention also provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned LED chip defect detection method is implemented.

[0115] The beneficial effects of the present invention are as follows: The three-dimensional reconstruction module accurately obtains the structural data of the LED chip, and further analyzes the electrical connection of the chip, which can better understand the integrity of the internal electrical connection of the chip and provide solid data support for subsequent defect detection and stability evaluation. By dividing the metallization layer into external and internal data, and respectively performing temperature equilibrium defect detection and particle swarm image defect detection, potential defects on the surface and inside are effectively identified, improving the comprehensiveness and accuracy of defect detection and ensuring the early discovery of problems in the chip production process. Using a machine learning model to train the detection data to generate a prediction model for electrical connection defects of the LED chip enables the system not only to perform real-time defect detection but also to predict future electrical connection problems, thus giving early warnings and making targeted optimizations. Through the prediction data of electrical connection defects, the stability of the circuit connection of the LED chip is evaluated, which can accurately reflect the risks existing in the circuit, predict the stability of the circuit in advance, and provide guarantee for the long-term stable operation of the chip. The system presents the evaluation results through data visualization, generates a detailed circuit defect detection report, helps engineers quickly understand the quality and stability of the chip, and provides data support for subsequent improvements. Therefore, the present invention improves the accuracy of detecting subtle material-level defects inside the chip through automated three-dimensional structure reconstruction, comprehensive defect detection, intelligent prediction, and evaluation.

[0116] Therefore, from any perspective, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to cover all changes falling within the meaning and scope of the equivalent elements of the application documents within the present invention.

[0117] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for detecting LED chip defects, characterized in that It includes the following steps: Step S1: Obtain the structural data of the LED chip sample; perform chip electrical connection on the LED chip based on the structural data of the LED chip sample to generate chip electrical connection data; confirm the key levels of electrical connection for the chip electrical connection data, and perform 3D reconstruction on the confirmed key levels of electrical connection to obtain the 3D structural data of the electrical connection metallization layer; Step S2: Divide the 3D structural data of the metallization layer into the external 3D structural data of the metallization layer and the internal 3D structural data of the metallization layer; perform temperature balance defect detection on the external 3D structural data of the metallization layer to generate surface defect detection data of the metallization layer; perform particle swarm defect detection on the internal 3D structural data of the metallization layer to generate internal defect detection data of the metallization layer; integrate the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer; Step S2 includes the following steps: Step S21: Divide the 3D structural data of the metallization layer into the external 3D structural data of the metallization layer and the internal 3D structural data of the metallization layer based on the thickness of the 3D structure of the metallization layer; Step S22: Use an infrared imaging sensor to analyze the surface temperature distribution of the chip metallization layer of the LED chip to generate surface temperature distribution data of the chip metallization layer; perform temperature balance defect detection on the external 3D structural data of the metallization layer according to the surface temperature distribution data of the chip metallization layer to generate surface defect detection data of the metallization layer; Step S22 includes the following steps: Step S221: Use an infrared imaging sensor to collect the surface temperature image of the chip metallization layer of the LED chip to obtain the surface temperature image of the metallization layer; Step S222: Perform image preprocessing on the surface temperature image of the metallization layer to generate a standard surface temperature image of the metallization layer, where the image preprocessing includes image correction and image denoising; perform image data conversion on the standard surface temperature image of the metallization layer to generate temperature information data of the metallization layer; Step S223: Perform temperature distribution mapping on the temperature information data of the metallization layer to generate surface temperature distribution data of the chip metallization layer; calculate the temperature difference between adjacent pixels of the standard surface temperature image of the chip metallization layer according to the surface temperature distribution data of the chip metallization layer to obtain the temperature difference of each group of adjacent pixels; Step S224: Analyze the uniformity of the surface temperature distribution data of the chip metallization layer through the temperature difference of each group of adjacent pixels to generate surface temperature uniformity data of the chip metallization layer; use the surface temperature uniformity data of the chip metallization layer to perform temperature balance defect detection on the external 3D structural data of the metallization layer to generate surface defect detection data of the metallization layer; Step S23: Use the particle pulse technology to emit high-speed particles on the LED chip to obtain high-speed particle pulse data; perform particle swarm defect detection on the internal 3D structural data of the metallization layer through the high-speed particle pulse data to generate internal defect detection data of the metallization layer; Step S23 includes the following steps: Step S231: Use the particle pulse technology to emit high-speed particles on the LED chip to obtain high-speed particle pulse data; Step S232: Identify the particle signal characteristics of the high-speed particle pulse data to generate particle signal characteristic data; analyze the particle propagation path of the high-speed particle pulse data based on the particle signal characteristic data to generate particle propagation path data; Step S233: Perform structure mapping on the particle propagation path data and the internal three-dimensional structure data of the metallization layer to generate the internal particle structure mapping data of the metallization layer; perform particle reflection and scattering analysis on the internal particle structure mapping data of the metallization layer respectively to generate the particle group image data of the metallization layer; Step S234: Quantify the uniformity of the particle pulse signal for the particle group image data of the metallization layer to generate the uniformity value of the particle pulse signal; detect the internal defects of the particle in the internal three-dimensional structure data of the metallization layer based on the uniformity value of the particle pulse signal to generate the internal defect detection data of the metallization layer; Step S24: Integrate the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain the defect detection data of the electrical connection metallization layer; Step S3: Perform model training on the defect detection data of the electrical connection metallization layer to generate a prediction model for electrical connection defects of the LED chip; import the three-dimensional structure data of the electrical connection metallization layer into the prediction model for electrical connection defects of the LED chip to predict the electrical connection defects of the chip and generate electrical connection defect prediction data; Step S4: Evaluate the stability of the chip circuit connection of the LED chip based on the electrical connection defect prediction data to generate the evaluation data of the chip circuit connection stability; visualize the evaluation data of the chip circuit connection stability to generate a defect detection report for the LED chip circuit.

2. The LED chip defect detection method according to claim 1, wherein Step S1 includes the following steps: Step S11: Obtain the structure data of the LED chip sample using an electron microscope; Step S12: Perform chip electrical connection on the LED chip based on the structure data of the LED chip sample to generate chip electrical connection data; Step S13: Use the chip electrical connection data to screen the structure data of the LED chip sample to obtain the electrical connection structure data of the LED chip sample; Step S14: Confirm the key electrical connection levels for the electrical connection structure data of the LED chip sample, and perform three-dimensional reconstruction on the confirmed key electrical connection levels to obtain the three-dimensional structure data of the electrical connection metallization layer.

3. The LED chip defect detection method according to claim 2, wherein, Step S14 also includes: Perform energy spectrum analysis on the electrical connection structure data of the LED chip sample to generate electrical connection energy spectrum data; use the electrical connection energy spectrum data to analyze the elemental composition of the electrical connection structure data of the LED chip sample. When an elemental composition is analyzed, mark the corresponding structure as the electrical connection metal layer; Perform elemental distribution analysis on the electrical connection metal layer to generate elemental distribution data of the electrical connection metal layer; identify the key metal layer of the electrical connection metal layer based on the elemental distribution data of the electrical connection metal layer to obtain the key electrical connection metal layer; Perform three-dimensional reconstruction on the electrical connection structure data of the LED chip sample based on the key electrical connection metal layer to generate the three-dimensional structure data of the metallization layer.

4. The LED chip defect detection method according to claim 1, characterized in that, Step S3 includes the following steps: Step S31: Extract defect features from the defect detection data of the electrical connection metallization layer to obtain metallization layer defect feature data; divide the metallization layer defect feature data into a dataset to generate a model training set and a model test set; Step S32: Use the support vector machine algorithm to train the model training set to generate a pre-model for predicting LED chip electrical connection defects; use the model test set to optimize and iterate the pre-model for predicting LED chip electrical connection defects, so as to generate a prediction model for LED chip electrical connection defects; Step S33: Import the three-dimensional structure data of the electrical connection metallization layer into the prediction model for LED chip electrical connection defects to predict chip electrical connection defects and generate electrical connection defect prediction data.

5. An LED chip defect detection device, characterized in that, An LED chip defect detection device for executing the LED chip defect detection method as described in Claim 1, the LED chip defect detection device includes: A three-dimensional reconstruction module, configured to obtain the structure data of an LED chip sample; perform chip electrical connection on the LED chip based on the structure data of the LED chip sample to generate chip electrical connection data; confirm the key electrical connection levels of the chip electrical connection data, and perform three-dimensional reconstruction on the confirmed key electrical connection levels to obtain the three-dimensional structure data of the electrical connection metallization layer; A defect detection module, configured to divide the three-dimensional structure data of the metallization layer into external three-dimensional structure data of the metallization layer and internal three-dimensional structure data of the metallization layer; perform temperature balance defect detection on the external three-dimensional structure data of the metallization layer to generate surface defect detection data of the metallization layer; perform particle swarm image defect detection on the internal three-dimensional structure data of the metallization layer to generate internal defect detection data of the metallization layer; integrate the surface defect detection data of the metallization layer and the internal defect detection data of the metallization layer to obtain defect detection data of the electrical connection metallization layer; A defect prediction module, configured to train a model on the defect detection data of the electrical connection metallization layer to generate a prediction model for LED chip electrical connection defects; import the three-dimensional structure data of the electrical connection metallization layer into the prediction model for LED chip electrical connection defects to predict chip electrical connection defects and generate electrical connection defect prediction data; A circuit stability evaluation module, configured to evaluate the stability of the chip circuit connection of the LED chip according to the electrical connection defect prediction data to generate chip circuit connection stability evaluation data; visualize the chip circuit connection stability evaluation data to generate an LED chip circuit defect detection report.

6. A computer device, characterized in that, It includes a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the method as described in any one of Claims 1-4 is implemented.

7. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the method as described in any one of Claims 1-4 is implemented.

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