Basic block linking method, translator, electronic device and readable storage medium

Abstract

An embodiment of the present invention provides a basic block linking method, a translator, an electronic device, and a readable storage medium. The method includes: during the process of executing target search code, determining whether a jump source basic block meets the unlinking condition; the target search code is used to search for the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the jump target basic block is the basic block to which the jump source basic block is to jump; the unlinking condition includes: the jump target basic block spans pages and the virtual-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state; if it is determined that the jump source basic block meets the unlinking condition, then perform basic block unlinking on the jump source basic block; perform basic block linking on the unlinked jump source basic block again. The embodiment of the present invention can reduce the number of times of searching for the jump target basic block when executing a direct jump instruction, and improve the efficiency of the translator in executing an application program.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and particularly to a basic block linking method, a translator, an electronic device, and a readable storage medium. Background Art

[0002] Binary translation can convert binary code of one ISA (Instruction Set Architecture) into binary code of another instruction set architecture. Through binary translation technology, an application program of one ISA (source architecture) can run on another ISA (target architecture).

[0003] Binary translation is performed in units of basic blocks (Translation Blocks, TBs). A basic block is a sequence of instructions that are executed sequentially in a program and has a single entry point and a single exit point. Once the program enters a basic block, all the instructions in it will be executed sequentially until the exit of the basic block, and there will be no control flow branches inside the basic block (except for sequential execution to the last instruction). The entry point is the first instruction of the basic block; the exit point is the last instruction of the basic block, and the last instruction can be a jump instruction, a function call instruction, or a program termination instruction, etc.

[0004] When a basic block ends with a jump instruction, when the program executes this jump instruction, it is necessary to transfer the control flow from the current basic block to another basic block, which involves a search operation for the basic block. This process usually requires a relatively high cost and affects the program execution efficiency. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide a basic block linking method that can overcome the above problems or at least partially solve the above problems, which can reduce the number of times of searching for the jump target basic block when executing a direct jump instruction and improve the efficiency of the translator in executing application programs.

[0006] Correspondingly, embodiments of the present invention also provide a system-level binary translator, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0007] In a first aspect, an embodiment of the present invention discloses a basic block linking method applied to a system-level binary translator. The method includes:

[0008] During the execution of the target search code, it is determined whether the jump source basic block meets the unlinking condition; the target search code is used to search for the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the jump source basic block is a basic block ending with a direct jump instruction; the jump target basic block is the basic block that the jump source basic block is to jump to; the unlinking condition includes: the jump target basic block spans pages and the virtual-to-physical address mapping relationship of the jump target basic block changes, and the jump source basic block is in the linked state;

[0009] If it is determined that the jump source basic block meets the unlinking condition, the basic block of the jump source basic block is unlinked;

[0010] The unlinked jump source basic block is re-linked for basic blocks.

[0011] In a second aspect, an embodiment of the present invention discloses a system-level binary translator, and the system-level binary translator includes:

[0012] A condition judgment module, configured to determine whether a jump source basic block meets the unlinking condition during the execution of the target search code; the target search code is used to search for the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the jump source basic block is a basic block ending with a direct jump instruction; the jump target basic block is the basic block that the jump source basic block is to jump to; the unlinking condition includes: the jump target basic block spans pages and the virtual-to-physical address mapping relationship of the jump target basic block changes, and the jump source basic block is in the linked state;

[0013] An unlinking module, configured to unlink the basic block of the jump source basic block if it is determined that the jump source basic block meets the unlinking condition;

[0014] A linking module, configured to re-link the basic block of the unlinked jump source basic block.

[0015] In a third aspect, an embodiment of the present invention discloses an electronic device, including: a processor, a memory, a communication interface, and a communication bus, and the processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the basic block linking method as described in any one of the foregoing.

[0016] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, and a program or instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, it can implement the basic block linking method as described in any one of the foregoing.

[0017] Fifth aspect, an embodiment of the present invention discloses a computer program product, including a computer program, which when executed by a processor performs the steps of the basic block linking method as described in any one of the foregoing.

[0018] The embodiments of the present invention include the following advantages:

[0019] The embodiments of the present invention improve the execution flow of the original target search code, and determine whether the jump source basic block meets the unlinking condition, where the unlinking condition includes: the jump target basic block spans pages and the virtual-to-physical address mapping relationship of the jump target basic block has changed, and the jump source basic block is in a linked state. When it is determined that the jump source basic block meets the unlinking condition, the jump source basic block is unlinked. Thus, the correct jump address (such as the second start address) can be used to re-link the jump source basic block, so that in the case of cross-page jumps and the virtual-to-physical address mapping relationship of the jump target basic block has changed, the execution of direct jump instructions can also be optimized, and direct jumps can be performed through the correct link instruction sequence (such as the second link instruction sequence), avoiding the need to execute the unoptimized instruction sequence for slow search every time, reducing the number of times to search for the jump target basic block when executing direct jump instructions, and improving the efficiency of the translator in executing application programs. Description of the Drawings

[0020] Figure 1 is a schematic diagram of a binary translation architecture of the present invention;

[0021] Figure 2 is a flowchart of the steps of an embodiment of the basic block linking method of the present invention;

[0022] Figure 3 is a block diagram of the structure of an embodiment of a system-level binary translator of the present invention;

[0023] Figure 4 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Detailed Embodiments

[0024] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] The terms "first", "second", etc. in the description and claims of the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the description and claims is used to describe the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects before and after are in an "or" relationship. In the embodiments of the present invention, the term "plurality" refers to two or more, and other quantifiers are similar.

[0026] Binary translation technology can solve the problem of application programs running across instruction set architectures at the binary level. Specifically, binary translation technology can convert an instruction sequence in one instruction set architecture into an instruction sequence in another instruction set architecture.

[0027] Refer to Figure 1 , a schematic diagram of the dynamic binary translation architecture is shown. As Figure 1 shown, dynamic binary translation adopts the method of "translating while running", translating the instructions of the client architecture into the instructions of the host architecture at runtime and running them on the host. After the translator reads the binary file of the target program (client program), it translates and executes at the granularity of basic blocks (TranslationBlock, TB). A basic block usually ends with a control flow change instruction (such as an indirect jump instruction, a function call instruction, etc.). Before executing a basic block, first search in the code cache area. If a translated basic block is found, execute that basic block. If a translated basic block is not found in the code cache area, translate that basic block and put the translated basic block into the code cache area, and then execute the translated basic block. After executing a basic block, search for the next basic block in the code cache area, and so on in a loop until the program execution ends.

[0028] Dynamic binary translators can be divided into user-level binary translators and system-level binary translators, and their application scopes are different. The application scope of user-level binary translators is mainly limited to the execution of a single user-mode program, which is suitable for executing target programs on different architectures without running the entire operating system, and is often used in software compatibility solutions that cross architectures but not operating systems. System-level binary translators, on the other hand, cover the operation of the entire system, including the operating system kernel and user-mode programs, and can simulate a complete computer system on different architectures. They are usually used in software compatibility solutions that cross both architectures and operating systems. System-level binary translators can also be used in scenarios such as virtualization, embedded development, and operating system migration.

[0029] The present invention provides a basic block linking method, which is applied to a system-level binary translator and can be used to optimize the execution of direct jump instructions.

[0030] Some concepts involved in the embodiments of the present invention will be explained below.

[0031] Guest Virtual Address (GVA) is the virtual address space allocated by the guest operating system for its processes or applications.

[0032] Guest Physical Address (GPA) is the address obtained by the guest operating system after converting GVA through its Memory Management Unit (MMU), and it is the "physical address" considered by the guest operating system or runtime environment. The guest operating system maps GVA to GPA, but these addresses are not real physical addresses and are further mapped to the host's address space by the binary translator or virtualization layer.

[0033] Host Virtual Address (HVA) is the virtual address used by the host operating system for its own processes and the guest.

[0034] In user-level binary translation, a basic block can be uniquely identified using GVA. Specifically, user-level binary translators mainly translate the binary code of a single user process. In the context of a single process, the guest virtual address GVA provides an independent and continuous virtual address space for the process. Each process uses a unique GVA, and the code and data within the process are organized and accessed according to GVA. Therefore, in this relatively independent process environment, using GVA can uniquely identify a basic block.

[0035] In system-level binary translation, both GVA and GPA are required to uniquely identify a basic block. Specifically, system-level binary translation involves the entire operating system and multiple processes managed by it. Different processes may have the same GVA, but their actual positions in physical memory are different. The guest physical address GPA represents the physical memory address from the perspective of the guest operating system, which can reflect the actual position of the basic block in physical memory. Therefore, relying solely on GVA cannot uniquely identify a basic block. It is necessary to combine GPA to distinguish different basic blocks corresponding to the same GVA in different processes. Therefore, in system-level binary translation, both GVA and GPA are required to uniquely identify a basic block.

[0036] Since the guest program runs in the host environment, the physical memory of the guest program is actually simulated by the virtual memory of the host. Therefore, it is necessary to establish a mapping relationship between GPA and HVA. This mapping relationship is maintained by the binary translation system to ensure that the physical memory accessed by the guest can be correctly mapped to the virtual memory space of the host. The relationship between GVA and HVA is indirect and requires GPA as an intermediate bridge. First, convert GVA to GPA, and then map GPA to HVA. Although GPA and HVA belong to different address spaces of the guest and the host respectively, they actually point to the same physical memory resource. For example, when the guest program accesses the memory corresponding to a certain GPA, the binary translation system will map it to an HVA, and these two addresses correspond to the same actual memory data.

[0037] Since in system-level binary translation, there is a one-to-one mapping relationship between the guest physical address GPA and the host virtual address HVA, the actual address corresponding to the guest virtual address GVA can be the guest physical address GPA or the host virtual address HVA.

[0038] Refer to Figure 2 , which shows the step flowchart of an embodiment of the basic block linking method of the present invention. The method is applied to a system-level binary translator, and the method may include the following steps:

[0039] Step 101, during the execution of the target search code, determine whether the jump source basic block meets the unlink condition; the target search code is used to search for the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the jump source basic block is a basic block ending with a direct jump instruction; the jump target basic block is the basic block to which the jump source basic block is to jump; the unlink condition includes: the jump target basic block spans pages and the virtual-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in the linked state;

[0040] Step 102: If it is determined that the jump source basic block meets the unlinking condition, then unlink the jump source basic block.

[0041] Step 103: Re-link the unlinked jump source basic block.

[0042] In system-level binary translation, it is necessary to use both the guest virtual address (GVA) and the actual address (guest physical address GPA or host virtual address HVA) to uniquely identify a basic block.

[0043] In the memory management of the operating system, to effectively manage memory, the memory is divided into pages of fixed size, and the page is the basic unit of memory management. The page mentioned here refers to the virtual page.

[0044] For ease of description, in the embodiments of the present invention, the system-level binary translator is also simply referred to as the translator. Before the translator executes the first basic block in a page, it checks whether the virtual-to-real address mapping relationship of the page is correct. The virtual-to-real address mapping relationship refers to the mapping relationship between the guest virtual address (GVA) and the actual address. This is because the operating system may perform various operations on the memory, such as page replacement and memory allocation adjustment, which may cause the virtual-to-real address mapping relationship to change. If the virtual-to-real address mapping relationship is correct (has not changed), it means that all address accesses within the page are predictable and secure. When executing the subsequent basic blocks in the page, there is no need to repeatedly check the virtual-to-real address mapping relationship of the page.

[0045] In the embodiments of the present invention, the jump source basic block refers to the basic block ending with a direct jump instruction. The jump target basic block refers to the basic block to which the direct jump instruction in the jump source basic block jumps.

[0046] The direct jump instruction clearly specifies the jump target address. During the program compilation or assembly stage, the jump target address of the direct jump instruction has been determined, and unless the program code is modified, the jump target will not change. The direct jump instruction carries the jump target address, and this jump target address points to the first instruction of the basic block (jump target basic block) to which it jumps. It can be understood that the address of a certain basic block described in the embodiments of the present invention refers to the address of the first instruction in the basic block. For example, the guest virtual address (GVA) of basic block B refers to the guest virtual address (GVA) of the first instruction in basic block B.

[0047] During the program running process, there may be two situations. One is that the jump target basic block and the jump source basic block are in the same page, which is called that the jump target basic block does not cross pages; the other is that the jump target basic block and the jump source basic block are not in the same page, which is called that the jump target basic block crosses pages.

[0048] Since the jump target address of a direct jump instruction is fixed, unlike the jump target address of an indirect jump instruction which can only be determined during execution, when translating a direct jump instruction, if it is determined that the jump target basic block spans pages, the translation of the direct jump instruction can be optimized by inserting a target instruction sequence. This target instruction sequence is used to optimize the execution of the direct jump instruction when it is determined that the direct jump instruction meets the optimization conditions during the execution of the direct jump instruction. It directly jumps through the link instruction sequence, reducing the search operation of basic blocks during the program execution while ensuring correct cross-page jumps and improving the program execution efficiency. The link instruction sequence is used to jump to the starting address in the code cache of the translated basic block corresponding to the jump target basic block.

[0049] Furthermore, the target instruction sequence is also used to not optimize the execution of the direct jump instruction when it is detected that the direct jump instruction does not meet the optimization conditions, jump to the unoptimized instruction sequence, perform basic block search according to the original process, and then perform the jump to ensure correct jump.

[0050] Among them, the optimization conditions include: the jump target basic block spans pages and the virtual-to-physical address mapping relationship of the jump target basic block spanning pages has not changed. That is, when executing the direct jump instruction in the jump source basic block this time, although the jump target basic block spans pages, the virtual-to-physical address mapping relationship of the jump target basic block has not changed compared with the virtual-to-physical address mapping relationship at the first cross-page link.

[0051] However, if when executing the direct jump instruction in the jump source basic block, the jump target basic block spans pages and the virtual-to-physical address mapping relationship changes, then every time the direct jump instruction in this jump source basic block is executed subsequently, it can only jump to the unoptimized instruction sequence for jumping. The unoptimized instruction sequence needs to jump to the target search code to execute the slow search logic, affecting the running efficiency of the application program.

[0052] Among them, the change in the virtual-to-physical address mapping relationship of the jump target basic block means that when executing the direct jump instruction in the jump source basic block this time and about to jump to the jump target basic block, the actual address (such as GPA2) corresponding to the client virtual address (such as GVA1) of the jump target basic block has changed compared with the actual address (such as GPA1) corresponding to the client virtual address (such as GVA1) of the jump target basic block when the jump source basic block and the jump target basic block were linked.

[0053] The target search code is used to execute the slow search logic, that is, to search for the host virtual address (HVA) of the translated basic block corresponding to the jump target basic block according to the client virtual address (GVA) of the jump target basic block (such as basic block 2). The host virtual address (HVA) of the translated basic block corresponding to the jump target basic block refers to the starting address of the translated basic block corresponding to the jump target basic block in the code cache.

[0054] In order to optimize the execution of direct jump instructions and reduce the number of times of executing the slow search logic even when the jump target basic block spans pages and the virtual-to-physical address mapping relationship changes, the embodiment of the present invention adds a judgment and processing operation to the slow search logic (i.e., the target search code). It is judged whether the jump source basic block meets the unlink condition. The unlink condition includes: the jump target basic block spans pages and the virtual-to-physical address mapping relationship of the jump target basic block changes, and the jump source basic block is in the linked state.

[0055] In one example, basic block 1 (jump source basic block) ends with a direct jump instruction that jumps to basic block 2 (jump target basic block).

[0056] During the translation stage, when translating the direct jump instruction in basic block 1, if it is recognized that basic block 2 spans pages, a placeholder instruction sequence is inserted before the unoptimized instruction sequence after the translation of the direct jump instruction, and a target instruction sequence is inserted before the placeholder instruction sequence. The target instruction sequence is an instruction sequence under the host architecture. The embodiment of the present invention does not limit the form of the target instruction sequence, and there may be different forms under different host architectures. The target instruction sequence may include one or more instructions under the host architecture in different host architectures.

[0057] Among them, the placeholder instruction sequence may include at least one no-operation instruction (such as the NOP instruction of the host architecture). The placeholder instruction sequence is used to reserve a position for subsequent basic block linking. The NOP instruction (No Operation) is an instruction widely used in computer architecture, and its function is "no operation". When the CPU executes the NOP instruction, it will not have any substantial impact on registers, memory, or program status, but simply consumes one or more clock cycles and then continues to execute the next instruction.

[0058] When the direct jump instruction in basic block 1 is executed for the first time and basic block 1 is in an unlinked state, the unoptimized instruction sequence is executed. The unoptimized instruction sequence will jump to the target lookup code to find the starting address of the translated basic block corresponding to basic block 2 in the code cache. If the translated basic block corresponding to basic block 2 is found in the code cache, basic block linking is performed on basic block 1 and basic block 2, and the execution jumps to the starting address of the translated basic block corresponding to basic block 2 in the code cache; if not found, it exits to the translation process, translates basic block 2, stores the translated basic block corresponding to basic block 2 in the code cache after translation, performs basic block linking on basic block 1 and basic block 2, and jumps to the starting address of the translated basic block corresponding to basic block 2 in the code cache. In addition, the virtual and physical address mapping relationship of basic block 2 during linking is recorded, that is, the client virtual address of basic block 2 (such as GVA1) and the corresponding physical address (such as GPA1) are recorded.

[0059] After basic block linking, the jump source basic block is in a linked state, and the placeholder instruction sequence is replaced by the link instruction sequence. Therefore, when the direct jump instruction in the jump source basic block is executed next time, if the target instruction sequence determines that the optimization condition is met, the link instruction sequence is directly executed, and then directly jumps to the starting address (HVA) of the translated basic block corresponding to the jump target basic block in the code cache, and the target lookup code will not be executed again. It can avoid executing the target lookup code each time to find the starting address (HVA) of the translated basic block corresponding to the jump target basic block in the code cache according to the GVA of the jump target basic block, and can improve the program running efficiency.

[0060] In a specific implementation, performing basic block linking on the jump source basic block (such as basic block 1) and the jump target basic block (such as basic block 2) means replacing the placeholder instruction sequence with a link instruction sequence, and this link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the jump target basic block in the code cache.

[0061] In the above example, the first basic block linking of basic block 1 and basic block 2 is called the first cross-page link, that is, the placeholder instruction sequence is replaced by the first link instruction sequence. The first link instruction sequence is used to jump to the first starting address of the translated basic block corresponding to basic block 2 in the code cache. For ease of description, in the embodiments of the present invention, the starting address of the translated basic block corresponding to the jump target basic block found during the first cross-page link in the code cache is called the first starting address; and the link instruction sequence generated during the first cross-page link is called the first link instruction sequence.

[0062] When the direct jump instruction in basic block 1 is executed for the Nth (N≥2) time, the target instruction sequence is executed. The target instruction sequence determines whether the direct jump instruction meets the optimization condition. If it meets the optimization condition, that is, the virtual-to-physical address mapping relationship of basic block 2 has not changed, which means that the actual address corresponding to the guest virtual address GVA1 of basic block 2 during this execution is still GPA1, then it can jump through the first link instruction sequence; if it does not meet the optimization condition, that is, the virtual-to-physical address mapping relationship of basic block 2 has changed, which means that the actual address corresponding to the guest virtual address GVA1 of basic block 2 during this execution is not GPA1, such as becoming GPA2, then it jumps through the execution of the unoptimized instruction sequence.

[0063] Since the jump target basic block (such as basic block 2) spans pages and the virtual-to-physical address mapping relationship has changed, then each subsequent execution can only use the unoptimized instruction sequence to achieve the jump. The unoptimized instruction sequence needs to jump to the target search code to execute the slow search logic, which affects the running efficiency of the application program.

[0064] The embodiment of the present invention optimizes the execution process of the target search code, so that when the target instruction sequence is executed, if it is determined that the direct jump instruction does not meet the optimization condition and jumps to the unoptimized instruction sequence and then executes the target search code, the jump source basic block that meets the unlink condition can be unlinked, and then the unlinked jump source basic block can be re-linked. Thus, when the jump target basic block spans pages and the virtual-to-physical address mapping relationship has changed, through unlinking and re-linking, the execution optimization of the direct jump instruction in the jump source basic block can also be achieved.

[0065] Specifically, by unlinking the jump source basic block (such as basic block 1), the previous first link instruction sequence can be cancelled. The first link instruction sequence is used to jump to the first starting address of the translated basic block corresponding to basic block 2 in the code cache. Since the virtual-to-physical address mapping relationship of basic block 2 may change during subsequent executions, therefore, in the case of a change, if the first link instruction sequence is still used for jumping, it may jump to an incorrect address. Therefore, the embodiment of the present invention unlinks the jump source basic block (such as basic block 1) that meets the unlink condition to cancel the previous first link instruction sequence, and re-finds the starting address of the translated basic block corresponding to basic block 2 in the code cache, which is called the second starting address. The second starting address is the correct address obtained after the virtual-to-physical address mapping relationship of basic block 2 has changed. Using this correct address (the second starting address) to re-link the jump source basic block (such as basic block 1), such as generating a second link instruction sequence, and using this second link instruction sequence can jump to the correct address after the virtual-to-physical address mapping relationship of basic block 2 has changed.

[0066] Thus, by performing basic block unlinking on the jump source basic block that meets the unlinking condition, and then re-linking the unlinked jump source basic block with the correct address, when the direct jump instruction in the jump source basic block is subsequently executed, the linked instruction sequence after re-linking (such as the second linked instruction sequence) can be executed, and thus directly jump to the starting address (HVA) of the translated basic block corresponding to the jump target basic block in the code cache, without having to execute the target search code. Each time the target search code is executed to find the starting address (HVA) of the translated basic block corresponding to the jump target basic block according to the GVA of the jump target basic block can be avoided, and the program running efficiency can be improved.

[0067] In practical applications, after the basic block linking between the jump source basic block and the jump target basic block across pages is performed for the first time, the virtual-to-physical address mapping relationship of the jump target basic block may change, but usually does not change frequently. Thus, through the embodiments of the present invention, after the virtual-to-physical address mapping relationship of the jump target basic block changes, the second linked instruction sequence generated by re-linking can be used for direct jump, and the program running efficiency can be improved.

[0068] In an alternative embodiment of the present invention, the operation of performing basic block linking on any jump source basic block may include:

[0069] Step S11: Determine whether the jump target basic block corresponding to the jump source basic block spans pages;

[0070] Step S12: If it is determined that the jump target basic block spans pages, determine whether the jump source basic block is the first cross-page link;

[0071] Step S13: If it is determined that the jump source basic block is the first cross-page link, use the first starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache to perform basic block linking on the jump source basic block, and record the virtual-to-physical address mapping relationship of the jump target basic block at the time of the first cross-page link;

[0072] Step S14: If it is determined that the jump source basic block is not the first cross-page link, use the second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache to perform basic block linking on the jump source basic block, and update the virtual-to-physical address mapping relationship of the jump target basic block recorded at the time of the first cross-page link.

[0073] In a specific implementation, if the jump target basic block does not span pages, that is, the jump target basic block and the jump source basic block are on the same virtual page, it is called a non-page-crossing jump. For the case of non-page-crossing jumps, the execution of direct jump instructions can also be optimized through basic block chaining. For example, basic block 3 ends with a direct jump instruction that is to jump to basic block 4, and basic block 3 and basic block 4 are on the same virtual page. When the direct jump instruction in basic block 3 is first executed to jump to basic block 4, basic block chaining can be performed on basic block 3 and basic block 4, so that subsequent executions can use the linked instruction sequence for direct jumps.

[0074] In order to achieve direct jump instruction execution optimization through basic block chaining even when the virtual-to-physical address mapping relationship of the jump target basic block changes during page-crossing jumps, the embodiments of the present invention improve the original basic block chaining process of the translator, and the improved process is as shown in steps S11 to S14.

[0075] Since the embodiments of the present invention optimize the case of page-crossing jumps, when performing basic block chaining on a certain jump source basic block, it is first determined whether the jump target basic block corresponding to the jump source basic block spans pages. If it is determined that the jump target basic block spans pages, it is further determined whether the jump source basic block is a first-time page-crossing link.

[0076] If it is determined that the jump source basic block is a first-time page-crossing link, the first start address in the code cache of the translated basic block corresponding to the jump target basic block found this time is used to perform basic block chaining on the jump source basic block, and the virtual-to-physical address mapping relationship of the jump target basic block at the time of the first page-crossing link is recorded, such as recording the client virtual address (such as GVA1) and the corresponding physical address (such as GPA1) of the jump target basic block. Recording the virtual-to-physical address mapping relationship of the jump target basic block at the time of the first page-crossing link is for the purpose of determining whether the virtual-to-physical address mapping relationship of the jump target basic block has changed during the next execution.

[0077] It should be noted that the placeholder instruction sequence generated during the translation phase is replaced during the first page-crossing link. For example, in the above example, during the translation phase, when translating the direct jump instruction in basic block 1, a placeholder instruction sequence is inserted before the unoptimized instruction after translation, and a target instruction sequence is inserted before the placeholder instruction sequence. When performing the first page-crossing link on basic block 1 and basic block 2, the placeholder instruction sequence is replaced with a first linked instruction sequence, and the first linked instruction sequence is used to jump to the first start address in the code cache of the translated basic block corresponding to basic block 2.

[0078] When the direct jump instruction in basic block 1 is executed next time, the target instruction sequence will be executed. If the target instruction sequence determines that basic block 2 spans pages and the virtual-to-physical address mapping relationship has changed, the unoptimized instruction sequence will be executed, and then it will jump to the target search code to execute step 101. Step 101 determines whether basic block 1 meets the unlink condition; since basic block 2 spans pages and the virtual-to-physical address mapping relationship has changed, and basic block 1 is in the linked state, it is determined that basic block 1 meets the unlink condition, and basic block unlinking can be performed on basic block 1.

[0079] Since the virtual-to-physical address mapping relationship of basic block 2 has changed during this execution, the first starting address that the first link instruction sequence generated during the first cross-page link is to jump to may point to an incorrect address. Therefore, basic block unlinking is performed on basic block 1 to cancel the first link instruction sequence and disconnect the link between basic block 1 and an incorrect jump address.

[0080] Further, the basic block unlinking of the jump source basic block may include:

[0081] Replacing the first link instruction sequence in the jump source basic block with a placeholder instruction sequence; the first link instruction sequence is generated during the first cross-page link of the jump source basic block, and the first link instruction sequence is used to jump to the first starting address of the translated basic block corresponding to the jump target basic block in the code cache, and the first starting address is found during the first cross-page link.

[0082] In the embodiment of the present invention, the basic block linking operation is to replace the placeholder instruction sequence with a link instruction sequence. Conversely, the basic block unlinking operation is to replace (restore) the link instruction sequence with a placeholder instruction sequence.

[0083] Since the first starting address pointed to by the first link instruction sequence generated during the first cross-page link may change due to the change of the virtual-to-physical address mapping relationship of the jump target basic block during subsequent execution, in the embodiment of the present invention, when it is determined that the jump source basic block meets the unlink condition, basic block unlinking is performed on the jump source basic block to restore the first link instruction sequence to a placeholder instruction sequence.

[0084] After basic block unlinking is performed on basic block 1, basic block 1 is in the unlinked state, and basic block linking can be performed on the unlinked basic block 1 again.

[0085] In step S14, if it is determined that the jump source basic block is not the first cross-page link, that is, it is a basic block link performed again after the basic block of the jump source basic block is unchained, then the second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is used to perform basic block linking on the jump source basic block, and the virtual and physical address mapping relationship of the jump target basic block at the time of the first cross-page link recorded is updated.

[0086] For example, after the basic block of basic block 1 is unchained as described above and basic block 1 is linked again, then this basic block link is not the first cross-page link. Since the virtual and physical address mapping relationship of basic block 2 has changed, it is necessary to use the second starting address of the translated basic block corresponding to basic block 2 found this time in the code cache to relink basic block 1. The second starting address is the starting address of the translated basic block corresponding to basic block 2 found after the virtual and physical address mapping relationship of basic block 2 changes when directly jumping to the instruction in basic block 1 is executed this time. Therefore, the second starting address is a correct jump address. Using the second starting address to relink basic block 1 can ensure that the jump is made to the correct address during the next execution.

[0087] In addition, since the virtual and physical address mapping relationship of the jump target basic block is recorded at the time of the first cross-page link, during the subsequent execution process, when determining whether the virtual and physical address mapping relationship of the jump target basic block has changed, it is compared with the virtual and physical address mapping relationship of the jump target basic block recorded at the time of the first cross-page link. Therefore, when performing cross-page link again, it is necessary to update the virtual and physical address mapping relationship of the jump target basic block recorded at the time of the first cross-page link. Thus, during the subsequent execution process, it can be compared with the updated record, which can ensure the correctness of the process.

[0088] Further, the relinking of the unchained jump source basic block may include:

[0089] Obtain the second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache, and replace the placeholder instruction sequence in the jump source basic block with a second link instruction sequence for jumping to the second starting address.

[0090] It should be noted that the starting address of the translated basic block corresponding to the jump target basic block in the code cache can be obtained by searching the target search code. Specifically, the target search code first searches in the code cache to see if there is a translated basic block corresponding to the jump target basic block. If it exists, it is directly found; if not, the current process exits and enters the translation process to translate the jump target basic block. After the translation is completed, the translated basic block corresponding to the jump target basic block is stored in the code cache, and the starting address of the translated basic block corresponding to the jump target basic block in the code cache is obtained.

[0091] It can be understood that during the process of re-linking the unchained jump source basic block, the placeholder instruction sequence in the jump source basic block is replaced with a second link instruction sequence, and this placeholder instruction sequence is restored when the jump source basic block is unchained.

[0092] When the direct jump instruction in basic block 1 is executed next time, the target instruction sequence is executed. The target instruction sequence can read the virtual-to-physical address mapping relationship of basic block 2 at the first cross-page link that has been recorded and compare it with the virtual-to-physical address mapping relationship of basic block 2 during this execution. Since the recorded virtual-to-physical address mapping relationship has been updated to the changed virtual-to-physical address mapping relationship during re-linking, the target instruction sequence detects that the virtual-to-physical address mapping relationship of basic block 2 during this execution has not changed and can directly jump using the link instruction sequence. Specifically, it directly jumps to the second starting address through the second link instruction sequence.

[0093] If the target instruction sequence detects that the virtual-to-physical address mapping relationship of basic block 2 during this execution has changed, it can jump to the unoptimized instruction sequence and then enter the target search code, that is, execute step 101. When it is determined that the unchaining condition is met, the basic block can be unchained again and the process of re-linking the basic block can be carried out.

[0094] The embodiment of the present invention improves the execution process of the original target search code. When it is determined that the unchaining condition is met, the jump source basic block is unchained, so that the jump source basic block can be re-linked with the correct jump address (such as the second starting address). In the case of cross-page jumps and changes in the virtual-to-physical address mapping relationship of the jump target basic block, the execution of the direct jump instruction can also be optimized, and fast jumps can be made through the correct link instruction sequence (such as the second link instruction sequence), avoiding slow searches using the unoptimized instruction sequence every time, which can improve the efficiency of the translator in executing application programs.

[0095] In a specific implementation, the direct jump instruction may include an unconditional jump instruction and a conditional jump instruction. An unconditional jump instruction refers to an instruction that, regardless of any conditions, the program will immediately jump to the specified target address and continue execution. Once the unconditional jump instruction is executed, the program will directly jump to the address specified in the instruction. A conditional jump instruction refers to an instruction that determines whether to jump to the specified target address based on specific conditions.

[0096] The conditional jump instruction has two jump branches: the branch is taken or not taken. When the condition of the conditional jump instruction is satisfied, the program will jump to the specified target address and continue execution. This situation is called the branch being taken, that is, the jump operation is executed. When the condition of the conditional jump instruction is not satisfied, the program will not perform a jump but continue to sequentially execute the next instruction. This situation is called the branch not being taken, that is, the jump operation is not executed.

[0097] Therefore, a direct jump instruction may have one jump target or two jump targets. For an unconditional jump instruction, there is only one jump target. For a conditional jump instruction, there are two jump targets.

[0098] In an embodiment of the present invention, the jump target basic block may include a first jump target basic block or a second jump target basic block; the first jump target basic block is the jump target of the unconditional jump instruction, or the jump target (taken) when the condition of the conditional jump instruction is satisfied; the second jump target basic block is the jump target (not taken) when the condition of the conditional jump instruction is not satisfied.

[0099] In an alternative embodiment of the present invention, the structure of each basic block may contain a first variable, and the initial value of the first variable is empty. The method may further include:

[0100] Step S21, if it is determined that the jump target basic block spans pages, record the pointer of the structure of the jump target basic block in the first variable in the structure of the jump source basic block;

[0101] Step S22, during the execution of the target search code, determine whether the jump source basic block is in a linked state by judging whether the value of the first variable in the structure of the jump source basic block is empty.

[0102] In the embodiment of the present invention, a first variable is newly added to the structure of each basic block. The first variable may be a pointer-type variable and is used to record the pointer of the structure of the linked jump target basic block in the structure of the jump source basic block. The initial value of the first variable is empty, indicating that there is no linked jump target basic block for this jump source basic block.

[0103] When the embodiment of the present invention executes step S12, if it is determined that the jump target basic block spans pages, the pointer to the structure of the jump target basic block is recorded in the first variable in the structure of the jump source basic block. For example, the pointer to the structure of basic block 2 is recorded in the first variable in the structure of basic block 1, and this pointer points to the structure of basic block 2.

[0104] Furthermore, a direct jump instruction may have one jump target or two jump targets. Therefore, two first variables can be used to record the two different jump targets respectively. For example, the first variable next_tb0 is used to record the pointer to the structure of the first jump target basic block, and the first variable next_tb1 is used to record the pointer to the structure of the second jump target basic block.

[0105] During the execution of step 101, when it is determined that the jump target basic block spans pages and the virtual-to-physical address mapping relationship of the jump target basic block changes, it is also necessary to determine whether the jump source basic block is in the linked state. At this time, the value of the first variable in the structure of the jump source basic block can be read. This value points to the structure of the linked jump target basic block. If the value read from the first variable is empty, it means that the jump source basic block does not have a linked jump target basic block and is in the unlinked state; if the value read from the first variable is not empty, it means that the jump source basic block is in the linked state.

[0106] By adding a first variable to the structure of the basic block in the embodiment of the present invention, it is possible to quickly determine whether the jump source basic block is in the linked state during the execution of the target search code.

[0107] In an alternative embodiment of the present invention, the structure of each basic block may include a second variable, and the initial value of the second variable is a first value. Determining whether the jump source basic block is a first cross-page link may include:

[0108] Read the value of the second variable in the structure of the jump source basic block. If the value of the second variable is the first value, it is determined that the jump source basic block is a first cross-page link; if the value of the second variable is a second value, it is determined that the jump source basic block is not a first cross-page link.

[0109] In the embodiment of the present invention, a second variable is added to the structure of each basic block. The second variable may be a boolean variable used to identify whether the basic block has performed a first cross-page link.

[0110] The initial value of the second variable is the first value (e.g., false), indicating that the basic block has not undergone the first cross-page link yet. If the value of the second variable in the structure of a certain basic block is the second value (e.g., true), it indicates that the basic block has undergone the first cross-page link.

[0111] When executing step S12, the value of the second variable in the structure of the jump source basic block can be read. According to whether the read value of the second variable is the first value or the second value, if the read value of the second variable is the first value, it means that the jump source basic block has not undergone the first cross-page link yet, and the basic block link performed on this jump source basic block this time is the first cross-page link. If the read value of the second variable is the second value, it means that the jump source basic block has undergone the first cross-page link, and the basic block link performed on this jump source basic block this time is not the first cross-page link but a re-cross-page link.

[0112] Furthermore, the method may further include:

[0113] In the case where it is determined that the jump source basic block is the first cross-page link, after performing the basic block link on the jump source basic block, the value of the second variable in the structure of the jump source basic block is set to the second value.

[0114] Specifically, after step S13 is executed, the value of the second variable in the structure of the jump source basic block is set to the second value, indicating that the jump source basic block has undergone the first cross-page link.

[0115] By adding a second variable to the structure of the basic block in the embodiments of the present invention, it is possible to quickly determine whether the jump source basic block is the first cross-page link this time during the execution of the basic block link.

[0116] The structure of the basic block is a data structure in the interpreter used to represent and store basic block information. It can be understood that the embodiments of the present invention do not limit the positions of the first variable and the second variable in the structure of the basic block.

[0117] It should be noted that in the embodiments of the present invention, during the execution phase, the jump source basic block and the jump target basic block refer to the basic blocks in the translated host instruction architecture. During the translation phase, the jump source basic block and the jump target basic block refer to the basic blocks in the client instruction architecture before translation. The unoptimized instruction sequence, link instruction sequence (including the first link instruction sequence and the second link instruction sequence), target instruction sequence, placeholder instruction sequence, and target search code are all instruction sequences in the host instruction architecture.

[0118] In a specific implementation, for a jump source basic block ending with a direct jump instruction, when the jump source basic block is executed for the first time, the jump source basic block is in an unlinked state. When the direct jump instruction is executed, the current process will exit and enter the translation context to translate the jump target basic block. After the translation is completed, the jump source basic block and the jump target basic block will be linked.

[0119] In one example, the embodiment of the present invention refers to the original basic block linking logic of the translator as the basic linking logic. The embodiment of the present invention adds the following steps shown as A1 to A4 before the basic linking logic:

[0120] A1. Determine whether the jump target basic block spans pages. If it does not span pages, execute A5; if it spans pages, execute A2.

[0121] A2. Record the pointer of the structure of the jump target basic block in the first variable in the structure of the jump source basic block; execute A3.

[0122] A3. Read the value of the second variable in the structure of the jump source basic block. If the value read from the second variable is the first value, it indicates that this is the first cross-page link of the jump source basic block. Then set the value of the second variable to the second value and execute A5; if the value read from the second variable is the second value, it indicates that this is a re-link of the jump source basic block, and execute A4.

[0123] A4. Obtain the second starting address of the translated basic block corresponding to the jump target basic block in the code cache, use this second starting address to replace the placeholder instruction sequence generated during the unlinking process, and update the virtual and physical address mapping relationship of the jump target basic block during the first cross-page link that has been recorded; exit the current basic block linking process.

[0124] A5. Execute the basic linking logic.

[0125] Among them, the basic linking logic includes: replacing the placeholder instruction sequence with the first link instruction sequence, and recording the virtual and physical address mapping relationship of the jump target basic block during the first cross-page link.

[0126] In a specific implementation, since the target search code needs to perform operations in multiple steps and contains a large number of instructions, the target search code can be used as common code and stored in a common basic block. There are various reasons for entering the target search code. For example, when executing a target instruction sequence, if it is detected that the jump target basic block spans pages and the virtual-to-physical address mapping relationship changes, then jump to the unoptimized instruction sequence, and then execute the target search code. Another example is that when executing a direct jump instruction in the jump source basic block and the jump source basic block is in an unlinked state, the target search code is executed to find the starting address of the translated basic block corresponding to the jump target basic block in the code cache. Another example is that when executing a direct jump instruction in the jump source basic block and the jump target basic block corresponding to the direct jump instruction is invalid due to code self-modification, the target search code is executed to find the starting address of the translated basic block corresponding to the jump target basic block in the code cache.

[0127] In one example, the operations performed by the original target search code of the translator in the embodiments of the present invention are referred to as slow search logic. The embodiments of the present invention add the following steps shown as B1 to B4 in this slow search logic:

[0128] B1. Determine whether the jump target basic block spans pages. If it spans pages, execute B2; if it does not span pages, execute B5;

[0129] B2. Read a first variable from the structure of the jump source basic block. If the value of the first variable read is empty, it indicates that the jump source basic block is in an unlinked state, and execute B5; if the value of the first variable read is not empty, it indicates that the jump source basic block is in a linked state, then execute B3;

[0130] B3. Determine whether the virtual-to-physical address mapping relationship of the jump target basic block has changed. If it has not changed, execute B5; if it has changed, execute B4;

[0131] B4. Determine that the jump source basic block meets the unlink condition, perform basic block unlinking on the jump source basic block, and replace the first link instruction sequence with a placeholder instruction sequence;

[0132] B5. Execute the slow search logic.

[0133] Further, in the embodiments of the present invention, when performing basic block chaining on any basic block, the client virtual address of the jump target basic block and the corresponding actual address may be recorded. The step of determining whether the virtual-to-physical address mapping relationship of the jump target basic block has changed in B3 may include: reading the client virtual address of the jump target basic block and the corresponding actual address recorded during basic block chaining, querying the actual address corresponding to the client virtual address of the jump target basic block during the current execution based on the read client virtual address of the jump target basic block, and determining whether the actual address queried during the current execution is consistent with the actual address read during basic block chaining. If they are consistent, it is determined that the virtual-to-physical address mapping relationship of the jump target basic block has not changed; if they are inconsistent, it is determined that the virtual-to-physical address mapping relationship of the jump target basic block has changed.

[0134] Among them, querying the actual address corresponding to the client virtual address of the jump target basic block during the current execution based on the read client virtual address of the jump target basic block may be performed through a software address translation lookaside buffer; exemplarily, querying through a software address translation lookaside buffer; the software address translation lookaside buffer is used to store the mapping relationship of the most recently used GVA to GPA to accelerate the address translation process. Therefore, querying the software address translation lookaside buffer based on the GVA can obtain the GPA corresponding to the GVA.

[0135] The slow search logic in B5 may include: searching for the translated basic block corresponding to the jump target basic block in the code cache. If found, obtaining the starting address of the translated basic block corresponding to the jump target basic block in the code cache and jumping to the execution at that starting address; if not found, entering the translation process, translating the jump target basic block, and after the translation is completed, saving the translated basic block corresponding to the jump target basic block to the code cache, obtaining the starting address of the translated basic block corresponding to the jump target basic block in the code cache, and jumping to the execution at that starting address.

[0136] It should be noted that the embodiments of the present invention do not limit the positions of B1 to B4 inserted, and they can be inserted at any position before or after the slow search logic, etc.

[0137] In summary, the embodiments of the present invention improve the execution process of the original target search code, and determine whether the jump source basic block meets the unlink condition. The unlink condition includes: the jump target basic block spans pages and the virtual-to-physical address mapping relationship of the jump target basic block changes, and the jump source basic block is in the linked state. When it is determined that the jump source basic block meets the unlink condition, the jump source basic block is unlinked. Thus, the correct jump address (such as the second start address) can be used to relink the jump source basic block, so that when there is a cross-page jump and the virtual-to-physical address mapping relationship of the jump target basic block changes, the execution of the direct jump instruction can also be optimized, and a direct jump can be performed through the correct link instruction sequence (such as the second link instruction sequence), avoiding the need to execute the unoptimized instruction sequence for slow search each time, reducing the number of times of searching for the jump target basic block when executing the direct jump instruction, and improving the efficiency of the translator in executing the application program.

[0138] It should be noted that for the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequence, because according to the embodiments of the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential for the embodiments of the present invention.

[0139] Referring to Figure 3 , a structural block diagram of an embodiment of a system-level binary translator of the present invention is shown. The system-level binary translator may include:

[0140] A condition judgment module 201, configured to determine whether a jump source basic block meets the unlink condition during the execution of the target search code; the target search code is used to search for the start address of the translated basic block corresponding to the jump target basic block in the code cache; the jump source basic block is a basic block ending with a direct jump instruction; the jump target basic block is the basic block to which the jump source basic block jumps; the unlink condition includes: the jump target basic block spans pages and the virtual-to-physical address mapping relationship of the jump target basic block changes, and the jump source basic block is in the linked state;

[0141] An unlink module 202, configured to unlink the jump source basic block if it is determined that the jump source basic block meets the unlink condition;

[0142] A link module 203, configured to relink the unlinked jump source basic block.

[0143] Optionally, the link module includes:

[0144] The first judgment sub-module is used to judge whether the jump target basic block corresponding to the jump source basic block crosses pages;

[0145] The second judgment sub-module is used to judge whether the jump source basic block is the first cross-page link if it is determined that the jump target basic block crosses pages;

[0146] The first link sub-module is used to, if it is determined that the jump source basic block is the first cross-page link, perform basic block linking on the jump source basic block by using the first starting address in the code cache of the translated basic block corresponding to the jump target basic block found this time, and record the virtual and real address mapping relationship of the jump target basic block during the first cross-page link;

[0147] The second link sub-module is used to, if it is determined that the jump source basic block is not the first cross-page link, perform basic block linking on the jump source basic block by using the second starting address in the code cache of the translated basic block corresponding to the jump target basic block found this time, and update the virtual and real address mapping relationship of the jump target basic block recorded during the first cross-page link.

[0148] Optionally, a first variable is included in the structure of each basic block, and the initial value of the first variable is empty. The system-level binary translator further includes:

[0149] The pointer recording module is used to, if it is determined that the jump target basic block crosses pages, record the pointer of the structure of the jump target basic block in the first variable in the structure of the jump source basic block;

[0150] The status judgment module is used to, during the process of executing the target search code, determine whether the jump source basic block is in the linked state by judging whether the value of the first variable in the structure of the jump source basic block is empty.

[0151] Optionally, a second variable is included in the structure of each basic block, and the initial value of the second variable is the first numerical value. The second judgment sub-module is specifically used for:

[0152] Read the value of the second variable in the structure of the jump source basic block. If the value of the second variable is the first numerical value, determine that the jump source basic block is the first cross-page link; if the value of the second variable is the second numerical value, determine that the jump source basic block is not the first cross-page link;

[0153] The system-level binary translator further includes:

[0154] A variable value update module, which is used to set the value of a second variable in the structure of the jump source basic block to a second numerical value after performing basic block linking on the jump source basic block when it is determined that the jump source basic block is a first cross-page link.

[0155] Optionally, the de-linking module is specifically used for:

[0156] Replacing the first link instruction sequence in the jump source basic block with a placeholder instruction sequence; the first link instruction sequence is generated when the jump source basic block makes a first cross-page link, and the first link instruction sequence is used to jump to the first starting address of the translated basic block corresponding to the jump target basic block in the code cache, and the first starting address is found during the first cross-page link.

[0157] Optionally, the linking module is specifically used for:

[0158] Obtaining the second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache, and replacing the placeholder instruction sequence in the jump source basic block with a second link instruction sequence, where the second link instruction sequence is used to jump to the second starting address.

[0159] Optionally, the jump target basic block includes a first jump target basic block or a second jump target basic block; the first jump target basic block is the jump target of an unconditional jump instruction or the jump target of a conditional jump instruction when the condition is satisfied; the second jump target basic block is the jump target of a conditional jump instruction when the condition is not satisfied.

[0160] Optionally, the system-level binary translator further includes:

[0161] An optimization execution module, which is used to execute a target instruction sequence when executing a direct jump instruction in the jump source basic block if it is determined that the jump target basic block crosses a page; the target instruction sequence is the content inserted when translating the direct jump instruction and determining that the jump target basic block crosses a page; the target instruction sequence is used to perform a jump through a link instruction sequence when it is detected that the direct jump instruction meets the optimization conditions, otherwise it jumps through an unoptimized instruction sequence; the optimization conditions include: the virtual-to-physical address mapping relationship of the jump target basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the unoptimized instruction sequence is used to jump to the target search code.

[0162] An embodiment of the present invention provides a system-level binary translator, which improves the execution process of the original target search code, and determines whether the jump source basic block meets the unlink condition. The unlink condition includes: the jump target basic block spans pages and the virtual-to-physical address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state. When it is determined that the jump source basic block meets the unlink condition, the jump source basic block is unlinked, so that the jump source basic block can be relinked with the correct jump address (such as the second start address). In the case of a cross-page jump and a change in the virtual-to-physical address mapping relationship of the jump target basic block, the execution of the direct jump instruction can also be optimized, and a direct jump can be performed through the correct link instruction sequence (such as the second link instruction sequence), avoiding the need to execute the unoptimized instruction sequence for slow search each time, reducing the number of times of searching for the jump target basic block when executing the direct jump instruction, and improving the efficiency of the translator in executing the application program.

[0163] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For the relevant parts, please refer to the partial description of the method embodiment.

[0164] Refer to Figure 4 , which is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. As Figure 4 shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction causes the processor to execute the steps of the basic block linking method in the foregoing embodiment.

[0165] An embodiment of the present invention provides a non-temporary computer-readable storage medium. When the instructions in the storage medium are executed by a program or a processor of a terminal, the terminal can execute the steps of the basic block linking method in the foregoing embodiment.

[0166] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is the difference from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0167] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a binary translator, or a computer program product. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0168] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for implementing the functions specified in Figure 1 one or more of the processes and / or Figure 1 blocks or multiple blocks.

[0169] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal device to work in a predictive manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device that implements the functions specified in Figure 1 one or more of the processes and / or Figure 1 blocks or multiple blocks.

[0170] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device, such that a series of operation steps are executed on the computer or other programmable terminal device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable terminal device provide steps for implementing the functions specified in Figure 1 one or more of the processes and / or Figure 1 blocks or multiple blocks.

[0171] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "including one..." does not exclude the presence of additional identical elements in the process, method, article or terminal device including the said element.

[0172] In this article, specific examples are used to elaborate on the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. At the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A basic block linking method, characterized in that: Applied to a system-level binary translator, the method comprises: In the process of executing the target search code, it is determined whether the jump source basic block meets the unlinking condition; the target search code is used to find the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the jump source basic block is a basic block ending with a direct jump instruction; the jump target basic block is the basic block to which the jump source basic block is to be jumped; the unlinking condition includes: the jump target basic block crosses pages and the virtual-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state; If it is determined that the jump source basic block meets the delinking condition, delinking the jump source basic block; The delinked jump source basic block is relinked.

2. The method according to claim 1, characterized in that The basic block linking operation is performed on any jump source basic block, including: Determine whether the jump target basic block corresponding to the jump source basic block crosses pages; If it is determined that the jump target basic block crosses pages, then determining whether the jump source basic block is linked across pages for the first time; If it is determined that the jump source basic block is linked across pages for the first time, the first starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is used to perform basic block linking on the jump source basic block, and the virtual-real address mapping relationship of the jump target basic block during the first cross-page linking is recorded; If it is determined that the jump source basic block is not the first cross-page link, the second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is used to perform basic block linking on the jump source basic block, and the virtual-to-real address mapping relationship of the jump target basic block during the first cross-page link that has been recorded is updated.

3. The method according to claim 2, characterized in that The structure of each basic block includes a first variable, and the initial value of the first variable is empty. The method further includes: If it is determined that the jump target basic block crosses pages, the pointer of the structure of the jump target basic block is recorded in the first variable in the structure of the jump source basic block; In the process of executing the target search code, it is determined whether the jump source basic block is in a linked state by judging whether the value of the first variable in the structure of the jump source basic block is empty.

4. The method according to claim 2, characterized in that: The structure of each basic block includes a second variable, the initial value of the second variable is a first value, and the determining whether the jump source basic block is the first cross-page link includes: Reading the value of a second variable in the structure of the jump source basic block, and if the value of the second variable is a first value, determining that the jump source basic block is the first cross-page link; if the value of the second variable is a second value, determining that the jump source basic block is not the first cross-page link; The method further comprises: When it is determined that the jump source basic block is linked across pages for the first time, after basic block linking is performed on the jump source basic block, the value of the second variable in the structure of the jump source basic block is set to a second value.

5. The method according to any one of claims 1 to 4, characterized in that: The step of performing basic block unlinking on the jump source basic block comprises: The first link instruction sequence in the jump source basic block is replaced with a placeholder instruction sequence; the first link instruction sequence is generated when the jump source basic block is linked across pages for the first time, and the first link instruction sequence is used to jump to the first starting address of the translated basic block corresponding to the jump target basic block in the code cache, and the first starting address is found during the first cross-page link.

6. The method according to any one of claims 1 to 4, characterized in that: The re-linking of the jump source basic block after delinking comprises: The second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is obtained, and the placeholder instruction sequence in the jump source basic block is replaced with a second link instruction sequence, where the second link instruction sequence is used to jump to the second starting address.

7. The method according to any one of claims 1 to 4, characterized in that: The jump target basic block includes a first jump target basic block or a second jump target basic block; the first jump target basic block is a jump target of an unconditional jump instruction, or a jump target of a conditional jump instruction when a condition is met; The second jump target basic block is the jump target of the conditional jump instruction when the condition is not satisfied.

8. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: When executing a direct jump instruction in the jump source basic block, if it is determined that the jump target basic block crosses pages, a target instruction sequence is executed; the target instruction sequence is the content inserted when translating the direct jump instruction and determining that the jump target basic block crosses pages; the target instruction sequence is used to jump through a link instruction sequence when it is detected that the direct jump instruction meets the optimization conditions, otherwise it jumps through a non-optimized instruction sequence; the optimization conditions include: the virtual-to-real address mapping relationship of the jump target basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the non-optimized instruction sequence is used to jump to the target search code.

9. A system-level binary translator, characterized in that: The system-level binary translator comprises: A conditional judgment module is used to judge whether a jump source basic block meets a delinking condition during the execution of a target search code; the target search code is used to find the starting address of a translated basic block corresponding to the jump target basic block in a code cache; the jump source basic block is a basic block ending with a direct jump instruction; the jump target basic block is a basic block to which the jump source basic block is to be jumped; the delinking condition includes: the jump target basic block crosses pages and the virtual-real address mapping relationship of the jump target basic block changes, and the jump source basic block is in a linked state; A delinking module, configured to delink the jump source basic block if it is determined that the jump source basic block satisfies the delinking condition; The linking module is used to re-link the jump source basic block after delinking.

10. The system-level binary translator according to claim 9, characterized in that: The link module comprises: The first judgment submodule is used to judge whether the jump target basic block corresponding to the jump source basic block crosses pages; A second judgment submodule is used to judge whether the jump source basic block is linked across pages for the first time if it is determined that the jump target basic block crosses pages; A first linking submodule is used to perform basic block linking on the jump source basic block using the first starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache if it is determined that the jump source basic block is linked across pages for the first time, and record the virtual-real address mapping relationship of the jump target basic block during the first cross-page linking; The second linking submodule is used to perform basic block linking on the jump source basic block if it is determined that the jump source basic block is not the first cross-page link, using the second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache, and updating the virtual-to-real address mapping relationship of the jump target basic block during the first cross-page link that has been recorded.

11. The system-level binary translator according to claim 10, characterized in that: The structure of each basic block includes a first variable, and the initial value of the first variable is empty. The system-level binary translator also includes: A pointer recording module, configured to record a pointer of a structure of the jump target basic block in a first variable in a structure of the jump source basic block if it is determined that the jump target basic block crosses pages; The state judgment module is used to determine whether the jump source basic block is in a linked state by judging whether the value of the first variable in the structure of the jump source basic block is empty during the execution of the target search code.

12. The system-level binary translator according to claim 10, characterized in that: The structure of each basic block includes a second variable, the initial value of the second variable is a first value, and the second judgment submodule is specifically used to: Reading the value of a second variable in the structure of the jump source basic block, and if the value of the second variable is a first value, determining that the jump source basic block is the first cross-page link; If the value of the second variable is a second value, it is determined that the jump source basic block is not the first cross-page link; The system-level binary translator also includes: The variable value updating module is used to set the value of the second variable in the structure of the jump source basic block to a second value after basic block linking is performed on the jump source basic block when it is determined that the jump source basic block is linked across pages for the first time.

13. The system-level binary translator according to any one of claims 9 to 12, characterized in that: The depolymerization module is specifically used for: The first link instruction sequence in the jump source basic block is replaced with a placeholder instruction sequence; the first link instruction sequence is generated when the jump source basic block is linked across pages for the first time, and the first link instruction sequence is used to jump to the first starting address of the translated basic block corresponding to the jump target basic block in the code cache, and the first starting address is found during the first cross-page link.

14. The system-level binary translator according to any one of claims 9 to 12, characterized in that: The link module is specifically used for: The second starting address of the translated basic block corresponding to the jump target basic block found this time in the code cache is obtained, and the placeholder instruction sequence in the jump source basic block is replaced with a second link instruction sequence, where the second link instruction sequence is used to jump to the second starting address.

15. The system-level binary translator according to any one of claims 9 to 12, characterized in that: The jump target basic block includes a first jump target basic block or a second jump target basic block; the first jump target basic block is a jump target of an unconditional jump instruction, or a jump target of a conditional jump instruction when a condition is met; The second jump target basic block is the jump target of the conditional jump instruction when the condition is not satisfied.

16. The system-level binary translator according to any one of claims 9 to 12, characterized in that: The system-level binary translator also includes: An optimization execution module is used to execute a target instruction sequence when executing a direct jump instruction in the jump source basic block, if it is determined that the jump target basic block crosses pages; the target instruction sequence is the content inserted when translating the direct jump instruction and determining that the jump target basic block crosses pages; the target instruction sequence is used to jump through a link instruction sequence when it is detected that the direct jump instruction meets the optimization condition, otherwise jump through a non-optimized instruction sequence; the optimization condition includes: the virtual-to-real address mapping relationship of the jump target basic block has not changed; the link instruction sequence is used to jump to the starting address of the translated basic block corresponding to the jump target basic block in the code cache; the non-optimized instruction sequence is used to jump to the target search code.

17. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the basic block linking method according to any one of claims 1 to 8.

18. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the basic block linking method as described in any one of claims 1 to 8 are implemented.

19. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the basic block linking method according to any one of claims 1 to 8 are implemented.

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