FPGA + DSP-based remote program updating method and system

Abstract

The invention discloses a remote program updating method and system based on FPGA + DSP, and the method comprises the steps: a main control platform located on the ground sends an uploading instruction and data to a space-based FPGA through a preset communication protocol, the FPGA carries out sum verification after receiving the data, the data is written into a plug-in SRAM if the verification is correct, and the data is sent to a server through a server; otherwise, returning to an error state and notifying the main control platform to resend the program code data, reading the data from the SRAM to perform CRC (cyclic redundancy check) after the data received by the FPGA is written into the SRAM, and sending a reset signal to the DSP after the verification is correct. And after the DSP responds to reset, the BootLoader program is read from the ROM to complete the work preparation for receiving the upper injection data, and then the data in the SRAM is read, so that the bootstrap and operation of the DSP are realized. According to the method, data uploading is completed by the DSP under the condition that equipment does not need to be disassembled, and a simple and effective method is provided for updating an image processing DSP program in a space-based environment.

Description

Technical Field

[0001] The present invention belongs to the field of remote program update of space-based platforms, and in particular relates to a method and system for remote program update based on FPGA+DSP. Background Art

[0002] Field Programmable Gate Arrays (FPGA) are programmable signal processing devices with rich logic resources and reprogrammable functions. Users can change configuration information to define functions according to design requirements. DSP (Digital Signal Processor) is a special processor for high-speed real-time processing of digital signals. Due to its high performance and software programmability, it has become one of the most popular products in the electronics industry. In recent years, more and more systems have combined the advantages of FPGA's high speed and high integration with the advantages of DSP in complex algorithm processing, resulting in a variety of FPGA+DSP application scenarios.

[0003] In harsh space environments, space-based equipment is prone to program failures, which is one of the main problems currently faced by space-based platforms. The current more reliable solution is to use three aerospace-grade Flash chips for triple-mode redundancy design when resources are sufficient. When a program error occurs in the device, the DSP program solidified in the Flash chip is read by storing three and taking two, and the device program is corrected. However, the inability to upgrade the solidified DSP program online and the expensive cost of aerospace-grade Flash chips are undoubtedly important factors restricting the further development of space-based equipment. Therefore, a DSP injection method with a different technical route is needed to break through these shackles. Summary of the invention

[0004] To solve the above technical problems, the present invention provides a method and system for remote program update based on FPGA+DSP. The method gives full play to the characteristics of rich FPGA logic resources, high speed and high performance, and uses external SRAM instead of Flash chip as storage device, so as to realize the function of DSP program on-track update.

[0005] To achieve the above object, the present invention adopts the following technical solutions:

[0006] A remote program update method based on FPGA+DSP, the method comprising the following steps:

[0007] Step 1: The main control platform obtains the binary data information of the DSP injection program;

[0008] Step 2: The main control platform sends binary data information about the DSP injection program to the FPGA through a preset communication protocol;

[0009] Step 3: After receiving the binary data information, FPGA decodes it. If the decoding is correct, continue to step 4; otherwise, notify the main control platform to resend the binary data information;

[0010] Step 4: FPGA writes the decoded binary data information into the external SRAM and generates a reset signal to send to DSP;

[0011] Step 5: After receiving the reset signal, the DSP reads the BootLoader program from the ROM of the FPGA and adjusts the device status;

[0012] Step 6: DSP reads the decoded binary data information from SRAM to complete DSP update and bootstrap.

[0013] On the other hand, the present invention provides a system for remote program update based on FPGA+DSP, comprising:

[0014] An information acquisition unit is used to acquire binary data information of the DSP injection program using the main control platform, and send the binary data information of the DSP injection program to the FPGA through a preset communication protocol;

[0015] The writing unit is used to decode the binary data information after receiving it by using FPGA. If the decoding is correct, the decoded binary data information is written into the external SRAM, and a reset signal is generated and sent to the DSP, otherwise, the main control platform is notified to resend the binary data information;

[0016] The update unit is used to read the BootLoader program from the ROM of the FPGA and adjust the device status after the DSP receives the reset signal; after the adjustment, the decoded binary data information is read from the SRAM to complete the DSP update and boot.

[0017] In a third aspect, the present invention provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; wherein, when the one or more programs are executed by the one or more processors, the one or more processors implement the aforementioned method of remote program update based on FPGA+DSP.

[0018] In a fourth aspect, the present invention provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, enables the processor to implement the aforementioned remote program update method based on FPGA+DSP.

[0019] The beneficial effects of the present invention are:

[0020] The main control platform in the design of the present invention is an indispensable part, which can upload different DSP binary upgrade files and adjust and update the DSP program in real time according to different application fields and current status.

[0021] The present invention uses an external SRAM chip to replace a Flash chip as a data storage chip, and uses the characteristics of SRAM that data can be written and original data can be overwritten to store the DSP program sent by the main control platform, thus providing a basis for DSP to complete on-track updating.

[0022] The design of the present invention does not need to use multiple aerospace-grade Flash chips, effectively reducing costs, and further utilizing the flexible and programmable characteristics of FPGA, and has strong operability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of the architecture of a remote program update based on FPGA+DSP of the present invention;

[0024] Figure 2 The figure is a flow chart of a remote program update based on FPGA+DSP of the present invention. DETAILED DESCRIPTION

[0025] The present invention will be further described below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described below are only used to explain the present invention, but not to limit the present invention, and the various technical features involved in the embodiments can be used in combination as long as they do not conflict with each other.

[0026] The data reading of SRAM is not destructive, and the information stored in the static storage unit is relatively stable. There is no need to regenerate the internal storage unit. At the same time, SRAM has a fast read and write speed, a simple structure, and a relatively controllable cost. It is connected to FPGA through a bidirectional bus. ROM is a read-only memory that can save data when power is off. The function of the program function is completed through the division of labor and cooperation between the two. Since the program stored in the nand flash chip cannot be directly run, only the more expensive nor flash chip can be selected in the program update. Due to the expensive cost, in the commonly used embedded systems, the nor flash chip with a very small capacity is mostly used as the startup medium. If the nor flash chip needs to be used for program update, the nor flash chip is required to have a large enough capacity, which is a great pressure on the overall cost control of the system. Most of the current on-track program functions are completed based on FPGA+flash chip, and the use of the flash chip capacity is very precise, which also limits the scale of program update. The iterative function design is limited by the capacity of the flash chip and can only make trade-offs. The starting point of the present invention is to effectively reduce costs while ensuring hardware reliability and complete functions and to ensure that the subsequent program function iteration scale is not limited as much as possible.

[0027] like Figure 1 As shown, a schematic diagram of the architecture of a remote program update method based on FPGA+DSP is shown. The main control platform modifies the updated DSP injection program and sends it to the FPGA through the uart serial port together with the injection instruction according to the preset communication protocol. In the data decoding module, the FPGA decodes the data after receiving the data information. After the instruction is parsed correctly, the data is parsed and a sum check is performed. If the check is correct, the data is written into the external SRAM, otherwise an error status is returned to notify the main control platform to resend the program code data. After the entire package of data is written into the SRAM, the FPGA reads the data from the SRAM for CRC check. After the check is correct, a reset signal rst is sent to the DSP. After the DSP responds to the reset, it first reads the BootLoader program stored in the ROM through the EMIF port to configure the hardware device environment. After the device status is ready, the DSP injection program code data is read from the SRAM to realize the self-boot and operation of the DSP. When the main control platform no longer transmits data, the FPGA data decoding process is interrupted. When the interruption time reaches the preset value, the DSP update process is actively terminated.

[0028] like Figure 2 As shown, a flowchart of a remote program update method based on FPGA+DSP is shown, and the specific steps are as follows:

[0029] Step 1: The main control platform obtains the binary data information of the DSP injection program;

[0030] Step 2: The main control platform sends the DSP program injection instruction and injection data to the FPGA through the preset communication protocol;

[0031] Step 3: After receiving the injection instruction and injection data, FPGA converts the serial data received from the uart serial port into parallel data and decodes the injection data. Since the injection data is sent together with the injection instruction, the injection instruction comes first and the injection data comes later, so the injection instruction is decoded first in the data decoding module. When the injection instruction is correct, the injection data is parsed, otherwise the main control platform is notified to resend the relevant data signal;

[0032] Step 4: FPGA writes the decoded data into the external SRAM and generates a reset signal to send to DSP;

[0033] Step 5: After receiving the reset signal, the DSP reads the BootLoader program from the ROM of the FPGA and adjusts the device status;

[0034] Step 6: After the DSP completes the preparation for receiving the injection data, it reads the injection data from the SRAM to complete the DSP update and bootstrap.

[0035] On the other hand, the present invention provides a remote program update system based on FPGA+DSP, wherein each unit included in the system can implement each step of the aforementioned method, specifically including:

[0036] An information acquisition unit is used to acquire binary data information of the DSP injection program using the main control platform, and send the binary data information of the DSP injection program to the FPGA through a preset communication protocol;

[0037] The writing unit is used to decode the binary data information after receiving it by using FPGA. If the decoding is correct, the decoded binary data information is written into the external SRAM, and a reset signal is generated and sent to the DSP, otherwise, the main control platform is notified to resend the binary data information;

[0038] The update unit is used to read the BootLoader program from the ROM of the FPGA and adjust the device status after the DSP receives the reset signal; after the adjustment, the decoded binary data information is read from the SRAM to complete the DSP update and boot.

[0039] In a third aspect, the present invention provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; wherein, when the one or more programs are executed by the one or more processors, the one or more processors implement the aforementioned method of remote program update based on FPGA+DSP.

[0040] In a fourth aspect, the present invention provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, enables the processor to implement the aforementioned remote program update method based on FPGA+DSP.

[0041] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A remote program update method based on FPGA+DSP, characterized in that: The method comprises the following steps: Step 1: The main control platform obtains the binary data information of the DSP injection program; Step 2: The main control platform sends binary data information about the DSP injection program to the FPGA through a preset communication protocol; Step 3: After receiving the binary data information, FPGA decodes it. If the decoding is correct, continue to step 4; otherwise, notify the main control platform to resend the binary data information; Step 4: FPGA writes the decoded binary data information into the external SRAM and generates a reset signal to send to DSP; Step 5: After receiving the reset signal, the DSP reads the BootLoader program from the ROM of the FPGA and adjusts the device status; Step 6: DSP reads the decoded binary data information from SRAM to complete DSP update and bootstrap.

2. The method for remote program update based on FPGA+DSP according to claim 1, characterized in that: In the step 1, the binary data information includes an injection instruction and injection data.

3. The method for remote program update based on FPGA+DSP according to claim 1, characterized in that: In the step 2, the main control platform sends binary data information about the DSP injection program to the FPGA through the uart serial port.

4. The method for remote program update based on FPGA+DSP according to claim 3, characterized in that: In the step 2, the FPGA converts the serial data received from the uart serial port into parallel data.

5. The method for remote program update based on FPGA+DSP according to claim 2, characterized in that: In the step 3, after receiving the injection instruction and injection data, the FPGA first decodes the injection instruction, and if the decoding is correct, then parses the injection data, otherwise notifies the main control platform to resend the binary data signal.

6. The method for remote program update based on FPGA+DSP according to claim 5, characterized in that: In the step 4, after the FPGA writes the decoded binary data information into the SRAM, the data is read from the SRAM for CRC verification, and a reset signal is sent to the DSP after the verification is correct.

7. The method for remote program update based on FPGA+DSP according to claim 6, characterized in that: In the step 5, the DSP reads the BootLoader program stored in the ROM through the EMIF port to configure the hardware device environment.

8. The method for remote program update based on FPGA+DSP according to claim 1, characterized in that: When the main control platform no longer transmits data, the FPGA data decoding process is interrupted. When the interruption time reaches the preset value, the DSP update process is actively terminated.

9. A remote program update system based on FPGA+DSP, characterized in that: include: An information acquisition unit is used to acquire binary data information of the DSP injection program using the main control platform, and send the binary data information of the DSP injection program to the FPGA through a preset communication protocol; The writing unit is used to decode the binary data information after receiving it by using FPGA. If the decoding is correct, the decoded binary data information is written into the external SRAM, and a reset signal is generated and sent to the DSP, otherwise, the main control platform is notified to resend the binary data information; The update unit is used to read the BootLoader program from the ROM of the FPGA and adjust the device status after the DSP receives the reset signal; after the adjustment, the decoded binary data information is read from the SRAM to complete the DSP update and boot.

10. An electronic device, characterized in that: include: one or more processors; A memory for storing one or more programs; When one or more programs are executed by the one or more processors, the one or more processors implement the FPGA+DSP-based remote program update method as described in any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: Executable instructions are stored thereon, and when the instructions are executed by the processor, the processor can implement the remote program update method based on FPGA+DSP as described in any one of claims 1-8.

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