CRC checking system and method, storage medium and program product

Abstract

The invention discloses a CRC (cyclic redundancy check) system, which is used for checking data sent from a host to a slave and comprises an upper computer control device and a programmable CRC circuit, and the programmable CRC circuit is configured to check data to be checked to generate a check result; the upper computer control device determines a plurality of parameters of the programmable CRC circuit according to a communication scene where the host and the slave are located, and applies the plurality of parameters to the programmable CRC circuit so as to solidify the programmable CRC circuit; calculating an expected CRC result through software based on data to be sent to the slave by the host; the acquisition slave uses received data to be received as data to be verified, and sends the data to be verified to the solidified programmable CRC circuit; reading a verification result generated when the solidified programmable CRC circuit completes verification of the to-be-verified data, and comparing the verification result with an expected CRC result; and in response to the fact that the verification result generated by the solidified programmable CRC circuit is inconsistent with the expected CRC result, instructing the host to send the data to the slave again.

Description

Technical Field

[0001] The present invention relates to the field of CRC verification, and in particular to a CRC verification system, method, storage medium and program product. Background Art

[0002] In the on-chip system, the operating frequency has increased and the on-chip interconnection distance has decreased due to the advancement of integrated circuit manufacturing technology, resulting in an increase in the probability of error signal flipping and inter-level signal crosstalk, and on-chip data stream transmission verification has become increasingly critical. CRC verification is widely used in large-scale data stream communication due to its high error detection rate and low implementation cost. The existing CRC verification system has a rigid circuit structure, which is difficult to adapt to different application scenarios and change flexibly. In addition, the security verification mechanism is not comprehensive, which is easy to cause data errors. Summary of the invention

[0003] The present application provides a CRC checking system, a CRC checking method, a non-transitory computer-readable storage medium, and a computer program product.

[0004] One aspect of the present application relates to a CRC verification system for verifying data sent from a host to a slave, comprising a host control device and a programmable CRC circuit, wherein the programmable CRC circuit is configured to verify the data to be verified to generate a verification result; the host control device comprises: a parameter configuration module, configured to: determine multiple parameters of the programmable CRC circuit according to the communication scenario in which the host and the slave are located, and apply the multiple parameters to the programmable CRC circuit to solidify the structure and function of the programmable CRC circuit according to the communication scenario; an expected calculation module, configured to: calculate the expected CRC result by software based on the data to be sent by the host to the slave; a data scheduling module, configured to: obtain the data to be received by the slave as the data to be verified, and send the data to be verified to the solidified programmable CRC circuit; a result reading module, configured to: read the verification result generated by the solidified programmable CRC circuit after completing the verification of the data to be verified, and compare it with the expected CRC result; and an operation response module, configured to: in response to the verification result generated by the solidified programmable CRC circuit being inconsistent with the expected CRC result, instruct the host to resend the data to the slave.

[0005] In some embodiments, the programmable CRC circuit includes: a parameter solidification subcircuit, configured to receive multiple parameters, and solidify the CRC check algorithm and the actual working circuit structure of the programmable CRC circuit based on the multiple parameters; a check subcircuit, configured to check the data to be checked to generate a check result; an interrupt subcircuit, configured to generate an interrupt signal in response to an event in the solidified programmable CRC circuit during the check of the data to be checked; and a result memory, configured to store the check result generated by the check subcircuit.

[0006] In some embodiments, the check subcircuit includes a first check subcircuit and a second check subcircuit with the same structure, the first check subcircuit and the second check subcircuit each include a serial CRC structure circuit and a parallel CRC structure circuit, and each is configured to check the data to be checked and generate a check result; and the serial CRC structure circuit is a pipeline-configurable circuit structure, and the parallel CRC structure circuit is a pulsating matrix array carry structure.

[0007] In some embodiments, the parameter configuration module of the upper computer control device is further configured to: determine one or more of the following parameters of the programmable CRC circuit according to the communication scenarios in which the host and the slave are located: a lockstep enabling parameter indicating whether to enable both the first check subcircuit and the second check subcircuit; a selection enabling parameter indicating which of the serial CRC structure circuit and the parallel CRC structure circuit to select; when both the first check subcircuit and the second check subcircuit are enabled, the delay parameters of the first check subcircuit and the second check subcircuit respectively; when the serial CRC structure circuit is selected, the number of pipeline stages of the pipeline-stage configurable circuit structure; and when the parallel CRC structure circuit is selected, the matrix configuration parameters of the pulsating matrix array carry structure.

[0008] In some embodiments, the host computer control device also includes a data sorting module; the data sorting module is configured to: divide all data to be sent from the host to the slave into one or more data groups according to the host ID and the slave ID, and the data with the same host ID and the same slave ID are the same data group; the expected calculation module is also configured to: calculate one or more expected CRC results corresponding to one or more data groups respectively through software in units of data groups; and the result reading module is also configured to: read the solidified programmable CRC circuit to complete the verification of the data to be verified in units of data groups and generate one or more verification results corresponding to one or more data groups respectively, and compare the one or more verification results with the one or more expected CRC results respectively.

[0009] In some embodiments, the host computer control device also includes a monitoring module configured to monitor an interrupt signal generated by an interrupt subcircuit of the solidified programmable CRC circuit; and the operation response module of the host computer control device is also configured to: in response to the monitored interrupt signal, execute processing corresponding to the monitored interrupt signal.

[0010] In some embodiments, the interrupt subcircuit of the cured programmable CRC circuit is further configured to: in response to an operational error of the cured programmable CRC circuit, generate an internal error interrupt as an interrupt signal; and in response to the cured programmable CRC circuit generating a predetermined number of check results each time, generate a check result interrupt as an interrupt signal; and the operation response module of the upper computer control device is further configured to: in response to detecting an internal error interrupt, issue an instruction for repairing the error; and in response to detecting a check result interrupt, instruct the result reading module to read the check result from the result memory of the cured programmable CRC circuit for comparison.

[0011] In some embodiments, the interrupt subcircuit of the solidified programmable CRC circuit is also configured to, when both the first check subcircuit and the second check subcircuit are enabled, generate an internal error interrupt when the check result generated by the first check subcircuit is inconsistent with the check result generated by the second check subcircuit; and the operation response module of the upper computer control device is also configured to: in response to monitoring the internal error interrupt, reset the solidified programmable CRC circuit and re-execute the process of checking the data to be checked.

[0012] In some embodiments, the result memory of the solidified programmable CRC circuit includes, based on the multiple parameters, multiple result interrupt status registers corresponding to the multiple data groups respectively and multiple sub-storage spaces corresponding to the multiple data groups respectively, each result interrupt status register is configured to indicate that the verification of the corresponding data group is completed, and each sub-storage space is configured to store the verification result of the corresponding data group; the result reading module of the upper computer control device is also configured to: in response to the verification result interrupt detected by the monitoring module, check one or more result interrupt status identification registers to determine the data group for which verification has been completed, read the verification result generated by the solidified programmable CRC circuit from the sub-storage space corresponding to the data group for which verification has been completed, and compare it with the expected CRC result.

[0013] Another aspect of the present application provides a CRC verification method for verifying data sent from a host to a slave, including: determining multiple parameters of a programmable CRC circuit according to the communication scenario in which the host and the slave are located, and applying the multiple parameters to the programmable CRC circuit to solidify the structure and function of the programmable CRC circuit according to the communication scenario; calculating an expected CRC result through software based on the data to be sent by the host to the slave; obtaining data to be received by the slave as data to be verified, and sending the data to be verified to the solidified programmable CRC circuit; reading the verification result generated by the solidified programmable CRC circuit for verifying the data to be verified, and comparing it with the expected CRC result; and in response to the verification result generated by the solidified programmable CRC circuit being inconsistent with the expected CRC result, instructing the host to resend the data to the slave.

[0014] Another aspect of the present application provides a non-transitory computer-readable storage medium having a computer program stored thereon, and the computer program implements the above-mentioned CRC verification method when executed by a processor.

[0015] Another aspect of the present application provides a computer program product, including a computer program, which implements the above-mentioned CRC checking method when executed by a processor.

[0016] According to the CRC verification system, CRC verification method, computer-readable storage medium and computer program of the present application, the work of the programmable CRC circuit is controlled and scheduled by the host computer control device. The structure and function of the programmable CRC circuit can be solidified according to the communication scene where the host and the slave are located, so the structure and function of the programmable CRC circuit can be flexibly changed according to actual needs, so the CRC verification system according to the present application can be adapted to various communication scenes, greatly increasing the application flexibility. In addition, the expected CRC result is calculated by software, which alleviates the hardware calculation pressure of the programmable CRC circuit. At the same time, by comparing the expected CRC result calculated by the software with the verification result calculated by the hardware of the programmable CRC circuit, the reliability of the verification can be improved and the safety mechanism of the CRC verification system can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic structural block diagram of a CRC check system according to an embodiment of the present application;

[0018] Figure 2 is a schematic structural block diagram of a CRC check system according to an embodiment of the present application;

[0019] Figure 3 is a schematic structural block diagram of a check subcircuit according to an embodiment of the present application;

[0020] Figure 4 is a schematic diagram of a circuit structure with configurable pipeline stages according to an embodiment of the present application;

[0021] Figure 5 Schematic diagram of a systolic matrix array carry structure according to an embodiment of the present application

[0022] Figure 6 A diagram showing a schematic structure of a result storage device according to an embodiment of the present application;

[0023] Figure 7 Flow chart of a CRC verification method according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] In the field of data security verification, CRC (Cyclic Redundancy Check) verification is widely used in large-scale data stream communication scenarios due to its significant advantages of high error detection rate and low implementation cost. The circuit structure of the existing CRC verification system is rigid, and it is difficult to adapt to different application scenarios and flexibly change, and the security verification mechanism is not comprehensive, which is easy to cause data errors. Based on this, the present application provides a CRC verification system, method, storage medium and program product that can adapt to a variety of communication scenarios and has a more complete data verification mechanism. The CRC verification system, method, storage medium and program product according to the present application can be used in the vehicle-mounted field, and is used for the verification of communication data during the communication process of various devices in the vehicle to ensure the accuracy and security of the data stream transmitted by the vehicle-mounted system.

[0025] Figure 1 The schematic block diagram of the CRC check system 1000 according to an embodiment of the present application. The CRC check system 1000 is used to check the data sent from the host to the slave, including the host control device 100 and the programmable CRC circuit 200. The data sent from the host to the slave is transmitted through a physical link. The CRC check system 1000 is used to check whether a transmission error occurs during the transmission of the data through the physical link.

[0026] The host computer control device 100 and the programmable CRC circuit 200 can be connected in communication. The host computer control device 100 is implemented by a computing device, such as a computer or an embedded device with similar functions. The host computer control device 100 runs a special control software, which is developed based on the operating system platform, and uses various programming interfaces and library functions to realize the interaction with the programmable CRC circuit 200 and the calculation and configuration of various parameters, and is responsible for controlling and scheduling the work of the programmable CRC circuit 200, and realizing the comprehensive control of the CRC verification process. It should be understood that the host computer control device 100 can also interact with the host and the slave.

[0027] The programmable CRC circuit 200 is the execution core of the CRC check system, and is configured to check the data to be checked to generate a check result. Specifically, after the programmable CRC circuit 200 receives the parameters from the host computer control device, it performs a CRC check calculation on the input data to be checked. Exemplarily, the CRC circuit 200 according to the embodiment of the present application is an application-specific integrated circuit (ASIC), which contains basic digital circuit elements such as shift registers and XOR gates. These elements are connected and work together according to the parameters set by the host computer control device 100 to realize the function of the CRC circuit.

[0028] The host computer control device 100 includes a parameter configuration module 110, an expected calculation module 120, a data scheduling module 130, a result reading module 140, and an operation response module 150. It is easy to understand that each function of the host computer control device 100 is implemented by software, for example, the host computer control device 100 implements the functions of the above modules by executing a software program by a processor.

[0029] The parameter configuration module 120 is configured to determine multiple parameters of the programmable CRC circuit 200 according to the communication scenarios of the host and the slave, and apply the multiple parameters to the programmable CRC circuit 200 to solidify the structure and function of the programmable CRC circuit 200 according to the communication scenarios.

[0030] The master and slave are devices that interact with each other. The master is the device or node that initiates the transmission of data or instructions, and the slave is responsible for receiving data or instructions from the master. For example, in an in-vehicle system, the CPU or ECU, as the master, can send data or instructions to multiple sensors as slaves.

[0031] In some embodiments, the host control device 100 may have the same physical entity as one or more hosts (that is, relying on the same physical entity to operate), in which case, the function of the host control device 100 is realized by the host running the corresponding software, and the parameters determined by the parameter configuration module 120 of the host control device 100 are applied to the programmable CRC circuit 200 through the physical interface of the host. The host control device 100 may also be a separate physical entity different from the host (that is, relying on a different physical entity to operate), in which case, the function of the host control device 100 is realized by its own running of the corresponding software, and the parameters determined by the parameter configuration module 120 of the host control device 100 are applied to the programmable CRC circuit 200 through its own physical interface. In various cases, the host control device 100 can communicate and control with the host. In short, the concept of distinguishing between the host and the host control device 100 does not necessarily mean the distinction between the two in terms of specific distributed physical deployment, but only represents the distinction between the two at the software function level. Software with different functions can have a unified physical entity and share a set of interfaces, or they can be applied to different physical entities and act on different interfaces. In the present application, the host and the upper computer control device 100 respectively have the functions of generating data to be sent to the slave and controlling the operation of the programmable CRC circuit. As an example, each function can be implemented by running different functional software on mutually distinguishable physical entities; in this case, the host and the upper computer control device 100 respectively have mutually distinguishable physical entities and can communicate with each other.

[0032] The communication scenarios of the host and slaves include, for example, the number of hosts and slaves involved in the communication, the communication mode, the node traffic size, etc. The number of hosts and slaves refers to the number of devices involved in the communication. The communication mode includes, for example, serial communication, parallel communication, network-based communication, etc. Node traffic refers to the amount of data transmitted or received by each device node per unit time.

[0033] The multiple parameters of the programmable CRC circuit 200 mainly include CRC algorithm parameters and system operating parameters. CRC algorithm parameters refer to which CRC algorithm the programmable CRC circuit 200 uses when performing verification. Common CRC algorithms include, for example, CRC-8, CRC-16, CRC-32, etc. Different algorithms generate different polynomials, and the error detection capabilities and applicable scenarios are also different. For example, the CRC-8 algorithm is relatively simple and has a fast calculation speed. It is suitable for scenarios where the requirements for data accuracy are not particularly high, the amount of data is small, and the requirements for real-time performance are high, such as some simple short message transmissions or data verification inside small devices. CRC-32 has a stronger error detection capability due to the characteristics of its generating polynomial, and can detect more types of errors, but the amount of calculation is relatively large, which is suitable for use in scenarios with extremely high requirements for data integrity and large data transmission volume, such as network file transmission, data storage verification of large databases, etc. According to the data importance, data volume, and real-time requirements in real-time application scenarios, the CRC verification algorithm is determined after comprehensive weighing to ensure that the overall operating efficiency of the system is not affected as much as possible while meeting the verification accuracy. CRC algorithm parameters include CRC polynomial coefficients, CRC register initial values, CRC polynomial bit width, etc., which are used to implement the corresponding CRC algorithm through hardware circuits.

[0034] The system operating parameters are the internal configuration required for the programmable CRC circuit 200 to work, and are used to construct the circuit structure of the actual operation of the programmable CRC circuit 200, for example, including the number of various registers, interrupt control parameters (such as interrupt trigger conditions, interrupt priority arrangements, etc.), parameters for configuring the circuit structure, etc. After determining the multiple parameters of the programmable CRC circuit 200, these multiple parameters are applied to the programmable CRC circuit 200, so that the programmable CRC circuit 200 implements the functions that the host computer control device 100 wants to implement according to these multiple parameters. In a specific embodiment, these parameters are loaded onto an ASIC as the programmable CRC circuit 200, for example, through a hardware description language, and the ASIC configures the corresponding circuit structure according to these parameters and loads an algorithm to implement the functions corresponding to these parameters. More specific system operating parameters will be described in detail later.

[0035] Solidifying the structure and functions of the programmable CRC circuit 200 means that the internal structure and achievable functions of the CRC circuit which originally has certain programmability are determined by hardware description language or the like.

[0036] The expected calculation module 120 is configured to calculate the expected CRC result by software based on the data that the host is going to send to the slave. The expected calculation module 120 obtains the data that the host is going to send to the slave in advance, and calculates the expected CRC result of the data to be sent on the software side through a software algorithm. The data that the host is going to send to the slave is the data on the host side, which refers to the data before being transmitted through the physical link, that is, the data before being transmitted through the physical link on the host side. The expected CRC result here is the CRC check code that should be obtained in an ideal error-free situation according to the CRC check algorithm identical to the solidified CRC programmable circuit 200. The expected CRC result can be stored in a predetermined storage module of the host control device 100.

[0037] The data scheduling module 130 is configured to obtain the data to be received by the slave as the data to be verified, and send the data to be verified to the hardened programmable CRC circuit.

[0038] The data transmission from the host to the slave is carried out normally via the physical link. During the transmission process, when the data is transmitted to the side close to the slave, a copy of the transmitted data is bypassed to the CRC verification system 1000. Thus, the data scheduling module 130 of the host control device 100 obtains the data to be received by the slave (that is, the data bypassed during the transmission process) as the data to be verified. The CRC verification system 1000 can be set close to the side of the slave to verify the data to be received by the slave. The data to be received by the slave is the data on the slave side, which refers to the data to be sent to the slave after passing through the physical link from the host to the slave.

[0039] Preferably, the data scheduling module 130 of the upper computer control device 100 needs to consider the maximum data calculation amount of the solidified programmable CRC circuit 200 during the process of sending the data to be verified. For example, in the case where the solidified programmable CRC circuit 200 only supports the calculation of 100 data at a time, if the host has more than 100 data to send to the slave, these data are bypassed to the CRC verification system 1000 as the data to be verified during the transmission to the slave, and the data to be verified bypassed to the CRC verification system 1000 is temporarily stored in a predetermined storage part of the upper computer control device 100, and the data scheduling module 140 of the upper computer control device 100 sends the data transmitted from the host to the slave to the solidified programmable CRC circuit 200 in batches from the predetermined storage part with a scheduling of transmitting less than 100 data each time.

[0040] The result reading module 140 is configured to read the verification result generated by the fixed programmable CRC circuit after verifying the data to be verified, and compare it with the expected CRC result.

[0041] The solidified programmable CRC circuit 200 generates a check result through calculation of its hardware structure, such as a check code generated by the solidified programmable CRC circuit 200. The expected CRC result calculated by the software is calculated based on the data to be sent by the host, and the check result calculated by the solidified programmable CRC circuit 200 is calculated based on the data to be received by the slave (i.e., the data transmitted to the side close to the slave through the physical link). By comparing the check result with the expected CRC result calculated by the software algorithm, it can be determined whether an error occurs in the data transmission process. If the check result generated by the hardware calculation of the solidified programmable CRC circuit 200 is consistent with the expected CRC result, it is considered that the data transmission from the host to the slave is correct.

[0042] The operation response module 150 is configured to instruct the host to resend the data to the slave in response to the verification result generated by the hardened programmable CRC circuit being inconsistent with the expected CRC result.

[0043] If the check result generated by the solidified programmable CRC circuit is inconsistent with the expected CRC result after comparison by the result reading module 140, it is considered that an error occurs in the data transmission process from the host to the slave, and the host is therefore instructed to resend the data to be sent to the slave. In the process of the host resending the data to be sent to the slave, the data scheduling module 130 of the upper computer control device 100 again sends the received data from the slave as the data to be checked to the solidified programmable CRC circuit 200 for verification until the check result generated by the solidified programmable CRC circuit 200 is consistent with the expected CRC result.

[0044] According to the CRC check system 1000 of the above embodiment, the work of the programmable CRC circuit 200 is controlled and scheduled by the host computer control device 100. The structure and function of the programmable CRC circuit 200 can be solidified according to the communication scene in which the host and the slave are located, so the structure and function of the programmable CRC circuit 200 can be flexibly changed according to actual needs, so the CRC check system 1000 according to the above embodiment can adapt to various communication scenes, greatly increasing the application flexibility. In addition, by calculating the expected CRC result through software, the hardware calculation pressure of the programmable CRC circuit 200 is alleviated. At the same time, by comparing the expected CRC result calculated by the software with the verification result calculated by the hardware of the programmable CRC circuit 200, the reliability of the verification can be improved and the safety mechanism of the CRC check system 1000 can be improved.

[0045] In some embodiments, see Figure 2 The programmable CRC circuit 200 includes a parameter hardening subcircuit 220 , a check subcircuit 240 , a result memory 260 , and an interrupt subcircuit 280 .

[0046] The parameter curing subcircuit 220 is configured to receive a plurality of parameters, and to cure the CRC check algorithm and the circuit structure of the actual operation of the programmable CRC circuit 200 based on the plurality of parameters. As described above, the host computer control device 100 determines a plurality of parameters of the programmable CRC circuit 200 according to the communication scenario. The parameter curing subcircuit 220 is used, for example, to apply these parameters to the main circuit (e.g., the check subcircuit 240, the result memory 260, and the interrupt subcircuit 280), thereby curing the programmable CRC circuit 200 according to the parameters, more specifically, curing the check subcircuit 240, the result memory 260, and the interrupt subcircuit 280, so that the cured programmable CRC circuit 200 operates according to the pre-set parameters. The programmable CRC circuit 200 cured by the parameter curing subcircuit 220 is a cured programmable CRC circuit 200.

[0047] The check subcircuit 240 is configured to check the data to be checked to generate a check result. The check subcircuit 240 is used to perform CRC check calculation on the data to generate a check result.

[0048] The interrupt subcircuit 280 is configured to generate an interrupt signal in response to a predetermined event in the process of verifying the data to be verified by the hardened programmable CRC circuit 200. The interrupt subcircuit 280 is mainly responsible for monitoring various key events and states of the programmable CRC circuit 200 during operation. When a predetermined event occurs, such as the occurrence of an internal error, the completion of data transmission, the arrival of a specific time threshold, etc., an interrupt signal is generated in time and reported to the upper computer control device 100.

[0049] The result memory 260 is configured to store the check result generated by the syndrome circuit 240. The check result (eg, check code) generated by the syndrome circuit 240 is stored in the result memory 260.

[0050] It is easy to understand that the programmable CRC circuit 200 being solidified means that the check subcircuit 240, the interrupt subcircuit 280 and the result memory 260 in the programmable CRC circuit 200 are solidified, obtaining the check subcircuit 240, the result memory 260 and the interrupt subcircuit 280 of the solidified programmable CRC circuit 200.

[0051] According to the CRC check system 1000 of the above embodiment, the structure and function of the programmable CRC circuit 200 can be solidified according to the communication scenario in which the host and the slave are located. More specifically, the check subcircuit 240, the result memory 260 and the interrupt subcircuit 280 can be configured according to the parameters received by the parameter solidification subcircuit 220. Therefore, the structure and function of the programmable CRC circuit 200 can be flexibly changed according to actual needs.

[0052] In some embodiments, see Figure 3 The check subcircuit includes a first check subcircuit 242 and a second check subcircuit 244 of the same structure. The first check subcircuit 242 and the second check subcircuit 244 each include a serial CRC structure circuit and a parallel CRC structure circuit, and each is configured to check the data to be checked and generate a check result. The serial CRC structure circuit calculates the check result by a serial result carry method, and the parallel CRC structure circuit can process multiple bits of data at the same time to calculate the check result in parallel.

[0053] In this embodiment, the serial CRC structure circuit is a pipeline-stage configurable circuit structure, and the parallel CRC structure circuit is a systolic matrix array carry structure.

[0054] Figure 4 A schematic diagram of a pipeline-stage configurable circuit structure according to an embodiment of the present application is shown. A pipeline-stage configurable circuit structure refers to dividing the data processing flow into multiple pipeline stages based on a serial CRC structure circuit, and the number of pipeline stages can be adjusted according to the needs of the actual communication scenario. In a specific implementation, the data processing flow is divided into multiple pipeline stages by inserting pipeline registers into the calculation path. The calculation path is divided into N+1 segments by inserting N pipeline registers, so that the length of each path segment is shorter, thereby adapting to a higher hardware operating frequency. The number of inserted pipeline registers can be configured by the upper computer control device 100 through software, so that different numbers of pipeline registers can be configured in different communication scenarios, corresponding to different system operating frequencies. Figure 4 In the example shown, xor_op1, xor_op2, xor_op3, xor_opN-1, xor_opN represent bit-by-bit CRC check operations, and Pipe 1, Pipe 2, ... Pipe M represent inserted pipeline registers. The check coefficient (Poly_i) is the check coefficient of each register position on the CRC serial pipeline calculation path. These coefficients determine how each register participates in the CRC check calculation during the bit-by-bit processing of data along the serial path. The check coefficient reflects how each stage should perform XOR operations on the data to gradually generate the CRC check code.

[0055] Figure 5A schematic diagram of a systolic matrix array carry structure according to an embodiment of the present application is shown. The systolic matrix array carry structure refers to organizing the calculation units in the form of a matrix array on the basis of parallel CRC calculation, and transmitting carry signals between the units in the matrix through a special systolic carry method to achieve high-speed and accurate CRC verification of large-scale data. The matrix configuration parameters of the systolic matrix array carry structure can be configured by the host computer control device 100 through software. Figure 5 In the example shown, Matrix_Coef[i] represents the value of the systolic matrix parameter of the i-th bit, Dat_i[i] represents the value of the i-th bit of the current data to be verified, and prev_result represents the last calculation result of the verification data stream of the current batch. Figure 5 The two-dimensional systolic matrix array carry structure is shown in FIG. 1 , and its parameters are also present in the form of a two-dimensional matrix on each internal processing unit. Figure 5 In the figure, a solid dot indicates that there are actual calculation parameters at that location, and a hollow dot indicates that there are no calculation parameters configured at that location, and the default value of the parameter is 0.

[0056] According to the CRC check system 1000 of the above embodiment, the check subcircuit 240 includes a first check subcircuit 242 and a second check subcircuit 244 of the same structure, indicating that the check subcircuit 240 has been processed in lockstep. Lockstep is a safety mechanism, two or more identical processing units, these processing units are completely the same in hardware design, including circuit structure, component parameters, etc. They receive the same instructions or data as input, and after the processing unit completes the operation, there is a special comparison circuit to compare their output results. Lockstep provides the reliability and security of the check subcircuit 240. Furthermore, the serial CRC structure circuit is a pipeline-level configurable circuit structure, and the specific working serial CRC structure circuit can be configured according to actual conditions, which increases the actual application space; the parallel CRC structure circuit is a pulsating matrix array carry structure, which greatly increases the circuit's operational efficiency while achieving almost unchanged area. .

[0057] In some embodiments, the parameter configuration module 110 of the upper computer control device 100 is further configured to determine one or more of the following parameters of the programmable CRC circuit 200 according to the communication scenarios in which the host and the slave are located: a lockstep enabling parameter indicating whether both the first check subcircuit 242 and the second check subcircuit 244 are enabled; a selection enabling parameter indicating which of the serial CRC structure circuit and the parallel CRC structure circuit is to be selected; when both the first check subcircuit 242 and the second check subcircuit 244 are enabled, the delay parameters of the first check subcircuit 242 and the second check subcircuit 244 respectively; when the serial CRC structure circuit is selected, the number of pipeline stages of the pipeline-stage configurable circuit structure; and when the parallel CRC structure circuit is selected, the matrix configuration parameters of the pulsating matrix array carry structure.

[0058] The lockstep enabling parameter indicating whether to enable both the first check subcircuit 242 and the second check subcircuit 244 is a parameter indicating whether to enable the lockstep. In the case where both the first check subcircuit 242 and the second check subcircuit 244 are enabled, that is, in the case where the lockstep is enabled, the parameters for determining the programmable CRC circuit 200 determined by the parameter configuration module 110 of the upper computer control device 100 also include: the delay parameters of the first check subcircuit 242 and the second check subcircuit 244 respectively. In the lockstep function, one of the first check subcircuit 242 and the second check subcircuit 244 performs delay processing at the input end, and the other performs delay processing at the output end, and the delay time of the two is the same. The delay parameter refers to the parameter for delay processing at the above-mentioned input end or output end.

[0059] The selection enabling parameter indicating which of the serial CRC structure circuit and the parallel CRC structure circuit is selected is a parameter indicating whether the solidified programmable CRC circuit 200 selects the serial CRC structure circuit or the parallel CRC structure circuit. In order to reduce power consumption and processing overhead, only one of the circuit structures is enabled at the same time. The serial CRC structure circuit and the parallel CRC structure circuit are respectively adapted to processing scenarios under different applications: the serial CRC structure circuit is suitable for general scenarios with small data volume, small speed requirements and high area requirements; the parallel CRC structure circuit is suitable for large data volume scenarios with high speed requirements and low area requirements. The parameter configuration module 110 of the upper computer control device 100 can enable different circuit structures according to the actual communication scenario. When the lockstep function is enabled, the first check subcircuit 242 and the second check subcircuit 244 are enabled at the same time; when the serial CRC structure circuit is selected, the serial CRC structure circuit is enabled in both the first check subcircuit 242 and the second check subcircuit 244; when the parallel CRC structure circuit is selected, the parallel CRC structure circuit is enabled in both the first check subcircuit 242 and the second check subcircuit 244. When a serial CRC structure circuit is selected, the parameters of the programmable CRC circuit 200 determined by the parameter configuration module 110 of the host computer control device 100 also include the number of pipeline stages of the circuit structure with configurable pipeline stages; when a parallel CRC structure circuit is selected, the parameters of the programmable CRC circuit 200 determined by the parameter configuration module 110 of the host computer control device 100 also include the matrix configuration parameters of the pulsating matrix array carry structure.

[0060] In other words, the host control device 100 determines that the multiple parameters of the programmable CRC circuit 200 may include the above parameters according to the communication scenarios of the host and the slave.

[0061] Furthermore, the host control device 100 determines the multiple parameters of the programmable CRC circuit 200 according to the communication scenario of the host and the slave, and can also include: interrupt control parameters and the number of various registers. Exemplarily, the interrupt control parameters include interrupt trigger condition settings, interrupt priority arrangements, etc. Various registers include, for example, error interrupt status registers and result interrupt status registers. The error interrupt status register and the result interrupt status register will be described in detail in conjunction with the following text.

[0062] Furthermore, the first check subcircuit 242 and the second check subcircuit 244 each include a plurality of CRC operation cores, which are pre-configured for executing different CRC algorithms. For example, the first check subcircuit 242 and the second check subcircuit 244 each include a CRC-8 core, a CRC-16 core and a CRC-32 core, which are used to execute CRC-8, CRC-16 and CRC-32 algorithms, respectively. The upper computer control device 100 determines which CRC operation core in the first check subcircuit 242 and the second check subcircuit 244 of the programmable CRC circuit 200 is enabled according to the communication scenario in which the host and the slave are located, thereby determining the CRC check algorithm of the programmable CRC circuit 200. Preferably, in the solidified programmable CRC circuit 200, only one CRC operation core is enabled, and the same CRC operation core is enabled in the first check subcircuit 242 and the second check subcircuit 244 at the same time, and the unenabled CRC operation core is not enabled, thereby reducing energy consumption.

[0063] According to the CRC check system 1000 of the above embodiment, the host computer control device 100 can determine whether to enable lock step and select a serial CRC structure circuit or a parallel CRC structure circuit according to the actual communication scenario, and the specific configuration parameters of the serial CRC structure circuit or the parallel CRC structure circuit can be configured according to the actual communication scenario.

[0064] In some embodiments, the host computer control device 100 also includes a data sorting module; the data sorting module is configured to: divide all data to be sent by the host to the slave into one or more data groups according to the host ID and the slave ID, and the data with the same host ID and the same slave ID are the same data group; the expected calculation module 120 is also configured to: calculate one or more expected CRC results corresponding to one or more data groups respectively by software in units of data groups; and the result reading module 140 is also configured to: read the solidified programmable CRC circuit to complete the verification of the data to be verified in units of data groups and generate one or more verification results corresponding to the one or more data groups respectively, and compare the one or more verification results with the one or more expected CRC results respectively.

[0065] The CRC check system according to the present embodiment can be applied to the communication process between one or more hosts and one or more slaves. Each host has its own host ID, and each slave has its own slave ID as its identification. The data sorting module obtains the data to be sent from the host to the slave in advance, and is divided into multiple data groups according to the sending node (host ID) and the destination node (slave ID) of the data to be sent to the slave. The data with the same host ID and the same slave ID (that is, the data with the same transmission path) are the same data group. In some examples, the number of data groups can be the number of hosts × the number of slaves, that is, each host to each slave The transmission path corresponds to a data group. In other examples, the number of data groups can be less than the number of hosts × the number of slaves, and different combinations of hosts to slaves can correspond to the same data group. Further, a data group ID is added to each data group as the identification of the data group. Further, a Start flag indicating the start of transmission and an End flag indicating the end of transmission are added to each data group, and corresponding flow control bits are added to sort the data in each data group into a format supported by the programmable CRC circuit 200. The flow control bit is a bit that identifies the sending node and the destination node of the data, which can be a data group ID. The data sorting module is a module that interacts with the host. The data that the host is going to send to the slave is sorted as described above before being sent by the host to the slave.

[0066] The expected calculation module 120 of the host control device 100 calculates one or more expected CRC results by software in units of data groups, that is, for each data group, calculates an expected CRC result corresponding to the data group.

[0067] Accordingly, the check subcircuit 240 of the solidified programmable CRC circuit 200 checks the check data in units of data groups and generates one or more check results corresponding to one or more data groups, respectively. The result reading module 140 of the upper computer control device 100 compares the one or more check results with one or more expected CRC results. In this case, the result reading module of the upper computer control device 100 queries the data group ID whose check result generated by the solidified programmable CRC circuit 200 is inconsistent with the expected CRC result, and instructs the corresponding host to resend the data corresponding to the data group ID to the corresponding slave. In this way, the upper computer control device 100 can easily determine which data group or groups have errors during the transmission process, that is, it is easy to determine that the data transmission from which sending node to which destination node has errors, so that it is easy to perform subsequent processing.

[0068] The CRC check system 1000 of the above embodiment can be applied to the communication process between one or more hosts and one or more slaves, that is, the communication process from multiple sending nodes to multiple destination nodes. In this case, the data to be checked includes multiple data groups. The data scheduling module 130 of the host control device 100 can use at least one of the following methods to send the multiple data groups as the data to be checked to the solidified programmable CRC circuit 200: data of the same data group is sent in sequence, data of the same data group is sent out of order, and data of different data groups is sent alternately.

[0069] According to the CRC check system 1000 of the above embodiment, it can be applied to the communication of multiple hosts and multiple slaves according to the needs of actual communication scenarios, and is suitable for flexible expansion in scenarios where the number of host / slave devices and device types change.

[0070] In some embodiments, the host computer control device 100 further includes a monitoring module configured to monitor an interrupt signal generated by the interrupt subcircuit 280 of the hardened programmable CRC circuit 200. The operation response module 150 of the host computer control device 100 is further configured to, in response to detecting the interrupt signal, execute a process corresponding to the detected interrupt signal.

[0071] The interrupt subcircuit 280 of the solidified programmable CRC circuit 200 generates interrupt signals according to the interrupt control parameters pre-configured by the parameter configuration module of the host control device 100 and the rules of these parameters. These interrupt signals will be reported to the host control device 100, and the monitoring module of the host control device 100 monitors the triggering of these interrupt signals. According to the interrupt control parameters, the interrupt subcircuit 280 of the solidified programmable CRC circuit 200 generates different types of interrupt signals during operation, and the operation response module 150 of the host control device 100 performs corresponding processing according to the type of interrupt signal received. Various interrupt signals will be described in detail later.

[0072] According to the CRC verification system 1000 of the above embodiment, the host computer control device 100 monitors the operation process of the solidified programmable CRC circuit 200, that is, monitors the overall verification process of the solidified programmable CRC circuit 200, promptly discovers and handles situations that occur during the data verification process, and improves the reliability of the CRC verification system 1000.

[0073] In some embodiments, the interrupt subcircuit 280 of the programmable CRC circuit 200 is further configured to: generate an internal error interrupt as an interrupt signal in response to an operation error of the cured programmable CRC circuit 200; and generate a check result interrupt as an interrupt signal in response to each predetermined number of check results generated by the cured programmable CRC circuit 200. The operation response module 150 of the host control device 100 is further configured to: issue an instruction to repair the error in response to detecting an internal error interrupt; and read the check result from the result memory 260 of the cured programmable CRC circuit 200 in response to detecting a check result interrupt.

[0074] The solidified programmable CRC circuit 200 includes a plurality of error interrupt status registers, and the number and configuration of the error interrupt status registers are also configured according to the communication scenario via the parameter configuration module 110 of the host computer control device 100. When an operation error occurs in the solidified programmable CRC circuit 200, the corresponding error interrupt status register is set, and the interrupt subcircuit 280 generates an internal error interrupt according to the error interrupt status register being set, and the internal error interrupt is reported to the host computer control device 100.

[0075] Operation errors of the solidified programmable CRC circuit 200 include, for example, lockstep errors, register parity errors, and host computer early read errors. Lockstep errors refer to two (or more) processing units that should produce the same output with the same input and produce different outputs; in this case, the operation response module 150 of the host computer control device 100 can issue instructions to reset the programmable CRC circuit 200. Register parity error refers to the data actually configured in the register being inconsistent with the expected value; in this case, the operation response module 150 of the host computer control device 100 can issue instructions to reconfigure the register stack. Early read back errors refer to the host computer control device 100 reading the check result in advance when the solidified programmable CRC circuit 200 has not completed the check calculation; in this case, the operation response module 150 of the host computer control device 100 can issue instructions to clear the erroneous instructions read in advance. Furthermore, the operation response module 150 of the host control device 100 can record the operation error of the programmable CRC circuit 200 into the error log according to the detected internal error interrupt. The instruction for repairing the error can be sent to the solidified programmable CRC circuit 200, or to a specific module in the host control device 100.

[0076] The result memory 260 of the solidified programmable CRC circuit 200 includes one or more result interrupt status registers, and the number and configuration of the result interrupt status registers are also configured according to the communication scenario via the parameter configuration module 110 of the host computer control device 100. When the solidified programmable CRC circuit 200 completes the verification and generates the verification result, the corresponding result interrupt status register is set, and the interrupt subcircuit 280 generates a verification completion interrupt in response to the result interrupt status register being set, and the verification completion interrupt is reported to the host computer control device 100. The configuration of the result interrupt status register will be described in detail later.

[0077] In response to detecting the check result interrupt, the operation response module 150 of the host control device 100 instructs the result reading module 140 to read the check result from the result memory 260 of the hardened programmable CRC circuit 200 for comparison.

[0078] According to the CRC check system 1000 of the above embodiment, the host computer control device 100 monitors the operation process of the solidified programmable CRC circuit 200 and performs different processing for different interrupt signals, thereby improving the error correction capability of the CRC check system and increasing its practicality.

[0079] In some embodiments, the interrupt subcircuit 280 of the cured programmable CRC circuit 200 is further configured to generate an internal error interrupt when the check result generated by the first check subcircuit 242 is inconsistent with the check result generated by the second check subcircuit 244, while both the first check subcircuit 242 and the second check subcircuit 244 are enabled. The operation response module 150 of the host control device 100 is further configured to: in response to monitoring the internal error interrupt, reset the cured programmable CRC circuit and re-execute the process of checking the data to be checked.

[0080] Enabling both the first check subcircuit 242 and the second check subcircuit 244 means enabling the lockstep function. The inconsistency between the check result generated by the first check subcircuit 242 and the check result generated by the second check subcircuit 244 means that a lockstep error occurs. At this time, the upper computer control device 100 resets the solidified programmable CRC circuit and re-executes the process of checking the data to be checked to ensure the accuracy of the check result.

[0081] According to the CRC checking system 1000 in the above embodiment, the CRC checking system 1000 adds lockstep detection, thereby improving the checking performance of the CRC checking system 1000 .

[0082] In some embodiments, the result memory 260 of the solidified programmable CRC circuit 200 includes, based on multiple parameters, multiple result interrupt status registers corresponding to the multiple data groups and multiple sub-storage spaces corresponding to the multiple data groups, each result interrupt status register is configured to indicate that the verification of the corresponding data group is completed, and each sub-storage space is configured to store the verification result of the corresponding data group; the result reading module 140 of the upper computer control device 100 is also configured to: in response to the verification result interruption detected by the monitoring module, check one or more result interrupt status identification registers to determine the data group for which verification has been completed, read the verification result generated by the solidified programmable CRC circuit 200 from the sub-storage space corresponding to the data group for which verification has been completed, and compare it with the expected CRC result.

[0083] Figure 6 FIG. 2 is a diagram showing a schematic structure of the result memory 260 of the programmable CRC circuit 200. Figure 6 As shown, the result memory 260 includes a first register group 262 and a second register group 264, each including several registers. The registers in the first register group 262 are used when a separate interrupt triggers (to be described in detail later), and the first register group 262 includes a plurality of result interrupt status registers, each of which corresponds to each data group. The number of the plurality of result interrupt status registers included in the first register group 262 is configured by the parameter configuration module 110 of the host computer control device 100, and is configured to be the same as the number of data groups, that is, each data group corresponds to each result interrupt status register one by one. The second register group 264 is used when batch interrupt triggers (to be described in detail later). Similar to the first register group 262, the second register group 264 includes a plurality of result interrupt status registers, and the number of result interrupt status registers is configured by the parameter configuration module 110 of the host computer control device 100, and is configured to be the same as the number of data groups, that is, each data group corresponds to each result interrupt status register one by one. Each result interrupt status register is configured to indicate that the verification of the corresponding data group is completed. More specifically, the solidified programmable CRC circuit 200 completes the verification of the data to be verified in units of data groups and generates one or more verification results corresponding to one or more data groups. One or more result interrupt status registers have a corresponding relationship with one or more data groups. When the solidified programmable CRC circuit 200 completes the verification of a certain data group and generates a corresponding verification result, the result interrupt status register corresponding to the data group is set. For example, the default value of the result interrupt status register is 0, and when the data group completes the verification, the result interrupt status register corresponding to the data group is set to 1. The number of result interrupt status registers and sub-storage spaces and the corresponding relationship with the data groups are configured according to multiple parameters determined by the parameter configuration module 110 of the host computer control device 100.

[0084] More specifically, the solidified programmable CRC circuit generates a predetermined number of check results each time, for example, each predetermined number of result interrupt status registers are set, generating a check result interrupt. For example, when the predetermined number is 1, the solidified programmable CRC circuit 200 generates a check result interrupt each time it completes a check (1 result interrupt status register is set), and this situation is called a single interrupt trigger. When the predetermined number is 10, the solidified programmable CRC circuit 200 generates a check result interrupt each time it completes 10 checks (10 result interrupt status registers are set). The situation where the predetermined number is greater than 1 is called a batch interrupt trigger. The predetermined number can be set by the parameter configuration module 110 of the host computer control device 100 according to the actual communication scenario as a parameter of the programmable CRC circuit 200. For example, in a large batch multi-data group transmission application scenario, the predetermined number is set to be greater than 1, and the check result interrupt is triggered only when the batch check result is generated, which can reduce the number of triggering of the check result interrupt and reduce the response pressure of the host computer control device 100.

[0085] In addition, the first register group 262 and the second register group 264 may also include a host computer advance read error identification register, the number of which may be configured to be the same as the number of result interrupt status registers, for identifying a host computer advance read error event occurring in the corresponding data group. In one configuration, only one of the first register group 262 and the second register group 264 is enabled.

[0086] like Figure 5 As shown, the result memory 260 also includes a storage space 266, which is divided into a plurality of sub-storage spaces. The number of the plurality of sub-storage spaces is configured by the parameter configuration module 110 of the host control device 100, and is configured to be the same as the number of data groups, that is, each data group corresponds to each sub-storage space one by one. When the check sub-circuit 240 of the solidified programmable CRC circuit 200 completes the check of the data group and generates a check result, the check result is stored in the sub-storage space corresponding to the data group.

[0087] When the monitoring module of the host control device 100 detects the interruption of the verification result, it means that the verification of the data group has been completed in the solidified programmable CRC circuit 200. The result reading module 140 of the host control device 100 can determine which data group or groups have been verified by checking one or more result interruption status identification registers, and more specifically determine the ID of the data group that has been verified, and read the verification result generated by the solidified programmable CRC circuit 200 from the sub-storage space corresponding to the data group that has been verified, and compare it with the expected CRC result.

[0088] In practical applications, since the number of data groups is the same as the number of result interrupt status registers and sub-storage spaces, dividing fewer data groups can reduce the number of result interrupt status registers, sub-storage spaces and other registers, and reduce hardware overhead. Therefore, the data sorting module of the host control device 100 can minimize the number of data groups according to the communication scenario. For example, there are M hosts to N hosts for data transmission, but the first transmission is the first M / 2 hosts to N hosts, and the second transmission is the last M / 2 hosts to N hosts. The number of data groups can be set to M / 2×N instead of M×N.

[0089] Furthermore, the storage space 265 of the result memory 260 also includes an error detection module for self-detecting possible storage errors within the storage space 265 of the result memory 260. When a storage error occurs, the interrupt subcircuit 280 is notified to generate an internal error interrupt as an interrupt signal.

[0090] Furthermore, the result storage 260 also includes a reset module 266 for controlling the logic of reading and writing the storage space 265 and resetting in case of abnormality.

[0091] Furthermore, the result memory 260 also includes an address mapping module 267 for configuring and storing a mapping code from the storage address of each sub-storage space in the storage space 365 to the storage address of the host computer control device 100 .

[0092] Furthermore, the result memory 260 also includes a write-set mapping module 268, including a plurality of registers corresponding to the plurality of sub-storage spaces respectively. By modifying the identification value of the register in the write-set mapping module, the verification result stored in the sub-storage space corresponding to the register can be cleared, and this mode of clearing the stored verification result is called write-clear. Alternatively, the result memory 260 may not include the write-set mapping module 268; in this case, the verification result stored in the sub-storage space can be cleared while being read by the upper computer control device 100, and at the same time, the corresponding result interrupt status register is cleared, and this mode of clearing the stored verification result is called read-clear. In practical applications, it is preferred to adopt the read-clear mode to reduce the hardware implementation cost.

[0093] According to the CRC verification system 1000 of the above embodiment, when there are more data to be verified, the verification of some data groups is completed earlier. The upper computer control device 100 can clearly know the data groups whose verification has been completed and read the verification results from the corresponding sub-storage space.

[0094] In some embodiments, the host control device 100 also includes a system reset module, which is configured to reset the solidified programmable CRC circuit 200 after completing the effective transmission of all data to be sent from the host to the slave, so that the solidified programmable CRC circuit 200 is restored to the default state, that is, its solidified parameters are removed. The effective transmission of all data to be sent from the host to the slave means that the solidified programmable CRC circuit 200 completes the verification of all transmitted data groups, and the verification result generated by the solidified programmable CRC circuit 200 is consistent with the expected CRC result, and the data is successfully received by the slave. Restoring the programmable CRC circuit 200 to the default state means removing the solidified parameters in the programmable CRC circuit 200, the circuit structure and function inside the programmable CRC circuit 200 will be restored to the default state, and the various parameters of the programmable CRC circuit 200 can be reconfigured.

[0095] According to the CRC check system 1000 of the above embodiment, after completing the data transmission from the host to the slave, the programmable CRC circuit 200 is restored to the default state, and the various parameters of the programmable CRC circuit 200 can be reconfigured according to the actual communication scenario of the next data transmission.

[0096] Another aspect of the present application provides a CRC verification method for verifying data sent from a host to a slave. Figure 7 , Figure 7 is a flow chart of a CRC verification method according to an embodiment of the present application, and the CRC verification method includes the following steps S710-S750. It is easy to understand that the CRC verification method is executed by a computing device, for example, by the host computer control device 100 according to the aforementioned embodiment.

[0097] In S710, multiple parameters of the programmable CRC circuit are determined according to the communication scenarios of the host and the slave, and the multiple parameters are applied to the programmable CRC circuit to solidify the structure and function of the programmable CRC circuit according to the communication scenarios;

[0098] In S720, based on the data to be sent from the host to the slave, an expected CRC result is calculated by software;

[0099] In S730, the slave receives the received data as the data to be verified, and sends the data to be verified to the solidified programmable CRC circuit;

[0100] In S740, a check result generated by the solidified programmable CRC circuit for checking the data to be checked is read and compared with an expected CRC result; and

[0101] In S750 , in response to the fact that the check result generated by the hardened programmable CRC circuit is inconsistent with the expected CRC result, the host is instructed to resend the data to the slave.

[0102] In some embodiments, the programmable CRC circuit includes: a parameter solidification subcircuit, configured to receive multiple parameters, and solidify the CRC check algorithm and the actual working circuit structure of the programmable CRC circuit based on the multiple parameters; a check subcircuit, configured to check the data to be checked to generate a check result; an interrupt subcircuit, configured to generate an interrupt signal in response to an event in the solidified programmable CRC circuit during the check of the data to be checked; and a result memory, configured to store the check result generated by the check subcircuit.

[0103] In some embodiments, the check subcircuit includes a first check subcircuit and a second check subcircuit with the same structure, the first check subcircuit and the second check subcircuit each include a serial CRC structure circuit and a parallel CRC structure circuit, and each is configured to check the data to be checked and generate a check result; and the serial CRC structure circuit is a pipeline-configurable circuit structure, and the parallel CRC structure circuit is a pulsating matrix array carry structure.

[0104] In some embodiments, step S710 also includes: determining one or more of the following parameters of the programmable CRC circuit according to the communication scenarios in which the host and the slave are located: a lockstep enable parameter indicating whether to enable both the first check subcircuit and the second check subcircuit; a selection enable parameter indicating which of the serial CRC structure circuit and the parallel CRC structure circuit is to be selected; when both the first check subcircuit and the second check subcircuit are enabled, respective delay parameters of the first check subcircuit and the second check subcircuit; when the serial CRC structure circuit is selected, the number of pipeline stages of the pipeline-stage configurable circuit structure; and when the parallel CRC structure circuit is selected, the matrix configuration parameters of the systolic matrix array carry structure.

[0105] In some embodiments, the CRC verification method also includes: dividing all data to be sent by the host to the slave into one or more data groups according to the host ID and the slave ID, and the data with the same host ID and the same slave ID are the same data group; step S720 also includes: taking the data group as a unit, calculating one or more expected CRC results corresponding to the one or more data groups respectively by software; step S740 also includes: reading the solidified programmable CRC circuit to complete the verification of the data to be verified in units of data groups and generate one or more verification results corresponding to the one or more data groups respectively, and comparing the one or more verification results with the one or more expected CRC results respectively.

[0106] In some embodiments, the CRC verification method further includes: monitoring an interrupt signal generated by an interrupt subcircuit of the programmable CRC circuit; and step S750 further includes: in response to monitoring the interrupt signal, executing processing corresponding to the monitored interrupt signal.

[0107] In some embodiments, the interrupt subcircuit of the cured programmable CRC circuit is also configured to: generate an internal error interrupt as an interrupt signal in response to an operational error of the cured programmable CRC circuit; and generate a check result interrupt as an interrupt signal in response to the cured programmable CRC circuit generating a predetermined number of check results each time; and step S750 also includes: in response to detecting an internal error interrupt, issuing an instruction for repairing the error; and in response to detecting a check result interrupt, instructing a result reading module to read the check result from the result memory of the cured programmable CRC circuit for comparison.

[0108] In some embodiments, the interrupt subcircuit of the programmable CRC circuit is also configured to generate an internal error interrupt when the check result generated by the first check subcircuit is inconsistent with the check result generated by the second check subcircuit when both the first check subcircuit and the second check subcircuit are enabled; and step S750 also includes: in response to monitoring the internal error interrupt, resetting the solidified programmable CRC circuit and re-executing the process of checking the data to be checked.

[0109] In some embodiments, the result memory of the solidified programmable CRC circuit includes multiple result interrupt status registers corresponding to the multiple data groups respectively and multiple sub-storage spaces corresponding to the multiple data groups respectively, each result interrupt status register is configured to indicate that the verification of the corresponding data group is completed, and each sub-storage space is configured to store the verification result of the corresponding data group; S740 also includes: in response to the verification result interrupt detected by the monitoring module, checking one or more result interrupt status identification registers to determine the data group for which verification is completed, reading the verification result generated by the solidified programmable CRC circuit from the sub-storage space corresponding to the data group for which verification is completed, and comparing it with the expected CRC result.

[0110] In some embodiments, the method further includes resetting the hardened programmable CRC circuit 200 after completing the valid transmission of all data to be sent from the host to the slave.

[0111] The specific details of the CRC verification method according to the present application can be referred to the description of the CRC verification system according to the present application, which will not be repeated here.

[0112] Another aspect of the present application provides a non-transitory computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the CRC checking method according to the present application is implemented.

[0113] The specific details of the non-transitory computer-readable storage medium according to the present application can be referred to the description of the CRC verification system according to the present application, which will not be repeated here.

[0114] Another aspect of the present application provides a computer program product, including a computer program, which implements the CRC checking method according to the present application when executed by a processor.

[0115] The specific details of the computer program product according to the present application can be referred to the description of the CRC verification system according to the present application, which will not be repeated here.

[0116] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0117] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A CRC check system for checking data sent from a host to a slave, comprising a host control device and a programmable CRC circuit, wherein the programmable CRC circuit is configured to check the data to be checked to generate a check result; The host computer control device comprises: A parameter configuration module, configured to: determine a plurality of parameters of the programmable CRC circuit according to a communication scenario in which the host and the slave are located, and apply the plurality of parameters to the programmable CRC circuit to solidify the structure and function of the programmable CRC circuit according to the communication scenario; An expected calculation module, configured to: calculate an expected CRC result by software based on the data to be sent by the host to the slave; The data scheduling module is configured to: obtain the data to be received by the slave as the data to be verified, and send the data to be verified to the solidified programmable CRC circuit; A result reading module is configured to: read the verification result generated by the programmable CRC circuit after the verification of the data to be verified, and compare it with the expected CRC result; and The operation response module is configured to: in response to the verification result generated by the hardened programmable CRC circuit being inconsistent with the expected CRC result, instruct the host to resend the data to the slave.

2. The system according to claim 1, wherein: The programmable CRC circuit comprises: A parameter solidification subcircuit, configured to receive the plurality of parameters and solidify the CRC check algorithm and the actual working circuit structure of the programmable CRC circuit based on the plurality of parameters; A check subcircuit, configured to check the data to be checked to generate the check result; an interrupt subcircuit configured to generate an interrupt signal in response to an event in which the hardened programmable CRC circuit is checking the data to be checked; and The result memory is configured to store the verification result generated by the verification subcircuit.

3. The system according to claim 2, wherein: The check subcircuit comprises a first check subcircuit and a second check subcircuit having the same structure, wherein the first check subcircuit and the second check subcircuit each comprise a serial CRC structure circuit and a parallel CRC structure circuit, and each is configured to check the data to be checked and generate a check result; and The serial CRC structure circuit is a pipeline-level configurable circuit structure, and the parallel CRC structure circuit is a systolic matrix array carry structure.

4. The system according to claim 3, wherein: The parameter configuration module of the host control device is further configured to: determine one or more of the following parameters of the programmable CRC circuit according to the communication scenario in which the host and the slave are located: a lockstep enabling parameter indicating whether to enable both the first syndrome sub-circuit and the second syndrome sub-circuit; A selection enabling parameter indicating which of the serial CRC structure circuit and the parallel CRC structure circuit is selected; delay parameters of the first syndrome subcircuit and the second syndrome subcircuit respectively when both the first syndrome subcircuit and the second syndrome subcircuit are enabled; In the case of selecting the serial CRC structure circuit, the number of pipeline stages of the circuit structure that can be configured by the pipeline stage; as well as In case of selecting the parallel CRC structure circuit, the matrix configuration parameters of the systolic matrix array carry structure.

5. The system according to claim 2, wherein: The host computer control device also includes a data sorting module; The data sorting module is configured to: divide all the data to be sent by the host to the slave into one or more data groups according to the host ID and the slave ID, and the data with the same host ID and the same slave ID are the same data group; The expected calculation module is further configured to: calculate one or more expected CRC results respectively corresponding to one or more data groups by software, taking the data group as a unit; and The result reading module is also configured to: read the solidified programmable CRC circuit to complete the verification of the data to be verified in units of the data group to generate one or more verification results corresponding to the one or more data groups respectively, and compare the one or more verification results with the one or more expected CRC results respectively.

6. The system according to claim 5, wherein: The host computer control device further includes a monitoring module configured to monitor an interrupt signal generated by an interrupt subcircuit of the solidified programmable CRC circuit; and The operation response module of the host computer control device is also configured to: in response to detecting the interrupt signal, execute processing corresponding to the detected interrupt signal.

7. The system according to claim 6, wherein: The interrupt subcircuit of the cured programmable CRC circuit is further configured to: generate an internal error interrupt as the interrupt signal in response to an operation error of the cured programmable CRC circuit; and generate a check result interrupt as the interrupt signal in response to each predetermined number of check results generated by the cured programmable CRC circuit; and The operation response module of the host computer control device is also configured to: in response to monitoring the internal error interrupt, issue an instruction for repairing the error; and in response to monitoring the verification result interrupt, instruct the result reading module to read the verification result from the result memory of the solidified programmable CRC circuit for comparison.

8. The system according to claim 7, wherein: The interrupt subcircuit of the hardened programmable CRC circuit is further configured to, when both the first check subcircuit and the second check subcircuit are enabled, generate the internal error interrupt when the check result generated by the first check subcircuit is inconsistent with the check result generated by the second check subcircuit; and The operation response module of the host computer control device is also configured to: in response to detecting the internal error interrupt, reset the solidified programmable CRC circuit and re-execute the process of verifying the data to be verified.

9. The system according to claim 7, wherein: The result memory of the hardened programmable CRC circuit includes, based on the multiple parameters, multiple result interrupt status registers corresponding to the multiple data groups respectively and multiple sub-storage spaces corresponding to the multiple data groups respectively, each result interrupt status register is configured to indicate that the verification of the corresponding data group is completed, and each sub-storage space is configured to store the verification result of the corresponding data group; The result reading module of the host computer control device is also configured as: In response to the verification result interrupt being detected by the monitoring module, the one or more result interrupt status identification registers are checked to determine the data group for which verification has been completed, the verification result generated by the solidified programmable CRC circuit is read from the sub-storage space corresponding to the data group for which verification has been completed, and compared with the expected CRC result.

10. CRC verification method, used to verify the data sent from the host to the slave, including: Determine multiple parameters of a programmable CRC circuit according to a communication scenario in which the host and the slave are located, and apply the multiple parameters to the programmable CRC circuit to solidify the structure and function of the programmable CRC circuit according to the communication scenario; Calculate an expected CRC result by software based on the data to be sent by the host to the slave; Acquire the data received by the slave as the data to be verified, and send the data to be verified to the solidified programmable CRC circuit; Reading a verification result generated by the solidified programmable CRC circuit for verifying the data to be verified, and comparing it with the expected CRC result; as well as In response to the verification result generated by the hardened programmable CRC circuit being inconsistent with the expected CRC result, the host is instructed to resend the data to the slave.

11. A non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the CRC checking method according to claim 10 when executed by a processor.

12. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the CRC checking method according to claim 10 is implemented.

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