Serial SPI slave circuit system based on shift register

Abstract

The invention discloses a serial SPI slave circuit system based on a shift register, which comprises an SPI host and a plurality of SPI slave systems, and each SPI slave comprises an SCLK interface, a CSB interface, an MOSI interface, an MISO interface, an LD interface, a CSB falling edge detection circuit, a plurality of selectors MUX, a shift register STREG and a shadow register SWREG. In application, the problems that the SPI multi-slave system has too many pins, circuit implementation is complex and operation steps are tedious can be effectively solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a serial SPI slave circuit system based on a shift register. Background Art

[0002] SPI interface is widely used in modern embedded chip systems. SPI is a high-speed synchronous communication bus, mainly used for direct communication between microcontrollers and various peripheral devices. It has the advantages of high speed, low power consumption and high scalability. The common SPI interface connection is relatively simple, requiring only 4 wires (SCLK, MOSI, MISO, CSB).

[0003] Traditional SPI can control multiple slave devices by adding a CSB interface, but adding a CSB interface will bring additional overhead to the host device IO pins and cause PCB wiring problems. At the same time, the traditional SPI bus often uses the data transmission method of register address plus register data, which makes the internal circuit implementation of the device more complicated and the operation steps cumbersome. During fast communication, some time will be consumed in transmitting the register address. Summary of the invention

[0004] The purpose of the present invention is to provide a serial SPI slave circuit system based on a shift register, which effectively solves the problems of too many pins in a SPI serial interface multi-slave system, complex circuit implementation and cumbersome operation steps.

[0005] To achieve the above functions, the present invention designs a serial SPI slave circuit system based on a shift register, including an SPI host and multiple SPI slaves, which are SPI slave 0 to SPI slave N in sequence; the SPI host and each SPI slave respectively have an SCLK interface, a CSB interface, a MOSI interface, a MISO interface, and an LD interface, and each SPI slave internally includes a CSB falling edge detection circuit, multiple selectors MUX, a shift register STREG, and a shadow register SWREG.

[0006] The CSB interface of the SPI master is connected to the CSB interface of each SPI slave respectively, the SCLK interface of the SPI master is connected to the SCLK interface of each SPI slave respectively, the LD interface of the SPI master is connected to the LD interface of each SPI slave respectively, the MOSI interface of the SPI master is connected to the MOSI interface of SPI slave 0, starting from SPI slave 0, the MISO interface of each SPI slave is connected to the MOSI interface of the next SPI slave in turn, until the MISO interface of SPI slave N is connected to the MISO interface of the SPI master.

[0007] As a preferred technical solution of the present invention: the CSB falling edge detection circuit inside the SPI slave includes a register REG and a group of combinational logic, the register REG has an input port D, an output port Q, and a clock port; the combinational logic has two input ports, namely input port A and input port B, and also has an output port.

[0008] Among them, register REG runs in the SCLK clock domain, its clock port is connected to the SCLK interface of the SPI slave, register REG input port D is connected to the CSB interface of the SPI slave, register REG output port Q is connected to the combinational logic input port B, and combinational logic input port A is connected to the CSB interface of the SPI slave; the combinational logic inverts the input port A and ANDs it with the input port B to generate a CSB falling edge detection pulse output signal CSB_FALL, which is output from the output port of the combinational logic.

[0009] As a preferred technical solution of the present invention: the multiple shift registers STREG inside the SPI slave are sequentially from STREG0 to STREGn; the multiple shadow registers SWREG are sequentially from SWREG0 to SWREGn, and the multiple selectors MUX include MUXk0 and MUXk1, where k∈{0,1,2,…,n};

[0010] Each shift register STREG and each shadow register SWREG has an input port D, an output port Q, and a clock port; each selector MUX has a 0 input port, a 1 input port, an output port, and a selection signal port.

[0011] The SCLK interface of the SPI slave is connected to the clock ports of all shift registers STREG, the CSB interface of the SPI slave is connected to the selection signal ports of all selectors MUXk1, and the output port CSB_FALL of the CSB falling edge detection circuit is connected to the selection signal ends of all selectors MUXk0; except for the selector MUX01, the 0 input ports of all selectors MUXk1 are connected to the output port Q of the shift register STREGk, and the 0 input port of the selector MUX01 is connected to the MOSI interface of the SPI slave 0.

[0012] The 1 input port of all selectors MUXk1 is connected to the output port Q of the shift register STREGk, and the output port of selector MUXk1 is connected to the 0 input port of selector MUXk0; the 1 input port of selector MUXk0 is connected to the output port Q of the shadow register SWREGk, and the output port of selector MUXk0 is connected to the input port D of the shift register STREGk.

[0013] As a preferred technical solution of the present invention: the SPI slave includes shadow registers SWREG, the number of shadow registers SWREG is less than or equal to the number of shift registers STREG, the input port D of the shadow register SWREGk is connected to the output port Q of the shift register STREGk, where k∈{0,1,2,…,n}; the output port Q of the shadow register SWREGk is connected to the inside of the SPI slave; the clock ports of all shadow registers SWREG are connected to the LD interface of the SPI slave, and when the LD interface rises, the shadow register SWREG samples the output value of the shift register STREG and finally outputs it to the corresponding circuit inside the SPI slave.

[0014] As a preferred technical solution of the present invention: when the CSB interface is high inside the SPI slave, the data in the shift register STREG remains unchanged; when a falling edge of the CSB interface occurs, the shift register STREG loads the data on the shadow register SWREG; when the CSB interface is low, the data to be written at each SCLK rising edge is shifted from the MOSI interface into the shift register STREG, and at the same time, the data to be read is output from the last stage of the shift register STREG to the MISO interface.

[0015] Beneficial effects:

[0016] Compared with the prior art, the advantages of the present invention include:

[0017] The present invention designs a serial SPI slave circuit system based on a shift register, comprising an SCLK interface, a CSB interface, a MOSI interface, a MISO interface, an LD interface, a CSB falling edge detection circuit, a plurality of selectors, a shift register and a shadow register. In application, when there are three or more slave devices, the problem of too many pins in the SPI serial interface multi-slave system, complex circuit implementation and cumbersome operation steps can be effectively solved, the circuit design complexity of the SPI device is reduced, and the pin number requirement of the SPI host is reduced. The transmission register address is cancelled, and the data transmission performance of the SPI is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a traditional multi-slave SPI communication system provided according to an embodiment of the present invention;

[0019] Figure 2 It is a schematic diagram of a serial SPI slave circuit system based on a shift register provided according to an embodiment of the present invention;

[0020] Figure 3 The figure is a schematic diagram of the internal circuit of a serial SPI slave based on a shift register provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present invention.

[0022] A shift register-based serial SPI slave circuit system provided by an embodiment of the present invention includes an SPI host and multiple SPI slaves, the number of the SPI slaves is not less than one, and they are SPI slave 0 to SPI slave N in sequence; the SPI host and each SPI slave respectively have an SCLK interface, a CSB interface, a MOSI interface, a MISO interface, and an LD interface, and each SPI slave internally includes a CSB falling edge detection circuit, multiple selectors MUX, a shift register STREG, and a shadow register SWREG.

[0023] The traditional multi-slave SPI communication system schematic diagram is shown in Figure 1. Figure 1 The SPI master has an SCLK interface, a MISO interface, a MOSI interface, and multiple CSB interfaces, and the number of CSB interfaces is the same as the number of SPI slaves; the SPI slaves each have a CSB interface, an SCLK interface, a MISO interface, and a MOSI interface; each CSB interface of the SPI master is respectively connected to the CSB interface of each SPI slave, the SCLK interface of the SPI master is respectively connected to the SCLK interface of each SPI slave, the MISO interface of the SPI master is respectively connected to the MISO interface of each SPI slave, and the MOSI interface of the SPI master is respectively connected to the MOSI interface of each SPI slave.

[0024] Compared with the traditional multi-slave SPI communication system, the serial SPI slave circuit system designed by the present invention refers to Figure 2 , the CSB interface of the SPI master is connected to the CSB interface of each SPI slave respectively, the SCLK interface of the SPI master is connected to the SCLK interface of each SPI slave respectively, the LD interface of the SPI master is connected to the LD interface of each SPI slave respectively, the MOSI interface of the SPI master is connected to the MOSI interface of SPI slave 0, starting from SPI slave 0, the MISO interface of each SPI slave is connected to the MOSI interface of the next SPI slave in turn, until the MISO interface of SPI slave N is connected to the MISO interface of the SPI master.

[0025] Figure 2In the case where there are three SPI slaves, namely SPI slave 0, SPI slave 1 and SPI slave 2, when sending data transmission, the host data first transmits the data to be written by SPI slave 2 to SPI slave 0 through the MOSI interface through the SPI host. After multiple shifts, the data is transmitted to SPI slave 1 from the MISO interface of SPI slave 0. The SPI host continues to send the data to be written by SPI slave 1, and so on until the data to be written by SPI slave 2 is transmitted from the MISO interface of SPI slave 1 to SPI slave 2. At this time, the SPI host sends the data to be written by SPI slave 0 to SPI slave 0, and SPI slave 0 sends the data to be written by SPI slave 1 to SPI slave 1. At the same time as the transmission occurs, the data to be read by SPI slave 0 is transmitted to SPI slave 1 through the MISO interface of SPI slave 0, the data to be read by SPI slave 1 is transmitted to SPI slave 2 through the MISO interface of SPI slave 1, and the data to be read by SPI slave 2 is transmitted to the SPI host through the MISO interface of SPI slave 2.

[0026] Reference Figure 3 The CSB falling edge detection circuit inside the SPI slave includes a register REG and a set of combinational logic. The register REG has an input port D, an output port Q, and a clock port; the combinational logic has two input ports, namely input port A and input port B, and also has an output port.

[0027] Among them, register REG runs in the SCLK clock domain, its clock port is connected to the SCLK interface of the SPI slave, register REG input port D is connected to the CSB interface of the SPI slave, register REG output port Q is connected to the combinational logic input port B, and combinational logic input port A is connected to the CSB interface of the SPI slave; the combinational logic inverts the input port A and ANDs it with the input port B to generate a CSB falling edge detection pulse output signal CSB_FALL, which is output from the output port of the combinational logic.

[0028] The multiple shift registers STREG inside the SPI slave are sequentially from STREG0 to STREGn, the multiple shadow registers SWREG are sequentially from SWREG0 to SWREGn, and the multiple selectors MUX include MUXk0 and MUXk1, where k∈{0,1,2,…,n}.

[0029] Each shift register STREG and each shadow register SWREG has an input port D, an output port Q, and a clock port; each selector MUX has a 0 input port, a 1 input port, an output port, and a selection signal port.

[0030] The SCLK interface of the SPI slave is connected to the clock ports of all shift registers STREG, the CSB interface of the SPI slave is connected to the selection signal ports of all selectors MUXk1 (k=0~n), and the CSB falling edge detection circuit output port CSB_FALL is connected to the selection signal ends of all selectors MUXk0 (k=0~n); except for the selector MUX01, the 0 input ports of all selectors MUXk1 (k=1~n) are connected to the output port Q of the shift register STREGk (k=1~n), and the 0 input port of the selector MUX01 is connected to the MOSI interface of the SPI slave 0.

[0031] The 1 input port of all selectors MUXk1 (k=0~n) is connected to the output port Q of the shift register STREGk (k=0~n), and the output port of selector MUXk1 (k=0~n) is connected to the 0 input port of selector MUXk0 (k=0~n); the 1 input port of selector MUXk0 (k=0~n) is connected to the output port Q of the shadow register SWREGk (k=0~n), and the output port of selector MUXk0 (k=0~n) is connected to the input port D of the shift register STREGk (k=0~n).

[0032] The SPI slave contains shadow registers SWREG, and the number of shadow registers SWREG is less than or equal to the number of shift registers STREG. Figure 3 The number of shadow registers SWREG and shift registers STREG is equal; the input port D of shadow register SWREGk (k=0~n) is connected to the output port Q of shift register STREGk (k=0~n); shadow register SWREG is a register actually used for logic control and state feedback inside the SPI slave, and the output port Q of shadow register SWREGk is connected to the inside of the SPI slave; the clock ports of all shadow registers SWREG are connected to the LD interface of the SPI slave, and when the LD interface rises, the shadow register SWREG samples the output value of the shift register STREG and finally outputs it to the corresponding circuit inside the SPI slave.

[0033] When the CSB interface is high inside the SPI slave, the data in the shift register STREG remains unchanged; when the falling edge of the CSB interface occurs, the shift register STREG is loaded with the data on the shadow register SWREG; when the CSB interface is low, the data to be written is shifted into the shift register STREG from the MOSI interface at each SCLK rising edge, and the data to be read is output from the last stage of the shift register STREG to the MISO interface.

[0034] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

Claims

1. A serial SPI slave circuit system based on a shift register, characterized in that: It includes an SPI master and multiple SPI slaves, which are SPI slave 0 to SPI slave N in sequence; the SPI master and each SPI slave have an SCLK interface, a CSB interface, a MOSI interface, a MISO interface, and an LD interface respectively, and each SPI slave includes a CSB falling edge detection circuit, multiple selectors MUX, a shift register STREG, and a shadow register SWREG; The CSB interface of the SPI master is connected to the CSB interface of each SPI slave respectively, the SCLK interface of the SPI master is connected to the SCLK interface of each SPI slave respectively, the LD interface of the SPI master is connected to the LD interface of each SPI slave respectively, the MOSI interface of the SPI master is connected to the MOSI interface of SPI slave 0, starting from SPI slave 0, the MISO interface of each SPI slave is connected to the MOSI interface of the next SPI slave in turn, until the MISO interface of SPI slave N is connected to the MISO interface of the SPI master.

2. A serial SPI slave circuit system based on a shift register according to claim 1, characterized in that: The CSB falling edge detection circuit inside the SPI slave includes a register REG and a set of combinational logic. The register REG has an input port D, an output port Q, and a clock port. Combinational logic has two input ports, namely input port A and input port B, and one output port; Among them, register REG runs in the SCLK clock domain, its clock port is connected to the SCLK interface of the SPI slave, register REG input port D is connected to the CSB interface of the SPI slave, register REG output port Q is connected to the combinational logic input port B, and combinational logic input port A is connected to the CSB interface of the SPI slave; the combinational logic inverts the input port A and ANDs it with the input port B to generate a CSB falling edge detection pulse output signal CSB_FALL, which is output from the output port of the combinational logic.

3. A serial SPI slave circuit system based on a shift register according to claim 2, characterized in that: The multiple shift registers STREG inside the SPI slave are from STREG0 to STREGn in sequence; The plurality of shadow registers SWREG are sequentially from SWREG0 to SWREGn, and the plurality of selectors MUX include MUXk0 and MUXk1, where k∈{0,1,2,…,n}; Each shift register STREG and each shadow register SWREG respectively has an input port D, an output port Q, and a clock port; each selector MUX respectively has a 0 input port, a 1 input port, an output port, and a selection signal port; The SCLK interface of the SPI slave is connected to the clock port of all shift registers STREG, the CSB interface of the SPI slave is connected to the selection signal port of all selectors MUXk1, and the CSB falling edge detection circuit output port CSB_FALL is connected to the selection signal end of all selectors MUXk0; Except for the selector MUX01, the 0 input port of all selectors MUXk1 is connected to the output port Q of the shift register STREGk, and the 0 input port of the selector MUX01 is connected to the MOSI interface of the SPI slave 0; The 1 input port of all selectors MUXk1 is connected to the output port Q of the shift register STREGk, and the output port of selector MUXk1 is connected to the 0 input port of selector MUXk0; the 1 input port of selector MUXk0 is connected to the output port Q of the shadow register SWREGk, and the output port of selector MUXk0 is connected to the input port D of the shift register STREGk.

4. A serial SPI slave circuit system based on a shift register according to claim 3, characterized in that: The SPI slave contains shadow registers SWREG, the number of shadow registers SWREG is less than or equal to the number of shift registers STREG, the input port D of shadow register SWREGk is connected to the output port Q of shift register STREGk, where k∈{0,1,2,…,n}; the output port Q of shadow register SWREGk is connected to the inside of the SPI slave; the clock ports of all shadow registers SWREG are connected to the LD interface of the SPI slave, and when the LD interface rises, the shadow register SWREG samples the output value of the shift register STREG and finally outputs it to the corresponding circuit inside the SPI slave.

5. The serial SPI slave circuit system based on a shift register according to claim 2, characterized in that: When the CSB interface is high inside the SPI slave, the shift register STREG data remains unchanged; When the falling edge of the CSB interface occurs, the shift register STREG loads the data on the shadow register SWREG; when the CSB interface is low, the data to be written is shifted into the shift register STREG from the MOSI interface at each SCLK rising edge, and the data to be read is output from the last stage of the shift register STREG to the MISO interface.

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